TWI655667B - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

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TWI655667B
TWI655667B TW106135676A TW106135676A TWI655667B TW I655667 B TWI655667 B TW I655667B TW 106135676 A TW106135676 A TW 106135676A TW 106135676 A TW106135676 A TW 106135676A TW I655667 B TWI655667 B TW I655667B
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Taiwan
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mask
dielectric layer
gate
fin
region
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TW106135676A
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TW201833989A (zh
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林經祥
黃泰鈞
包天一
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台灣積體電路製造股份有限公司
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    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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Abstract

根據本發明一些實施例，提供一種半導體結構的製造方法。上述方法包含凹蝕閘極電極，其位於基底上的半導體鰭片上，使介電層的上表面形成第一凹陷。上述方法包含形成第一遮罩於凹蝕的閘極電極上的第一凹陷內。上述方法亦包含凹蝕第一導電接觸物，其位於半導體鰭片的源極/汲極區上，使介電層的上表面形成第二凹陷。上述方法更包含形成第二遮罩於凹蝕的第一導電接觸物上的第二凹陷內。

Description

半導體結構及其製造方法
本發明一些實施例係有關於半導體結構及其製造方法，特別係有關於半導體裝置中，位於閘極結構上及位於導電接觸物上的遮罩及其製造方法。
隨著半導體工業已經進入奈米技術製程節點，以追求更高的裝置密度、更高的效能和更低的成本。來自製造和設計問題的挑戰造就三維設計的發展，例如鰭式場效電晶體的發展。典型的鰭式場效電晶體是由從例如被蝕刻掉的基底之矽層的一部分所形成的從基底所延伸的薄且垂直的“鰭片”(或鰭結構)所製造。鰭式場效電晶體的通道形成在此鰭片上。閘極設置(例如包覆)在此鰭片上。在通道的兩側上具有一個閘極允許從兩側進行通道的閘極控制。然而，在半導體製程中，執行這些部件和過程存在挑戰。
根據本發明一些實施例，提供一種半導體結構的製造方法。上述方法包含凹蝕基底上的半導體鰭片上的閘極電極，使介電層的上表面形成第一凹陷。上述方法包含形成第一遮罩於凹蝕的閘極電極上的第一凹陷內。上述方法亦包含凹蝕 半導體鰭片的源極/汲極區上的第一導電接觸物，使介電層的上表面形成第二凹陷。上述方法更包含形成第二遮罩於凹蝕的第一導電接觸物上的第二凹陷內。
根據本發明一些實施例，提供一種半導體結構的製造方法。上述方法包含形成鰭片於基底上及形成環繞鰭片的隔離區。上述方法包含形成虛置閘極結構於鰭片上及磊晶成長源極/汲極區於虛置閘極結構的相對兩側。上述方法包含形成層間介電層於隔離區上，層間介電層且環繞該虛置閘極結構。上述方法亦包含以主動閘極結構取代該虛置閘極結構，並凹蝕主動閘極結構，以形成第一凹陷。上述方法亦包含形成第一遮罩於第一凹陷內，並形成穿過層間介電層的第一導電接觸物，耦接至源極/汲極區。上述方法更包含凹蝕第一導電接觸物，以形成第二凹陷，及形成第二遮罩於第二凹陷內。
根據本發明一些實施例，提供一種半導體結構。上述結構包含設置於基底上的第一鰭片，及環繞第一鰭片的下表面的隔離區。上述結構包含沿第一鰭片的側壁及上表面設置的閘極結構及設置於第一鰭片上的源極/汲極區，其鄰接於閘極結構。上述結構亦包含設置於隔離區上的介電層，其環繞閘極結構，及包含設置於閘極結構上的第一遮罩，第一遮罩具有上表面，與介電層的上表面齊平。上述結構更包含穿過介電層，並接觸源極/汲極區的第一導電接觸物，並包含設置於第一導電接觸物上的第二遮罩，第二遮罩具有上表面，其與介電層的上表面齊平。
30‧‧‧鰭式場效電晶體
32‧‧‧基底
34‧‧‧隔離區
36‧‧‧鰭片
38‧‧‧閘極介電層
40‧‧‧閘極電極
42‧‧‧源極/汲極區
44‧‧‧源極/汲極區
50‧‧‧基底
50B‧‧‧第一區
50C‧‧‧第二區
52‧‧‧鰭片
54‧‧‧隔離區
56‧‧‧鰭片
58‧‧‧虛置介電層
60‧‧‧虛置閘極層
62‧‧‧遮罩層
70‧‧‧虛置閘極
72‧‧‧遮罩
76‧‧‧虛置閘極
78‧‧‧遮罩
80‧‧‧閘極密封間隙物
82‧‧‧磊晶源極/汲極區
84‧‧‧磊晶源極/汲極區
86‧‧‧閘極間隙物
88‧‧‧層間介電層
90‧‧‧凹陷
92‧‧‧閘極介電層
94‧‧‧閘極電極
96‧‧‧閘極介電層
98‧‧‧閘極電極
100‧‧‧凹陷
102‧‧‧凹陷
104‧‧‧遮罩
106‧‧‧遮罩
108‧‧‧開口
110‧‧‧開口
112‧‧‧導電接觸物
114‧‧‧導電接觸物
116‧‧‧凹陷
118‧‧‧凹陷
120‧‧‧遮罩
122‧‧‧遮罩
126‧‧‧導電接觸物
128‧‧‧導電接觸物
130‧‧‧導電接觸物
132‧‧‧導電接觸物
136‧‧‧絕緣襯層
138‧‧‧絕緣襯層
本揭露的各種樣態最好的理解方式為閱讀以下說明書的詳說明並配合所附圖式。應該注意的是，本揭露的各種不同特徵部件並未依據工業標準作業的尺寸而繪製。事實上，為使說明書能清楚敘述，各種不同特徵部件的尺寸可以任意放大或縮小。
第1圖是鰭式場效電晶體的三維立體圖的其中一示例；第2-6、7A-7C、8A-8C、9A-9C、10A-10C、11A-11C、12A-12C、13A-13C、14A-14C、15A-15C、16A-16C、17A-17C、18A-18C、19A-19C及20A-20C圖是根據一些實施例，形成鰭式場效電晶體之中間各階段的剖面圖；第21A-21C及22A-22C圖是根據一些實施例，形成鰭式場效電晶體之中間各階段的剖面圖。
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵部件。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。例如，若是本說明書以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方，即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦包含了將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。另外，本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符 號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或特徵部件與另一(複數)元件或(複數)特徵部件的關係，可使用空間相關用語，例如”在...之下”、”下方”、”下部”、”上方”、”上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語涵蓋使用或操作中的裝置的不同方位。例如，若翻轉圖式中的裝置，描述為位於其他元件或特徵部件”下方”或”在...之下”的元件，將定位為位於其他元件或特徵部件”上方”。因此，範例的用語”下方”可涵蓋上方及下方的方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
根據各種不同的實施例，提供鰭式場效電晶體(Fin Field-Effect Transistor,FinFET)及其形成方法，並繪示形成鰭式場效電晶體的中間各個階段。在本說明書所討論的一些實施例中，使用閘極優先製程來形成鰭式場效電晶體。在其他實施例，可使用後閘極製程(有時稱為替代閘極製程)。在此討論各種不同的實施例，所屬技術領域中具有通常知識者可了解，在不脫離本發明其他實施例的範圍內可做任何修改。雖然在此討論的方法之實施例是以特定順序執行，但在其他的方法實施例可以任何合理的順序執行，並且可包含比在此討論的實施例少或多的步驟。
在具體說明所繪示的實施例之前，將大略地說明本發明實施例的一些有益的部件和觀點。一般而言，本發明實 施例所述的半導體裝置及其形成方法提供了簡易且低成本的製程流程，在形成連接至閘極電極的穿孔時，降低閘極電極與源極/汲極接觸物之間的電性短路/漏電的機率。此外，簡易且低成本的製程流程允許縮短閘極電極的佈局，讓閘極電極上方的穿孔能更接近源極/汲極接觸物上方的穿孔。更具體而言，例如這些探討的實施例之製程包含將遮罩設置於閘極電極和源極/汲極接觸物兩者上方，以允許連接至閘極電極和源極/汲極接觸物兩者的穿孔能自我對準。這些位於閘極電極和源極/汲極接觸物上方的遮罩確保即使穿孔錯位時，上方的穿孔不使閘極電極與源極/汲極接觸物之間產生短路。
第1圖繪示鰭式場效電晶體(FinFET)30的一個示例之三維立體圖。鰭式場效電晶體30包含位於基底32上的鰭片36。基底32包含隔離區34，且鰭片36凸出於相鄰的兩個隔離區34之間。閘極介電層38沿著鰭片36的側壁和上表面而形成，且閘極電極40位於閘極介電層38上方。源極/汲極區42和44設置在閘極介電層38和閘極電極40相對兩側的鰭片36上。第13圖進一步繪示之後圖式的剖面圖。剖面A-A橫跨鰭式場效電晶體30的通道、閘極介電層38和閘極電極40。剖面B/C-B/C與剖面A-A垂直，且為沿鰭片36的縱軸以及例如為源極/汲極區42和44之間電流流動的方向。為了簡潔，後續對應的圖式所示的剖面亦可參考上述對應剖面的敘述。
在本說明書中，一些實施例所探討鰭式場效電晶體的形成是使用後閘極製程。在其他實施例，則可使用閘極優先製程。此外，一些實施例可使用於平面裝置，例如平面鰭式 場效電晶體。
第2-20C圖是根據一些實施例，製造鰭式場效電晶體中間各階段的剖面示意圖。在第2-6圖中，除了多個鰭式場效電晶體以外，是沿第1圖的A-A剖面線繪示。在第7A-20C圖中，圖式名稱最後標示”A”指的是沿A-A剖面線繪示，圖式名稱最後標示”B”指的是沿B/C-B/C剖面線繪示基底的第一區，圖式名稱最後標示”C”指的是沿B/C-B/C剖面線繪示基底的第二區。
第2圖繪示基底50。基底50可為半導體基底，例如塊材(bulk)半導體、絕緣上覆半導體(semiconductor-on-insulation,SOI)基底，類似的摻雜(例如，摻雜p型或n型摻雜質)或未摻雜的基底。基底50可以是晶圓，例如為矽晶圓。一般而言，絕緣上覆半導體基底包含形成在絕緣層上的一層半導體材料。絕緣層可例如為埋入氧化(buried oxide,BOX)層、氧化矽層或類似的材料。提供絕緣層在基底上，一般基底為矽或玻璃基底。其他的基底則可使用例如為多重層或梯度(gradient)基底。在一些實施例，基底50可為半導體材料，其可包含矽、鍺；基底50亦可為化合物半導體，其包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；基底50亦可為合金半導體，其包SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP或上述組合。
基底50具有第一區50B及第二區50C。第一區50B(對應到後續圖式名稱最後標示為“B”的圖式)可用來形成n型裝置，例如為NMOS電晶體，NMOS電晶體可例如為n型鰭式場 效電晶體。第二區50C(對應到後續圖式名稱最後標示為“C”的圖式)可用來形成p型裝置，例如為PMOS電晶體，PMOS例如為p型鰭式場效電晶體。
第3-4圖繪示形成鰭片52及位於相鄰兩個鰭片52之間的隔離區54。在第3圖，鰭片52形成在基底50內。在一些實施例，可藉由在基底50內蝕刻出溝槽，以形成鰭片52。蝕刻可使用任何適合的蝕刻製程，例如反應離子蝕刻(reactive ion etch,RIE)、中子束蝕刻(neutral beam etch,NBE)，類似的製程或上述組合。上述蝕刻可為非等向性。
在第4圖，在相鄰的兩個鰭片52之間形成絕緣材料54，以形成隔離區54。絕緣材料54可為氧化物，例如氧化矽及/或含碳氧化物、氮化物、類似材料或上述組合，且可藉由高密度電漿化學氣相沉積(high density plasma chemical vapor deposition,HDP-CVD)、流動式化學氣相沉積(flowable chemical vapor deposition,FCVD)(例如，以遠距電漿系統執行以化學氣相沉積為主的材料沉積，以及執行後硬化讓材料轉變成其他的材料，例如氧化物)、旋轉塗布、類似方法或上述組合。可使用任意適合的方法形成其他的絕緣材料。形成絕緣材料後，可執行退火製程。在所繪示的實施例中，絕緣材料54是由流動式化學氣相沉積製程所形成的氧化矽。絕緣材料54亦可稱為隔離區54。此外，在第4圖中，可執行平坦化製程，例如為化學機械研磨(chemical mechanical polish,CMP)以移除多餘的絕緣材料54，而形成共平面的隔離區54的上表面及鰭片52的上表面。
第5圖繪示產生隔離區54的凹陷，以形成淺溝槽隔離(Shallow Trench Isolation,STI)區54。讓隔離區54產生凹陷，使得第一區50B和第二區50C的鰭片56在相鄰的兩個隔離區54之間凸出。此外，隔離區54的上表面可以是如圖式所繪示的平坦表面、或是凸面的表面、凹面的表面(例如為碟形)或上述組合。可藉由適合的蝕刻而形成平坦、凸面或凹面的隔離區54的上表面。可使用適合蝕刻製程形成隔離區54的凹陷，例如對隔離區54的材料具有選擇性的蝕刻製程。例如，可使用CERTAS®蝕刻、應用材料(Applied Materials)SICONI機台或稀釋氫氟酸(dHF)移除化學氧化物。
所屬技術領域中具有通常知識者可瞭解在第2-5圖描述的製程僅僅只是如何形成鰭片56的一個示例。在一些實施例，介電層形成在基底50的上表面；蝕刻而產生穿透介電層的溝槽；在溝槽內進行磊晶成長，以形成同質磊晶結構；以及產生介電層的凹陷，使得同質磊晶結構凸出於介電層，而產生鰭片。在其他的實施例，使用異質磊晶結構形成鰭片。例如，在第4圖所示的半導體條狀物52(或鰭片)產生凹陷，且在此凹陷處磊晶成長與半導體條狀物52不同的材料。
在其他一些實施例，在基底50的上表面形成介電層；蝕刻而產生穿透介電層的溝槽；使用與基底50不同的材料，在溝槽內進行磊晶成長，以形成異質磊晶結構；以及使介電層產生凹陷，使得異質磊晶結構凸出於介電層，而產生鰭片56。
在一些實施例，在同質磊晶或異質磊晶結構設置 處，經由執行磊晶成長而形成同質磊晶或異質磊晶結構，成長材料可在生成過程中使用原位(in situ)摻雜，如此可免除在此之前與之後的佈植製程，但也可一起使用原位及佈植摻雜。此外，在NMOS區磊晶成長與PMOS區不同的材料是有利的。在各種不同的實施例，鰭片56可包含矽鍺(SixGe1-x，其中x介於約0-1之間)、碳化矽、純鍺或大致上為純的鍺、三五族化合物半導體、二四族化合物半導體或類似材料。例如，可用來形成三五族化合物半導體材料包含InAs、AlAs、GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlP、GaP及類似材料，但不限於此。
在第5圖，可在鰭片56、鰭片52及/或基底50內形成適合的井區。例如，可在第一區50B形成P型井區，並在第二區50C形成N型井區。
可使用光阻或其他的遮罩(未繪示)達到在不同的區域50B和50C進行不同的佈植步驟。例如，在第一區50B的鰭片56和隔離區54上形成光阻。圖案化光阻以露出基底50的第二區50C，例如為PMOS區。光阻可藉由旋轉技術形成，且可藉由適合的微影技術圖案化。圖案化光阻後，將n型雜質摻雜至第二區50C，另外，光阻可作為遮罩來實質上避免n型雜質摻植入第一區50B，例如NMOS區。可將n型雜質，例如磷、砷或類似的摻雜質佈植在第二區50C，且使其濃度等於或小於1018cm-3(例如介於約1017cm-3至約1018cm-3的範圍)。佈植後，使用例如為適合的灰化製程移除光阻。
第二區50C佈植後，在第二區50C的鰭片56和隔離 區54上形成光阻。圖案化光阻以露出基底50的第一區50B。光阻可藉由旋轉技術形成，且可藉由適合的微影技術圖案化。圖案化光阻後，將p型雜質摻雜至第一區50B，另外，光阻可作為遮罩來實質上避免p型雜質摻植入第二區50C，例如PMOS區。可將p型雜質，例如硼、二氟化硼或類似的摻雜質佈植在第一區50B，且使其濃度等於或小於1018cm-3(例如介於約1017cm-3至約1018cm-3的範圍)。佈植後，使用例如為適合的灰化製程移除光阻。
在第一區50B及第二區50C佈植後，可執行退火以活化植入的p型及n型雜質。可在第一區50B(例如為NMOS區)佈植以形成p型井區，在第二區50C(例如為PMOS區)形成n型井區。在一些實施例，磊晶鰭片的成長材料可在生成過程中使用原位(in situ)摻雜，如此可免除在此之前與之後的佈植製程，但也可一起使用原位及佈植摻雜。
在第6圖，形成虛置介電層58於鰭片56上。虛置介電層58可例如為氧化矽、氮化矽、上述組合或類似材料，且可依據適合的技術來沉積或熱生成。虛置閘極層60形成在虛置介電層58上，且遮罩層62形成在虛置閘極層60上。虛置閘極層60可沉積在虛置介電層58上，並經由例如化學機械研磨製程、回蝕刻製程或上述組合平坦化。遮罩層62可沉積於虛置閘極層60上。虛置閘極層60可由多晶矽或非晶矽製成，也可使用其他相較於蝕刻隔離區54具有高蝕刻選擇比的材料。遮罩層62可包含例如氧化矽、氮化矽或類似材料。在此示例，形成越過第一區50B和第二區50C的單一虛置閘極層60和單一遮罩層62。在其他 實施例，可在第一區50B和第二區50C形成分隔的虛置閘極層，且可在第一區50B和第二區50C形成分隔的遮罩層。
在第7A、7B及7C圖中，可藉由適合的微影和蝕刻技術圖案化遮罩層62，以在第一區50B形成遮罩72(如第7B圖所繪示)，在第二區50C形成遮罩78(如第7C圖所繪示)。可藉由適合的蝕刻技術，將遮罩72和遮罩78的圖案轉移至虛置閘極層60及虛置介電層58，以在第一區50B形成虛置閘極70，在第二區50C形成虛置閘極76。虛置閘極70及虛置閘極76覆蓋個別的鰭片56的通道區。虛置閘極70及虛置閘極76可具有縱長方向(或延伸方向)，其垂直於個別的磊晶鰭片的縱長方向(或延伸方向)。
在第8A、8B及8C圖中，可個別在虛置閘極70及虛置閘極76及/或鰭片56所露出的表面形成閘極密封間隙物80。可在熱氧化及沉積後，執行非等向性蝕刻形成閘極密封間隙物80。
形成閘極密封間隙物80後，可執行佈植以形成輕摻雜源極/汲極區(lightly doped drain,LDD)。在第17圖探討與此相似的佈植，可在第一區50B(例如為NMOS區)上形成遮罩(例如為光阻)，以露出第二區50C(例如為PMOS區)，並可將p型雜質佈植至第二區50C露出的鰭片56上。之後，可移除遮罩。接下來，可在第二區50C上形成遮罩(例如為光阻)，以露出第一區50B，並可將n型雜質佈植至第一區50B露出的鰭片56上。之後，可移除遮罩。n型雜質可為任何先前所述的n型雜質，且p型雜質可為任何先前所述的p型雜質。輕摻雜源極/汲極區可 具有濃度約介於1015cm-3至約1016cm-3範圍間的雜質。可使用退火以活化經佈植的雜質。
此外，在第8A、8B及8C圖中，磊晶源極/汲極區82及磊晶源極/汲極區84形成在鰭片56內。在第一區50B，磊晶源極/汲極區82形成在鰭片56內，使得每一個虛置閘極70設置在個別相鄰的一對磊晶源極/汲極區82之間。在一些實施例，磊晶源極/汲極區82可延伸至鰭片52。在第二區50C，磊晶源極/汲極區84形成在鰭片56內，使得每一個虛置閘極76設置在個別相鄰的一對磊晶源極/汲極區84之間。在一些實施例，磊晶源極/汲極區84可延伸至鰭片52。
第一區50B(例如NMOS區)的磊晶源極/汲極區82可藉由下述方法形成：在第二區50C(例如PMOS區)形成遮罩，並在第一區50B共形沉積虛置間隙物層，之後執行非等向性蝕刻，並在第一區50B沿著虛置閘極70及/或閘極密封間隙物80的側壁形成虛置閘極間隙物(未繪示)。之後，蝕刻第一區50B的磊晶鰭片的源極/汲極區，以產生凹陷，在第一區50B凹陷內磊晶成長而形成磊晶源極/汲極區82。磊晶源極/汲極區82可包含任意適合的材料，例如適用於n型鰭式場效電晶體。例如，當鰭片56為矽時，磊晶源極/汲極區82可包含矽、SiC、SiCP、SiP或類似材料。磊晶源極/汲極區82可具有由個別的鰭片56表面凸起的表面，且可具有刻面。接下來，例如藉由蝕刻來移除第一區50B的虛置閘極間隙物以及第二區50C上的遮罩。
第二區50C(例如PMOS區)的磊晶源極/汲極區84可藉由下述方法形成：在第一區50B(例如NMOS區)形成遮罩，並 在第二區50C共形沉積虛置間隙物層，之後執行非等向性蝕刻，並在第二區50C沿著虛置閘極76及/或閘極密封間隙物80的側壁形成虛置閘極間隙物(未繪示)。之後，蝕刻第二區50C的磊晶鰭片的源極/汲極區，以產生凹陷，在第二區50C的凹陷內磊晶成長而形成磊晶源極/汲極區84。磊晶源極/汲極區84可包含任意適合的材料，例如適用於p型鰭式場效電晶體。例如，當鰭片56為矽時，磊晶源極/汲極區84可包含SiGe、SiGeB、Ge、GeSn或類似材料。磊晶源極/汲極區84可具有由個別的鰭片56表面凸起的表面，且可具有刻面。接下來，例如藉由蝕刻來移除第二區50C的虛置閘極間隙物以及第一區50B上的遮罩。
在第9A、9B及9C圖中，在閘極密封間隙物80上，沿著虛置閘極70和虛置閘極76側壁形成閘極間隙物86。閘極間隙物86可藉由共形沉積一材料後，執行非等向性蝕刻此材料而形成。閘極間隙物86的材料可為氮化矽、SiCN、含碳氧化矽、上述組合或類似的材料。閘極間隙物86亦可沿遮罩72及遮罩78的側壁往上延伸。
可將摻雜質佈植至磊晶源極/汲極區82及磊晶源極/汲極區84及/或磊晶鰭片，以形成源極/汲極區，與上述的形成輕摻雜源極/汲極區的製程相似，接下來執行退火。源極/汲極區可具有濃度介於約1019cm-3至約1021cm-3範圍間的雜質。在第一區50B(例如NMOS區)的源極/汲極區摻雜n型雜質，可為任意先前所述的n型雜質，在第二區50C(例如PMOS區)的源極/汲極區摻雜p型雜質，可為任意先前所述的p型雜質。在其他實施例，磊晶源極/汲極區82及磊晶源極/汲極區84可在生成過程 中，使用原位摻雜。
在第10A、10B及10C圖，在第9A、9B及9C圖所繪示的結構上沉積層間介電層88。在一實施例，層間介電層88是藉由流動式化學氣相沉積形成的可流動的薄膜。在一些實施例，層間介電層88由介電材料形成，例如磷酸矽酸鹽玻璃(Phospho-Silicate Glass,PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass,BSG)、硼摻雜磷酸矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass,BPSG)、未摻雜的矽酸鹽玻璃(undoped Silicate Glass,USG)或類似材料，且可藉由任意適合的方法沉積，例如化學氣相沉積、旋轉塗佈、電漿增強化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)或上述組合。
在第11A、11B及11C圖，可執行平坦化製程(例如化學機械研磨)使得層間介電層88的上表面與虛置閘極70和虛置閘極76的上表面齊平。化學機械研磨也可移除虛置閘極70和虛置閘極76上的遮罩72及遮罩78。因此，虛置閘極70及虛置閘極76的上表面由層間介電層88所露出。
在第12A、12B及12C圖，以蝕刻步驟移除虛置閘極70、虛置閘極76、閘極密封間隙物80及位於虛置閘極70和虛置閘極76正下方的虛置介電層58的部份，以形成凹陷90。每一個凹陷90露出個別的鰭片56的通道區。每一個通道區設置在相鄰的一對磊晶源極/汲極區82及84之間。在移除的過程中，當蝕刻虛置閘極70及虛置閘極76時，虛置介電層58可作為蝕刻停止層。移除虛置閘極70和虛置閘極76後，可移除虛置介電層58及 閘極密封間隙物80。
在第13A、13B及13C圖，形成閘極介電層92、閘極介電層96、閘極電極94及閘極電極98來得到替代閘極。閘極介電層92及閘極介電層96共形沉積於凹陷90內，例如鰭片56的上表面和側壁、閘極間隙物86的側壁及層間介電層88的上表面。根據一些實施例，閘極介電層92及閘極介電層96包含氧化矽、氮化矽或上述多重層。在其他實施例，閘極介電層92及閘極介電層96包含高介電常數(high-k)介電材料，且在這些實施例，閘極介電層92及閘極介電層96可具有大於約7.0的k值，且可包含金屬氧化物或Hf、Al、Zr、La、Mg、Ba、Ti、Pb及上述組合的矽化物。閘極介電層92及閘極介電層96的形成方法可包含分子束沉積(Molecular-Beam Deposition,MBD)、原子層沉積(Atomic Layer Deposition,ALD)、電漿增強化學氣相沉積或類似方法。
接下來，個別在閘極介電層92和閘極介電層96上沉積閘極電極94及閘極電極98，且填充凹陷90剩餘的部份。閘極電極94及閘極電極98可由含金屬材料形成，例如TiN、TaN、TaC、Co、Ru、Al、W、上述組合或上述多重層。填充閘極電極94及閘極電極98後，可執行平坦化製程(例如化學機械研磨)，以移除閘極介電層92及閘極介電層96多餘的部份和閘極電極94及閘極電極98超出層間介電層88的上表面的部份的材料。之後，留下來的閘極電極94、閘極電極98、閘極介電層92及閘極介電層96的部份之材料因而形成了鰭式場效電晶體的替代閘極。
可同時形成閘極介電層92及閘極介電層96使得閘極介電層92及閘極介電層96由相同材料形成，可同時形成閘極電極94及閘極電極98使得閘極電極94及閘極電極98由相同材料形成。然而，在其他實施例，閘極介電層92及閘極介電層96由不同製程形成，使得閘極介電層92及閘極介電層96由不同材料形成，且閘極電極94及閘極電極98由不同製程形成，使得閘極電極94及閘極電極98由不同材料形成。當使用不同的製程時，可使用不同的遮罩步驟以遮蓋和露出適合的區域。
在第14A、14B及14C圖，以蝕刻步驟使得閘極介電層92、閘極介電層96、閘極電極94及閘極電極98產生凹陷，以形成凹陷100及凹陷102。蝕刻步驟可包含非等向性乾蝕刻。例如，蝕刻步驟可包含使用反應氣體的乾蝕刻製程，其選擇性地蝕刻閘極介電層92、閘極介電層96、閘極電極94及閘極電極98，而不蝕刻層間介電層88或閘極間隙物86。
在第15A、15B及15C圖，個別在凹陷100及凹陷102內以及閘極介電層92、閘極介電層96、閘極電極94及閘極電極98上方形成遮罩104及遮罩106。在之後的自我對準接觸物蝕刻步驟，遮罩104及遮罩106給予閘極間隙物86保護，確保自我對準接觸物不讓閘極電極94及閘極電極98之一與相應的源極/汲極區82及84上方的接觸物產生短路。遮罩104及遮罩106可包含例如氮化矽或類似材料。遮罩104及遮罩106的材料組成可確保較高的膜密度及非揮發性之蝕刻副產物。遮罩104及遮罩106可藉由形成化學氣相沉積、物理氣相沉積(physical vapor deposition,PVD)、原子層沉積、介電質上旋轉塗佈 (spin-on-dielectric)製程，類似方法或上述組合。形成遮罩104及遮罩106後，可執行化學機械研磨使得遮罩104及遮罩106的上表面與層間介電層88和閘極間隙物86齊平。
在第16A、16B及16C圖，形成穿透層間介電層88的開口108及開口110，以個別露出部份的源極/汲極區82及84。開口108及開口110可同時由相同的製程形成，或分別用不同的製程形成。開口108及開口110可使用適合的微影和蝕刻技術形成。
在第17A、17B及17C圖，個別在開口108及開口110內形成導電接觸物112及導電接觸物114。襯層(未繪示，例如擴散阻障層、黏著層或類似的層)和傳導材料形成在開口108及開口110內。襯層可包含鈦、氮化鈦、鉭、氮化鉭或類似材料。傳導材料可為銅、銅合金、銀、金、鎢、鋁、鎳、鈷或類似材料。可執行平坦化製程(例如為化學機械研磨)，以移除超出層間介電層88的表面的材料。剩餘的襯層及傳導材料在開口內形成導電接觸物112及導電接觸物114。可執行退火製程，個別在磊晶的源極/汲極區82和導電接觸物112之間的界面，以及在磊晶的源極/汲極區84和導電接觸物114之間的界面產生矽化物。接觸物112物理且電性耦接至磊晶的源極/汲極區82，而導電接觸物114物理且電性耦接至磊晶的源極/汲極區84。
在第18A、18B及18C圖，以蝕刻步驟使得導電接觸物112及導電接觸物114產生凹陷，以形成凹陷116和凹陷118。蝕刻步驟可包含非等向性乾蝕刻或等向性蝕刻。例如，蝕刻步驟可包含使用含鹵素為主的反應氣體之乾蝕刻製程，使其選擇 性地蝕刻導電接觸物112及導電接觸物114，而不蝕刻層間介電層88、遮罩104或遮罩106。
在第19A、19B及19C圖，個別在凹陷116及凹陷118內，並在導電接觸物112及導電接觸物114上方形成遮罩120及遮罩122。之後在閘極電極94及閘極電極98上方形成接觸物的過程中，遮罩120及遮罩122給予導電接觸物112及導電接觸物114保護，確保接觸物不與源極/汲極區82及84上方的導電接觸物112及導電接觸物114產生短路。遮罩120及遮罩122可包含例如氮化矽、碳氧化矽(silicon oxycarbide,SiOC)、碳化矽、類似材料或上述組合。遮罩120及遮罩122的材料組成可確保較高的膜密度及非揮發性之蝕刻副產物。遮罩120及遮罩122可藉由任意適合的方法形成，例如化學氣相沉積，其包含電漿增強化學氣相沉積，或介電質上旋轉塗佈製程。在一些實施例，電漿增強化學氣相沉積製程的電漿源可為遠端電漿系統。在一些實施例，電漿源可為感應耦合電漿(inductively coupled plasma,ICP)或類似的電漿。
在一些實施例，使用含有自由基(例如，包含於第一反應源)電漿成分及未激發成分(例如，包含於第二反應源)的組合形成遮罩120及遮罩122，並且，以第一反應源為H2、O2、類似氣體或上述組合，第二反應源為包含矽氧烷源及稀釋源，稀釋源為He、類似氣體或上述組合的情況下沉積遮罩120及遮罩122。在一些實施例，製程溫度介於約200℃至約500℃的範圍間，在製程期間的壓力介於約1Torr至約10Torr的範圍間。在一些實施例，遠距電漿源使用功率介於約1000Watts至約 4000Watts的範圍間的射頻或微波。在一些實施例，第一反應源包含H2，其流量介於約500cm3/min(sccm)至約25000sccm的範圍間，第一反應源亦包含O2，其流量介於約0sccm至約20sccm的範圍間，第二反應源(例如矽氧烷源)的流量介於約1sccm至約30sccm的範圍間。
形成遮罩120及遮罩122後，可執行化學機械研磨，使得遮罩120、遮罩122、遮罩104、遮罩106、層間介電層88的上表面與閘極間隙物86齊平。
在第20A、20B及20C圖，形成個別穿透遮罩120、遮罩122、遮罩104及遮罩106的導電接觸物126、導電接觸物128、導電接觸物130及導電接觸物132。用來形成導電接觸物126及導電接觸物128的開口個別穿透遮罩120及遮罩122。用來形成接觸物130及接觸物132的開口個別穿透遮罩104及遮罩106。這些開口可同時用相同製程形成，或用分開的製程形成。上述開口可使用適合的微影和蝕刻技術形成。襯層(例如擴散阻障層、黏著層或類似的層)和傳導材料形成在開口內。襯層可包含鈦、氮化鈦、鉭、氮化鉭或類似材料。傳導材料可為銅、銅合金、銀、金、鎢、鋁、鎳、鈷或類似材料。可執行平坦化製程(例如為化學機械研磨)，以移除超出層間介電層88及遮罩表面的材料。剩餘的襯層及傳導材料在開口內形成接觸物126、接觸物128、接觸物130及接觸物132。導電接觸物126物理且電性耦接至導電接觸物112，導電接觸物128物理且電性耦接至導電接觸物114，導電接觸物130物理且電性耦接至閘極電極94，且導電接觸物132物理且電性耦接至閘極電極98。
在此實施例，先形成位於閘極電極上方的遮罩104及遮罩106，再形成位於源極/汲極接觸物上方的遮罩120及遮罩122。但在其他實施例，可改變順序，先形成遮罩120及遮罩122。在其他實施例，遮罩104及遮罩106形成在源極/汲極接觸物上方，且遮罩120及遮罩122形成在閘極電極上方。
雖然未清楚的繪示，所屬技術領域中具有通常知識者可瞭解能在第20A、20B及20C圖所示的結構執行額外的製程步驟。例如，可在層間介電層88上方形成金屬層間介電層及其對應的金屬層。
第21A-21C及22A-22C圖是根據一些實施例，形成鰭式場效電晶體中間各階段的製程剖面圖。第21A-21C及22A-22C圖的實施例與第2-20圖所繪示的實施例相似，除了此實施例包含位於源極/汲極接觸物112、114與遮罩120、122之間的絕緣襯層。到第21A-21C圖為止，中間結構的材料和製程可與上述第1-18圖所述的實施例相似，在此不再重複敘述。關於這些實施例的細節與先前所述實施例的細節相似，在此不再重複敘述。
第21A、21B及21C圖，絕緣襯層136及絕緣襯層138形成在第18A、18B及18C圖所繪示的結構上方，且位於凹陷116及凹陷118內，以及源極/汲極接觸物112及源極/汲極接觸物114上方。在一些實施例，絕緣襯層136及絕緣襯層138可為金屬氧化物或金屬氮化物，其包含鋁、鈦、鉿、鋯、鉭、不同金屬的組成、類似材料或上述組合，且可藉由原子層沉積、化學氣相沉積、類似方法或上述組合形成。
在一些實施例，用來形成絕緣襯層136及絕緣襯層138的原子層沉積製程包含在原子層沉積製程前的電漿製程，其包含含氫源，例如H2、NH3、類似材料或上述組合。電漿的好處在於能清潔表面，並移除自然生成氧化層以促進黏著能力。電漿的壓力介於約1Torr至約10Torr的範圍間，電漿的功率介於約100Watts至約1500Watts的範圍間。
在一些實施例，形成絕緣襯層136及絕緣襯層138可包含電漿製程的後處理，其包含以氫為主的化學物質，例如H2、NH3、類似材料或上述組合。後處理的好處在於能藉由移除雜質(例如有機源)，而使薄膜密實。後處理的壓力介於約1Torr至約10Torr的範圍間，後處理的功率介於約100Watts至約1500Watts的範圍間。
在一些實施例，在一些實施例，原子層沉積製程包含以金屬源作為第一反應源，其流量介於約10sccm至約300sccm的範圍間；以及以含氮源作為第二反應源，其流量介於約1000sccm至約10000sccm的範圍間。在這些實施例，原子層沉積製程的溫度介於約200℃至約400℃的範圍間，且壓力介於約1Torr至約10Torr的範圍間。
形成絕緣襯層136及絕緣襯層138後，可移除超出層間介電層88、遮罩104及遮罩106的上表面多餘的絕緣襯層136及絕緣襯層138。
在第22A、22B及22C圖，形成個別穿越遮罩120、遮罩122、遮罩104及遮罩106的導電接觸物126、導電接觸物128、導電接觸物130及導電接觸物132。用來形成導電接觸物 126及導電接觸物128的開口個別穿透遮罩120和絕緣襯層136，以及穿透遮罩122和絕緣襯層138。用來形成接觸物130及接觸物132的開口個別穿越遮罩104及遮罩106。這些開口可同時用相同製程形成，或用分開的製程形成。上述開口可使用適合的微影和蝕刻技術形成。襯層(例如擴散阻障層、黏著層或類似的層)和傳導材料形成在開口內。襯層可包含鈦、氮化鈦、鉭、氮化鉭或類似材料。傳導材料可為銅、銅合金、銀、金、鎢、鋁、鎳、鈷或類似材料。可執行平坦化製程(例如為化學機械研磨)，以移除超出層間介電層88及遮罩表面的材料。剩餘的襯層及傳導材料在開口內形成接觸物126、接觸物128、接觸物130及接觸物132。導電接觸物126物理且電性耦接至導電接觸物112，導電接觸物128物理且電性耦接至導電接觸物114，導電接觸物130物理且電性耦接至閘極電極94，且導電接觸物132物理且電性耦接至閘極電極98。
在此實施例，先形成位於閘極電極上方的遮罩104及遮罩106，再形成位於源極/汲極接觸物上方的遮罩120及遮罩122。但在其他實施例，可改變順序，先形成遮罩120及遮罩122。在其他實施例，遮罩104及遮罩106形成在源極/汲極接觸物上方，且遮罩120及遮罩122形成在閘極電極上方。
雖然未清楚的繪示，所屬技術領域中具有通常知識者可瞭解能在第22A、22B及22C圖所示的結構執行額外的製程步驟。例如，可在層間介電層88上方形成金屬層間介電層及其對應的金屬層。
在其他一些實施例，用來形成鰭式場效電晶體的 導電接觸物可用替代接觸物技術形成。替代接觸物藉由先形成虛置接觸物，再以導電接觸物取代虛置接觸物而形成。虛置接觸物可藉由將替代接觸物圖案經由三層微影傳遞至虛置接觸物材料而形成，其包含圖案化虛置接觸物材料上的遮罩層，之後在遮罩層的頂部形成光阻。可在之後的步驟使用乾蝕刻製程移除部份的虛置接觸物，並形成層間介電層，圍繞剩餘的虛置接觸物。
藉由在閘極電極和源極/汲極接觸物上提供自我對準遮罩，在形成穿孔至閘極電極及/或源極/汲極接觸物時，可降低閘極電極與源極/汲極接觸物之間的電性短路/漏電的機率。此外，這些位於閘極電極和源極/汲極接觸物兩者上方的自我對準遮罩允許縮短閘極電極的佈局，讓閘極電極上方的穿孔能更接近源極/汲極接觸物上方的穿孔。這些位於閘極電極和源極/汲極接觸物的遮罩確保即使穿孔錯位時，上方的穿孔不使閘極電極與源極/汲極接觸物之間產生短路。
根據本發明一些實施例，提供一種半導體結構的製造方法。上述方法包含凹蝕基底上的半導體鰭片上的閘極電極，以從介電層的上表面形成第一凹陷。上述方法包含形成第一遮罩於凹蝕的閘極電極上的第一凹陷內。上述方法亦包含凹蝕半導體鰭片的源極/汲極區上的第一導電接觸物，以從介電層的上表面形成第二凹陷。上述方法更包含形成第二遮罩於凹蝕的第一導電接觸物上的第二凹陷內。
根據本發明一些實施例，提供一種半導體結構的製造方法。上述方法包含形成鰭片於基底上及形成環繞鰭片的 隔離區。上述方法包含形成虛置閘極結構於鰭片上及磊晶成長源極/汲極區於虛置閘極結構的相對兩側。上述方法包含形成層間介電層於隔離區上，層間介電層且環繞該虛置閘極結構。上述方法亦包含以主動閘極結構取代該虛置閘極結構，並凹蝕主動閘極結構，以形成第一凹陷。上述方法亦包含形成第一遮罩於第一凹陷內，並形成穿過層間介電層的第一導電接觸物，耦接至源極/汲極區。上述方法更包含凹蝕第一導電接觸物，以形成第二凹陷，及形成第二遮罩於第二凹陷內。
根據本發明一些實施例，提供一種半導體結構。上述結構包含設置於基底上的第一鰭片，及環繞第一鰭片的下表面的隔離區。上述結構包含沿第一鰭片的側壁及上表面設置的閘極結構及設置於第一鰭片上的源極/汲極區，其鄰接於閘極結構。上述結構亦包含設置於隔離區上的介電層，其環繞閘極結構，及包含設置於閘極結構上的第一遮罩，第一遮罩具有上表面，與介電層的上表面齊平。上述結構更包含穿過介電層，並接觸源極/汲極區的第一導電接觸物，並包含設置於第一導電接觸物上的第二遮罩，第二遮罩具有上表面，其與介電層的上表面齊平。
以上敘述許多實施例的特徵，使所屬技術領域中具有通常知識者能夠清楚理解本揭示的概念。所屬技術領域中具有通常知識者能夠理解，其可利用本發明揭示內容作為基礎，以設計或更動其他製程及結構而完成相同於上述實施例的目的及/或達到相同於上述實施例的優點。所屬技術領域中具有通常知識者亦能夠理解，不脫離本揭示之精神和範圍的等效構造可在不脫離本揭示之精神和範圍內作各種之更動、替代與潤飾。

Claims (11)

  1. 一種半導體結構的製造方法，包括：凹蝕一閘極電極，其位於一基底上的一半導體鰭片上，使得該閘極電極的一上表面上形成一第一凹陷；形成一第一遮罩於該凹蝕的閘極電極上的該第一凹陷內；凹蝕一第一導電接觸物，其位於該半導體鰭片的一源極/汲極區上，使該第一導電接觸物的一上表面上形成一第二凹陷；以及形成一第二遮罩於該凹蝕的第一導電接觸物上的該第二凹陷內。
  2. 如申請專利範圍第1項所述之方法，其中在形成該第二凹陷之前或之後，形成該第一凹陷。
  3. 如申請專利範圍第1或2項所述之方法，更包括：形成一絕緣襯層於該第二凹陷內，該絕緣襯層位於該第一導電接觸物與該第二遮罩間。
  4. 如申請專利範圍第3項所述之方法，其中該絕緣襯層為包括鋁、鈦、鉿、鋯、鉭、上述組合的金屬氧化物或金屬氮化物，且其中該第二遮罩包括氮氧化矽、碳化矽、含碳的氧化矽或上述組合。
  5. 如申請專利範圍第1或2項所述之方法，更包括：形成一介電層於該基底的該半導體鰭片上，其中該介電層環繞該閘極電極及該第一導電接觸物；形成穿過該第一遮罩的一第二導電接觸物，其耦接至該閘極電極；以及形成穿過該第二遮罩的一第三導電接觸物，其電性耦接至該第一導電接觸物。
  6. 如申請專利範圍第5項所述之方法，其中該介電層、該第二導電接觸物及該第三導電接觸物的上表面齊平。
  7. 如申請專利範圍第1或2項所述之方法，更包括：形成一虛置閘極結構於該半導體鰭片上；形成一閘極間隙物於該虛置閘極結構的側壁上；形成環繞該閘極間隙物及該虛置閘極結構的該介電層；以及以一主動閘極結構取代該虛置閘極結構，該主動閘極結構包括位於該半導體鰭片上的一閘極介電層，及位於該閘極介電層上的該閘極電極。
  8. 一種半導體結構，包括：一第一鰭片，設置於一基底上；一隔離區，環繞該第一鰭片的下表面；一閘極結構，沿該第一鰭片的側壁及上表面設置；一源極/汲極區，設置於該第一鰭片上，且鄰接於該閘極結構；一介電層，設置於該隔離區上，且環繞該閘極結構；一第一遮罩，設置於該閘極結構上，該第一遮罩具有一上表面，其與該介電層的一上表面齊平；一第一導電接觸物，穿過該介電層以接觸該源極/汲極區；以及一第二遮罩，設置於該第一導電接觸物上，該第二遮罩具有一上表面，其與該介電層的該上表面齊平。
  9. 如申請專利範圍第8項所述之半導體結構，更包括：一絕緣襯層，該絕緣襯層位於該第一導電接觸物與該第二遮罩之間。
  10. 如申請專利範圍第8或9項所述之半導體結構，其中該第一遮罩的材料組成與該第二遮罩的材料組成不同。
  11. 如申請專利範圍第8或9項所述之半導體結構，其中該第一遮罩包括氮化矽、且其中該第二遮罩包括氮氧化矽、碳化矽或上述組合。
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