TW202109680A - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TW202109680A
TW202109680A TW109129472A TW109129472A TW202109680A TW 202109680 A TW202109680 A TW 202109680A TW 109129472 A TW109129472 A TW 109129472A TW 109129472 A TW109129472 A TW 109129472A TW 202109680 A TW202109680 A TW 202109680A
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dielectric layer
region
layer
air gap
interlayer dielectric
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TW109129472A
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TWI755831B (zh
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劉書豪
陳國儒
李凱璿
翁翊軒
楊正宇
陳亮吟
張惠政
育佳 楊
章勳明
周孟翰
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台灣積體電路製造股份有限公司
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Priority claimed from US16/879,894 external-priority patent/US11456383B2/en
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Abstract

一種半導體裝置，包括延伸自半導體基底的鰭片；於鰭片上的閘極堆疊；於閘極堆疊的側壁上的第一間隔物；在鄰近於第一間隔物的鰭片中的源極／汲極區；延伸至閘極堆疊、第一間隔物以及源極／汲極區上方的層間介電質(ILD)層，此層間介電質層包括第一部分以及第二部分，其中層間介電質層的第二部分比層間介電質的第一部分更靠近閘極堆疊；延伸穿過層間介電質層，並且接觸源極／汲極區的接觸插塞；於接觸插塞的側壁上的第二間隔物；以及於第一間隔物與第二間隔物之間的氣隙，其中層間介電質層的第一部分延伸跨過氣隙，並且實體接觸第二間隔物，其中層間介電質層的第一部分將氣隙密封。

Description

半導體裝置及其形成方法
本發明實施例是關於半導體技術，特別是關於一種鰭式場效電晶體及其形成方法。
半導體裝置被用於各種電子應用，例如個人電腦、行動電話、數位相機以及其他電子設備。通常藉由依序地在半導體基板上沉積材料的絕緣層或介電質層、導電層、以及半導體層，並利用微影製程圖案化各種材料層以形成電路組件及元件來製造半導體裝置。
半導體產業透過不斷縮小最小特徵尺寸(minimum feature size)來持續提升各種電子組件（例如：電晶體、二極體、電阻器、電容器等等）的積集度(integration density)，其允許在一給定面積內整合更多的部件。然而，隨著最小特徵尺寸的縮小，應解決的額外問題也隨之出現。
本發明實施例提供一種半導體裝置，包括延伸自半導體基底的鰭片；於鰭片上的閘極堆疊；於閘極堆疊的側壁上的第一間隔物；在鄰近於第一間隔物的鰭片中的源極／汲極區；延伸至閘極堆疊、第一間隔物以及源極／汲極區上方的層間介電質(ILD)層，此層間介電質層包括第一部分以及第二部分，其中層間介電質層的第二部分比層間介電質的第一部分更靠近閘極堆疊；延伸穿過層間介電質層，並且接觸源極／汲極區的接觸插塞；於接觸插塞的側壁上的第二間隔物；以及於第一間隔物與第二間隔物之間的氣隙，其中層間介電質層的第一部分延伸跨過氣隙，並且實體接觸第二間隔物，其中層間介電質層的第一部分將氣隙密封。
本發明實施例提供一種半導體裝置，包括從基板突出的鰭片；於鰭片的通道區上的閘極結構；在鄰近於通道區的鰭片中的磊晶區；於閘極結構上的第一介電質層，此第一介電質層包括以第一摻質摻雜的第一區域；延伸穿過第一介電質層，且接觸磊晶區的接觸插塞；於第一介電質層上的第二介電質層；以及於接觸插塞與閘極結構之間的氣隙，其中氣隙的上部區以第一區域為邊界，並且其中氣隙藉由第一區域與第二介電質層分離。
本發明實施例提供一種半導體裝置形成方法，包括形成閘極堆疊於半導體鰭片上，且形成磊晶源極／汲極區於鄰近於閘極堆疊的半導體鰭片中。沉積第一介電質層於閘極堆疊上，且於磊晶源極／汲極區上。形成開口於第一介電質層中，以露出磊晶源極／汲極區，且沉積犧牲材料於開口中。沉積導電材料於開口中的犧牲材料上，之後移除犧牲材料以形成凹槽。以及，以摻質佈植第一介電質層，在佈植第一介電質層之後，凹槽被第一介電質層覆蓋。
以下發明實施例提供了許多不同的實施例或範例，用於實施本發明之不同特徵。各部件和其配置的具體範例描述如下，以簡化本發明實施例之說明。當然，這些僅僅是範例，並非用以限制。舉例而言，敘述中若提及第一部件形成在第二部件之上或上，可能包含所形成的第一和第二部件為直接接觸的實施例，也可能包含額外的部件形成在第一和第二部件之間，使得它們不直接接觸的實施例。此外，本發明實施例可能在不同的範例中重複參考數字及∕或字母。如此重複是為了簡明和清楚，而非用以表示所討論的不同實施例及∕或配置之間的關係。
再者，其中可能用到與空間相對用詞，例如「在……之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞，是為了便於描述圖式中一個（些）部件或特徵與另一個（些）部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（旋轉90度或其他方位），其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
根據一些實施例，形成氣隙圍繞鰭式場效電晶體裝置的源極／汲極磊晶區的接觸件。氣隙的低介電常數（k值）可減少鰭式場效電晶體裝置的閘極堆疊與接觸件之間的電容值(capacitance)，其可改善鰭式場效電晶體裝置的高速（例如：交流電(AC)）操作。在一些實施例中，執行佈植製程以在相鄰的層間介電質(ILD)層中佈植摻質，導致層間介電質層膨脹且密封氣隙的上部區。在一些實施例中，在佈植期間，層間介電質層上存在額外的介電質層（例如：蝕刻停止層）可導致層間介電質層橫向膨脹得更多且垂直膨脹得更少。藉由密封氣隙，減少或消除了後續所沉積的導電材料進入氣隙的機會。因此，減少或消除了由於氣隙中存在導電材料而形成電性短路的機會。
在第1圖中，根據一些實施例繪示出鰭式場效電晶體的示例的3D視圖。此鰭式場效電晶體包括基板50（例如：半導體基板）上的鰭片52。隔離區56設置於基板50中，且鰭片52從相鄰的隔離區56之間向上突出。雖然隔離區56被描述／繪示為與基板50分離，本文所使用的詞語「基板」可用於僅指稱半導體基板，或用於指稱包含隔離區的半導體基板。此外，雖然鰭片52被繪示為和基板50一樣的單一連續材料，但鰭片52及／或基板50可包含單一材料或複數種材料。在本文中，鰭片52指的是在相鄰的隔離區56之間延伸的部分。
閘極介電質層92沿著鰭片52的側壁，且在鰭片52的頂面上方，而閘極電極94在閘極介電質層92上方。源極／汲極區82設置於鰭片52相對於閘極介電質層92與閘極電極94的相反側。第1圖進一步繪示用於後續圖式中的參考剖面。剖面A-A沿著閘極電極94的縱軸，並在例如垂直於鰭式場效電晶體的源極／汲極區82之間的電流的方向上。剖面B-B垂直於剖面A-A且沿著鰭片52的縱軸，並且在鰭式場效電晶體的源極／汲極區82之間的電流的方向上。剖面C-C平行於剖面A-A且延伸穿過鰭式場效電晶體的源極／汲極區。為了清楚起見，後續的圖式參照這些參考橫截面。
本文討論的一些實施例是在使用後閘極(gate-last)製程形成的鰭式場效電晶體的情況下討論的。在其他實施例中，可使用前閘極(gate-first)製程。此外，一些實施例考慮到在平面裝置（像是平面式場效電晶體）中使用的面向。
第2圖至第33B圖為根據一些實施例之製造鰭式場效電晶體的中間階段的剖面圖。第2圖至第7圖繪示在第1圖中所繪示的參考剖面A-A，不包含多重鰭片／鰭式場效電晶體。第8A、9A、10A、11A、12A、13A、14A、15A、30A、31A、32A以及33A根據第1圖中所繪示的參考剖面A-A來繪示，而第8B、9B、10B、11B、12B、13B、14B、14C、15B、16、17、18、19、21、22、23、26、27A、27B、28、30B、31B、32B、與33B圖根據第1圖中所繪示的相似的剖面B-B來繪示，不包含多重鰭片／鰭式場效電晶體。第10C圖與第10D圖依照第1圖中所繪示的參考剖面C-C來繪示，不包含多重鰭片／鰭式場效電晶體。
在第2圖中，提供基板50。基板50可為半導體基板，例如塊體半導體(bulk semiconductor)、絕緣體上覆半導體(semiconductor-on-insulator，SOI)基板或類似者，其可為摻雜的(例如：用p型或n型摻質)或無摻雜的。基板50可為晶圓，像是矽晶圓。一般來說，絕緣體上覆半導體基板為形成於絕緣層上方的一層半導體材料。絕緣層可能為例如：埋藏氧化物(buried oxide，BOX)層、氧化矽層、或類似者。在基板上提供絕緣層，通常是矽基板或玻璃基板。也可使用其他基板，例如多層基板或梯度(gradient)基板。在一些實施例中，基板50的半導體材料可包含矽；鍺；化合物半導體，包含碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide)；合金半導體，包含矽鍺(silicon-germanium)、磷砷化鎵(gallium arsenide phosphide)、砷化鋁銦(aluminum indium arsenide)、砷化鋁鎵(aluminum gallium arsenide)、砷化鎵銦(gallium indium arsenide)、磷化鎵銦(gallium indium phosphide)及∕或磷砷化鎵銦(gallium indium arsenide phosphide)；或前述之組合。
基板50具有區域50N和區域50P。區域50N可用於形成n型裝置，例如NMOS電晶體（像是n型鰭式場效電晶體）。區域50P可用於形成p型裝置，例如PMOS電晶體（像是p型鰭式場效電晶體）。區域50N可與區域50P實體分離（如分離符號51所示），且可於區域50N與區域50P之間設置任何數量的裝置部件（例如：其他主動裝置、摻雜區、隔離結構等等）。
在第3圖中，於基板50中形成鰭片52。鰭片52為半導體條(strip)。在一些實施例中，鰭片52可藉由在基板50中蝕刻溝槽來形成於基板50中。蝕刻步驟可為任何可接受的蝕刻製程，例如反應離子蝕刻(reactive ion etch, RIE)、中性粒子束蝕刻(neutral beam etch, NBE)、類似製程、或上述的組合。蝕刻可為非等向性的。
鰭片可透過任何適合的方法圖案化。例如，鰭片可利用包括雙重圖案化或多重圖案化的一道或多道光微影製程來圖案化鰭片。一般來說，雙重圖案化或多重圖案化製程結合了光微影製程及自我對準製程，可創造具有例如比使用單一、指向性的光微影製程能獲得的節距還要更小的節距的圖案。舉例來說，在一實施例中，一犧牲層在基板上形成，並且以光微影製程進行圖案化。間隔物沿著圖案化的犧牲層以自我對準製程形成。接著移除犧牲層，剩下的間隔物可接著用來將鰭片圖案化。在一些實施例中，遮罩（或其他層）可保留在鰭片52上。
在第4圖中，絕緣材料54形成於基板50上且形成於相鄰的鰭片52之間。絕緣材料54可為氧化物，像是氧化矽、氮化物、類似者或上述的組合，且可藉由高密度電漿化學氣相沉積(high density plasma chemical vapor deposition, HDP-CVD)、流動式CVD(flowable CVD, FCVD)（例如：在遠程電漿系統中進行的基於CVD的材料沉積，以及後固化(post curing)以使其轉化為另一種材料，像是氧化物）、類似者或上述的組合來形成。也可使用其他可接受的製程來形成絕緣材料。在繪示的實施例中，絕緣材料54為藉由FCVD製程形成的氧化矽。一旦形成絕材料後，可執行退火製程。在一實施例中，形成絕緣材料54，使得多餘的絕緣材料54覆蓋鰭片52。雖然絕緣材料54被繪示為單一層，但在一些實施例中可使用多層。舉例來說，在一些實施例中，可先沿著基板50和鰭片52的表面形成襯層（未繪示）。在形成襯層之後，可於襯層上方形成如上文所討論的填充材料。
在第5圖中，對絕緣材料54進行移除製程以移除鰭片52上方多餘的絕緣材料54。在一些實施例中，可利用像是化學機械研磨(CMP)、回蝕刻製程、上述的組合、或類似者來進行平坦化製程。平坦化製程使鰭片52露出，且使得鰭片52和絕緣材料54的頂面在平坦化製程完成之後是齊平的。在遮罩保留於鰭片52上的實施例中，平坦化製程可露出遮罩或移除遮罩，使得遮罩或者鰭片52的頂面在平坦化製程完成之後分別與絕緣材料54的頂面齊平。
在第6圖中，絕緣材料54被凹蝕以形成淺溝槽隔離(STI)區56。絕緣材料54被凹蝕使得區域50N以及區域50P中的鰭片52的上部從相鄰的淺溝槽隔離區56中突出。此外，淺溝槽隔離區56的頂面可具有如圖所示的平坦表面、凸起(convex)頂面、凹陷(concave)頂面（例如碟狀(dishing)）或上述之組合。淺溝槽隔離區56的頂面可透過適當的蝕刻製程形成平坦的、凸起的及／或凹陷的表面。可透過合適的蝕刻製程來凹蝕淺溝槽隔離區域56，像是對於絕緣材料54有選擇性的蝕刻製程（例如：以比蝕刻鰭片52的材料更快的速率來蝕刻絕緣材料54的材料）。舉例來說，可使用稀釋氫氟酸(dHF)去除氧化物。
關於第2圖至第6圖所描述的製程僅為形成鰭片52的方法的一個示例。在一些實施例中，鰭片可藉由磊晶成長製程形成。舉例來說，介電質層可形成於基板50的頂面上方，且可蝕刻穿過介電質層的溝槽以露出下方的基板50。可於溝槽中成長同質磊晶(homoepitaxial)結構，且可凹蝕介電質層使得同質磊晶結構從介電質層突出以形成鰭片。此外，在一些實施例中，異質磊晶(heteroepitaxial)結構可用於鰭片52。舉例來說，第5圖中的鰭片52可被凹蝕，且可在經凹蝕的鰭片52上磊晶成長與鰭片52不同的材料。在這樣的實施例中，鰭片52包含經凹蝕的材料以及設置於經凹蝕的材料上方的磊晶成長的材料。在進一步的實施例中，介電質層可形成於基板50的頂面上，且可蝕刻穿過介電質層的溝槽。可使用不同於基板50的材料在溝槽中磊晶成長異質磊晶結構，且介電質層可被凹蝕使得異質磊晶結構從介電質層突出以形成鰭片52。在磊晶成長同質磊晶或異質磊晶結構的一些實施例中，磊晶成長材料可在成長過程中被原位摻雜，其可省去之前和之後的佈植，儘管原位和佈植摻雜亦不排除可一起使用。
更進一步地，在區域50N（例如：NMOS區域）中磊晶生長與區域50P（例如，PMOS區域）中的材料不同的材料可為有利的。在各種實施例中，鰭片52的上部可由矽鍺（Six Ge1-x ，其中x可在 0 至 1的範圍內）、碳化矽、純鍺或部分純鍺、III-V族化合物半導體、II-IV族化合物半導體、或類似者。舉例來說，可形成III-V族化合物半導體的材料包括但不限於：砷化銦、砷化鋁、砷化鎵、磷化銦、氮化鎵、砷化鎵銦、砷化鋁銦、銻化鎵、銻化鋁、磷化鋁、磷化鎵、以及類似者。
更進一步地，在第6圖中，可在鰭片52及／或基板50中形成適當的井（未繪示）。在一些實施例中，可在區域50N中形成P井，且可在區域50P中形成N井。在一些實施例中，在區域50N和區域50P中皆形成P井或N井。
在具有不同類型的井的實施例中，可以使用光阻或其他遮罩（未繪示）實現用於區域50N和區域50P的不同佈植步驟。舉例來說，可以在區域50N中的鰭片52和淺溝槽隔離區56上方形成光阻。圖案化光阻以露出基板50的區域50P（例如：PMOS區域）。可利用旋轉塗布技術來形成光阻，且利用可接受的光微影技術將其圖案化。一旦光阻被圖案化，就在區域50P中執行n型雜質佈植，並且光阻可作為遮罩以實質上防止n型雜質被佈植到區域50N（例如NMOS區域）中。n型雜質可為佈植到此區域中的磷、砷、銻或類似者，其濃度等於或小於1018 cm-3 ，例如在約1016 cm-3 及大約1018 cm-3 之間。在佈植之後，藉由例如可接受的灰化製程(ashing process)來移除光阻。
在佈植區域50P之後，在區域50P中的鰭片52以及淺溝槽隔離區56上方形成光阻。將光阻圖案化以露出基板50中的區域50N（例如：NMOS區域）。可利用旋轉塗布技術來形成光阻，且利用可接受的光微影技術將其圖案化。一旦光阻被圖案化，就在區域50N中執行p型雜質佈植，並且光阻可作為遮罩以實質上防止p型雜質被佈植到區域50P（例如：PMOS區域）中。p型雜質可為佈植到此區域中的硼、氟化硼、銦或類似者，其濃度等於或小於1018 cm-3 ，例如在約1016 cm-3 及大約1018 cm-3 之間。在佈植之後，藉由例如可接受的灰化製程來移除光阻。
在佈植區域50N及區域50P之後，可執行退火步驟以修復佈植損傷且活化被佈植的p型及／或n型雜質。在一些實施例中，成長磊晶鰭片的材料可以在成長期間被原位摻雜，其可以省去佈植，儘管原位和佈植摻雜亦不排除可一起使用。
在第7圖中，於鰭片52上方形成虛置介電質層60。虛置介電質層60可例如為氧化矽、氮化矽、上述的組合或類似者，且可根據可接受的技術來沉積或熱生長。虛置閘極層62形成於虛置介電質層60上方，且遮罩層64形成於虛置閘極層62上方。虛置閘極層62可沉積於虛置介電質層60上方且接著藉由例如CMP來平坦化。遮罩層64可沉積於虛置閘極層62上方。虛置閘極層62可為導電或非導電材料，且可選自包括非晶矽、多晶矽(polysilicon)、多晶矽鍺(poly-SiGe)、金屬氮化物、金屬矽化物、金屬氧化物以及金屬的群組。虛置閘極層62可藉由物理氣相沉積(PVD)、CVD、濺鍍沉積、或本發明所屬技術領域中已知且用於沉積所選擇的材料的其他技術。虛置閘極層62可藉由在蝕刻隔離區的步驟中具有高蝕刻選擇性的其他材料所形成。遮罩層64可包括例如氧化矽、氮化矽、上述的組合或類似者。在這個例子中，單一虛置閘極層62與單一遮罩層64橫跨區域50N與區域50P而形成。應注意的是，為了說明，所顯示的虛置介電質層60僅覆蓋鰭片52。在一些實施例中，可沉積虛置介電質層60，使得虛置介電質層60覆蓋淺溝槽隔離區56且在虛置閘極層62與淺溝槽隔離區56之間延伸。
第8A至第15B圖繪示實施例裝置的製造過程中的各種額外步驟。第8A至第15B圖繪示區域50N與區域50P的任一個之中的部件。舉例來說，第8A至第15B圖中繪示的結構於區域50N和區域50P中皆可適用。在本文中搭配圖式描述區域50N和區域50P的結構差異（若有的話）。
在第8A圖與第8B圖中，可藉由可接受的光微影以及蝕刻技術來圖案化遮罩層64（參照第7圖）以形成遮罩74。遮罩74的圖案可接著轉移至虛置閘極層62。在一些實施例中（未繪示），遮罩74的圖案也可藉由可接受的蝕刻技術轉移至虛置介電質層60以形成虛置閘極72。虛置閘極72覆蓋鰭片52的各個通道區58。遮罩74的圖案可被用於將每個虛置閘極72與相鄰的虛置閘極實體分離。虛置閘極72也可具有實質上垂直於相應的磊晶鰭片52的長度方向。
進一步地，在圖8A和8B中，可以在虛置閘極72、遮罩74及 ／或鰭片52所露出的表面上形成閘極密封間隔物80。可藉由熱氧化或沉積以及隨後的非等向性蝕刻來形成閘極密封間隔物80。閘極密封間隔物80可由氧化矽、氮化矽、氮氧化矽或類似者形成。
在形成閘極密封間隔物80之後，可執行輕摻雜源極／汲極(lightly doped source/drain, LDD)區域（未明顯繪示）的佈植。在不同裝置類型的實施例中，類似於上文所討論的第6圖中的佈植，可在區域50N上方形成遮罩（例如光阻），同時露出區域50P，且可將適合的雜質類型（例如：p型）佈植進入區域50P中的露出的鰭片52。可接著移除遮罩。隨後，可在區域50P上方形成遮罩（例如光阻），同時露出區域50N，且可將適合的雜質類型（例如：n型）佈植進入區域50N中的被露出的鰭片52。可接著移除遮罩。n型雜質可為任何前文所討論的n型雜質，以及p型雜質可為任何前文所討論的p型雜質。輕摻雜源極／汲極可具有從約1015 cm-3 至約1019 cm-3 的雜質濃度。可利用退火製程以修復佈植損傷且活化經佈植的雜質。
在第9A圖與第9B圖中，在閘極密封間隔物80上方沿著虛置閘極72以及遮罩74的側壁形成閘極間隔物86。閘極間隔物86可藉由保形地沉積絕緣材料且隨後非等向性蝕刻絕緣材料來形成。閘極間隔物86的絕緣材料可為氧化矽、氮化矽、氮氧化矽、碳氮化矽、上述的組合、或類似者。
應注意的是，以上揭露的內容大致上描述了形成間隔物與輕摻雜源極／汲極區的製程。可利用其他製程或順序，舉例來說，可利用少數或額外的間隔物，可利用不同的步驟順序（例如：在形成閘極間隔物86之前可以不蝕刻閘極密封間隔物80、產生「L形」閘極密封間隔物、可形成和移除間隔物、及／或類似者）。更進一步地，可利用不同的結構與步驟形成n型裝置與p型裝置。舉例來說，n型裝置的輕摻雜源極／汲極區可在形成閘極密封間隔物80之前形成，而p型裝置的輕摻雜源極／汲極區可在形成閘極密封間隔物80之後形成。
在第10A圖與第10B圖中，根據一些實施例在鰭片52中形成磊晶源極／汲極區82。在一些情況下，可形成磊晶源極／汲極區82以在各個通道區58中施加應力，從而提升性能。在鰭片52中形成磊晶源極／汲極區82，使得每個虛置閘極72設置於每個相鄰一對磊晶源極／汲極區82之間。在一些實施例中，磊晶源極／汲極區82可延伸進入（且也可穿過）鰭片52。在一些實施例中，利用閘極間隔物86將磊晶源極／汲極區82與虛置閘極72以適當的橫向距離分離，使得磊晶源極／汲極區82不會使隨後形成的鰭式場效電晶體的閘極產生短路。
可藉由遮蔽區域50P（例如：PMOS區域）、並蝕刻區域50N中的鰭片52的源極／汲極區以在鰭片52中形成凹槽來形成在區域50N（例如：NMOS區域）中的磊晶源極／汲極區82。接著，在凹槽中磊晶成長區域50N中的磊晶源極／汲極區82。 磊晶源極／汲極區82可包括任何可接受的材料，像是適合n型鰭式效電晶體的材料。舉例來說，若鰭片52為矽，在區域50N中的磊晶源極／汲極區82可包括在通道區58中施加拉伸應變(tensile strain)的材料，例如矽、碳化矽、磷摻雜碳化矽、磷化矽、或類似者。在區域50N中的磊晶源極／汲極區82可具有從鰭片52的相應表面升起的表面，且可包含刻面(facet)。
可藉由遮蔽區域50N（例如：NMOS區域）、並蝕刻區域50P中的鰭片52的源極／汲極區以在鰭片52中形成凹槽來形成在區域50P（例如：PMOS區域）中的磊晶源極／汲極區82。接著，在凹槽中磊晶成長區域50P中的磊晶源極／汲極區82。 磊晶源極／汲極區82可包括任何可接受的材料，像是適合p型鰭式效電晶體的材料。舉例來說，若鰭片52為矽，在區域50P中的磊晶源極／汲極區82可包括在通道區58中施加壓縮應變(compressive strain)的材料，例如矽鍺、硼摻雜矽鍺、鍺、鍺錫、或類似者。在區域50P中的磊晶源極／汲極區82可具有從鰭片52的對應表面升起的表面，且可包含刻面。
磊晶源極／汲極區82及／或鰭片52可佈植摻質以形成源極／汲極區，類似於前文討論的形成輕摻雜源極／汲極的步驟，接著進行退火製程。源極／汲極區可具有介於約1019 cm-3 及約1021 cm-3 的雜質濃度。n型雜質及／或p型雜質可為任何前文所討論的雜質。在一些實施例中，磊晶源極／汲極區82可在成長時進行原位摻雜。
作為使用磊晶製程形成在區域50N以及區域50P中的磊晶源極／汲極區82的結果，磊晶源極／汲極區的上表面具有橫向朝外延伸超過鰭片52的側壁的刻面。在一些實施例中，如第10C圖所示，這些刻面導致相同的鰭式場效電晶體中的相鄰的源極／汲極區82合併。在其他實施例中，如第10D圖所示，相鄰的源極／汲極區82在磊晶製程完成之後保持分離。在繪示於第10C圖以及第10D圖的實施例中，形成閘極間隔物86，其覆蓋鰭片52在淺溝槽隔離區56上方延伸的側壁的一部分，從而阻擋磊晶成長。在一些實施例中，可調整用來形成閘極間隔物86的間隔物蝕刻以移除間隔物材料，使得磊晶成長區域延伸至淺溝槽隔離區56的表面。
在第11A圖與第11B圖中，根據一些實施例，沉積第一層間介電質(interlayer dielectric, ILD)88於第10A圖與第10B圖中所繪示的結構上方。第一層間介電質88可由介電材料形成，且可藉由適合的方法沉積，像是CVD、電漿輔助CVD(plasma-enhanced, PECVD)、或FCVD。介電材料可包括磷矽酸鹽玻璃(phospho-silicate glass, PSG)、硼矽酸鹽玻璃(boro-silicate glass, BSG)、硼摻雜磷矽酸鹽玻璃(boron-doped phospho-silicate glass, BPSG)、無摻雜的矽酸鹽玻璃(undoped silicate glass, USG)或類似者。也可使用其他使用任何可接受的製程形成的絕緣材料。在一些實施例中，接觸蝕刻停止層(contact etch stop layer, CESL)87設置於第一層間介電質88以及磊晶源極／汲極區82、遮罩74、以及閘極間隔物86之間。接觸蝕刻停止層87可包括介電材料，像是氮化矽、氧化矽、氮氧化矽、或類似者，此介電材料具有與上方的第一層間介電質88不同的蝕刻速率。在一些實施例中，接觸蝕刻停止層87可形成為具有介於約2nm及約5nm之間的厚度，例如約3nm。在一些情況下，控制接觸蝕刻停止層87的厚度能夠控制隨後形成的源極／汲極接觸件118的尺寸（例如：寬度或高度），或者能夠控制隨後形成的氣隙120的尺寸（例如：寬度或高度）（見第26圖）。
在第12A圖與第12B圖中，可執行平坦化製程（例如CMP）以使第一層間介電質88的頂面與虛置閘極72或遮罩74的頂面齊平。平坦化製程也可移除虛置閘極72上的遮罩74，以及沿著遮罩74側壁的部分閘極密封間隔物80與部分閘極間隔物86。在平坦化製程之後，虛置閘極72、閘極密封間隔物80、閘極間隔物86以及第一層間介電質88的頂面齊平。因此，虛置閘極72的頂面透過第一層間介電質88露出。在一些實施例中，在平坦化製程使第一層間介電質88的頂面以及遮罩74的頂面齊平的情況下，可保留遮罩74。
在第13A圖與第13B圖中，在一道或多道蝕刻步驟中移除虛置閘極72以及遮罩74（如果有的話）以形成凹槽90。也可移除虛置介電質層60在凹槽90中的部分。在一些實施例中，只移除虛置閘極72而保留虛置介電質層60，且虛置介電質層60藉由凹槽90露出。在一些實施例中，從晶粒的第一區域（例如：核心邏輯區域）中的凹槽90中移除虛置介電質層60，且保留在晶粒的第二區域（例如：輸入／輸出區域）中的凹槽90中的虛置介電質層60。在一些實施例中，以非等向性乾式蝕刻製程移除虛置閘極72。舉例來說，蝕刻製程可包括使用一種或多種反應氣體的乾式蝕刻製程，此反應氣體對虛置閘極72進行選擇性蝕刻，而不蝕刻第一層間介電質88、閘極間隔物86或接觸蝕刻停止層87。每個凹槽90露出及／或在相應的鰭片52的通道區58上方。每個通道區58設置在每個相鄰一對磊晶源極／汲極區82之間。在移除步驟期間，虛置介電質層60在蝕刻虛置閘極72時可作為蝕刻停止層。在移除虛置閘極72之後，虛置介電質層60可接著被可選地移除。
在第14A圖與第14B圖中，形成閘極介電質層92與閘極電極94作為置換閘極。第14C圖繪示第14B圖的區域89的細節視圖。閘極介電質層92保形地沉積於凹槽90中，例如在鰭片52的頂面和側壁上以及在閘極密封間隔物80／閘極86的側壁上。閘極介電質層92也可形成於第一層間介電質88的頂面上。根據一些實施例，閘極介電質層92包括氧化矽、氮化矽、或上述的多層。在一些實施例中，閘極介電質層92可包括高介電常數介電材料，且在一些實施例中，閘極介電質層92可具有高於約7.0的介電常數，且可包括氧化金屬或鉿、鋁、鋯、鑭、錳、鋇、鈦、鉛的矽酸鹽，以及上述的組合。閘極介電質層92的形成方法可包括分子束沉積(Molecular-Beam Deposition, MBD)、ALD、PECVD、以及類似者。在虛置介電質層60的一部分保留於凹槽90中的實施例中，閘極介電質層92包括虛置介電質層60的材料（例如：氧化矽）。
閘極電極94對應地沉積在閘極介電質層92上方，且填充凹槽90的其餘部分。閘極電極94可包括含金屬的材料，例如氮化鈦、氧化鈦、氮化鉭、碳化鉭、鈷、釕、鋁、鎢、上述的組合或上述的多層。舉例來說，雖然第14B圖中繪示單層閘極電極94，閘極電極94可包括任何數量的襯層94A、任何數量的功函數調整層94B、以及填充材料94C，如第14C圖所示。在填充凹槽90之後，執行例如CMP的平坦化製程以移除閘極介電質層92以及閘極電極94的材料的多餘部分，此多餘部分在層間介電質88的頂面上方。閘極電極94的材料以及閘極介電質層92的剩餘部分因此形成所得到的鰭式場效電晶體的置換閘極。閘極電極94及閘極介電質層92可被統稱為「閘極堆疊」。閘極與閘極堆疊可沿著鰭片52的通道區58的側壁延伸。
在區域50N以及區域50P中形成閘極介電質層92的步驟可同時進行，使得在每個區域中的閘極介電質層92以相同材料形成，且可同時進行形成閘極電極94的步驟，使得在每個區域中的閘極電極94以相同材料形成。在一些實施例中，在每個區域中的閘極介電質層92藉由不同的步驟形成，使得閘極介電質層92可為不同材料，及／或在每個區域中的閘極電極94藉由不同的步驟形成，使得閘極電極94可為不同材料。當使用不同製程時，可使用各種遮罩步驟來遮蔽以及露出適當的區域。
在第15A圖與第15B圖中，根據一些實施例於第一層間介電質88上方沉積第二層間介電質108。在一些實施例中，第二層間介電質108為藉由流動式CVD形成的流動薄膜。在一些實施例中，第二層間介電質108由介電材料形成，像是PSG、BSG、 BPSG、USG、氧化矽或類似者，且可藉由任何適合的方法沉積，例如CVD、PECVD或類似者。可執行一平坦化製程（例如CMP）以平坦化第二層間介電質層108的表面。在一些實施例中，第二層間介電質層108可被形成為具有介於約10nm與約30nm之間的厚度，例如約15nm。控制第二層間介電質層108的厚度與寬度也能夠控制將氣隙120密封的膨脹區130的尺寸，將在下文針對第26圖進行描述。
根據一些實施例，在沉積第二層間介電質層108之前，沉積硬遮罩96於結構上。硬遮罩96可包括一層或多層介電材料，像是氮化矽、氮氧化矽、或類似者，且可具有與上方的第二層間介電質層108不同的蝕刻速率。在一些實施例中，硬遮罩96可形成為具有介於約2nm與約4nm之間的厚度，例如約3nm。在一些實施例中，硬遮罩96由與接觸蝕刻停止層87相同的材料形成，或者形成為具有與接觸蝕刻停止層87大約相同的厚度。隨後形成的源極／汲極接觸件118（見第26圖）穿過硬遮罩96與接觸蝕刻停止層87以接觸磊晶源極／汲極區82的頂面，且閘極接觸件132（見第31A圖與第31B圖）穿過硬遮罩96以接觸閘極電極94的頂面。
第16圖至第26圖根據一些實施例繪示形成具有氣隙120的源極／汲極接觸件118（見第26圖）的中間階段。源極／汲極接觸件118與磊晶源極／汲極區82實體接觸且電性接觸。源極／汲極接觸件118也可稱為「接觸件118」或「接觸插塞118」。為了清楚表示，第16圖至第24圖顯示為第15B圖的區域111的詳細視圖。第16圖繪示第15B圖中顯示的相同結構的區域111。
第17圖中，根據一些實施例，在第一層間介電質88以及第二層間介電質108中形成開口110以露出磊晶源極／汲極區82。可利用適合的光微影以及蝕刻技術來形成開口110。舉例來說，可在第二層間介電質108上形成光阻（例如：單層或多層光阻結構）。光阻可接著被圖案化以露出在對應於開口110的區域中的第二層間介電質層108。可接著執行一道或多道適合的蝕刻製程，使用圖案化的光阻作為蝕刻遮罩以蝕刻開口110。一道或多道蝕刻製程可包括濕式蝕刻製程及／或乾式蝕刻製程。在一些實施例中，接觸蝕刻停止層87及／或硬遮罩96在形成開口110時可用來作為蝕刻停止層。如第17圖所示，也可移除接觸蝕刻停止層87延伸至磊晶源極／汲極的部分。在一些實施例中，開口110可延伸至磊晶源極／汲極區82的頂面下方，並且延伸進入磊晶源極／汲極區82當中。在一些實施例中，一道或多道蝕刻製程可移除第一層間介電質層88的材料以露出觸蝕刻停止層87。開口110可具有如第17圖中所示的錐形(tapered)側壁，或可具有不同輪廓的側壁（例如：垂直側壁）。在一些實施例中，開口110可具有介於約10nm及約30nm的寬度W1。可橫跨開口110的頂部、橫跨開口110的底部或者橫跨開口110的任何位置來測量寬度W1。在一些情況下，控制寬度W1可控制隨後形成的源極／汲極接觸件118及／或氣隙120的尺寸（參照第26圖）。
在第18圖中，根據一些實施例在開口110上形成虛置間隔物層112。在一些實施例中，虛置間隔物層112可形成為延伸至第二層間介電質層108、接觸蝕刻停止層87、以及磊晶源極／汲極區82上方的毯覆層(blanket layer)。虛置間隔物層112的材料可包括例如矽、多晶矽、非晶矽、類似者或上述之組合。在一些實施例中，虛置間隔物層112的材料為相對於其他層可被高選擇性地蝕刻的材料，其他層可例如為第二層間介電質層108、接觸蝕刻停止層87或接觸間隔物層114（於下文敘述）。可藉由PVD、CVD、ALD、或類似者來沉積虛置間隔物層112。在一些實施例中，虛置間隔物層112可形成為具有介於約3nm及約9nm的厚度，例如約6nm。在一些實施例中，虛置間隔物層112的厚度大約相當於隨後形成的氣隙120的寬度W2（見第21圖）。
在第19圖中，根據一些實施例在虛置間隔物層112上形成接觸間隔物層114。在形成接觸間隔物層114之前，可執行適合的非等向性乾式蝕刻製程以移除虛置間隔物層112橫向延伸至第二層間介電質層108及磊晶源極／汲極區82上的區域。由於乾式蝕刻製程的非等向性，保留了虛置間隔物層112沿著開口110的側壁延伸的區域。在一些實施例中，非等向性乾式蝕刻製程也可蝕刻磊晶源極／汲極區82的材料，且因此使開口110更加延伸進入磊晶源極／汲極區82中。
在一些實施例中，接觸間隔物層114可形成為延伸至第二層間介電質層108、虛置間隔物層112以及磊晶源極／汲極區82上方的毯覆層。接觸間隔物層114可包括一層或多層，其材料為例如氧化矽、氮化矽、氮氧化矽、碳氮化矽、類似者或上述之組合。可藉由PVD、CVD、ALD、或類似者來沉積接觸間隔物層114。在一些實施例中，接觸間隔物層114可形成為具有介於約2nm及約5nm的厚度，例如約3nm。在形成接觸間隔物層114之後，可執行適合的非等向性乾式蝕刻製程以移除接觸間隔物層114橫向延伸至第二層間介電質層108、虛置間隔物層112以及磊晶源極／汲極區82上的區域。由於乾式蝕刻製程的非等向性，保留了接觸間隔物層114沿著開口110的側壁延伸的區域（例如：沿著虛置間隔物層112延伸的區域）。在一些情況下，控制接觸間隔物層114的厚度可以控制隨後形成的源極／汲極接觸件118及／或氣隙120的尺寸（見第26圖）。
參照第20圖，根據一些實施例在開口110中沉積一種或多種導電材料，形成源極／汲極接觸件118。在一些實施例中，源極／汲極接觸件118的導電材料包括保形地沉積在開口110的表面上（例如：在接觸間隔物層114上）的襯層（未分別顯示）以及沉積在襯層上以填充開口110的導電填充材料。在一些實施例中，襯層包括鈦、鈷、鎳、氮化鈦、氧化鈦、氮化鉭、氧化鉭、類似者或上述的組合。在一些實施例中，導電填充材料包括鈷、鎢、銅、鋁、金、銀、上述的合金、類似者、或上述的組合。可藉由一道或多道適合的製程來沉積襯層或導電填充材料，像是CVD、PVD、ALD、濺鍍(sputtering)、鍍覆(plating)或類似者。
在一些實施例中，可在磊晶源極／汲極區82的上部部分上形成矽化物區116，以改善磊晶源極／汲極區82與源極／汲極接觸件118之間的電性連結。在一些實施例中，可藉由使磊晶源極／汲極區82的上部部分與襯層反應來形成矽化物區116。在一些實施例中，可在磊晶源極／汲極區82上沉積另外的材料以與磊晶源極／汲極區82反應，以形成矽化物區116。矽化物區116可包括矽化鈦、矽化鎳、類似者或上述的組合。在一些實施例中，執行一道或多道退火製程以促進矽化物形成反應。在沉積源極／汲極接觸件118的導電填充材料之後，可藉由平坦化製程（例如CMP）移除多餘的材料以形成與第二層間介電質層108的頂面共平面的源極／汲極接觸件118的頂面。
參照第21圖，根據一些實施例移除虛置間隔物層112的材料以形成氣隙120。可藉由適合的蝕刻製程以移除虛置間隔物層112的材料，像是乾式蝕刻製程。相對於第二層間介電質層108、接觸蝕刻停止層87或接觸間隔物層114的材料，蝕刻製程可對虛置間隔物層112的材料有選擇性。舉例來說，在虛置間隔物層112包括矽且接觸間隔物層114包括氮化矽的實施例中，蝕刻製程可包括在電漿蝕刻製程中使用HBr、O2 、He、CH3 F、H2 、類似者或上述的組合作為製程氣體，此電漿蝕刻製程選擇性地蝕刻虛置間隔物層112的矽。也可以使用其他材料或蝕刻製程。
在一些實施例中，氣隙120可形成為具有介於約0.5nm及約4nm的寬度W2，例如約2.5nm。在一些情況下，形成具有較大寬度W2的氣隙120可造成電容值減少以及裝置性能改善，將於下文詳細敘述。氣隙120可具有實質上均勻的寬度或者沿著垂直長度（例如：延伸遠離基板50的長度）變化的寬度。舉例來說，氣隙120底部附近（例如：靠近磊晶源極／汲極區82）的寬度可小於頂部附近（例如：靠近第二層間介電質層108）的寬度。在一些實施例中，氣隙120的底部可延伸進入磊晶源極／汲極區82（如第21圖中所示），或者氣隙120的底部可位於磊晶源極／汲極區82的頂面或在磊晶源極／汲極區82的頂面上方。氣隙120可在相對於垂直軸的角度延伸，如第21圖中所示，或者可實質地沿著垂直軸延伸。
在一些情況下，藉由在源極／汲極接觸件118與閘極堆疊92/94之間形成氣隙120，可減少源極／汲極接觸件118與閘極堆疊92/94之間的電容值。相對於例如氧化矽、氮化矽或類似者的其他間隔物材料，由於空氣的介電常數（k值）較低，約為k＝1，因此可以藉由此種方式來減少電容值。藉由使用氣隙120來減少電容值，鰭式場效電晶體裝置在高頻率的操作下可具有更快的響應速度(response speed)以及更佳的效能。
參照第22圖，在第二層間介電質層108、源極／汲極接觸件118以及氣隙120上方形成蓋層122。蓋層122可形成為延伸跨過氣隙120的毯覆層，使得氣隙120被封閉。在一些實施例中，蓋層122的一些材料可部分地延伸進入氣隙120（如第22圖中所示），但在其他實施例中，氣隙120保持為不含蓋層122的材料。使用此方法，氣隙120並未被蓋層122填充，但為相鄰於源極／汲極接觸件118的空氣封閉區域。在一些實施例中，蓋層122隨後被用做蝕刻停止層以形成源極／汲極接觸件118上方的導電元件136，於下文的第32A圖與第32B圖描述。
蓋層122可包括一層或多層材料，例如氮化矽、氮氧化矽、碳氮化矽、碳氮氧化矽、類似者或上述之組合。可藉由PVD、CVD、ALD、或類似者來沉積接觸蓋層122。在一些實施例中，蓋層122可形成為具有介於約6nm及約16nm的厚度，例如約11nm。在一些情況下，較厚的蓋層122可減少第二層間介電質層108在佈植製程124期間垂直膨脹的量，將在下文中的第23圖中描述。在一些情況下，可藉由控制蓋層的厚度來控制佈植的摻質的佈植深度，也將在下文中的第23圖中描述。
在第23圖中，根據一些實施例穿過蓋層122執行佈植製程124，以使用摻質佈植第二層間介電質層108來密封氣隙120。在一些實施例中，佈植的摻質導致第二層間介電質層108的佈植區126的體積相對於第二層間介電質層108的非佈植區有所增加。氣隙120提供相鄰的佈植區126可膨脹進入的體積。佈植區126膨脹進入氣隙120的部分在此被稱為膨脹區130。在一些實施例中，可控制佈植製程124，使得膨脹區130完全延伸跨過氣隙120的寬度而密封氣隙120。舉例來說，可控制佈植製程124的劑量、佈植深度、摻質種類、角度、佈植能量或其他特性來控制佈植區126的膨脹，將在下文更詳細地敘述。氣隙120的上部區可以膨脹區130為邊界，及／或氣隙120的下部區域可以源極／汲極區82為邊界。
藉由以這種方式形成膨脹區130以密封氣隙120，可以防止隨後沉積的材料進入氣隙120。在一些情況下，隨後沉積的材料進入氣隙120可能會導致製程缺陷或裝置故障。舉例來說，可隨後蝕刻蓋層122且沉積導電材料以形成導電元件136（見第32B圖），而膨脹區130可防止導電材料沉積在氣隙120中導致電性短路。此外，在一些情況下，第二層間介電質層108的材料可為具有低於其他材料（例如：可用來密封氣隙120的氮化矽）的k值的氧化矽。使用此方法，相對於使用另一種材料來密封氣隙120，使用第二層間介電質層108的材料來密封氣隙120可減少電容值。
在一些實施例中，藉由佈植製程124佈植的摻質種類包括Ge、Ar、Xe、Si、類似者或上述的組合。在一些實施例中，佈植的摻質為原子半徑大於矽的原子種類。舉例來說，當佈植進入包含矽的第二層間介電質層108時，更大尺寸的佈植摻質可導致第二層間介電質層108的佈植區126的體積增加，形成膨脹區130。在一些實施例中，佈植製程124包括以與垂直軸成介於約0度與約60度之間的角度佈植摻質。在一些情況下，取決於應用或裝置型態(geometry)，控制佈植角度可為有利的。舉例來說，可以一定角度執行佈植製程124以減少散亂效應(straggle effect)。在一些實施例中，佈植的摻質劑量可介於約1014 原子/cm2 以及約 1016 原子/cm2 之間。在一些實施例中，佈植的摻質濃度可等於或少於約1022 cm-3 ，例如介於約1019 原子/cm2 以及約 1022 原子/cm2 之間。增加佈植區126中的佈植劑量或增加摻質濃度可增加佈植區126的膨脹程度。在一些實施例中，佈植溫度在介於約-100 °C至約450 °C的範圍內。
繼續參照第23圖，佈植深度D1標示出從第二層間介電質層的頂部所測量的第二層間介電質層108中的最大摻質濃度的深度。在一些實施例中，佈植深度D1可介於約0nm與約20nm之間，例如約5nm。在一些情況下，佈植深度D1大致上對應於佈植區126中具有最大膨脹量的位置。因此，藉由控制佈植深度D1，可控制膨脹區130的位置。已觀察到在第二層間介電質層108上方的佈植深度D1可導致氣隙120的密封不完全。已觀察到大於10nm的佈植深度D1可導致較大的摻植區128，將於下文詳細描述。在一些實施例中，佈植深度D1可由佈植製程124的參數以及蓋層122的厚度來決定。舉例來說，可藉由增加佈植能量來增加佈植深度D1。在一些實施例中，以介於約2keV與約30keV之間的佈植能量來佈植摻質，例如約20keV。如另一個例子，藉由增加蓋層122的厚度，摻質在到達第二層間介電質層108之前需要旅行較長距離以穿過蓋層122，因而減少佈植深度D1。使用此方法，可藉由控制佈植能量及／或蓋層122的厚度來控制佈植深度D1。
參照第24圖，根據一些實施例顯示例示性的摻質濃度輪廓200。輪廓200顯示從蓋層122的表面所測量的經佈植的摻質濃度的實驗數據。曲線202A顯示由第一佈植劑量所導致的第一濃度輪廓，以及曲線202B顯示由第二佈植劑量所導致的第二濃度輪廓，此第二佈植劑量大於第一佈植劑量。曲線202A與曲線202B皆對應於具有大致上相同的佈植能量的佈植步驟。對應於第二佈植劑量的曲線202B在第二層間介電質層108中顯示的摻質濃度大於對應於第一佈植劑量的曲線202A。如輪廓200所示，佈植摻質的最大濃度在第二層間介電質層108中的佈植深度D1處。對於輪廓200，佈植深度D1約5nm，雖然在其他情況下可有不同的佈植深度D1。由於曲線202A與曲線202B對應於具有大致上相同的佈植能量的佈植步驟，所以曲線202A與曲線202B的佈植深度D1大約相同。
在一些實施例中，在執行佈植製程124之前在第二層間介電質層108上形成蓋層122，以促進佈植區126的橫向膨脹，並且抑制佈植區126的垂直膨脹。舉例來說，第二層間介電質層108上方的蓋層122的存在可防止第二層間介電質108在垂直方向上膨脹。使用此方法，可將第二層間介電質層108的膨脹限制為橫向膨脹至氣隙120中。藉由在佈植製程124之前形成蓋層122以促進層間介電質層108的橫向膨脹，可形成更均勻的膨脹區130，且更完整地密封氣隙120 。此外，可使用具有較小佈植劑量的佈植製程124將氣隙120藉由膨脹區130密封，來減少佈植損害。
在一些情況下，在第二層間介電質層108上方的蓋層122可減少第二層間介電質層108的垂直膨脹。舉例來說，第25圖顯示實驗數據300，其測量上方具有蓋層122的第二層間介電質層108的厚度。數據300顯示第二層間介電質層在執行佈植製程124之前以及在執行佈植製程124之後的厚度。標示於“Ref”的點顯示出第二層間介電質層108在執行佈植製程124之前的厚度，而其餘的點顯示出第二層間介電質層108在執行佈植製程124之後的厚度。如第25圖所示，上方的蓋層122可使得第二層間介電質層108幾乎沒有或者沒有垂直膨脹，且第二層間介電質層108的厚度可保持實質上地均勻。使用此方法，使用蓋層122可使得第二層間介電質層108及／或蓋層122的頂面在執行佈植製程124之後更加平坦。更平坦的第二層間介電質層108或蓋層122可改善後續製程步驟的均勻度以及對準性(alignment)。在一些實施例中，較厚的蓋層122相較於較薄的蓋層122更能抑制垂直膨脹。在一些實施裡中，較薄的蓋層122（例如比約6nm薄）可部分抑制垂直膨脹，使得垂直膨脹小於不存在蓋層122的情況。以下關於第28、29圖，描述不存在蓋層122的一實施例。
在一些實施例中，可控制佈植製程124以控制佈植區126的尺寸，且因而控制膨脹區130的尺寸。舉例來說，第26圖顯示膨脹區130沿著氣隙120延伸長度L1的一實施例，長度L1約等於第二層間介電質層108的厚度。在一些實施例中，在第二層間介電質層108的整個厚度中佈植摻質，且所有在氣隙120露出的第二層間介電質層 108都膨脹至氣隙120中，作為膨脹區130。使用此方法，第二層間介電質層108的厚度可決定膨脹區130的長度L1。在一些實施例中，膨脹區130的長度L1可介於第二層間介電質層108的厚度的約10%和約105%之間，取決於層間介電質層108的厚度以及佈植條件。在一些實施例中，佈植深度D1可決定膨脹區130的長度L1，因為較大的佈植深度D1可形成具有較大L1的膨脹區130。藉由控制膨脹區130的尺寸，也可控制氣隙120的垂直長度（例如：頂部與底部之間的距離）。在一些實施例中，氣隙120的垂直長度可介於約12nm以及約25nm之間，例如約16nm。
第27A圖以及第27B圖顯示一實施例，其中使用兩步驟佈植製程124A-B來形成膨脹區130。參照上文的第23圖及第26圖，在一些情況下，在佈植製程124所佈植的摻質遷移穿過氣隙120且進入靠近氣隙120的底部的摻質區128。在一些情況下，摻質區128可位於鰭片52的通道區58附近。在一些情況下，摻質區128中的摻質可導致通道電阻增加，或者可導致其他不想要的影響，例如佈植損害。在第27A圖以及第27B圖中顯示的兩步驟佈植製程124A-B可減少遷移進入氣隙120的摻質的量，且因此可減少摻質區128的尺寸或者摻質濃度。在一些情況下，兩步驟佈植製程124A-B可阻止摻質形成摻質區128。在一些實施例中，兩步驟佈植製程124A-B包括佈植能量或劑量相對較小的第一佈植製程124A，以及隨後的佈植能量或劑量相對較大的第二佈植製程124B。在一些實施例中，第一佈植製程124A的佈植角度、摻質種類、溫度、或其他參數可與第二佈植製程124B不同。
參照第27A圖，在形成蓋層122之後執行第一佈植製程124A，相似於第23圖。在一些實施例中，第一佈植製程124A使用相對小的第一佈植能量，且因此第一佈植深度D2相對地較淺。舉例來說，第一佈植深度D2可介於約0nm (例如：位於或靠近第二層間介電質層108的頂部)以及約5nm之間，例如約1nm。如第27A圖所示，第一佈植製程124A形成密封氣隙120的第一膨脹區130A。第一膨脹區130A阻止由第二佈植製程124B所佈植的摻質遷移至氣隙120中。由於相對較小的第一佈植能量，少量摻質進入氣隙120中，且因此摻質區128較小及／或具有較小的摻質濃度。舉例來說，由第一佈植製程124A所形成的摻質區128可小於上文關於第23圖或第26圖所描述的佈植製程所形成的摻質區。
參照第27B圖，第二佈植製程124B在第一佈植製程124A之後執行。在一些實施例中，第二佈植製程124B使用相對大的第二佈植能量，且因此第二佈植深度D3大於第一佈植深度D2。舉例來說，第二佈植深度D3可介於約1nm及約10nm之間，例如約5nm。如第27B圖中所示，第二佈植製程124B增加第一膨脹區130A的尺寸，以形成進一步密封氣隙120的第二膨脹區130B。第二膨脹區130B大於第一膨脹區130A，且相較於第一膨脹區130A更完整地密封氣隙120。由於第一膨脹區130A的存在，阻止了由第二佈植製程124B佈植的摻質遷移至氣隙120中。因此，阻止了來自第二佈植製程124B的摻質到達摻質區128。在一些情況下，由整體的兩步驟佈植製程124A-B所形成的摻質區128可小於由以上所描述的第23圖或第26圖的佈植步驟124所形成的摻雜區。使用此方法，可藉由使用如本文所述的兩步驟佈植製程124A-B來減少或消除由摻質區128所造成的不想要的影響。
參照第28圖與第29圖，其中顯示在形成蓋層122之前執行佈植製程124的一實施例。如第28圖中所示，在垂直膨脹不受蓋層122的限制的情況下，佈植製程124導致第二層間介電質層108橫向膨脹以及垂直膨脹。除了形成膨脹區130的橫向膨脹之外，垂直膨脹導致第二層間介電質層108的厚度增加。在一些實施例中，第二層間介電質層108的厚度可增加介於約0.5nm與約3nm之間距離的D4。舉例來說，第29圖顯示測量上方不具有蓋層122的第二層間介電質的厚度的實驗數據400。數據400顯示第二層間介電質層在佈植製程124之前的厚度，以及第二層間介電質層108在執行佈植製程124之後的厚度。標示於“Ref”的點顯示出第二層間介電質層108在執行佈植製程124之前的厚度，而其餘的點顯示出第二層間介電質層108在執行使用兩種不同的佈植劑量的佈植製程124之後的厚度。如第29圖所示，在沒有上方的蓋層122情況下，第二層間介電質層108的厚度因垂直膨脹而增加。數據400也顯示較高的佈植劑量可導致第二層間介電質層有較大程度的垂直膨脹。
第30A圖至第32B圖為根據一些實施例的製造鰭式場效電晶體的額外階段的剖面圖。第30A圖至32B圖顯示與第14A圖和14B圖中所顯示的結構相同的截面圖。第30A圖與第30B圖顯示形成膨脹區130之後的結構，例如在執行第26圖中所描述的佈植製程124之後，或是在執行第27A圖與第27B圖中所描述的兩步驟佈植製程124A-B之後。
在第31A圖與第31B圖，形成穿過蓋層122、第二層間介電質層108以及硬遮罩96的閘極接觸件132。首先可穿過蓋層122、第二層間介電質層108以及硬遮罩96形成閘極接觸件132的開口。可使用可接受的光微影及蝕刻技術來形成開口。在開口中形成襯層（例如：擴散阻障層(diffusion barrier layer)、附著層(adhesion layer)或類似者）以及導電材料。襯層可包括鈦、氮化鈦、鉭、氮化鉭、類似者、或上述的組合。導電材料可為銅、銅合金、銀、金、鎢、鈷、鋁、鎳、類似者、或上述的組合。可執行平坦化製程（例如化學機械研磨）以從蓋層122的表面移除多餘的材料。剩餘的襯層與導電材料在開口中形成閘極接觸件132。閘極接觸件132實體耦合且電性耦合至閘極電極94。源極／汲極接觸件118與閘極接觸件132可在不同製程中形成，或者可在同一製程中形成。雖然顯示為在同一剖面中形成，應當理解每個源極／汲極接觸件118與閘極接觸件132也可在不同剖面中形成，其可避免接觸件的短路。
在第32A圖與第32B圖中，根據一些實施例形成導電部件136以接觸源極／汲極接觸件118。導電部件 136可包括一條或多條金屬線及／或一個或多個導孔，使其與源極／汲極接觸件118實體接觸且電性接觸。在一些實施例中，也可形成一些接觸閘極接觸件132的導電部件136（在第32A圖與第32B圖中未顯示）。導電部件136可為，例如，重分布層(redistribution layer)。可用任何適合的技術形成導電部件136。
在一些實施例中，可先在蓋層122上形成介電質層134，且導電部件136形成於介電質層134中。介電質層134可由適合的介電材料形成，例如低介電常數介電材料、高分子（例如聚醯亞胺(polyimide)）、氧化矽、氮化矽、碳化矽、碳氮化矽、碳氮氧化矽、類似者、或上述的組合。可使用適合的製程形成介電質層134，例如旋轉塗布、CVD、PVD、ALD或類似者。可穿過介電質層134與蓋層122形成導電部件136的開口（未繪示），以露出源極／汲極接觸件118。可使用可接受的光微影與蝕刻技術形成開口。在一些情況下，使用膨脹區130密封氣隙120可避免氣隙120在形成開口時露出。舉例來說，由於例如光微影失準(photolithographic misalignment)，開口可以形成為在氣隙120上延伸。使用此方法，阻擋了後續沉積的材料進入氣隙120。
在一些實施例中，可使用單一及／或雙鑲嵌(damascene)製程、導孔優先製程(via-first process)或是金屬優先製程(metal-first process)來形成導電部件136的材料。在開口中形成襯層（例如：擴散阻障層、附著層或類似者）以及導電材料。襯層可包括鈦、氮化鈦、鉭、氮化鉭、或類似者，可使用像是CVD、ALD或類似者的沉積製程來形成。導電材料可為銅、銅合金、銀、金、鎢、鈷、鋁、鎳、類似者、或上述的組合。可以藉由電化學電鍍(electro-chemical plating)製程、CVD、ALD、PVD、類似者或上述的組合在開口中的擴散阻擋層上方形成導電材料。襯層的材料及／或導電材料被膨脹區130阻擋進入氣隙120。可執行平坦化製程（例如化學機械研磨）以從介電質層134的表面移除多餘的材料。剩餘的襯層與導電材料形成導電部件136。在其他實施例中，可使用其他技術形成導電部件136。
第33A圖與第33B圖繪示出在形成蓋層122之前執行佈植製程124的一實施例中，導電部件136的形成。在第33A-B圖中顯示的實施例與先前關於第28圖與第29圖描述的實施例相似。如第33A-B圖所示，沒有蓋層122所提供的對於垂直膨脹的限制，佈植製程124導致第二層間介電質層108的厚度增加。第二層間介電質層108的平坦度也可能減少。形成導電部件136以接觸源極／汲極接觸件118，且可與前文關於第32A-B圖所描述的導電部件類似。
本文的實施例可實現一些優點。藉由在鰭式場效電晶體裝置的源極／汲極接觸件與閘極堆疊之間形成氣隙，可減少源極／汲極接觸件與閘極堆疊之間的電容值。電容值的減少可改善鰭式場效電晶體裝置的速度或者高頻率操作。此外，藉由使用摻質佈植層間介電質層來密封氣隙的頂部。被佈植的摻質導致層間介電質層膨脹且延伸跨越氣隙，而將氣隙密封。藉由密封氣隙，可阻擋不想要的材料進入氣隙因而降低裝置效能或者導致製程缺陷。在一些情況下，使用獨立的兩個佈植步驟可減少靠近鰭式場效電晶體裝置的通道區的佈植摻質的量。此外，藉由在佈植摻質之前形成蓋層，可抑制層間介電質層的垂直膨脹，導致更均勻的頂面。
在一些實施例中，一種半導體裝置包括延伸自半導體基底的鰭片；於鰭片上的閘極堆疊；於閘極堆疊的側壁上的第一間隔物；在鄰近於第一間隔物的鰭片中的源極／汲極區；延伸至閘極堆疊、第一間隔物以及源極／汲極區上方的層間介電質(ILD)層，此層間介電質層包括第一部分以及第二部分，其中層間介電質層的第二部分比層間介電質的第一部分更靠近閘極堆疊；延伸穿過層間介電質層，並且接觸源極／汲極區的接觸插塞；於接觸插塞的側壁上的第二間隔物；以及於第一間隔物與第二間隔物之間的氣隙，其中層間介電質層的第一部分延伸跨過氣隙，並且實體接觸第二間隔物，其中層間介電質層的第一部分將氣隙密封。在一實施例中，層間介電質層具有第一厚度，且其中層間介電質層的第二部分具有介於第一厚度的10%至105%之間的第二厚度。在一實施例中，半導體裝置包括於閘極堆疊與第一間隔物上的蝕刻停止層，其中蝕刻停止層的一部分暴露於氣隙。在一實施例中，層間介電質層的第一部分具有第一摻質濃度，以及其中層間介電質層的第二部分具有低於第一摻質濃度的第二摻質濃度。在一實施例中，摻質包括Ge、Ar、Si或Xe。在一實施例中，第二間隔物比氣隙更延伸靠近半導體基板。在一實施例中，接觸插塞比氣隙更延伸靠近半導體基板。在一實施例中，第二間隔物包括氮化矽。在一實施例中，裝置包括於層間介電質層上的蓋層。在一實施例中，層間介電質層的第一部分上的蓋層的第一區域比起層間介電質層的第二部分上的蓋層的第二區域更加延伸靠近半導體基板。
在一些實施例中，一種半導體裝置包括從基板突出的鰭片；於鰭片的通道區上的閘極結構；在鄰近於通道區的鰭片中的磊晶區；於閘極結構上的第一介電質層，此第一介電質層包括以第一摻質摻雜的第一區域；延伸穿過第一介電質層，且接觸磊晶區的接觸插塞；於第一介電質層上的第二介電質層；以及於接觸插塞與閘極結構之間的氣隙，其中氣隙的上部區以第一區域為邊界，並且其中氣隙藉由第一區域與第二介電質層分離。在一實施例中，氣隙的下部區以磊晶區為邊界。在一實施例中，磊晶區鄰近於氣隙的區域被第一摻質摻雜。在一實施例中，第一區域中的第一摻質的最大濃度在第一介電質層的頂面的下方介於1nm與5nm之間處。在一實施例中，第一區域包括第一摻質的濃度，此濃度介於1019 cm-3 與 1022 cm-3 之間。在一實施例中，第二介電質層的一部分突出至第一區域中。
在一些實施例中，一種半導體裝置形成方法包括形成閘極堆疊於半導體鰭片上；形成磊晶源極／汲極區於鄰近於閘極堆疊的半導體鰭片中；沉積第一介電質層於閘極堆疊上，且於磊晶源極／汲極區上；形成開口於第一介電質層中，以露出磊晶源極／汲極區；沉積犧牲材料於開口中；沉積導電材料於開口中的犧牲材料上；移除犧牲材料以形成凹槽；以及以摻質佈植第一介電質層，其中在佈植第一介電質層之後，凹槽被第一介電質層覆蓋。在一實施例中，犧牲材料為矽。在一實施例中，此方法包括沉積第二介電質層於開口中的犧牲材料上。在一實施例中，此方法包括在佈植第一介電質層之前沉積第三介電質層於第一介電質層上。
以上概述數個實施例之部件，以便在本揭露所屬技術領域中具有通常知識者可更易理解本揭露的觀點。在本揭露所屬技術領域中具有通常知識者應理解，他們能以本揭露為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及∕或優勢。在本揭露所屬技術領域中具有通常知識者也應理解到，此類等效的製程和結構並無悖離本揭露的精神與範圍，且他們能在不違背本揭露之精神和範圍之下，做各式各樣的改變、取代和替換。
50:基板 50N,50P,89,111:區域 51:分離符號 52:鰭片 54:絕緣材料 56:淺溝槽隔離區 58:通道區 60:虛置介電質層 62:虛置閘極層 64:遮罩層 72:虛置閘極 74:遮罩 80:閘極密封間隔物 82:磊晶源極／汲極區 86:閘極間隔物 87:接觸蝕刻停止層 88:第一層間介電質 90:凹槽 92:閘極介電質層 94:閘極電極 94A:襯層 94B:功函數調整層 94C:填充材料 96:硬遮罩 108:第二層間介電質 110:開口 112:虛置間隔物層 114:接觸間隔物層 116:矽化物區 118:源極／汲極接觸件 120:氣隙 122:蓋層 124:佈植製程 126:佈植區 128:摻質區 130:膨脹區 130A:第一膨脹區 130B:第二膨脹區 132:閘極接觸件 134:介電質層 136:導電元件 200:輪廓 202A,202B:曲線 300,400:實驗數據 A-A,B-B,C-C:截面 D1:佈植深度 D2:第一佈植深度 D3:第二佈植深度 D4:距離 L1:長度 W1,W2:寬度
配合所附圖式來閱讀以下詳細敘述為理解本揭露的各個方面的最佳方式。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製。事實上，為了清楚地起見，可能任意地放大或縮小元件的尺寸。 第1圖根據一些實施例繪示出鰭式場效電晶體的3D視圖的例子。 第2、3、4、5、6、7、8A、8B、9A、9B、10A、10B、10C、10D、11A、11B、12A、12B、13A、13B、14A、14B、14C、15A以及15B圖為根據一些實施例之製造鰭式場效電晶體的中間階段的剖面圖。 第16、17、18、19、20、21、22及23圖為根據一些實施例之製造具有氣隙的鰭式場效電晶體的中間階段的剖面圖。 第24圖根據一些實施例顯示摻質濃度輪廓的實驗數據。 第25圖根據一些實施例顯示測量上方具有蓋層的層間介電質的厚度的實驗數據。 第26、27A、27B以及28圖為根據一些實施例之製造具有氣隙的鰭式場效電晶體的中間階段的剖面圖。 第29圖根據一些實施例顯示測量上方不具有蓋層的層間介電質的厚度的實驗數據。 第30A、30B、31A、31B、32A、32B、33A以及33B 圖為根據一些實施例之製造具有氣隙的鰭式場效電晶體的中間階段的剖面圖。
50:基板
52:鰭片
58:通道區
82:磊晶源極/汲極區
86:閘極間隔物
92:閘極介電質層
94:閘極電極
96:硬遮罩
108:第二層間介電質
114:接觸間隔物層
116:矽化物區
118:源極/汲極接觸件
120:氣隙
122:蓋層
124:佈植製程
126:佈植區
128:摻質區
130:膨脹區
D1:佈植深度

Claims (20)

  1. 一種半導體裝置，包括： 一鰭片，延伸自一半導體基底； 一閘極堆疊，於該鰭片上； 一第一間隔物，於該閘極堆疊的一側壁上； 一源極／汲極區，在鄰近於該第一間隔物的該鰭片中； 一層間介電質(ILD)層，延伸至該閘極堆疊、該第一間隔物以及該源極／汲極區上方，該層間介電質層包括一第一部分以及一第二部分，其中該層間介電質層的該第二部分比該層間介電質的該第一部分更靠近該閘極堆疊； 一接觸插塞，延伸穿過該層間介電質層，並且接觸該源極／汲極區； 一第二間隔物，於該接觸插塞的一側壁上；以及 一氣隙(air gap)，於該第一間隔物與該第二間隔物之間，其中該層間介電質層的該第一部分延伸跨過該氣隙，並且實體接觸該第二間隔物，其中該層間介電質層的該第一部分將該氣隙密封。
  2. 如請求項1所述之半導體裝置，其中該層間介電質層具有一第一厚度，且其中該層間介電質層的該第二部份具有介於該第一厚度的10%至105%之間的一第二厚度。
  3. 如請求項1所述之半導體裝置，更包括一蝕刻停止層於該閘極堆疊上與該第一間隔物上，其中該蝕刻停止層的一部份暴露於該氣隙。
  4. 如請求項1所述之半導體裝置，其中該層間介電質層的該第一部分具有一第一摻質濃度，以及其中該層間介電質層的該第二部分具有低於該第一摻質濃度的一第二摻質濃度。
  5. 如請求項4所述之半導體裝置，其中該第一摻質濃度的該摻質包括Ge、Ar、Si或Xe。
  6. 如請求項1所述之半導體裝置，其中該第二間隔物比該氣隙更延伸靠近該半導體基板。
  7. 如請求項1所述之半導體裝置，其中該接觸插塞比該氣隙更延伸靠近該半導體基板。
  8. 如請求項1所述之半導體裝置，其中該第二間隔物包括氮化矽。
  9. 如請求項1所述之半導體裝置，更包括一蓋層於該層間介電質層上。
  10. 如請求項9所述之半導體裝置，其中該層間介電質層的該第一部分上的該蓋層的一第一區域比起該層間介電質層的該第二部分上的該蓋層的一第二區域更加延伸靠近該半導體基板。
  11. 一種半導體裝置，包括： 一鰭片，從一基板突出； 一閘極結構，於該鰭片的一通道區上； 一磊晶區，在鄰近於該通道區的該鰭片中； 一第一介電質層，於該閘極結構上，該第一介電質層包括以一第一摻質摻雜的一第一區域； 一接觸插塞，延伸穿過該第一介電質層，且接觸該磊晶區； 一第二介電質層，於該第一介電質層上；以及 一氣隙，於該接觸插塞與該閘極結構之間，其中該氣隙的一上部區以該第一區域為邊界，並且其中該氣隙藉由該第一區域與該第二介電質層分離。
  12. 如請求項11所述之半導體裝置，其中該氣隙的一下部區以該磊晶區為邊界。
  13. 如請求項11所述之半導體裝置，其中該磊晶區鄰近於該氣隙的一區域被該第一摻質摻雜。
  14. 如請求項11所述之半導體裝置，其中該第一區域中的該第一摻質的最大濃度在該第一介電質層的一頂面的下方介於1nm與5nm之間處。
  15. 如請求項11所述之半導體裝置，其中該第一區域包括該第一摻質的一濃度，該濃度介於1019 cm-3 與 1022 cm-3 之間。
  16. 如請求項11所述之半導體裝置，其中該第二介電質層的一部分突出至該第一區域中。
  17. 一種半導體裝置形成方法，包括： 形成一閘極堆疊於一半導體鰭片上； 形成一磊晶源極／汲極區於鄰近於該閘極堆疊的該半導體鰭片中； 沉積一第一介電質層於該閘極堆疊上，且於該磊晶源極／汲極區上； 形成一開口於該第一介電質層中，以露出該磊晶源極／汲極區； 沉積一犧牲材料於該開口中； 沉積一導電材料於該開口中的該犧牲材料上； 移除該犧牲材料以形成一凹槽；以及 以一摻質佈植該第一介電質層，其中在佈植該第一介電質層之後，該凹槽被該第一介電質層覆蓋。
  18. 如請求項17所述之半導體裝置形成方法，其中該犧牲材料為矽。
  19. 如請求項17所述之半導體裝置形成方法，更包括沉積一第二介電質層於該開口中的該犧牲材料上。
  20. 如請求項17所述之半導體裝置形成方法，更包括在佈植該第一介電質層之前沉積一第三介電質層於該第一介電質層上。
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