TWI792439B - 半導體元件的製造方法 - Google Patents

半導體元件的製造方法 Download PDF

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TWI792439B
TWI792439B TW110127075A TW110127075A TWI792439B TW I792439 B TWI792439 B TW I792439B TW 110127075 A TW110127075 A TW 110127075A TW 110127075 A TW110127075 A TW 110127075A TW I792439 B TWI792439 B TW I792439B
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Taiwan
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layer
source
region
metal layer
semiconductor
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TW110127075A
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TW202238762A (zh
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林芮萍
李振銘
楊復凱
王美勻
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例提供一種方法，包含：形成閘極堆疊，經 由磊晶在閘極堆疊的一側上生長源極/汲極區，在源極/汲極區上方沉積接觸蝕刻終止層(CESL)，在CESL上方沉積層間介電質，蝕刻層間介電質及CESL以形成接觸開口，以及蝕刻源極/汲極區以使得接觸開口延伸至源極/汲極區中。方法更包含沉積延伸至接觸開口中的金屬層。金屬層的水平部分、豎直部分以及拐角部分具有實質上均勻的厚度。執行退火製程以使金屬層與源極/汲極區反應，從而形成源極/汲極矽化物區。填充接觸開口以形成源極/汲極接觸插塞。

Description

半導體元件的製造方法
本發明實施例是有關於一種電晶體的製作方法。
隨著積體電路的大小的持續縮小，接觸電阻在改良積體電路的效能方面起著愈來愈重要的作用。源極/汲極矽化物區與上覆接觸插塞之間的接觸電阻是效能改良的因素中的一者。
根據本發明的一些實施例，一種半導體元件的製造方法包括：形成閘極堆疊；經由磊晶在閘極堆疊的一側上生長源極/汲極區；在源極/汲極區上方沉積CESL；在CESL上方沉積層間介電質；蝕刻層間介電質及CESL以形成接觸開口；蝕刻源極/汲極區以使得接觸開口延伸至源極/汲極區中；沉積延伸至接觸開口中的金屬層，其中金屬層的水平部分、豎直部分以及拐角部分具有實質上均勻的厚度；執行退火製程以使金屬層與源極/汲極區反應，其中形成源極/汲極矽化物區；以及填充接觸開口以形成源極/汲極接觸插塞。
根據本發明的一些實施例，一種半導體元件的製造方法 包括：蝕刻層間介電質及CESL以形成接觸開口且顯露半導體區，其中半導體區位於多層堆疊的旁邊，且多層堆疊包括多個犧牲層及多個半導體層，且其中多個犧牲層及多個半導體層交替安置；蝕刻半導體區以使接觸開口進一步延伸至半導體區中，其中半導體區具有高於多層堆疊的第二頂部表面的第一頂部表面，且執行蝕刻半導體區直至接觸開口的底部表面低於多個半導體層中的最頂部半導體層的頂部表面；沉積金屬層，其中金屬層延伸至接觸開口中；在金屬層上方沉積頂蓋層；以及執行退火製程，其中使金屬層的底部部分與半導體區反應以形成矽化物區。
根據本發明的一些實施例，一種半導體元件的製造方法包括：蝕刻層間介電質及層間介電質之下的CESL以形成接觸開口，其中經由接觸開口顯露CESL之下的半導體區；沉積延伸至開口中的介電層開口；對介電層執行非等向性蝕刻製程以移除介電層的水平部分，其中介電層的豎直部分保留在開口中以形成介電環；使用PECVD製程來沉積延伸至開口中的金屬層；以及使用PVD製程在金屬層上方沉積氮化鈦層；以及使金屬層的底部部分與半導體區反應以形成矽化物區，金屬層沉積為共形層，且氮化鈦層沉積為非共形層。
10:晶圓
10C-10C,16C-16C,28B-28B,28C-28C,A1-A1,A2-A2,B-B:參考 橫截面
20,120:基底
20':基底條
22,22':多層堆疊
22A:第一層
22B:第二層
23,78:溝渠
24:半導體條
26,126:隔離區
26T:頂部表面
28:突出鰭片
30:虛設閘極堆疊
32:虛設閘極介電質
34:虛設閘極電極
36:硬罩幕
38:閘極間隙壁
38':鰭式間隙壁
41:橫向凹口
42,58:凹口
44:內間隙壁
48:區
48-1,48-2,148,148-1,148-2:源極/汲極區
48A,48B,48C,148A,148B,148C:子層
49:空隙
50,150:CESL
52,76,152,176:ILD
62:閘極介電質
68:閘極電極
70,170:閘極堆疊
74,174:閘極罩幕
75,175:蝕刻終止層
78BOT:底部表面
79:位置
80:介電層
80':介電層
82:介電區
83:頂部表面
84,184:金屬層
85:拐角區
86,90,190:頂蓋層
88,188,188-1,188-2:矽化物區
88':延伸區
92:填充金屬
94,194:源極/汲極接觸插塞
96:GAA電晶體
98:閘極接觸插塞
178:源極/汲極接觸開口
180:層
187B:區
192:金屬填充區
196:鰭式場效電晶體
200:製程流程
202,204,206,208,210,212,214,216,218,220,222,224,226,228,230,232,234,236,238,240,242,244,246:製程
D1:深度
LD1:橫向尺寸
T1,T3:底部厚度
T2,T4:側壁厚度
當結合隨附圖式閱讀時，根據以下詳細描述最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，出於論述清楚起見，可任意地增大或減小各種特徵的尺寸。
圖1至圖4、圖5A、圖5B、圖6A、圖6B、圖7A、圖7B、圖8A、圖8B、圖9A、圖9B、圖10A、圖10B、圖10C、圖11A、圖11B、圖12A、圖12B、圖13A、圖13B、圖14A、圖14B、圖15A、圖15B、圖16A、圖16B、圖16C、圖17A、圖17B、圖18A、圖18B、圖18C、圖19A、圖19B、圖20A、圖20B、圖20C、圖21A、圖21B、圖22A、圖22B、圖22C、圖23A、圖23B、圖23C、圖24A以及圖24B示出根據一些實施例的形成全環繞閘極(Gate All-Around；GAA)電晶體及接觸插塞的中間階段的橫截面圖。
圖25至圖27、圖28A、圖28B以及圖28C示出根據一些實施例的形成鰭式場效電晶體(Fin Field-Effect Transistor；FinFET)的接觸插塞的透視圖及橫截面圖。
圖29示出根據一些實施例的形成GAA電晶體及接觸插塞的製程流程。
以下揭露內容提供用於實施本發明的不同特徵的許多不同的實施例或實例。下文描述組件及配置的特定實例以簡化本揭露。當然，此等組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，在第二特徵上方或上形成第一特徵可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦可包含可在第一特徵與第二特徵之間形成額外特徵以使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及清楚的目的，且本身並不指示所論述的各種實施例及/或組態之間的關係。
此外，為易於描述，本文中可使用諸如「在......之下」、「在......下方」、「下部」、「上覆」、「上部」以及類似者的空間相對術語來描述如圖式中所示出的一個元件或特徵與另一元件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
本發明實施例提供一種電晶體、接觸插塞以及形成其的方法。根據本揭露的一些實施例，在形成電晶體的源極/汲極接觸插塞時，蝕刻源極/汲極區上方的接觸蝕刻終止層(Contact Etch Stop Layer；CESL)及層間介電質(Inter-Layer Dielectric；ILD)以顯露源極/汲極區。亦深度蝕刻源極/汲極區以形成延伸至源極/汲極區中的接觸開口。隔離層形成為延伸至接觸開口中，且使用共形沉積方法以形成延伸至接觸開口中的金屬層，所述金屬層與源極/汲極區形成源極/汲極矽化物區。藉由採用共形沉積製程，金屬層在其需要較厚之處較厚，因此矽化物區可在隨後形成的源極/汲極接觸插塞的拐角處較厚。源極/汲極矽化物區為源極/汲極接觸插塞提供大型著陸區域。因此減小了接觸電阻。本文中所論述的實施例將提供使得能夠製造或使用本揭露的主題的實例，且所屬領域中具通常知識者將易於理解在保持於不同實施例的所涵蓋範疇內的同時可進行的修改。貫穿各個視圖及說明性實施例，相同的附圖標號用於指代相同元件。儘管方法實施例可論述為以特定次序執行，但其他方法實施例可以任何邏輯次序執行。
圖1至圖4、圖5A、圖5B、圖6A、圖6B、圖7A、圖 7B、圖8A、圖8B、圖9A、圖9B、圖10A、圖10B、圖10C、圖11A、圖11B、圖12A、圖12B、圖13A、圖13B、圖14A、圖14B、圖15A、圖15B、圖16A、圖16B、圖16C、圖17A、圖17B、圖18A、圖18B、圖18C、圖19A、圖19B、圖20A、圖20B、圖20C、圖21A、圖21B、圖22A、圖22B、圖22C、圖23A、圖23B、圖23C、圖24A以及圖24B示出根據本揭露的一些實施例的形成環繞式閘極(GAA)電晶體的中間階段的橫截面圖。對應製程亦示意性地反映於圖29中所繪示的製程流程200中。
參考圖1，繪示晶圓10的透視圖。晶圓10包含多層結構，所述多層結構包括基底20上的多層堆疊22。根據一些實施例，基底20為半導體基底，所述半導體基底可為矽基底、矽鍺(silicon germanium；SiGe)基底或類似者，同時可使用其他基底及/或結構，諸如絕緣層上半導體(semiconductor-on-insulator；SOI)、應變SOI、絕緣層上矽鍺或類似者。基底20可摻雜為p型半導體，但在其他實施例中，其可摻雜為n型半導體。
根據一些實施例，多層堆疊22經由用於沉積交替材料的一系列沉積製程而形成。相應製程在圖29中所繪示的製程流程200中示出為製程202。根據一些實施例，多層堆疊22包括由第一半導體材料形成的第一層22A及由與第一半導體材料不同的第二半導體材料形成的第二層22B。
根據一些實施例，第一層22A的第一半導體材料由以下各者形成或包括以下各者：SiGe、Ge、Si、GaAs、InSb、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb或類似者。根據一些實施例，第一層22A(例如，SiGe)的沉積是經由磊晶生長，且對應沉積 方法可為氣相磊晶(Vapor-Phase Epitaxy；VPE)、分子束磊晶(Molecular Beam Epitaxy；MBE)、化學氣相沉積(Chemical Vapor deposition；CVD)、低壓CVD(Low Pressure CVD；LPCVD)、原子層沉積(Atomic Layer Deposition；ALD)、超高真空CVD(Ultra High Vacuum CVD；UHVCVD)、減壓CVD(Reduced Pressure CVD；RPCVD)或類似者。根據一些實施例，第一層22A形成為在約30埃與約300埃之間的範圍內的第一厚度。然而，在保持在實施例的範疇內的同時可使用任何合適的厚度。
一旦第一層22A已沉積於基底20上方，第二層22B則沉積於第一層22A上方。根據一些實施例，第二層22B由諸如以下各者的第二半導體材料形成或包括所述第二半導體材料：Si、SiGe、Ge、GaAs、InSb、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、其組合或類似者，其中第二半導體材料與第一層22A的第一半導體材料不同。舉例而言，根據第一層22A為矽鍺的一些實施例，第二層22B可由矽形成，或反之亦然。應瞭解，材料的任何合適組合可用於第一層22A及第二層22B。
根據一些實施例，第二層22B使用與用於形成第一層22A的沉積技術類似的沉積技術磊晶生長於第一層22A上。根據一些實施例，第二層22B形成為與第一層22A的厚度類似的厚度。第二層22B亦可形成為與第一層22A不同的厚度。根據一些實施例，第二層22B可形成為在例如約10埃與約500埃之間的範圍內的第二厚度。
一旦第二層22B已形成於第一層22A上方，則重複沉積製程，以在多層堆疊22中形成剩餘層，直至已形成多層堆疊22 的所要最頂部層。根據一些實施例，第一層22A具有彼此相同或類似的厚度，且第二層22B具有彼此相同或類似的厚度。第一層22A亦可具有與第二層22B的厚度相同或不同的厚度，根據一些實施例，第一層22A在後續製程中移除，且在整個描述中替代地稱為犧牲層22A。根據替代實施例，第二層22B是犧牲的，且在後續製程中移除。
根據一些實施例，一些襯墊氧化物層及硬罩幕層(未繪示)形成於多層堆疊22上方。這些層經圖案化，且用於多層堆疊22的後續圖案化。
參考圖2，在蝕刻製程中圖案化多層堆疊22及下伏基底20的一部分，以使得形成溝渠23。相應製程在圖29中所繪示的製程流程200中示出為製程204。溝渠23延伸至基底20中。多層堆疊的剩餘部分在下文中稱為多層堆疊22'。在多層堆疊22'之下，保留基底20的一些部分，且在下文中稱為基底條20'。多層堆疊22'包含半導體層22A及半導體層22B。在下文中，半導體層22A替代地稱為犧牲層，且半導體層22B替代地稱為奈米結構。多層堆疊22'的部分及下伏基底條20'統稱為半導體條24。
在上文所示出的實施例中，可藉由任何合適的方法圖案化GAA電晶體結構。舉例而言，可使用一或多個微影製程(包含雙圖案化製程或多圖案化製程)來圖案化所述結構。大體而言，雙重圖案化製程或多重圖案化製程將微影製程與自對準製程合併，從而使具有例如小於可另外使用單個、直接微影製程獲得的圖案的間距的圖案得以產生。舉例而言，在一個實施例中，犧牲層形成於基底上方且使用微影製程經圖案化。間隙壁使用自對準 製程形成於圖案化犧牲層旁邊。接著移除犧牲層，且剩餘間隙壁可接著用於圖案化GAA結構。
圖3示出隔離區26的形成，所述隔離區26在整個描述中亦稱為淺溝渠隔離(Shallow Trench Isolation；STI)區。相應製程在圖29中所繪示的製程流程200中示出為製程206。STI區26可包含內襯氧化物(未繪示)，所述內襯氧化物可為經由基底20的表面層的熱氧化而形成的熱氧化物。內襯氧化物亦可為使用例如ALD、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition；HDPCVD)、CVD或類似者形成的沉積氧化矽層。STI區26亦可包含內襯氧化物上方的介電材料，其中可使用可流動化學氣相沉積(Flowable Chemical Vapor Deposition；FCVD)、旋轉塗佈、HDPCVD或類似者來形成介電材料。可接著執行諸如化學機械研磨(Chemical Mechanical Polish；CMP)製程或機械磨削製程的平坦化製程來使介電材料的頂部表面齊平，且介電材料的剩餘部分為STI區26。
接著使STI區26凹陷，以使得半導體條24的頂部部分突出高於STI區26的剩餘部分的頂部表面26T以形成突出鰭片28。突出鰭片28包含多層堆疊22'且可包含基底條20'的頂部部分。可經由乾式蝕刻製程執行STI區26的凹陷，其中NF3及NH3例如用作蝕刻氣體。在蝕刻製程期間，可產生電漿。亦可包含氬氣。根據本揭露的替代實施例，經由濕式蝕刻製程執行STI區26的凹陷。舉例而言，蝕刻化學品可包含HF。
參考圖4，虛設閘極堆疊30及閘極間隙壁38形成於(突出)鰭片28的頂部表面及側壁上。相應製程在圖29中所繪示的 製程流程200中示出為製程208。虛設閘極堆疊30可包含虛設閘極介電質32及在虛設閘極介電質32上方的虛設閘極電極34。可藉由氧化突出鰭片28的表面部分以形成氧化層或藉由沉積諸如氧化矽層的介電層來形成虛設閘極介電質32。可例如使用多晶矽或非晶矽來形成虛設閘極電極34，亦可使用其他材料，諸如非晶碳。虛設閘極堆疊30中的每一者亦可包含虛設閘極電極34上方的一個(或多個)硬罩幕36。硬罩幕36可由氮化矽、氧化矽、碳氮化矽、氧碳氮化矽或其多層形成。虛設閘極堆疊30可跨接單個或多個突出鰭片28及突出鰭片28之間的STI區26。虛設閘極堆疊30亦具有與突出鰭片28的縱向方向垂直的縱向方向。虛設閘極堆疊30的形成包含：形成虛設閘極介電層，在虛設閘極介電層上方沉積虛設閘極電極層，沉積一或多個硬罩幕層以及接著經由圖案化製程圖案化所形成層。
接著，閘極間隙壁38形成於虛設閘極堆疊30的側壁上。根據本揭露的一些實施例，閘極間隙壁38由諸如以下各者的介電材料形成：氮化矽(SiN)、氧化矽(SiO2)、碳氮化矽(SiCN)、氮氧化矽(SiON)、氧碳氮化矽(SiOCN)或類似者，且可具有單層結構或包含多個介電層的多層結構。閘極間隙壁38的形成製程可包含沉積一個或多個介電層，且接著對介電層執行非等向性蝕刻製程。介電層的剩餘部分為閘極間隙壁38。
圖5A及圖5B示出圖4中所繪示的結構的橫截面圖。圖5A示出圖4中的參考橫截面A1-A1、A2-A2，所述橫截面切割穿過突出鰭片28的未由閘極堆疊30及閘極間隙壁38覆蓋的部分，且垂直於閘極長度方向。亦示出位於突出鰭片28的側壁上的鰭式 間隙壁38'。圖5B示出圖4中的參考橫截面B-B，所述參考橫截面平行於突出鰭片28的縱向方向。
參考圖6A及圖6B，突出鰭片28的不直接位於虛設閘極堆疊30及閘極間隙壁38之下的部分經由蝕刻製程凹陷以形成凹口42。相應製程在圖29中所繪示的製程流程200中示出為製程210。舉例而言，可使用C2F6；CF4；SO2；HBr、Cl2以及O2的混合物；HBr、Cl2、O2以及CH2F2的混合物；或類似者來執行乾式蝕刻製程以蝕刻多層半導體堆疊22'及下伏基底條20'。凹口42的底部至少與多層半導體堆疊22'的底部齊平或可低於(如圖6B中所繪示)所述底部。蝕刻可為非等向性的，以使得多層半導體堆疊22'的面向凹口42的側壁為豎直且筆直的，如圖6B中所繪示。
參考圖7A及圖7B，使犧牲半導體層22A橫向凹陷以形成橫向凹口41，所述橫向凹口41自相應上覆及下伏奈米結構22B的邊緣凹陷。相應製程在圖29中所繪示的製程流程200中示出為製程212。犧牲半導體層22A的橫向凹陷可經由濕式蝕刻製程達成，所述濕式蝕刻製程使用對犧牲半導體層22A的材料(例如，矽鍺(SiGe))比對奈米結構22B及基底20的材料(例如，矽(Si))更具選擇性的蝕刻劑。舉例而言，在犧牲半導體層22A由矽鍺形成且奈米結構22B由矽形成的實施例中，可使用諸如鹽酸(HCl)的蝕刻劑來執行濕式蝕刻製程。濕式蝕刻製程可使用浸漬製程、噴塗製程、旋轉塗佈製程或類似者來執行，且可使用任何合適的製程溫度(例如，在約400℃與約600℃之間)執行。根據替代實施例，經由等向性乾式蝕刻製程或乾式蝕刻製程與濕式蝕刻製程的組合來執行犧牲半導體層22A的橫向凹陷。
參考圖8A及圖8B，內間隙壁44形成於橫向凹口41中。相應製程在圖29中所繪示的製程流程200中示出為製程214。內間隙壁44充當隨後形成的源極/汲極區與閘極結構之間的隔離特徵。形成製程可包含沉積共形介電層且接著微調共形介電層。內間隙壁層可藉由諸如CVD、ALD或類似者的共形沉積製程沉積。內間隙壁層可包括諸如氮化矽或氮氧化矽的材料，但可利用任何合適的材料，諸如具有k值小於約3.5的低介電常數(低k)材料。可接著非等向性蝕刻內間隙壁層以形成內間隙壁44。
儘管內間隙壁44的內側壁及外側壁在圖9B中示意性地示出為筆直的，但內間隙壁44的內側壁可以是凸出的，且內間隙壁44的外側壁可以是凹入的或凸出的。內間隙壁44可用於防止對隨後形成的源極/汲極區的損壞，所述損壞可由用於形成替換閘極結構的後續蝕刻製程引起。
參考圖9A及圖9B，磊晶源極/汲極區48形成於凹口42中。相應製程在圖29中所繪示的製程流程200中示出為製程216。根據一些實施例，源極/汲極區48可對用作對應GAA電晶體的通道的奈米結構22B施加應力，藉此改良效能。取決於所得電晶體為p型電晶體抑或n型電晶體，p型雜質或n型雜質可利用磊晶的續行(proceeding)來進行原位摻雜。舉例而言，當所得電晶體為p型電晶體時，可生長矽鍺硼(SiGeB)、矽硼(SiB)或類似者。相反，當所得電晶體為n型電晶體時，可生長矽磷(SiP)、矽碳磷(SiCP)或類似者。在凹口42填充有磊晶區48之後，磊晶區48的進一步磊晶生長使得磊晶區48水平地擴展且可形成小平面(facets)。磊晶區48的進一步生長亦可使得相鄰磊晶區48彼此合 併。可產生空隙(空氣間隙)49(圖9A)。根據一些實施例，磊晶區48可包含表示為48A、48B以及48C的多個子層。子層具有不同濃度/原子百分比的矽、鍺以及摻雜物。
在磊晶製程之後，磊晶區48可進一步植入有p型雜質或n型雜質以形成亦使用參考標號48表示的源極區及汲極區。根據本揭露的替代實施例，當磊晶區48在磊晶期間原位摻雜有p型雜質或n型雜質時跳過植入製程，且磊晶區48亦為源極/汲極區。
圖10A、圖10B以及圖10C示出形成CESL 50及ILD 52之後的結構的橫截面圖。相應製程在圖29中所繪示的製程流程200中示出為製程218。圖10C示出圖10B中的參考橫截面10C-10C。CESL 50可由氧化矽、氮化矽、碳氮化矽或類似者形成，且可使用CVD、ALD或類似者形成。ILD 52可包含使用例如FCVD、旋轉塗佈、CVD或任何其他適合的沉積方法形成的介電材料。ILD 52可由含氧介電材料形成，所述含氧介電材料可為矽氧化物類材料，諸如氧化矽、磷矽酸鹽玻璃(Phospho-Silicate Glass；PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass；BSG)、硼摻雜磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass；BPSG)、未摻雜矽酸鹽玻璃(Undoped Silicate Glass；USG)或類似者。
圖11A及圖11B至圖14A及圖14B示出用於形成替換閘極堆疊的製程。在圖11A及圖11B中，執行諸如CMP製程或機械磨削製程的平坦化製程以使ILD 52的頂部表面齊平。相應製程在圖29中所繪示的製程流程200中示出為製程220。根據一些實施例，平坦化製程可移除硬罩幕36以顯露虛設閘極電極34，如圖11A中所繪示。根據替代實施例，平坦化製程可顯露硬罩幕36且 止於硬罩幕36。根據一些實施例，在平坦化製程之後，虛設閘極電極34(或硬罩幕36)、閘極間隙壁38以及ILD 52的頂部表面在製程變化內齊平。
接著，在一或多個蝕刻製程中移除虛設閘極電極34(及硬罩幕36，若剩餘)，以使得形成凹口58，如圖12A及圖12B中所繪示。相應製程在圖29中所繪示的製程流程200中示出為製程222。亦移除虛設閘極介電質32在凹口58中的部分。根據一些實施例，經由非等向性乾式蝕刻製程移除虛設閘極電極34及虛設閘極介電質32。舉例而言，可使用以比ILD 52更快的速率選擇性地蝕刻虛設閘極電極34的反應氣體來執行蝕刻製程。每一凹口58暴露及/或上覆多層堆疊22'的包含隨後完成的奈米FET中的未來通道區的部分。多層堆疊22'的所述部分位於相鄰對磊晶源極/汲極區48之間。
接著移除犧牲層22A以在奈米結構22B之間延伸凹口58，且所得結構繪示於圖13A及圖13B中。相應製程在圖29中所繪示的製程流程200中示出為製程224。犧牲層22A可藉由執行使用對犧牲層22A的材料更具選擇性的蝕刻劑的諸如濕式蝕刻製程的等向性蝕刻製程移除，而與犧牲層22A相比，奈米結構22B、基底20、STI區26保持相對不蝕刻。根據犧牲層22A包含例如SiGe，且奈米結構22B包含例如Si或SiC的一些實施例，可使用四甲基氫氧化銨(tetra methyl ammonium hydroxide；TMAH)、氫氧化銨(NH4OH)或類似者以移除犧牲層22A。
參考圖14A及圖14B，形成閘極介電質62。相應製程在圖29中所繪示的製程流程200中示出為製程226。根據一些實施 例，閘極介電質62中的每一者包含界面層及界面層上的高k介電層。界面層可由氧化矽形成或包括氧化矽，所述氧化矽可經由諸如ALD或CVD的共形沉積製程沉積。根據一些實施例，高k介電層包括一或多個介電層。舉例而言，高k介電層可包含以下各者的金屬氧化物或矽酸鹽：鉿、鋁、鋯、鑭、錳、鋇、鈦、鉛以及其組合。
接著形成閘極電極68。在形成時，導電層首先形成於高k介電層上且填充凹口58的剩餘部分。相應製程在圖29中所繪示的製程流程200中示出為製程228。閘極電極68可包含含金屬的材料，諸如TiN、TaN、TiAl、TiAlC、鈷、釕、鋁、鎢、其組合及/或其多層。舉例而言，儘管在圖14A及圖14B中，示出單層以表示閘極電極68，但閘極電極68可包括任何數目個層，所述任何數目個層包含任何數目個頂蓋/黏著層、功函數層以及可能的填充材料。閘極介電質62及閘極電極68亦填充奈米結構22B的鄰近者之間的空間，且填充奈米結構22B的底部奈米結構與下伏基底條20'之間的空間。在填充凹口58之後，執行諸如CMP製程或機械磨削製程的平坦化製程以移除閘極介電質及閘極電極68的材料的多餘部分，所述多餘部分位於ILD 52的頂部表面上方。閘極電極68及閘極介電質62統稱為所得奈米FET的閘極堆疊70。
在圖15A及圖15B中所繪示的製程中，使閘極堆疊70凹陷，以使得凹口直接形成於閘極堆疊70上方及閘極間隙壁38的相對部分之間。包括介電材料(諸如氮化矽、氮氧化矽或類似者)的一或多個層的閘極罩幕74填充於凹口中的每一者中，隨後執行平坦化製程以移除在ILD 52上方延伸的介電材料的多餘部 分。相應製程在圖29中所繪示的製程流程200中示出為製程230。
如由圖15A及圖15B進一步示出，蝕刻終止層75及ILD 76沉積於ILD 52上方及閘極罩幕74上方。相應製程在圖29中所繪示的製程流程200中示出為製程232。根據一些實施例，蝕刻終止層75經由ALD、CVD、PECVD或類似者形成，且可由氮化矽、碳化矽、氮氧化矽、氧化鋁、氮化鋁或類似者或其多層形成。ILD 76經由FCVD、CVD、PECVD或類似者形成。ILD 76由介電材料形成，所述介電材料可由氧化矽、PSG、BSG、BPSG、USG或類似者中選出。
圖16A、圖16B、圖16C、圖17A、圖17B、圖18A、圖18B、圖18C、圖19A、圖19B、圖20A、圖20B、圖20C、圖21A、圖21B、圖22A、圖22B、圖22C、圖23A、圖23B以及圖23C示出根據一些實施例的源極/汲極矽化物區及源極/汲極接觸插塞的形成。參考圖16A、圖16B以及圖16C，蝕刻ILD 76、蝕刻終止層75、ILD 52以及CESL 50以形成溝渠78。相應製程在圖29中所繪示的製程流程200中示出為製程234。圖16C示出圖16B中的參考橫截面16C-16C，其中溝渠78自第一電晶體的第一源極/汲極區48(亦稱為源極/汲極區48-1)延伸至第二電晶體的第二源極/汲極區48(亦稱為源極/汲極區48-2)。根據一些實施例，源極/汲極區48-1為p型電晶體的p型源極/汲極區，且源極/汲極區48-2為n型電晶體的n型源極/汲極區。源極/汲極區48-1及源極/汲極區48-2彼此相鄰，且藉由介電區82彼此分隔開。介電區82可為CESL 50及ILD 52的部分，或可為除CESL 50及ILD 52之外的另一介電區。根據一些實施例，介電區82未凹陷，且突出高 於溝渠78的底部表面78BOT。根據替代實施例，亦使介電區82凹陷為與溝渠78的底部表面78BOT相同的水平或低於所述底部表面。使用虛線示出介電區82的對應頂部表面83。
根據一些實施例，可使用相同製程氣體或不同製程來蝕刻ILD 76、蝕刻終止層75以及ILD 52。接著，蝕刻CESL 50以顯露下伏源極/汲極區48(包含源極/汲極區48-1源極/汲極區48-2)。蝕刻製程可為乾式蝕刻製程或濕式蝕刻製程，且蝕刻化學品取決於CESL 50、ILD 76、蝕刻終止層75以及ILD 52的材料。在蝕刻穿過CESL 50之後，執行額外乾式蝕刻製程以蝕刻源極/汲極區48，以使得溝渠78延伸至源極/汲極區48中。蝕刻氣體可包含CxHyFz、HBr、Cl2及/或類似者。此外，蝕刻氣體可與CESL 50的蝕刻氣體不同(若採用乾式蝕刻)。蝕刻源極/汲極區48的處理條件可與蝕刻CESL 50的處理條件不同。舉例而言，用於源極/汲極區48的乾式蝕刻的偏壓功率可高於用於CESL 50的乾式蝕刻的偏壓功率。根據一些實施例，溝渠78以深度D1延伸至源極/汲極區48中，所述深度D1可大於約5奈米，且可在約5奈米與約10奈米之間的範圍內。
再次參考圖16B，根據本揭露的一些實施例，溝渠78的底部78BOT低於多個奈米結構22B當中的最頂部奈米結構22B。溝渠78的底部78BOT亦可相對於多個奈米結構22B的水平高度而處於各種水平高度。舉例而言，繪製多個虛線以展示溝渠78的底部78BOT的可能位置79。舉例而言，底部78BOT可與最頂部奈米結構22B的頂部或底部齊平或低於所述頂部或底部，或可與自頂部計數(以最頂奈米結構22B為第一奈米結構往下計數)的 第二奈米結構22B或第三奈米結構22B的頂部或底部齊平或低於所述頂部或底部。例如使底部溝渠78降低為與最頂部奈米結構22B的頂部或甚至底部齊平或低於所述頂部或甚至底部可改良裝置效能。然而，形成深度延伸至源極/汲極區48中的溝渠78可引起矽化物區的後續形成的問題。因此，調整製程以解決彼等問題，如後續段落中所論述。
參考圖17A及圖17B，形成介電層80。根據一些實施例，介電層80由介電材料(諸如氮化矽、氮氧化矽、氧化矽、氧碳氮化矽或類似者)形成。接著，執行非等向性蝕刻製程以移除介電層80的水平部分，從而留下介電層80的豎直部分作為形成環的隔離層。在圖18A、圖18B以及圖18C中示出所得結構。相應製程在圖29中所繪示的製程流程200中示出為製程236。參考圖18C，當介電區82具有低於凹入源極/汲極區48的頂部表面的頂部表面83時，介電層80可在源極/汲極區48的側壁上延伸，其中對應介電層80示出為虛線介電層80'。
參考圖19A、圖19B以及圖19C，沉積金屬層84(諸如鈦層或鈷層或類似者)。相應製程在圖29中所繪示的製程流程200中示出為製程238。歸因於溝渠78的延伸深度，可經由諸如PECVD製程的共形沉積製程來執行金屬層84的沉積。根據一些實施例，可藉由使用諸如TiClx的金屬鹵化物作為處理氣體來沉積金屬層84。氫氣(H2)亦可用作處理氣體的一部分。TiClx與氫氣反應以形成元素鈦及HCl，且HCl氣體經由真空抽吸抽空。可在約300℃與約500℃之間的範圍內的溫度下執行反應。作為共形沉積製程的結果，金屬層84的不同部分(諸如水平部分、豎直部分以及拐角 部分)具有均勻厚度或實質上均勻的厚度。金屬層84的底部厚度T1及側壁厚度T2彼此相等或接近，例如其中比率|T1-T2|/T2小於約20%或小於約10%。根據一些實施例，金屬層84的厚度T1及厚度T2可在約1奈米與約4奈米之間的範圍內。
圖19A、圖19B以及圖19C進一步示出頂蓋層86的沉積，所述頂蓋層86可為金屬氮化物層，諸如氮化鈦層。相應製程亦在圖29中所繪示的製程流程200中示出為製程238。根據一些實施例，使用CVD、PVD、PECVD或類似者形成頂蓋層86。頂蓋層86的底部厚度T3及側壁厚度T4可彼此相等或接近，例如其中比率|T3-T4|/T4小於約20%或約10%。替代地，底部厚度T3大於側壁厚度T4。舉例而言，比率(T3-T4)/T4可大於約0.5或大於約1.0，且可在約1.0與約5.0之間的範圍內。
參考圖20A、圖20B以及圖20C，執行退火製程。根據一些實施例，在約400℃與約600℃之間的範圍內的溫度下執行退火製程。金屬層84、頂蓋層86的沉積及退火製程可在其間沒有真空破壞(vacuum break)的情況下在相同環境下原位執行。歸因於用於沉積金屬層84的高溫，且進一步歸因於退火製程，金屬層84的底部部分與源極/汲極區48反應以形成矽化物區88。相應製程在圖29中所繪示的製程流程200中示出為製程240。在退火製程之後保留金屬層84的側壁部分。矽化物區88可由矽化物及/或鍺化物形成。
在後續製程中，可在蝕刻製程中移除頂蓋層86。根據一些實施例，執行額外蝕刻製程以移除金屬層84的剩餘部分。根據替代實施例，剩餘金屬層84未經蝕刻，且保留於最終接觸插塞中。
圖21A及圖21B示出另一頂蓋層90的沉積，所述頂蓋層90可包括金屬氮化物，諸如氮化鈦。相應製程在圖29中所繪示的製程流程200中示出為製程242。接著，如圖22A、圖22B以及圖22C中所繪示，沉積填充金屬92，諸如鈷、鎢、鋁或類似者。相應製程在圖29中所繪示的製程流程200中示出為製程244。可執行諸如CMP製程或機械磨削製程的平坦化製程以移除多餘材料。相應製程在圖29中所繪示的製程流程200中示出為製程246。所得結構繪示於圖23A、圖23B以及圖23C中。包含導電層90及填充金屬92(及金屬層84，若未移除)的剩餘導電層統稱為源極/汲極接觸插塞94。
返回參考圖19B，藉由使用共形沉積製程來沉積金屬層84，金屬層84具有均勻厚度。特定言之，諸如區85的底部拐角區處的金屬層84的厚度具有與其他部分(諸如豎直部分及水平部分)的厚度相同的厚度。所得矽化物區88的大小/厚度與金屬層84的厚度相關。因此，矽化物區88的接近底部拐角區85的部分(圖20B)亦具有增加的厚度。此使得矽化物區88具有延伸區88'(圖23B)，且延伸矽化物區88'亦為厚的。根據一些實施例，延伸區88'的橫向尺寸LD1大於約2奈米，且可在約2奈米與約3奈米之間的範圍內。厚且寬的延伸矽化物區88'的形成增大了源極/汲極接觸插塞94的低電阻著陸區的大小，且改良了GAA電晶體的效能。在接觸插塞的習知接觸形成製程中，PVD用於沉積金屬層84。然而，PVD產生不均勻的厚度。舉例而言，在拐角區85(圖19B)中，金屬層84極薄，且延伸矽化物區88'(圖23B)並不存在或具有極小厚度。矽化物區88的接近拐角的末端部分亦極薄且具有 高電阻。
圖24A及圖24B示出閘極接觸插塞98的形成。形成製程包含蝕刻ILD 76、蝕刻終止層75以及閘極罩幕74以顯露閘極電極68，填充導電材料，諸如Ti、TiN、W、Co或類似者，且執行平坦化製程。因此，形成GAA電晶體96。
圖25至圖27、圖28A、圖28B以及圖28C示出根據一些實施例的形成FinFET 196(圖28A)的源極/汲極區的橫截面圖及透視圖。圖28B示出圖28A中的參考橫截面28B-28B。圖28C示出圖28A中的參考橫截面28C-28C。用GAA電晶體96中的對應特徵的附圖標號加數字「100」表示FinFET 196中的特徵。舉例而言，GAA電晶體96中的源極/汲極區表示為48，且因此FinFET 196中的源極/汲極區表示為源極/汲極區148(包含源極/汲極區148-1及源極/汲極區148-2)，且可包含子層148A、子層148B以及子層148C(圖28B)。基底表示為基底120(圖25)，隔離區表示為隔離區126(圖25)，閘極罩幕表示為174(圖28A)。FinFET 196中的特徵的材料及形成製程亦可與GAA電晶體96中的相同特徵類似，且不在本文中重複。
如圖28A、圖28B以及圖28C中所繪示，FinFET 196包含閘極堆疊170以及源極/汲極區148-1及源極/汲極區148-2(圖28B)。源極/汲極區148-1及源極/汲極區148-2中的每一者可屬於p型或n型。示出CESL 150、ILD 152、蝕刻終止層175以及ILD 176。亦示出源極/汲極接觸插塞194及矽化物區188(包含矽化物區188-1及矽化物區188-2)。
圖28B及圖28C示出源極/汲極區148-1及源極/汲極區 148-2以及矽化物區188-1及矽化物區188-2的詳細視圖。接觸插塞194包含頂蓋層190(諸如氮化鈦)及金屬填充區192。
可使用與用於形成接觸插塞94(圖24B)相同的製程來形成如圖28B及圖28C中所繪示的接觸插塞194。圖25至圖27示出實例製程的橫截面圖。亦可參考前述實施例來發現材料、形成製程以及結構的細節。參考圖25，形成源極/汲極區148-1及源極/汲極區148-2，且彼此接近。CESL 150共形地形成於源極/汲極區148-1及源極/汲極區148-2上，且ILD 152形成於CESL 150上方。蝕刻ILD 152及CESL 150以形成源極/汲極接觸開口178。接著，如圖26中所繪示，深度蝕刻源極/汲極區148-1及源極/汲極區148-2，例如其中移除的頂部部分具有大於約5奈米或在約5奈米與約10奈米之間的範圍內的厚度。介電層(與圖17B及圖18B中的層180類似，未繪示)可或可不形成為延伸至源極/汲極接觸開口178中。圖27示出金屬層184的形成，所述金屬層184使用諸如PECVD的共形沉積製程沉積。金屬層184可(在不同部分之間)具有小於約20%或小於約10%的厚度變化。後續製程與圖19A/圖19B至圖24A/圖24B中所繪示的製程基本上相同，且在未在本文中示出。所得FinFET 196如圖28A、圖28B以及圖28C中所繪示。
應瞭解，源極/汲極區148的深度蝕刻可改良所得電晶體的效能。然而，深度蝕刻使得所得金屬層184在PVD用於形成金屬層184時為更非共形的，金屬層184將在區187A(圖25)中為厚的，且在區187B中為薄的。因此，形成於區187B中的矽化物區將是薄的且小的，且接觸電阻將是高的。此外，區187A中及ILD 176上方的過厚金屬層184可能需要額外製程來移除。
本揭露的實施例具有一些有利特徵。藉由深蝕刻源極/汲極區，改良所得電晶體的效能。藉由使用共形沉積製程來形成用於形成矽化物區的金屬層，所得矽化物區的邊緣部分是厚的，且矽化物區具有用於上覆源極/汲極接觸插塞的增加的著陸區。因此，金屬層的共形沉積亦解決由源極/汲極區的深度蝕刻引入的問題。
根據本揭露的一些實施例，一種方法包括：形成閘極堆疊；經由磊晶在閘極堆疊的一側上生長源極/汲極區；在源極/汲極區上方沉積CESL；在CESL上方沉積層間介電質；蝕刻層間介電質及CESL以形成接觸開口；蝕刻源極/汲極區以使得接觸開口延伸至源極/汲極區中；沉積延伸至接觸開口中的金屬層，其中金屬層的水平部分、豎直部分以及拐角部分具有實質上均勻的厚度；執行退火製程以使金屬層與源極/汲極區反應，其中形成源極/汲極矽化物區；以及填充接觸開口以形成源極/汲極接觸插塞。在一實施例中，使用PECVD製程來沉積金屬層。在一實施例中，方法更包括在金屬層上方沉積氮化鈦層，其中氮化鈦層沉積為具有側壁厚度及大於側壁厚度的底部厚度。在一實施例中，使用PVD製程來沉積氮化鈦層。在一實施例中，使用第一蝕刻化學品來蝕刻CESL，且使用與第一蝕刻化學品不同的第二蝕刻化學品來蝕刻源極/汲極區。在一實施例中，閘極堆疊形成於包括交替安置的多個奈米結構及多個犧牲層的多層堆疊上，且接觸開口具有與多個奈米結構中的最頂部奈米結構的底部表面齊平或低於所述底部表面的底部。在一實施例中，接觸開口的底部與多個奈米結構中的第 二奈米結構的頂部表面齊平或低於所述頂部表面，其中第二奈米結構自最頂部奈米結構向下計數。在一實施例中，源極/汲極矽化物區橫向延伸超出源極/汲極接觸插塞的邊緣大於約2奈米的距離。在一實施例中，方法更包括：在沉積金屬層之前，沉積延伸至接觸開口中的介電層；以及蝕刻以移除介電層的水平部分，其中介電層的豎直部分保留在接觸開口中以形成介電環。在一實施例中，藉由使金屬鹵化物與氫氣反應來形成金屬層。
根據本揭露的一些實施例，一種方法包括：蝕刻層間介電質及CESL以形成接觸開口且顯露半導體區，其中半導體區位於多層堆疊的旁邊，且多層堆疊包括多個犧牲層及多個半導體層，且其中多個犧牲層及多個半導體層交替安置；蝕刻半導體區以使接觸開口進一步延伸至半導體區中，其中半導體區具有高於多層堆疊的第二頂部表面的第一頂部表面，且執行蝕刻半導體區直至接觸開口的底部表面低於多個半導體層中的最頂部半導體層的頂部表面；沉積金屬層，其中金屬層延伸至接觸開口中；在金屬層上方沉積頂蓋層；以及執行退火製程，其中使金屬層的底部部分與半導體區反應以形成矽化物區。在一實施例中，金屬層為共形的，且頂蓋層為非共形的且包括水平部分，所述水平部分具有大於頂蓋層的豎直部分的第二厚度的第一厚度。在一實施例中，使用PECVD來執行沉積金屬層。在一實施例中，使用PVD來執行沉積頂蓋層。在一實施例中，使用濕式蝕刻製程來蝕刻CESL，且使用乾式蝕刻製程來蝕刻半導體區。使用乾式蝕刻製程來蝕刻CESL及半導體區兩者，且使用不同蝕刻氣體來蝕刻CESL及半導體區。
根據本揭露的一些實施例，一種方法包括：蝕刻層間介電質及層間介電質之下的CESL以形成接觸開口，其中經由接觸開口顯露CESL之下的半導體區；沉積延伸至開口中的介電層開口；對介電層執行非等向性蝕刻製程以移除介電層的水平部分，其中介電層的豎直部分保留在開口中以形成介電環；使用PECVD製程來沉積延伸至開口中的金屬層；以及使用PVD製程在金屬層上方沉積氮化鈦層；以及使金屬層的底部部分與半導體區反應以形成矽化物區，金屬層沉積為共形層，且氮化鈦層沉積為非共形層。在一實施例中，金屬層包括鈦，且沉積金屬層包括使用氯化鈦作為前驅體。在一實施例中，方法更包括在顯露半導體區之後，改變蝕刻化學品以進一步蝕刻半導體區。
前述概述若干實施例的特徵，使得所屬領域中具通常知識者可更佳地理解本揭露的態樣。所屬領域中具通常知識者應瞭解，其可易於使用本揭露作為設計或修改用於進行本文中所引入的實施例的相同目的及/或實現相同優點的其他製程及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬領域中具通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
200:製程流程
202,204,206,208,210,212,214,216,218,220,222,224,226,228,230,232,234,236,238,240,242,244,246:製程

Claims (9)

  1. 一種半導體元件的製造方法，包括：形成閘極堆疊；經由磊晶在所述閘極堆疊的一側上生長源極/汲極區；在所述源極/汲極區上方沉積接觸蝕刻終止層(CESL)；在所述CESL上方沉積層間介電質；蝕刻所述層間介電質及所述CESL以形成接觸開口；蝕刻所述源極/汲極區以使得所述接觸開口延伸至所述源極/汲極區中；使用電漿增強化學氣相沉積(PECVD)製程來沉積延伸至所述接觸開口中的金屬層，其中所述金屬層的水平部分、豎直部分以及拐角部分具有實質上均勻的厚度；執行退火製程以使所述金屬層與所述源極/汲極區反應，其中形成源極/汲極矽化物區；以及填充所述接觸開口以形成源極/汲極接觸插塞。
  2. 如請求項1所述的方法，其中使用第一蝕刻化學品來蝕刻所述CESL，且使用與所述第一蝕刻化學品不同的第二蝕刻化學品來蝕刻所述源極/汲極區。
  3. 如請求項1所述的方法，其中所述閘極堆疊形成於包括交替安置的多個奈米結構及多個犧牲層的多層堆疊上，且所述接觸開口具有與所述多個奈米結構中的最頂部奈米結構的底部表面齊平或低於所述底部表面的底部。
  4. 如請求項1所述的方法，其中所述源極/汲極矽化物區橫向延伸超出所述源極/汲極接觸插塞的邊緣大於約2奈米的距 離。
  5. 如請求項1所述的方法，更包括：在沉積所述金屬層之前，沉積延伸至所述接觸開口中的介電層；以及蝕刻以移除所述介電層的水平部分，其中所述介電層的豎直部分保留在所述接觸開口中以形成介電環。
  6. 一種半導體元件的製造方法，包括：蝕刻層間介電質及接觸蝕刻終止層(CESL)以形成接觸開口且顯露半導體區，其中所述半導體區位於多層堆疊的旁邊，且所述多層堆疊包括多個犧牲層及多個半導體層，且其中所述多個犧牲層及所述多個半導體層交替安置；蝕刻所述半導體區以使所述接觸開口進一步延伸至所述半導體區中，其中所述半導體區具有第一頂部表面，所述第一頂部表面高於所述多層堆疊的第二頂部表面，且執行所述蝕刻所述半導體區直至所述接觸開口的底部表面低於所述多個半導體層中的最頂部半導體層的頂部表面；使用電漿增強化學氣相沉積(PECVD)製程來沉積金屬層，其中所述金屬層延伸至所述接觸開口中；在所述金屬層上方沉積頂蓋層；以及執行退火製程，其中使所述金屬層的底部部分與所述半導體區反應以形成矽化物區。
  7. 如請求項6所述的方法，其中所述金屬層為共形的，且所述頂蓋層為非共形的且包括水平部分，所述水平部分具有第一厚度，所述第一厚度大於所述頂蓋層的豎直部分的第二厚度。
  8. 一種半導體元件的製造方法，包括：蝕刻層間介電質及所述層間介電質之下的接觸蝕刻終止層(CESL)以形成接觸開口，其中經由所述接觸開口顯露所述CESL之下的半導體區；沉積延伸至所述開口中的介電層；對所述介電層執行非等向性蝕刻製程以移除所述介電層的水平部分，其中所述介電層的豎直部分保留在所述開口中以形成介電環；使用電漿增強化學氣相沉積(PECVD)製程來沉積延伸至所述開口中的金屬層；以及使用物理氣相沉積(PVD)製程在所述金屬層上方沉積氮化鈦層；以及使所述金屬層的底部部分與所述半導體區反應以形成矽化物區。
  9. 如請求項8所述的方法，其中所述金屬層沉積為共形層，且所述氮化鈦層沉積為非共形層。
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