CN115172273A - 形成半导体器件的方法 - Google Patents

形成半导体器件的方法 Download PDF

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Publication number
CN115172273A
CN115172273A CN202210163300.6A CN202210163300A CN115172273A CN 115172273 A CN115172273 A CN 115172273A CN 202210163300 A CN202210163300 A CN 202210163300A CN 115172273 A CN115172273 A CN 115172273A
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layer
source
metal layer
contact
drain
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CN202210163300.6A
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林芮萍
李振铭
杨复凯
王美匀
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

形成半导体器件的方法包括：形成栅极堆叠件；通过外延在栅极堆叠件的侧上生长源极/漏极区；在源极/漏极区上方沉积接触蚀刻停止层(CESL)；在CESL上方沉积层间电介质；蚀刻层间电介质和CESL以形成接触开口；蚀刻源极/漏极区，使得接触开口延伸至源极/漏极区中。该方法还包括：沉积延伸至接触开口中的金属层。该金属层的水平部分、垂直部分和拐角部分具有基本均匀的厚度。执行退火工艺以使金属层与源极/漏极区反应，以形成源极/漏极硅化物区。填充该接触开口以形成源极/漏极接触插塞。

Description

形成半导体器件的方法
技术领域
本申请的实施例涉及形成半导体器件的方法。
背景技术
随着集成电路尺寸的不断缩小，接触电阻在提高集成电路性能提升方面发挥着越来越重要的作用。源极/漏极硅化物区与上面的接触插塞之间的接触电阻是性能提升的因素之一。
发明内容
本申请的一些实施例提供了一种形成半导体器件的方法，包括：形成栅极堆叠件；通过外延在所述栅极堆叠件的侧上生长源极/漏极区；在所述源极/漏极区上方沉积接触蚀刻停止层(CESL)；在所述接触蚀刻停止层上方沉积层间电介质；蚀刻所述层间电介质和所述接触蚀刻停止层以形成接触开口；蚀刻所述源极/漏极区，使得所述接触开口延伸至所述源极/漏极区中；沉积延伸至所述接触开口中的金属层，其中，所述金属层的水平部分、垂直部分和拐角部分具有基本均匀的厚度；执行退火工艺以使所述金属层与所述源极/漏极区反应，其中，形成源极/漏极硅化物区；以及填充所述接触开口以形成源极/漏极接触插塞。
本申请的另一些实施例提供了一种形成半导体器件的方法，包括：蚀刻层间电介质和接触蚀刻停止层(CESL)以形成接触开口并露出半导体区，其中，所述半导体区位于多层堆叠件的旁边，并且所述多层堆叠件包括多个牺牲层和多个半导体层，并且其中，所述多个牺牲层与所述多个半导体层交替定位；蚀刻所述半导体区以将所述接触开口进一步延伸至所述半导体区中，其中，所述半导体区具有高于所述多层堆叠件的第二顶面的第一顶面，并且蚀刻所述半导体区执行为直至所述接触开口的底面低于所述多个半导体层中的最顶半导体层的顶面；沉积金属层，其中，所述金属层延伸至所述接触开口中；在所述金属层上方沉积覆盖层；以及执行退火工艺，其中，所述金属层的底部与所述半导体区反应以形成硅化物区。
本申请的又一些实施例提供了一种形成半导体器件的方法，包括：蚀刻层间电介质和位于所述层间电介质下面的接触蚀刻停止层(CESL)以形成接触开口，其中，穿过所述接触开口露出位于所述接触蚀刻停止层下面的半导体区；沉积延伸至所述开口中的介电层；对所述介电层执行各向异性蚀刻工艺以去除所述介电层的水平部分，其中，所述介电层的垂直部分保留在所述开口中以形成介电环；使用等离子体增强化学气相沉积(PECVD)工艺来沉积延伸至所述开口中的金属层；以及使用物理气相沉积(PVD)工艺来在所述金属层上方沉积氮化钛层；以及使所述金属层的底部与所述半导体区反应以形成硅化物区。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图4、图5A、图5B、图6A、图6B、图7A、图7B、图8A、图8B、图9A、图9B、图10A、图10B、图10C、图11A、图11B、图12A、图12B、图13A、图13B、图14A、图14B、图15A、图15B、图16A、图16B、图16C、图17A、图17B、图18A、图18B、图18C、图19A、图19B、图20A、图20B、图20C、图21A、图21B、图22A、图22B、图22C、图23A、图23B、图23C、图24A和图24B示出根据一些实施例的形成全环栅(GAA)晶体管和接触插塞的中间阶段的截面图。
图25至图27、图28A、图28B和图28C示出根据一些实施例的形成用于鳍式场效应晶体管(FinFET)的接触插塞的立体图和截面图。
图29示出根据一些实施例的用于形成GAA晶体管和接触插塞的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
提供了晶体管、接触插塞及其形成方法。根据本发明的一些实施例，在晶体管的源极/漏极接触插塞的形成中，蚀刻源极/漏极区上方的接触蚀刻停止层(CESL)和层间电介质(ILD)以露出源极/漏极区。也深蚀刻源极/漏极区以形成延伸至源极/漏极区中的接触开口。形成延伸至接触开口内的隔离层，并且使用共形沉积方法形成延伸至接触开口内的金属层，该金属层与源极/漏极区形成源极/漏极硅化物区。通过采用共形沉积工艺，金属层在需要的地方更厚，因此硅化物区在后续形成的源极/漏极接触插塞的拐角处可能更厚。源极/漏极硅化物区为源极/漏极接触插塞提供较大的接合区。因此降低了接触电阻。本文讨论的实施例将提供实例，以使得能够进行或使用本发明的主题，并且本领域技术人员将容易理解可进行同时保持在不同实施例的预期范围内的修改。贯穿各个视图和说明性实施例，相似的参考标号用于指示相似的元件。尽管方法实施例可被讨论为以特定顺序执行，但其他方法实施例可以任何逻辑顺序执行。
图1至图4、图5A、图5B、图6A、图6B、图7A、图7B、图8A、图8B、图9A、图9B、图10A、图10B、图10C、图11A、图11B、图12A、图12B、图13A、图13B、图14A、图14B、图15A、图15B、图16A、图16B、图16C、图17A、图17B、图18A、图18B、图18C、图19A、图19B、图20A、图20B、图20C、图21A、图21B、图22A、图22B、图22C、图23A、图23B、图23C、图24A和图24B示出根据本发明的一些实施例的形成全环栅(GAA)晶体管的中间阶段的截面图。对应工艺也示意性地反映在如图29所示的工艺流程200中。
参考图1，示出晶圆10的立体图。晶圆10包括多层结构，该多层结构包括衬底20上的多层堆叠件22。根据一些实施例，衬底20是半导体衬底，该半导体衬底可以是硅衬底、硅锗(SiGe)衬底等，同时可使用其他衬底和/或结构，诸如绝缘体上半导体(SOI)应变SOI、绝缘体上硅锗等。衬底20可被掺杂为p型半导体，但在其他实施例中，它可被掺杂为n型半导体。
根据一些实施例，多层堆叠件22通过用于沉积交替材料的一系列沉积工艺形成。在图29所示的工艺流程200中，相应工艺被示出为工艺202。根据一些实施例，多层堆叠件22包括由第一半导体材料形成的第一层22A和由不同于第一半导体材料的第二半导体材料形成的第二层22B。
根据一些实施例，第一层22A的第一半导体材料由SiGe、Ge、Si、GaAs、InSb、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb等形成或包括以上材料。根据一些实施例，第一层22A(例如SiGe)的沉积是通过外延生长，并且对应的沉积方法可以是气相外延(VPE)、分子束外延(MBE)、化学气相沉积(CVD)、低压CVD(LPCVD)、原子层沉积(ALD)、超高真空CVD(UHVCVD)、减压CVD(RPCVD)等。根据一些实施例，第一层22A形成为介于约
Figure BDA0003515626460000041
与约
Figure BDA0003515626460000042
之间的范围内的第一厚度。然而，可使用任何合适的厚度同时保持在实施例的范围内。
一旦第一层22A已经沉积在衬底20上方，则第二层22B沉积在第一层22A上方。根据一些实施例，第二层22B由诸如Si、SiGe、Ge、GaAs、InSb、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、这些材料的组合等第二半导体材料形成或包括以上材料，第二半导体材料不同于第一层22A的第一半导体材料。例如，根据第一层22A是硅锗的一些实施例，第二层22B可由硅形成，反之亦然。应当了解，任何合适的材料组合可用于第一层22A和第二层22B。
根据一些实施例，使用类似于用于形成第一层22A的沉积技术来在第一层22A上外延生长第二层22B。根据一些实施例，第二层22B形成为与第一层22A的厚度类似的厚度。第二层22B也可形成为与第一层22A不同的厚度。根据一些实施例，第二层22B可形成为例如介于约
Figure BDA0003515626460000051
与约
Figure BDA0003515626460000052
Figure BDA0003515626460000053
之间的范围内的第二厚度。
一旦在第一层22A上方形成第二层22B，则重复沉积工艺以形成多层堆叠件22中的剩余层，直到形成多层堆叠件22的期望最顶层为止。根据一些实施例，第一层22A具有彼此相同或类似的厚度，并且第二层22B具有彼此相同或类似的厚度。第一层22A还可具有与第二层22B的厚度相同或不同的厚度。根据一些实施例，第一层22A在后续工艺中被去除，并且在整个说明书中可选地被称为牺牲层22A。根据可选的实施例，第二层22B是牺牲层，并且在后续工艺中被去除。
根据一些实施例，在多层堆叠件22上方形成有一些衬垫氧化物层和硬掩模层(未示出)。这些层被图案化，并用于多层堆叠件22的后续图案化。
参考图2，多层堆叠件22和下面的衬底20的一部分在蚀刻工艺中被图案化，从而形成沟槽23。在图29所示的工艺流程200中，相应工艺被示出为工艺204。沟槽23延伸至衬底20中。多层堆叠件的剩余部分在下文中被称为多层堆叠件22’。在多层堆叠件22’下面，衬底20的一些部分留下，并且在下文中被称为衬底条20’。多层堆叠件22’包括半导体层22A和22B。半导体层22A在下文中可选地被称为牺牲层，并且半导体层22B可选地被称为纳米结构。多层堆叠件22’的部分和下面的衬底条20’统称为半导体条24。
在上述实施例中，GAA晶体管结构可通过任何合适的方法图案化。例如，可以使用一种或多种光刻工艺来图案化结构，所述光刻工艺包括双重图案化或多重图案化工艺。通常，双重图案化或多重图案化工艺将光刻与自对准工艺相结合，从而允许创建例如间距小于可使用单个直接光刻工艺获得的间距的图案。例如，在一个实施例中，牺牲层形成在衬底上方，并使用光刻工艺进行图案化。使用自对准工艺在图案化牺牲层旁边形成间隔件。然后去除牺牲层，然后可以使用剩余的间隔件来图案化GAA结构。
图3示出隔离区26的形成，该等隔离区在整个说明书中也被称为浅槽隔离(STI)区。在图29所示的工艺流程200中，相应工艺被示出为工艺206。STI区26可包括衬垫氧化物(未示出)，该衬垫氧化物可以是通过衬底20的表面层的热氧化形成的热氧化物。衬垫氧化物也可以是使用例如ALD、高密度等离子体化学气相沉积(HDPCVD)、CVD等来形成的沉积氧化硅层。STI区26可还包括位于衬垫氧化物上方的介电材料，其中，可使用可流动化学气相沉积(FCVD)、旋涂、HDPCVD等来形成介电材料。然后可执行诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以使介电材料的顶面齐平，并且介电材料的剩余部分是STI区26。
然后使STI区26凹进，使得半导体条24的顶部突出高于STI区26的剩余部分的顶面26T，以形成突出鳍28。突出鳍28包括多层堆叠件22’并可包括衬底条20’的顶部。STI区26的凹进可通过干蚀刻工艺来执行，其中，NF3和NH3例如用作蚀刻气体。在蚀刻工艺期间，可以生成等离子体。也可包括氩气。根据本发明的可选的实施例，通过湿蚀刻工艺执行STI区26的凹进。例如，蚀刻化学物质可包括HF。
参考图4，在(突出)鳍28的顶面和侧壁上形成伪栅极堆叠件30和栅极间隔件38。在图29所示的工艺流程200中，相应工艺被示出为工艺208。伪栅极堆叠件30可包括伪栅极电介质32和位于伪栅极电介质32上方的伪栅电极34。可通过氧化突出鳍28的表面部分以形成氧化物层或通过沉积诸如氧化硅层的介电层来形成伪栅极电介质32。例如，可使用多晶硅或非晶硅来形成伪栅电极34，并且也可使用其他材料，诸如非晶碳。伪栅极堆叠件30中的每个也可以包括伪栅电极34上方的一个(或多个)硬掩模层36。硬掩模层36可由氮化硅、氧化硅、碳氮化硅、碳氮氧化硅或其多层形成。伪栅极堆叠件30可跨越单个或多个突出鳍28和突出鳍28之间的STI区26。伪栅极堆叠件30也具有与突出鳍28的纵长向方向垂直的纵长向方向。形成伪栅极堆叠件30包括形成伪栅极介电层，在伪栅极介电层上方沉积伪栅电极层，沉积一个或多个硬掩模层，然后通过图案化工艺对形成的层进行图案化。
接下来，在伪栅极堆叠件30的侧壁上形成栅极间隔件38。根据本发明的一些实施例，栅极间隔件38由诸如氮化硅(SiN)、氧化硅(SiO2)、碳氮化硅(SiCN)、氮氧化硅(SiON)、碳氮氧化硅(SiOCN)的介电材料形成，并可具有单层结构或包括多个介电层的多层结构。栅极间隔件38的形成工艺可包括沉积一个或多个介电层，然后对介电层执行行各向异性蚀刻工艺。介电层的剩余部分是栅极间隔件38。
图5A和图5B示出图4所示的结构的截面图。图5A示出图4中的参考截面A1-A1，该参考截面穿过突出鳍28的未被栅极堆叠件30和栅极间隔件38覆盖的部分，并且垂直于栅极纵长向方向。还示出突出鳍28的侧壁上的鳍间隔件38’。图5B示出图4中的参考截面B-B，该参考截面平行于突出鳍28的纵长向方向。
参考图6A和图6B，突出鳍28的不位于伪栅极堆叠件30和栅极间隔件38正下方的部分通过蚀刻工艺凹进以形成凹槽42。在图29所示的工艺流程200中，相应工艺被示出为工艺210。例如，可使用HBr、Cl2与O2的混合物、HBr、Cl2、O2与CH2F2的混合物、C2F6、CF4、SO2等执行干蚀刻工艺，来蚀刻多层半导体叠层22’和下面的衬底条20’。凹槽42的底部至少与多层半导体堆叠件22’的底部齐平或低于该底部(如图6B所示)。蚀刻可以是各向异性的，使得面向凹槽42的多层半导体堆叠件22’的侧壁是垂直且笔直的，如图6B所示。
参考图7A和图7B，牺牲半导体层22A横向凹进以形成横向凹槽41，该横向凹进从相应的上面和下面的纳米结构22B的边缘凹进。在图29所示的工艺流程200中，相应工艺被示出为工艺212。牺牲半导体层22A的横向凹进可通过湿蚀刻工艺实现，该蚀刻工艺使用对牺牲半导体层22A的材料(例如，硅锗(SiGe))比对纳米结构22B和衬底20的材料(例如，硅(Si))更具选择性的蚀刻剂。例如，在牺牲半导体层22A由硅锗形成并且纳米结构22B由硅形成的实施例中，可使用诸如盐酸(HCl)的蚀刻剂来执行湿蚀刻工艺。湿蚀刻工艺可使用浸渍工艺、喷涂工艺、旋涂工艺等来执行，并且可使用任何合适的工艺温度(例如，介于约400℃与约600℃之间)来执行。根据可选的实施例，牺牲半导体层22A的横向凹进通过各向同性干蚀刻工艺或干蚀刻工艺与湿蚀刻工艺的组合来执行。
参考图8A和图8B，在横向凹槽41中形成内部间隔件44。在图29所示的工艺流程200中，相应工艺被示出为工艺214。内部间隔件44用作后续形成的源极/漏极区与栅极结构之间的隔离部件。形成工艺可包括沉积共形介电层，然后修整共形介电层。可通过诸如CVD、ALD等的共形沉积工艺来沉积内部间隔件层。内部间隔件层可包括诸如氮化硅或氮氧化硅的材料，但可利用任何合适的材料，诸如k值小于约3.5的低介电常数(low-k)材料。然后可各向异性地蚀刻内部间隔件层以形成内部间隔件44。
尽管内部间隔件44的内侧壁和外侧壁在图9B中示意性地示出为直的，但内部间隔件44的内侧壁可以是凸的，并且内部间隔件44的外侧壁可以是凹的或凸的。内侧壁44可用于防止对后续形成的源极/漏极区的损坏，该损坏可能由后续用于形成替换栅极结构的蚀刻工艺引起。
参考图9A和图9B，在凹槽42中形成外延源极/漏极区48。在图29所示的工艺流程200中，相应工艺被示出为工艺216。根据一些实施例，源极/漏极区48可对用作对应GAA晶体管的沟道的纳米结构22B施加应力，从而提高性能。取决于所得晶体管是p型晶体管还是n型晶体管，可随着外延的进行来原位掺杂p型或n型杂质。例如，当所得晶体管是p型晶体管时，可生长硅锗硼(SiGeB)、硅硼(SiB)等。相反，当所得晶体管是n型晶体管时，可生长硅磷(SiP)、硅碳磷(SiCP)等。在凹槽42填充有外延区48之后，外延区48的进一步外延生长使得外延区48水平扩展，并且可形成小平面。外延区48的进一步生长也可使得相邻的外延区48彼此合并。可生成空隙(气隙)49(图9A)。根据一些实施例，外延区48可包括被表示为48A、48B和48C的多个子层。子层具有不同浓度/原子百分比的硅、锗、碳和掺杂剂。
在外延工艺之后，外延区48可进一步注入有p型或n型杂质以形成源极区和漏极区，也使用参考标号48表示。根据本发明的可选实施例，当在外延期间用p型或n型杂质原位掺杂外延区48时，跳过注入工艺，并且外延区48也是源极/漏极区。
图10A、图10B和图10C示出形成CESL 50和ILD 52之后结构的截面图。在图29所示的工艺流程200中，相应工艺被示出为工艺218。图10C示出图10B中的参考截面10C-10C。CESL 50可由氧化硅、氮化硅、碳氮化硅等形成，并可使用CVD、ALD等来形成。ILD 52可包括使用例如FCVD、旋涂、CVD或任何其他合适的沉积方法来形成的介电材料。ILD 52可由含氧介电材料形成，该含氧介电材料可以是基于氧化硅的材料，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼磷硅酸盐玻璃(BPSG)、未掺杂硅酸盐玻璃(USG)等。
图11A和图11B至图14A和图14B示出用于形成替换栅极堆叠件的工艺。在图11A和图11B中，执行诸如CMP工艺或机械研磨工艺的平坦化工艺以使ILD 52的顶面齐平。在图29所示的工艺流程200中，相应工艺被示出为工艺220。根据一些实施例，平坦化工艺可去除硬掩模36以露出伪栅电极34，如图11A所示。根据可选的实施例，平坦化工艺可露出并停止在硬掩模36上。根据一些实施例，在平坦化工艺之后，伪栅电极34(或硬掩模36)、栅极间隔件38和ILD 52的顶面在工艺变化内是齐平的。
接下来，在一个或多个蚀刻工艺中去除伪栅电极34(以及硬掩模36，如果剩余)，从而形成凹槽58，如图12A和图12B所示。在图29所示的工艺流程200中，相应工艺被示出为工艺222。凹槽58中的伪栅极电介质32的部分也被去除。根据一些实施例，通过各向异性干蚀刻工艺去除伪栅电极34和伪栅极电介质32。例如，可使用以比ILD 52更快的速率来选择性地蚀刻伪栅电极34的反应气体来执行蚀刻工艺。每个凹槽58暴露和/或覆盖多层堆叠件22’的部分，该部分包括随后完成的纳米FET中的将来的沟道区。多层堆叠件22’的部分位于外延源极/漏极区48的相邻对之间。
然后去除牺牲层22A以在纳米结构22B之间延伸凹槽58，并且所得结构在图13A和图13B中示出。在图29所示的工艺流程200中，相应工艺被示出为工艺224。可通过执行各向同性蚀刻工艺(诸如使用对牺牲层22A的材料具有选择性的蚀刻剂的湿蚀刻工艺)来去除牺牲层22A，而与牺牲层22A的材料相比，纳米结构22B、衬底20、STI区26相对地保持未蚀刻。根据牺牲层22A包括例如SiGe，并且纳米结构22B包括例如Si或SiC的一些实施例，四甲基氢氧化铵(TMAH)、氢氧化铵(NH4OH)等可用于去除牺牲层22A。
参考图14A和图14B，形成栅极电介质62。在图29所示的工艺流程200中，相应工艺被示出为工艺226。根据一些实施例，栅极电介质62中的每个包括界面层和界面层上的高k介电层。界面层可由氧化硅形成或包括氧化硅，该氧化硅可通过诸如ALD或CVD的共形沉积工艺来沉积。根据一些实施例，高k介电层包括一个或多个介电层。例如，高k介电层可包括铪、铝、锆、镧、锰、钡、钛、铅及其组合的金属氧化物或硅酸盐。
然后形成栅电极68。在形成中，首先在高k介电层上形成导电层并填充凹槽58的剩余部分。在图29所示的工艺流程200中，相应工艺被示出为工艺228。栅电极68可包括含金属材料，诸如TiN、TaN、TiAl、TiAlC、钴、钌、铝、钨、其组合和/或其多层。例如，尽管在图14A和图14B中，单层被示出为表示栅电极68，但是栅电极68可包括任何数量的层，包括任何数量的覆盖层/粘附层、功函层和可能的填充材料。栅极电介质62和栅电极68也填充相邻纳米结构22B之间的空间，并填充底部纳米结构22B与下面的衬底条20’之间的空间。在填充凹槽58之后，执行诸如CMP工艺或机械研磨工艺的平坦化工艺以去除栅极电介质的过量部分和栅电极68的材料，该等过量部分位于ILD 52的顶面上方。栅电极68和栅极电介质62统称为所得纳米FET的栅极堆叠件70。
在图15A和图15B所示的工艺中，使栅极堆叠件70凹进，从而在栅极堆叠件70正上方和栅极间隔件38的相对部分之间形成凹槽。将包括一层或多层介电材料(诸如氮化硅、氮氧化硅等)的栅极掩模74填充在每个凹槽中，然后进行平坦化工艺以去除介电材料的在ILD52上方延伸的过量部分。在图29所示的工艺流程200中，相应工艺被示出为工艺230。
如图15A和图15B进一步示出，蚀刻停止层75和ILD 76沉积在ILD 52上方和栅极掩模74上方。在图29所示的工艺流程200中，相应工艺被示出为工艺232。根据一些实施例，蚀刻停止层75通过ALD、CVD、PECVD等形成，并可由氮化硅、碳化硅、氮氧化硅、氧化铝、氮化铝等或其多层形成。ILD 76通过FCVD、CVD、PECVD等形成。ILD 76由介电材料形成，该介电材料可选自氧化硅、PSG、BSG、BPSG、USG等。
图16A、图16B、图16C、图17A、图17B、图18A、图18B、图18C、图19A、图19B、图20A、图20B、图20C、图21A、图21B、图22A、图22B、图22C、图23A、图23B和图23C示出根据一些实施例的硅化物区和源极/漏极接触插塞的形成。参考图16A、图16B和图16C，蚀刻ILD 76、蚀刻停止层75、ILD 52和CESL 50以形成沟槽78。在图29所示的工艺流程200中，相应工艺被示出为工艺234。图16C示出图16B中的参考截面16C-16C，其中，沟槽78从第一晶体管的第一源极/漏极区48(也被称为48-1)延伸至第二晶体管的第二源极/漏极区48(也被称为48-2)。根据一些实施例，源极/漏极区48-1是p型晶体管的p型源极/漏极区，而源极/漏极区48-2是n型晶体管的n型源极/漏极区。源极/漏极区48-1与48-2彼此相邻，并通过介电区82彼此分隔开。介电区82可以是CESL 50和ILD 52的一部分，或者可以是除CESL 50和ILD 52之外的另一介电区。根据一些实施例，介电区82不凹进，并且突出高于沟槽78的底面78BOT。根据可选的实施例，介电区82也凹进至与沟槽78的底面78BOT齐平或低于该底面78BOT。介电区82的对应顶面使用虚线83示出。
根据一些实施例，可使用相同的工艺气体或不同的工艺来蚀刻ILD 76、蚀刻停止层75和ILD 52。接下来，蚀刻CESL 50以露出下面的源极/漏极区48(包括48-1和48-2)。蚀刻工艺可以是干蚀刻工艺或湿蚀刻工艺，并且蚀刻化学物质取决于CESL 50、ILD 76、蚀刻停止层75和ILD 52的材料。在蚀刻穿过CESL 50之后，执行附加的干蚀刻工艺以蚀刻源极/漏极区48，使得沟槽78延伸至源极/漏极区48中。蚀刻气体可包括CxHyFz、HBr、Cl2等。此外，蚀刻气体可不同于CESL 50的蚀刻气体(如果采用干蚀刻)。蚀刻源极/漏极区48的工艺条件可不同于蚀刻CESL 50的工艺条件。例如，源极/漏极区48的干蚀刻的偏置功率可高于CESL 50的干蚀刻的偏置功率。根据一些实施例，沟槽78延伸至源极/漏极区48中深度D1，该深度D1可大于约5nm并可介于约5nm与约10nm之间的范围内。
再次参考图16B，根据本发明的一些实施例，沟槽78的底部78BOT低于多个纳米结构22B中的最顶纳米结构22B。沟槽78的底部78BOT也可相对于多个纳米结构22B的层级处于不同层级。例如，绘制多条虚线79以示出沟槽78的底部78BOT的可能位置。例如，底部78BOT可与最顶纳米结构22B的顶部或底部齐平或低于最顶纳米结构22B的顶部或底部，或者可与从顶部计数的第二或第三纳米结构22B的顶部或底部齐平或低于第二或第三纳米结构22B的顶部或底部。将底部沟槽78降低为例如使其与最顶纳米结构22B的顶部或甚至底部齐平或低于最顶纳米结构22B的顶部或甚至底部可提高器件性能。然而，形成深延伸至源极/漏极区48中的沟槽78可能导致后续形成硅化物区的问题。因此，如后续段落中所讨论，调整工艺以解决这些问题。
参考图17A和图17B，形成介电层80。根据一些实施例，介电层80由诸如氮化硅、氮氧化硅、氧化硅、碳氮氧化硅等的介电材料形成。接下来，执行各向异性蚀刻工艺以去除介电层80的水平部分，从而留下介电层80的垂直部分作为形成环的隔离层。所得结构在图18A、图18B和图18C中示出。在图29所示的工艺流程200中，相应工艺被示出为工艺236。参考图18C，当介电区82的顶面83低于凹进的源极/漏极区48的顶面时，介电层80可在源极/漏极区48的侧壁上延伸，其中，对应的介电层80被示出为虚线介电层80’。
参考图19A和图19B，沉积金属层84(诸如钛层或钴层等)。在图29所示的工艺流程200中，相应工艺被示出为工艺238。由于沟槽78的延伸深度，可通过诸如PECVD工艺的共形沉积工艺执行金属层84的沉积。根据一些实施例，可通过将诸如TiClx的金属卤化物用作工艺气体来沉积金属层84。氢气(H2)也可用作工艺气体的一部分。TiClx与氢反应以生成元素钛和HCl，并且通过抽真空排出HCl气体。反应可在约300℃与约500℃之间的范围内的温度下执行。由于共形沉积工艺，金属层84的不同部分(诸如水平部分、垂直部分和拐角部分)具有均匀的厚度或基本均匀的厚度。金属层84的底部厚度T1与侧壁厚度T2彼此相等或接近，例如，比率|T1-T2|/T2小于约20％或小于约10％。根据一些实施例，金属层84的厚度T1和T2可介于约1nm与约4nm之间的范围内。
图19A和图19B进一步示出覆盖层86的沉积，该覆盖层可以是金属氮化物层，诸如氮化钛层。在图29所示的工艺流程200中，相应工艺也被示为工艺238。根据一些实施例，使用CVD、PVD、PECVD等来形成覆盖层86。覆盖层86的底部厚度T3与侧壁厚度T4可彼此相等或接近，例如，比率|T3-T4|/T4小于约20％或约10％。可选地，底部厚度T3大于侧壁厚度T4。例如，比(T3-T4)/T4可大于约0.5或大于约1.0，并且可介于约1.0与约5.0之间的范围内。
参考图20A、图20B和图20C，执行退火工艺。根据一些实施例，介于约400℃与约600℃之间的范围内的温度下执行退火工艺。金属层84、覆盖层86的沉积和退火工艺可在相同的环境中原位执行，其间没有真空中断。由于用于沉积金属层84的升高的温度，并且进一步由于退火工艺，金属层84的底部与源极/漏极区48反应以形成硅化物区88。在图29所示的工艺流程200中，相应工艺被示出为工艺240。金属层84的侧壁部分在退火工艺之后保留。硅化物区88可由硅化物和/或锗化物形成。
在后续工艺中，可在蚀刻工艺中去除覆盖层86。根据一些实施例，执行附加蚀刻工艺以去除金属层84的剩余部分。根据可选的实施例，剩余的金属层84不被蚀刻，而是留在最终接触插塞中。
图21A和图21B示出另一覆盖层90的沉积，该覆盖层可包括金属氮化物，诸如氮化钛。在图29所示的工艺流程200中，相应工艺被示出为工艺242。接下来，如图22A、图22B和图22C所示，沉积诸如钴、钨、铝等的填充金属92。在图29所示的工艺流程200中，相应工艺被示出为工艺244。可执行诸如CMP工艺或机械研磨工艺的平坦化工艺以去除过量材料。在图29所示的工艺流程200中，相应工艺被示出为工艺246。所得结构在图23A、图23B和图23C中示出。剩余的导电层包括90和92(和84，如果没有去除的话)统称为源极/漏极接触插塞94。
再次参考图19B，通过使用共形沉积工艺来沉积金属层84，金属层84具有均匀的厚度。具体地，诸如区85的底部拐角区处的金属层84的厚度与诸如垂直和水平部分的其他部分的厚度相同。所得硅化物区88的尺寸/厚度与金属层84的厚度有关。因此，靠近底部拐角区85的硅化物区88(图20B)的部分也具有增加的厚度。这导致硅化物区88具有延伸区88’(图23B)，并且延伸硅化物区88’也较厚。根据一些实施例，延伸区88’的横向尺寸LD1大于约2nm，并且可介于约2nm与约3nm之间的范围内。形成较厚且较宽的延伸硅化物区88’增加源极/漏极接触插塞94的低阻接合区的尺寸，并提高GAA晶体管的性能。在接触插塞的传统接触件形成工艺中，PVD用于沉积金属层84。然而，PVD会导致不均匀的厚度。例如，在拐角区85(图19B)中，金属层84非常薄，并且延伸硅化物区88’(图23B)要么不存在，要么具有非常小的厚度。硅化物区88的靠近角部的端部也非常薄并具有高电阻。
图24A和图24B示出栅极接触插塞98的形成。形成工艺包括蚀刻ILD76、蚀刻停止层75和栅极掩模74以露出栅电极68，填充诸如Ti、TiN、W、Co等的导电材料，以及执行平坦化工艺。GAA晶体管96由此形成。
图25至图27、图28A、图28B和图28C示出根据一些实施例的FinFET196(图28A)的源极/漏极区的形成中的截面图和立体图。图28B示出图28A中的参考截面28B-28B。图28C示出图28A中的参考截面28C-28C。FinFET 196中的部件用GAA晶体管96中相应部件的参考标号加标号“100”来表示。例如，GAA晶体管96中的源极/漏极区表示为48，并且相应地，FinFET196中的源极/漏极区表示为148(包括148-1和148-2)，并可包括子层148A、148B和148C(图28B)。FinFET 196中部件的材料和形成工艺也可类似于GAA晶体管96中的类似部件，并在本文不再赘述。
如图28A、图28B和图28C所示，FinFET 196包括栅极堆叠件170和源极/漏极区148-1和148-2(图28B)。源极/漏极区148-1和148-2中的每个可以是p型或n型。示出CESL 150、ILD 152、蚀刻停止层175和ILD 176。还示出源极/漏极接触插塞194和硅化物区188(包括188-1和188-2)。
图28B和图28C示出源极/漏极区148-1和148-2以及硅化物区188-1和188-2的详细视图。接触插塞194包括覆盖层190(诸如氮化钛)和金属填充区192。
可使用与用于形成接触插塞94(图24B)相同的工艺来形成如图28B和图28C所示的接触插塞194。图25至图27示出示例性工艺的截面图。材料、形成工艺和结构的细节也可参考前述实施例。参考图25，形成源极/漏极区148-1和148-2，并且彼此靠近。CESL 150共形地形成在源极/漏极区148-1和148-2上，并且ILD 152形成在CESL 150上方。蚀刻ILD 152和CESL 150以形成源极/漏极接触开口178。接下来，如图26所示，深蚀刻源极/漏极区148-1和148-2，例如，去除的顶部部分的厚度大于约5nm或介于约5nm与约10nm之间的范围内。可形成或不形成介电层(类似于图17B和图18B中的层180，未示出)以延伸至源极/漏极接触开口178中。图27示出金属层184的形成，该金属层使用诸如PECVD的共形沉积工艺来沉积。金属层184可具有小于约20％或小于约10％的厚度变化(不同部分之间)。后续工艺与图19A/图19B至图24A/图24B所示基本相同，并在本文未示出。所得FinFET 196在图28A、图28B和图28C中示出。
应当了解，源极/漏极区148的深蚀刻可改善所得晶体管的性能。然而，当使用PVD形成金属层184时，深蚀刻使所得金属层184更加非共形，金属层184在区187A(图25)中将较厚，而在区187B中较薄。因此，区187B中形成的硅化物区将较薄且较小，并且接触电阻将较高。此外，区187A中和ILD 176上方的过厚的金属层184可能需要附加的工艺来去除。
本发明的实施例具有一些有利特征。通过深蚀刻源极/漏极区，提高所得晶体管的性能。通过使用共形沉积工艺以形成用于形成硅化物区的金属层，所得硅化物区的边缘部分较厚，并且硅化物区具有用于上面的源极/漏极接触插塞的增大的接合区。金属层的共形沉积因此也解决由源极/漏极区的深蚀刻引入的问题。
根据本发明的一些实施例，方法包括：形成栅极堆叠件；通过外延在所述栅极堆叠件的侧上生长源极/漏极区；在所述源极/漏极区上方沉积CESL；在所述CESL上方沉积层间电介质；蚀刻所述层间电介质和所述CESL以形成接触开口；蚀刻所述源极/漏极区，使得所述接触开口延伸至所述源极/漏极区中；沉积延伸至所述接触开口中的金属层，其中，所述金属层的水平部分、垂直部分和拐角部分具有基本均匀的厚度；执行退火工艺以使所述金属层与所述源极/漏极区反应，其中，形成源极/漏极硅化物区；以及填充所述接触开口以形成源极/漏极接触插塞。在实施例中，使用PECVD工艺来沉积所述金属层。在实施例中，所述方法还包括在所述金属层上方沉积氮化钛层，其中，所述氮化钛层被沉积为具有侧壁厚度和大于所述侧壁厚度的底部厚度。在实施例中，使用PVD工艺来沉积所述氮化钛层。在实施例中，使用第一蚀刻化学物质来蚀刻所述CESL，并且使用不同于所述第一蚀刻化学物质的第二蚀刻化学物质来蚀刻所述源极/漏极区。在实施例中，在包括交替定位的多个纳米结构和多个牺牲层的多层堆叠件上形成所述栅极堆叠件，并且所述接触开口具有与所述多个纳米结构中的最顶纳米结构的底面齐平或低于最顶纳米结构的底面的底部。在实施例中，所述接触开口的底部与所述多个纳米结构中的第二纳米结构的顶面齐平或低于第二纳米结构的顶面，其中，所述第二纳米结构从所述最顶纳米结构向下计数。在实施例中，所述源极/漏极硅化物区横向延伸超出所述源极/漏极接触插塞的边缘大于约2nm的距离。在实施例中，所述方法还包括：在沉积所述金属层之前，沉积延伸至所述接触开口中的介电层；以及蚀刻以去除所述介电层的水平部分，其中，所述介电层的垂直部分保留在所述接触开口中以形成介电环。在实施例中，通过使金属卤化物与氢反应来形成所述金属层。
根据本发明的一些实施例，方法包括：蚀刻层间电介质和CESL以形成接触开口并露出半导体区，其中，所述半导体区位于多层堆叠件的旁边，并且所述多层堆叠件包括多个牺牲层和多个半导体层，并且其中，所述多个牺牲层与所述多个半导体层交替定位；蚀刻所述半导体区以将所述接触开口进一步延伸至所述半导体区中，其中，所述半导体区具有高于所述多层堆叠件的第二顶面的第一顶面，并且蚀刻所述半导体区执行为直至所述接触开口的底面低于所述多个半导体层中的最顶半导体层的顶面；沉积金属层，其中，所述金属层延伸至所述接触开口中；在所述金属层上方沉积覆盖层；以及执行退火工艺，其中，所述金属层的底部与所述半导体区反应以形成硅化物区。在实施例中，所述金属层是共形的，并且所述覆盖层是非共形的并包括具有第一厚度的水平部分，所述第一厚度大于所述覆盖层的垂直部分的第二厚度。在实施例中，使用PECVD来执行沉积所述金属层。在实施例中，使用PVD来执行沉积所述覆盖层。在实施例中，使用湿蚀刻工艺来蚀刻所述CESL，并且使用干蚀刻工艺来蚀刻所述半导体区。使用干蚀刻工艺来蚀刻所述CESL和所述半导体区两者，并且使用不同的蚀刻气体来蚀刻所述CESL和所述半导体区。
根据本发明的一些实施例，方法包括：蚀刻层间电介质和位于所述层间电介质下面的CESL以形成接触开口，其中，通过所述接触开口露出位于所述CESL下方的半导体区；沉积延伸至所述开口中的介电层；对所述介电层执行各向异性蚀刻工艺以去除所述介电层的水平部分，其中，所述介电层的垂直部分保留在所述开口中以形成介电环；使用PECVD工艺来沉积延伸至所述开口中的金属层；以及使用PVD工艺来在所述金属层上方沉积氮化钛层；以及使所述金属层的底部与所述半导体区反应以形成硅化物区，所述金属层沉积为共形层，并且所述氮化钛层沉积为非共形层。在实施例中，所述金属层包括钛，并且沉积所述金属层包括使用氯化钛作为前体。在实施例中，所述方法还包括在露出所述半导体区之后，改变蚀刻化学物质以进一步蚀刻所述半导体区。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体器件的方法，包括：
形成栅极堆叠件；
通过外延在所述栅极堆叠件的侧上生长源极/漏极区；
在所述源极/漏极区上方沉积接触蚀刻停止层(CESL)；
在所述接触蚀刻停止层上方沉积层间电介质；
蚀刻所述层间电介质和所述接触蚀刻停止层以形成接触开口；
蚀刻所述源极/漏极区，使得所述接触开口延伸至所述源极/漏极区中；
沉积延伸至所述接触开口中的金属层，其中，所述金属层的水平部分、垂直部分和拐角部分具有基本均匀的厚度；
执行退火工艺以使所述金属层与所述源极/漏极区反应，其中，形成源极/漏极硅化物区；以及
填充所述接触开口以形成源极/漏极接触插塞。
2.根据权利要求1所述的方法，其中，使用等离子体增强化学气相沉积(PECVD)工艺来沉积所述金属层。
3.根据权利要求2所述的方法，还包括在所述金属层上方沉积氮化钛层，其中，所述氮化钛层沉积为具有侧壁厚度和大于所述侧壁厚度的底部厚度。
4.根据权利要求3所述的方法，其中，使用物理气相沉积(PVD)工艺来沉积所述氮化钛层。
5.根据权利要求1所述的方法，其中，使用第一蚀刻化学物质来蚀刻所述接触蚀刻停止层，并且使用不同于所述第一蚀刻化学物质的第二蚀刻化学物质来蚀刻所述源极/漏极区。
6.根据权利要求1所述的方法，其中，在包括交替定位的多个纳米结构和多个牺牲层的多层堆叠件上形成所述栅极堆叠件，并且所述接触开口具有与所述多个纳米结构中的最顶纳米结构的底面齐平或低于所述最顶纳米结构的底面的底部。
7.根据权利要求6所述的方法，其中，所述接触开口的底部与所述多个纳米结构中的第二纳米结构的顶面齐平或低于所述第二纳米结构的顶面，其中，所述第二纳米结构从所述最顶纳米结构向下计数。
8.根据权利要求1所述的方法，其中，所述源极/漏极硅化物区横向延伸超出所述源极/漏极接触插塞的边缘大于2nm的距离。
9.一种形成半导体器件的方法，包括：
蚀刻层间电介质和接触蚀刻停止层(CESL)以形成接触开口并露出半导体区，其中，所述半导体区位于多层堆叠件的旁边，并且所述多层堆叠件包括多个牺牲层和多个半导体层，并且其中，所述多个牺牲层与所述多个半导体层交替定位；
蚀刻所述半导体区以将所述接触开口进一步延伸至所述半导体区中，其中，所述半导体区具有高于所述多层堆叠件的第二顶面的第一顶面，并且蚀刻所述半导体区执行为直至所述接触开口的底面低于所述多个半导体层中的最顶半导体层的顶面；
沉积金属层，其中，所述金属层延伸至所述接触开口中；
在所述金属层上方沉积覆盖层；以及
执行退火工艺，其中，所述金属层的底部与所述半导体区反应以形成硅化物区。
10.一种形成半导体器件的方法，包括：
蚀刻层间电介质和位于所述层间电介质下面的接触蚀刻停止层(CESL)以形成接触开口，其中，穿过所述接触开口露出位于所述接触蚀刻停止层下面的半导体区；
沉积延伸至所述开口中的介电层；
对所述介电层执行各向异性蚀刻工艺以去除所述介电层的水平部分，其中，所述介电层的垂直部分保留在所述开口中以形成介电环；
使用等离子体增强化学气相沉积(PECVD)工艺来沉积延伸至所述开口中的金属层；以及
使用物理气相沉积(PVD)工艺来在所述金属层上方沉积氮化钛层；以及
使所述金属层的底部与所述半导体区反应以形成硅化物区。
CN202210163300.6A 2021-03-26 2022-02-22 形成半导体器件的方法 Pending CN115172273A (zh)

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