TWI808458B - 半導體裝置及其形成方法 - Google Patents
半導體裝置及其形成方法 Download PDFInfo
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- TWI808458B TWI808458B TW110129094A TW110129094A TWI808458B TW I808458 B TWI808458 B TW I808458B TW 110129094 A TW110129094 A TW 110129094A TW 110129094 A TW110129094 A TW 110129094A TW I808458 B TWI808458 B TW I808458B
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Abstract
一種裝置,包括:鰭片,從半導體基板延伸;閘極堆疊,位於鰭片上方;間隔物,位於閘極堆疊的側壁上;源極/汲極區,位於鄰近於間隔物的鰭片中;層間介電層(inter-layer dielectric, ILD),延伸於閘極堆疊、間隔物、及源極/汲極區上方;接觸插塞,延伸穿過ILD並接觸源極/汲極區;介電層,包括位於ILD的頂表面上的第一部分及延伸於ILD及接觸插塞之間的第二部分,其中第二部分的頂表面相較於ILD的頂表面更靠近基板;及氣隙,位於間隔物及接觸插塞之間,其中介電層的第二部分密封氣隙的頂部。
Description
本揭露是有關於一種半導體裝置及其形成方法,且特別是有關於一種具有FINFET裝置的半導體裝置及其製造方法。
半導體裝置用於各式各樣的電子應用中,例如個人電腦、手機、數位相機與其他電子裝置。半導體裝置的製造一般是透過於半導體基板上依序沉積絕緣或介電層、導電層以及半導體層的材料,並利用微影圖案化各種材料層以於半導體裝置上形成電路組件與元件。
半導體工業藉由逐步縮減最小部件尺寸來不斷增加積體電路(integrated circuits,ICs)中各種電子元件(例如,電晶體、二極體、電阻、電容等)的積體密度,允許將多個元件整合於一給定的面積中。然而,隨著最小部件尺寸微縮化,額外產生的問題須被解決。
本發明實施例提供一種半導體裝置,包括:鰭片,從半導體基板延伸;閘極堆疊,位於鰭片上方;間隔物,位於閘極堆疊的側壁上;源極/汲極區,位於鄰近於間隔物的鰭片中;層間介電層(inter-layer dielectric,ILD),延
伸於閘極堆疊、間隔物、及源極/汲極區上方;接觸插塞,延伸穿過ILD並接觸源極/汲極區;介電層,包括位於ILD的頂表面上的第一部分及延伸於ILD及接觸插塞之間的第二部分,其中第二部分的頂表面相較於ILD的頂表面更靠近基板;及氣隙,位於間隔物及接觸插塞之間,其中介電層的第二部分密封氣隙的頂部。
本發明實施例提供一種半導體裝置的形成方法,包括:形成從基板突出的鰭片;形成閘極結構於鰭片的通道區上方;沿著閘極結構的側壁形成閘極間隔物;形成磊晶區於鄰近於通道區的鰭片中;沉積第介電層於閘極結構及閘極間隔物上方,第一介電層包括第一介電材料;形成延伸穿過第一介電層並接觸磊晶區的接觸插塞,其中氣隙將接觸插塞及閘極間隔物間隔開;沉積第二介電層於第一介電層上方及接觸插塞上方,包括用第二介電層密封氣隙的下部區,其中第二介電層包括不同於第一介電材料的第二介電材料;蝕刻第二介電層以露出接觸插塞,其中在蝕刻第二介電層之後,第二介電層的剩餘部分密封氣隙的下部區;及沉積導電材料於接觸插塞上,包括沉積導電材料於接觸插塞及閘極間隔物之間、以及於第二介電層的剩餘部分上。
本發明實施例提供一種半導體裝置的形成方法,包括:形成閘極堆疊於半導體鰭片上方;形成磊晶源極/汲極區於鄰近於閘極堆疊層的半導體鰭片中;沉積第一介電層於閘極疊層上方及磊晶源極/汲極區上方;形成開口於第一介電層中,以露出磊晶源極/汲極區;沉積犧牲材料於開口內;沉積第一導電材料於開口內的犧牲材料上方;移除犧牲材料,以形成間隙;沉積第二介電層於第一介電層上方、第一導電材料上方、以及間隙上方,其中第二介電層延伸第一距離進間隙中;及蝕刻第二介電層,以露出第一導電材料,其中第二介電層的多個第一部分在蝕刻之後保留在間隙內。
50:基板
50N:區域
50P:區域
51:分隔器
52:鰭片
54:絕緣材料
56:淺溝槽隔離區
58:通道區
60:虛設介電層
62:虛設閘極層
64:遮罩層
72:虛設閘極
74:遮罩
80:閘極密封間隔物
82:磊晶源極/汲極區
86:閘極間隔物
87:接觸蝕刻停止層
88:第一層間介電質
89:區域
90:凹槽
92:閘極介電層
94:閘極電極
94A:襯層
94B:功函數調整層
94C:填充材料
96:硬遮罩
108:第二ILD
110:開口
111:區域
112:虛設間隔層
114:接觸間隔層
116:矽化物區
118:源極/汲極接觸件
120:氣隙
120’:初始氣隙
122:蝕刻停止層
123:密封件
123’:密封區
134:介電層
135:區域
136:導電部件
137:襯層
138:開口
139:凹槽
T1:厚度
T2:厚度
W1:寬度
W2:寬度
W3:寬度
H1:高度
H2:高度
H3:高度
D1:距離
D2:距離
D3:距離
D4:距離
A-A:剖面
B-B:剖面
C-C:剖面
本揭露從以下詳細描述中配合圖式可最好地被理解。應強調的是,依據業界的標準做法,各種部件並未按照比例繪製且僅用於說明的目的。事實上,為了清楚討論,各種部件的尺寸可任意放大或縮小。
第1圖係根據一些實施例,繪示出FinFET的示例的三維視圖。
第2圖、第3圖、第4圖、第5圖、第6圖、第7圖、第8A圖、第8B圖、第9A圖、第9B圖、第10A圖、第10B圖、第10C圖、第10D圖、第11A圖、第11B圖、第12A圖、第12B圖、第13A圖、第13B圖、第14A圖、第14B圖、第14C圖、第15A圖及第15B圖係根據一些實施例,繪示在FinFET的製造的中間階段的剖面圖。
第16圖、第17圖、第18圖、第19圖、第20圖、第21圖、第22圖、第23A圖、第23B圖、第24A圖、第24B圖、第25A圖、第25B圖、第26A圖、第26B圖、第27A圖、第27B圖及第28圖係根據一些實施例,繪示在製造具有氣隙的FinFETs的中間階段的剖面圖。
以下揭露提供了許多的實施例或範例,用於實施所提供的標的物之不同元件。各元件和其配置的具體範例描述如下,以簡化本發明實施例之說明。當然,這些僅僅是範例,並非用以限定本發明實施例。舉例而言,敘述中若提及第一元件形成在第二元件上方或之上,可能包含第一和第二元件直接接觸的實施例,也可能包含額外的元件形成在第一和第二元件之間,使得它們不直接接觸的實施例。此外,本發明實施例可能在各種範例中重複參考數值以及/或字母。如此重複是為了簡明和清楚之目的,而非用以表示所討論的不同實施
例及/或配置之間的關係。
再者,其中可能用到與空間相對用詞,例如「在......之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞,是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位,以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位),其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
根據一些實施例,在至FinFET裝置的源極/汲極磊晶區的接觸件周圍形成氣隙。氣隙的低介電常數(k值)可降低閘極堆疊與FinFET裝置的接觸件之間的電容,可提高FinFET的更高速度(例如,「AC」)操作。在一些實施例中,控制上方的蝕刻停止層的沉積製程,使得蝕刻停止層的部分延伸至氣隙中並密封(seal)氣隙的上部區。舉例而言,在ALD製程期間使用較低的前驅物劑量可導致蝕刻停止層的材料在氣隙的上部區中生長並且密封氣隙的下部區。在一些實施例中,可藉由控制劑量來控制蝕刻停止層延伸至氣隙中的距離。藉由密封氣隙,減少了或消除了隨後沉積的導電材料進入氣隙的機會。因此,減少了或消除了由於氣隙內存在導電材料而引起的滲漏(leakage)或電子短路的機會。
第1圖係根據一些實施例,繪示出FinFET的示例的三維視圖。FinFET包括位於基板50(例如,半導體基板)上的鰭片52。隔離區56設置於基板50中,並且鰭片52突出於相鄰的(neighboring)隔離區56上方及之間。儘管將隔離區56描述/繪示為與基板50分離,但是如本文所使用的術語「基板」可僅指半導體基板或包括隔離區的半導體基板。此外,儘管鰭片52被繪示為與基板50
一樣的單一連續材料,但是鰭片52及/或基板50可包括單一材料或材料的組合。在本文中,鰭片52指的是延伸於相鄰的隔離區56之間的部分。
閘極介電層92沿著側壁並位於鰭片52的頂表面上方,而閘極電極94位於閘極介電層92上方。源極/汲極區82相對於閘極介電層92及閘極電極94設置於鰭片52的兩側。第1圖進一步繪示出在後文的圖中使用的參考剖面。剖面A-A沿著閘極電極94的縱軸且在例如垂直於FinFET的源極/汲極區82之間的電流流動方向的方向上。剖面B-B垂直於剖面A-A,並且沿著鰭片52的縱軸且在例如FinFET的源極/汲極區82之間的電流流動的方向上。剖面C-C平行於剖面A-A,並且延伸穿過FinFET的源極/汲極區。為了清楚起見,後續圖式參考這些參考剖面。
本文討論的一些實施例是在使用閘極後製(gate-last)製程所形成之FinFETs的情境下討論的。在其他實施例中,可使用閘極先製(gate-first)製程。此外,一些實施例考慮了在例如平面FETs的平面裝置中使用的面向。
第2圖至第28圖係根據一些實施例,包括FinFETs的製造的中間階段的剖面圖。第2圖至第7圖繪示第1圖所示的參考剖面A-A,且第8A圖、第9A圖、第10A圖、第11A圖、第12A圖、第13A圖、第14A圖、第15A圖、第24A圖、第25A圖、第26A圖及第27A圖繪示沿第1圖中所示的參考剖面A-A,但差別在於繪示了多個鰭片/FinFET。第8B圖、第9B圖、第10B圖、第11B圖、第12B圖、第13B圖、第14B圖、第14C圖、第15B圖、第16圖、第17圖、第18圖、第19圖、第20圖、第21圖、第22圖、第23A圖、第23B圖、第24B圖、第25B圖、第26B圖、第27B圖及第28圖繪示沿著第1圖中所示的類似剖面B-B,但差別在於繪示了多個鰭片/FinFETs。第10C圖及第10D圖繪示沿著第1圖中所示的參考剖面C-C,但差別在於繪示了多個鰭片/FinFET。
在第2圖中,提供了基板50。基板50可為半導體基板,例如塊體半導體、絕緣體上覆半導體基板(semiconductor-on-insulator substrate)等,其可被摻雜(例如,以p型或n型摻質)或未摻雜。基板50可為晶圓(wafer),例如矽晶圓。總體而言,SOI基板為在絕緣層上形成的半導體材料層。絕緣層可例如為埋藏氧化物(buried oxide,BOX)層、氧化矽層等。提供絕緣層於通常為矽或玻璃基板的基板上。也可使用其他基板,例如多層或梯度基板。在一些實施例中,基板50的半導體材料可包括矽、鍺、化合物半導體、合金半導體、或其組合,上述化合物半導體包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦,上述合金半導體包括矽鍺、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、及/或磷砷化鎵銦。
基板50具有區域50N及區域50P。區域50N可用於形成n型裝置,例如NMOS電晶體,例如n型FinFETs。區域50P可用於形成p型裝置,例如PMOS電晶體,例如p型FinFETs。區域50N可與區域50P實體分離(如分隔器(divider)51所示),並且可設置任何數量的裝置部件(例如,其他主動裝置、摻雜區、隔離結構等)於區域50N及區域50P之間。
在第3圖中,鰭片52形成於基板50中。鰭片52為半導體條(strips)。在一些實施例中,可藉由在基板50中蝕刻溝槽而在基板50中形成鰭片52。蝕刻可為任何可接受的蝕刻製程,例如反應離子蝕刻(reactive ion etch,RIE)、中性束蝕刻(neutral beam etch,NBE)等、或其組合。蝕刻可為非等向性的。
可藉由任何合適的方法來圖案化鰭片。舉例而言,可使用一種或多種光學微影製程來圖案化鰭片,光學微影製程包括雙重圖案化製程或多重圖
案化製程。總體而言,雙重圖案化或多重圖案化製程結合了光學微影及自對準製程,從而允許創建例如間距小於使用單一直接光學微影製程所獲得的間距的圖案。舉例而言,在一實施例中,於基板上方形成犧牲層並使用光學微影製程將其圖案化。使用自對準製程在圖案化的犧牲層旁邊(alongside)形成間隔物。然後移除犧牲層,然後可使用剩餘的間隔物來圖案化鰭片。在一些實施例中,遮罩(或其他層)可保留在鰭片52上。
在第4圖中,絕緣材料54形成於基板50上方並且位於相鄰的鰭片52之間。絕緣材料54可為氧化物,例如氧化矽、氮化物等、或其組合,並且可藉由高密度電漿化學氣相沉積(high density plasma chemical vapor deposition,HDP-CVD)、流動式CVD(flowable CVD,FCVD)(例如,CVD基(CVD-based)材料在遠端電漿系統中的沉積及後固化(post curing),以使其轉化為另一種材料,例如氧化物)等、或其組合。可使用藉由任何可接受的製程所形成的其他絕緣材料。在所示的實施例中,絕緣材料54是藉由FCVD製程所形成的氧化矽。一旦形成絕緣材料,可進行退火製程。在一實施例中,形成絕緣材料54,使得多餘的絕緣材料54覆蓋鰭片52。儘管絕緣材料54被繪示為單層,但是一些實施例可利用複數層。舉例而言,在一些實施例中,可首先沿著基板50及鰭片52的表面形成襯層(未繪示)。然後,可於襯層上方形成例如前文所述之填充材料。
在第5圖中,對絕緣材料54施加移除製程以移除鰭片52上方的多餘絕緣材料54。在一些實施例中,可使用例如化學機械拋光(chemical mechanical polish,CMP)的平坦化製程、回蝕刻製程、其組合等。平坦化製程露出鰭片52,使得鰭片52及絕緣材料54的頂表面在平坦化製程完成後齊平。在遮罩保留於鰭片52上的實施例中,平坦化製程可露出遮罩或移除遮罩,使得在平坦化製程完
成後,遮罩或鰭片52各自的頂表面與絕緣材料54的頂表面齊平。
在第6圖中,將絕緣材料54凹蝕以形成淺溝槽隔離(Shallow Trench Isolation,STI)區56。將絕緣材料54凹蝕以使得位於區域50N及區域50P中之鰭片52的上部從相鄰的STI區56之間突出。再者,STI區56的頂表面可具有如圖所示的平坦表面、凸(convex)表面、凹(concave)表面(例如碟狀)、或其組合。可藉由適當的蝕刻將STI區56的頂表面形成為平坦的、凸的、及/或凹的。可使用可接受的蝕刻製程來將STI區56凹蝕,例如對絕緣材料54的材料具有選擇性的蝕刻製程(例如,相較於蝕刻鰭片52之材料的速率,以更快的速率蝕刻絕緣材料54的材料)。舉例而言,可使用例如稀氫氟(dilute hydrofluoric,dHF)酸移除氧化物。
參照第2圖至第6圖所述的製程僅為如何形成鰭片52的一示例。在一些實施例中,可藉由磊晶成長製程形成鰭片。舉例而言,可於基板50的頂表面上方形成介電層,並且溝槽可蝕刻穿過介電層,以露出下方的基板50。可於溝槽中磊晶成長同質磊晶(homoepitaxial)結構,並且將介電層凹蝕,使得同質磊晶結構從介電層突出以形成鰭片。此外,在一些實施例中,異質磊晶(heteroepitaxial)結構可用於鰭片52。舉例而言,可將第5圖中的鰭片52凹蝕,並且可在凹蝕的鰭片52上方磊晶成長與鰭片52不同的材料。在此實施例中,鰭片52包括凹蝕的材料以及設置於凹蝕的材料上方的磊晶成長材料。在另一實施例中,可於基板50的頂表面上方形成介電層,並且可蝕刻穿過介電層的溝槽。然後,可使用與基板50不同的材料在溝槽中磊晶成長異質磊晶結構,並且可將介電層凹蝕,使得異質磊晶結構從介電層突出以形成鰭片52。在一些實施例中,將同質磊晶結構或異質磊晶結構磊晶成長,可在成長期間原位摻雜磊晶成長的
材料,儘管原位摻雜及佈植摻雜可一起使用,但原位摻雜可避免先前及隨後的佈植。
更進一步,在區域50N(例如,NMOS區)中磊晶成長與區域50P(例如,PMOS區)中的材料不同的材料可能是有利的。在各個實施例中,鰭片52的上部可由例如下列材料所形成:矽鍺(SixGe1-x,其中x可在0至1的範圍內)、碳化矽、純或實質上純的鍺、III-V族化合物半導體、II-VI族化合物半導體等。舉例而言,用於形成III-V化合物半導體的可用材料包括但不限於下列材料:砷化銦、砷化鋁、砷化鎵、磷化銦、氮化鎵、砷化銦鎵、砷化銦鋁、鎵銻、鋁銻、磷化鋁、磷化鎵等。
進一步在第6圖中,可於鰭片52及/或基板50中形成適當的井區(未繪示)。在一些實施例中,可於區域50N中形成P井,並且可於區域50P中形成N井。在一些實施例中,在區域50N及區域50P中皆形成P井或N井。
在具有不同井型的實施例中,可使用光阻及/或其他遮罩(未繪示)來實現用於區域50N及區域50P的不同佈植步驟。舉例而言,可在區域50N中的鰭片52及STI區56上方形成光阻。將光阻圖案化,以露出基板50的區域50P,例如PMOS區。可藉由使用旋塗技術來形成光阻,並且可使用可接受的光學微影技術來將光阻圖案化。一旦將光阻圖案化,在區域50P中進行n型雜質(impurity)佈植,並且可將光阻用作遮罩以實質上防止將n型雜質佈植進區域50N中,例如NMOS區。n型雜質可為磷、砷、銻等,將其佈植於區域中至濃度等於或小於1018cm-3,例如介於約1016cm-3至約1018cm-3之間。佈植之後,例如藉由可接受的灰化製程來移除光阻。
在佈植區域50P之後,在區域50P中的鰭片52及STI區56上方形成
光阻。將光阻圖案化以露出基板50的區域50N,例如NMOS區。可藉由使用旋塗技術來形成光阻,並且可使用可接受的光學微影技術來將光阻圖案化。一旦將光阻圖案化,可在區域50N中進行p型雜質佈植,並且可將光阻用作遮罩以實質上防止將p型雜質佈植進區域50P中,例如PMOS區。p型雜質可為硼、氟化硼、銦等,將其佈植於區域中至濃度等於或小於1018cm-3,例如介於約1016cm-3至約1018cm-3之間。在佈植之後,可例如藉由可接受的灰化製程來移除光阻。
在佈植區域50N及區域50P之後,可進行退火以修復佈植損壞並活化佈植的p型及/或n型雜質。在一些實施例中,可在成長期間將磊晶鰭片的成長材料原位摻雜,儘管原位摻雜及佈植摻雜可一起使用,但原位摻雜可避免佈植。
在第7圖中,虛設介電層60形成於鰭片52上。虛設介電層60可例如為氧化矽、氮化矽、其組合等,並且可根據可接受的技術沉積或熱成長(thermally grown)虛設介電層60。在虛設介電層60上方形成虛設閘極層62,並且在虛設閘極層62上方形成遮罩層64。可在虛設介電層60上方沉積虛設閘極層62,然後例如藉由CMP將其平坦化。遮罩層64可沉積在虛設閘極層62上方。虛設閘極層62可為導電材料或非導電材料,並且可選自包括下列材料的群組:非晶矽、多晶矽(polycrystalline-silicon,polysilicon)、多晶矽鍺(polycrystalline silicon-germanium,poly-SiGe)、金屬氮化物、金屬矽化物、金屬氧化物、及金屬。可藉由物理氣相沉積(physical vapor deposition,PVD)、CVD、濺鍍沉積或用於沉積所選材料的其他技術來沉積虛設閘極層62。虛設閘極層62可由其他材料所製成,這些材料對隔離區的蝕刻具有高蝕刻選擇性。遮罩層64可包括例如氮化矽、氮氧化矽等。在此示例中,橫跨(across)區域50N及區域50P形成單一
虛設閘極層62及單一遮罩層64。應注意的是,僅用於說明性目的,將虛設介電層60繪示為僅覆蓋鰭片52。在一些實施例中,可沉積虛設介電層60,使得虛設介電層60覆蓋STI區56,延伸於虛設閘極層62及STI區56之間。
第8A圖至15B繪示出實施例裝置的製造中的各種額外步驟。第8A圖至第15B圖繪示出區域50N或區域50P。舉例而言,第8A圖至第15B圖所示的結構皆可適用於區域50N及區域50P。在每個圖式的正文中描述了區域50N及區域50P的結構上的差異(如果有的話)。
在第8A圖及第8B圖中,可使用可接受的光學微影及蝕刻技術來將遮罩層64(參照第7圖)圖案化以形成遮罩74。然後可將遮罩74的圖案轉移至虛設閘極層62以形成虛設閘極72。在一些實施例中(未繪示),也可藉由可接受的蝕刻技術將遮罩74的圖案轉移至虛設介電層60。虛設閘極72覆蓋鰭片52各自的通道區。遮罩74的圖案可用於將每個虛設閘極72與鄰近的虛設閘極72實體上分離。虛設閘極72也可具有長度方向,實質上垂直相應磊晶鰭片52的長度方向。
進一步在第8A圖及第8B圖中,可在虛設閘極72、遮罩74、及/或鰭片52的露出表面上形成閘極密封間隔物80。熱氧化或沉積隨後非等向性蝕刻,可形成閘極密封間隔物80。閘極密封間隔物80可由氧化矽、氮化矽、氮氧化矽等所形成。
在形成閘極密封間隔物80之後,可進行用於輕摻雜源極/汲極(lightly doped source/drain,LDD)區(未明確繪示出)的佈植。在具有不同裝置類型的實施例中,類似於前文在第6圖中討論的佈植,可在區域50N上方形成遮罩露出區域50P,且可將適當類型(例如,p型)的雜質佈植進區域50P中露出
的鰭片52中,上述遮罩例如光阻。然後可移除遮罩。隨後,可在區域50P上方形成遮罩露出區域50N,且可將適當類型(例如,n型)的雜質佈植進區域50N中露出的鰭片52中,上述遮罩例如光阻。n型雜質可為前文討論的任何n型雜質,並且p型雜質可為前文討論的任何p型雜質。輕摻雜的源極/汲極區可具有約1015cm-3至約1019cm-3的雜質濃度。退火可用於修復佈植損壞並活化佈植的雜質。
在第9A圖及第9B圖中,沿著虛設閘極72及遮罩74的側壁在閘極密封間隔物80上形成閘極間隔物86。閘極間隔物86可藉由保形地沉積絕緣材料並隨後非等向性蝕刻絕緣材料來形成。閘極間隔物86的絕緣材料可為氧化矽、氮化矽、氮氧化矽、氮碳化矽、其組合等。
應注意的是,前文揭露內容總體上描述了形成間隔物及LDD區的製程。可使用其他製程及順序。舉例而言,可利用更少或額外的間隔物、步驟的不同順序(例如,可在形成閘極間隔物86之前,蝕刻閘極密封間隔物80,得到「L形」閘極密封間隔物)、可形成及移除間隔物等。再者,可使用不同的結構及步驟來形成n型及p型裝置。舉例而言,可在形成閘極密封間隔物80之前,形成用於n型裝置的LDD區,可在形成閘極密封間隔物80之後,形成用於p型裝置的LDD區。
第10A圖及第10B圖係根據一些實施例,繪示在鰭片52中形成磊晶源極/汲極區82。在一些情況下,可形成磊晶源極/汲極區82,以在各個通道區58中施加應力,從而提高性能。在鰭片52中形成磊晶源極/汲極區82,使得每個虛設閘極堆疊72設置於各自相鄰的磊晶源極/汲極區對82之間。在一些實施例中,磊晶源極/汲極區82可延伸進鰭片52中,並且也可穿過鰭片52。在一些實施例中,閘極間隔物86用於將磊晶源極/汲極區82與虛設閘極72隔開適當的橫向距
離,使得磊晶源極/汲極區82不會與所得之FinFETs後續形成的閘極發生短路。
可藉由遮蔽例如PMOS區的區域50P並蝕刻區域50N中的鰭片52的源極/汲極區來形成例如NMOS區的區域50N中的磊晶源極/汲極區82,以在鰭片52中形成凹槽。然後,在凹槽中磊晶成長區域50N中的磊晶源極/汲極區82。磊晶源極/汲極區82可包括任何可接受的材料,例如適用於n型FinFETs的材料。舉例而言,如果鰭片52為矽,則區域50N中的磊晶源極/汲極區82可包括在通道區58中施加拉伸應變的材料拉伸應變(tensile strain)的材料,例如矽、碳化矽、磷摻雜的碳化矽、磷化矽等。區域50N中的磊晶源極/汲極區82可具有從鰭片52的相應表面凸起的表面並且可具有晶面(facets)。
可藉由遮蔽例如NMOS區的區域50N並蝕刻區域50P中鰭片52的源極/汲極區以在鰭片52中形成凹槽,來形成例如PMOS區的區域50P中的磊晶源極/汲極區82。然後,在凹槽中磊晶成長區域50P中的磊晶源極/汲極區82。磊晶源極/汲極區82可包括任何可接受的材料,例如適用於p型FinFETs的材料。舉例而言,如果鰭片52為矽,則區域50P中的磊晶源極/汲極區82可包括在通道區58中施加壓縮應力(compressive strain)的材料,例如矽鍺、摻雜硼的矽鍺、鍺、鍺錫等。區域50P中的磊晶源極/汲極區82更可具有從鰭片52的相應表面凸起的表面並且可具有晶面。
可用與前文討論用於形成輕摻雜源極/汲極區相似的製程以摻質佈植磊晶源極/汲極區82及/或鰭片52以形成源極/汲極區,隨後進行退火製程。源極/汲極區可具有介於約1019cm-3至約1021cm-3之間的雜質濃度。用於源極/汲極區的n型及/或p型雜質可為前文討論的任何雜質。在一些實施例中,可在成長期間原位摻雜磊晶源極/汲極區82。
作為用於在區域50N及區域50P中形成磊晶源極/汲極區82的磊晶製程的結果,磊晶源極/汲極區的上表面具有橫向擴展向外超過鰭片52側壁的晶面。在一些實施例中,這些晶面導致相同FinFET的鄰近源極/汲極區82如第10C圖所示地合併。在其他實施例中,如第10D圖所示,在磊晶製程完成之後,鄰近的源極/汲極區82保持分離。在第10C圖及第10D圖所示的實施例中,形成閘極間隔物86,將閘極間隔物86形成為覆蓋鰭片52的側壁的一部分,上述側壁延伸於STI區56上方,從而阻止了磊晶成長。在一些其他實施例中,可調整用於形成閘極間隔物86的間隔物蝕刻以移除間隔物材料,以允許磊晶成長區延伸至STI區56的表面。
在第11A圖及第11B圖中係根據一些實施例,係將第一層間介電質(interlayer dielectric,ILD)88沉積於第10A圖及第10B圖所示的結構上方。第一ILD 88可由介電材料所形成,並且可藉由任何合適的方法沉積,例如CVD、電漿增強CVD(plasma-enhanced CVD,PECVD)、或FCVD。介電材料可包括磷矽酸鹽玻璃(phosphoric silicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass,BPSG)、未摻雜的矽酸鹽玻璃(undoped silicate glass,USG)等。可使用任何藉由可接受的製程所形成的其他絕緣材料。在一些實施例中,接觸蝕刻停止層(contact etch stop layer,CESL)87設置於第一ILD 88與磊晶源極/汲極區82、遮罩74及閘極間隔物86之間。CESL 87可包括例如下列的介電材料:氮化矽、氧化矽、氮氧化矽等,並且可具有與上方的第一ILD 88的材料不同的蝕刻速率。在一些實施例中,可將CESL 87形成為具有約2nm至約5nm之間的厚度,例如約3nm。在一些情況下,控制CESL 87的厚度可控制源極/汲極接觸件118的尺寸(例如,寬度或高度)、及/或後續形
成的氣隙120的尺寸(例如,寬度或高度)(參照第17圖至第22圖)。
在第12A圖及第12B圖中,可進行例如CMP的平坦化製程,以使第一ILD 88的頂表面與虛設閘極72或遮罩74的頂表面齊平。平坦化製程也可移除虛設閘極72上的遮罩74、以及沿著遮罩74之側壁的閘極密封間隔物80、及閘極間隔物86的部分。在平坦化製程之後,虛設閘極72、閘極密封間隔物80、閘極間隔物86、及第一ILD 88的頂表面齊平。因此,虛設閘極72的頂表面從第一ILD 88露出。在一些實施例中,可保留遮罩74,在這種情況下,平坦化製程使第一ILD 88的頂表面與遮罩74的頂表面齊平。
在第13A圖及第13B圖中,在一個或多個蝕刻步驟中移除了虛設閘極72及遮罩74(如果有遮罩的話),從而形成了凹槽90。也可移除位於凹槽90中的虛設介電層60的部分。在一些實施例中,僅將虛設閘極72移除,並且保留虛設介電層60並且由凹槽90露出虛設介電層60。在一些實施例中,將虛設介電層60從晶粒的第一區(例如,核心邏輯(core logic)區)中的凹槽90移除,並保留在晶粒的第二區(例如,輸入/輸出區)中的凹槽90中。在一些實施例中,藉由非等向性乾式蝕刻製程移除虛設閘極72。舉例而言,蝕刻製程可包括使用一種或多種反應氣體的乾式蝕刻製程,反應氣體選擇性地蝕刻虛設閘極72,而僅少量或不蝕刻第一ILD 88、閘極間隔物86、或CESL 87。每個凹槽90露出及/或覆蓋相應的鰭片52的通道區。將每個通道區設置於相鄰之磊晶源極/汲極區58對(pairs)之間。在移除期間,當蝕刻虛設閘極72時,可將虛設介電層60用作蝕刻停止層。然後,在移除虛設閘極72之後,藉由適當的蝕刻製程可以可選地移除虛設介電層60。
在第14A圖及第14B圖中,形成閘極介電層92及閘極電極94用於
替換閘極(replacement gates)。第14C圖繪示出第14B圖的區域89的詳細視圖。閘極介電層92保形地沉積在凹槽90中,例如沉積於鰭片52的頂表面及側壁上、以及在閘極密封間隔物80/閘極間隔物86的側壁上。閘極介電層92也可形成於第一ILD 88的頂表面上。根據一些實施例,閘極介電層92包括氧化矽、氮化矽、或其多層。在一些實施例中,閘極介電層92包括高k介電材料,並且在這些實施例中,閘極介電層92可具有大於約7.0的k值,上述高k介電材料可包括金屬氧化物,或鉿、鋁、鋯、鑭、錳、鋇、鈦、鉛的矽化物、及其組合。閘極介電層92的形成方法可包括分子束沉積(Molecular-Beam Deposition,MBD)、ALD、PECVD等。在虛設介電層60的部分保留於凹槽90中的實施例中,閘極介電層92包括虛設介電層60的材料(例如,氧化矽)。
閘極電極94分別沉積於閘極介電層92上方,並填充凹槽90的其餘部分。閘極電極94可包括含金屬的材料,例如氮化鈦、氧化鈦、氮化鉭、碳化鉭、鈷、釕、鋁、鎢、其組合或複數層。舉例而言,儘管在第14B圖中繪示出單層閘極電極94,但是如第14C圖所示閘極電極94可包括任意數量的襯層94A、任意數量的功函數調整層94B、及填充材料94C。在填充凹槽90之後,可進行例如CMP的平坦化製程以移除閘極介電層92的多餘部分及閘極電極94的材料,這些多餘部分位於第一ILD 88的頂表面上方。閘極電極94及閘極介電層92的材料的剩餘部分因此形成所得之FinFETs的替換閘極。閘極電極94及閘極介電層92可統稱為「閘極堆疊」。閘極及閘極堆疊可沿著鰭片52的通道區58的側壁延伸。
可同時形成位於區域50N及區域50P中的閘極介電層92,使得各區域中的閘極介電層92是由相同的材料所形成,並且可同時形成閘極電極94,使得區域中的閘極電極94是由相同的材料所形成。在一些實施例中,可藉由不
同的製程來形成各區域中的閘極介電層92,使得閘極介電層92可為不同的材料,及/或可藉由不同的製程來形成各區域中的閘極電極94,使得閘極電極94可為不同的材料。使用不同的製程時,可使用各種遮蔽步驟來遮蔽及露出適當的區域。
第15A圖及第15B圖係根據一些實施例,將第二ILD 108沉積於第一ILD 88上方。在一些實施例中,第二ILD 108為藉由流動式CVD方法所形成的流動式膜(flowable film)。在一些實施例中,第二ILD 108是由例如PSG、BSG、BPSG、USG、氧化矽等的介電材料所形成,並且可藉由例如CVD及PECVD等任何合適的方法來沉積。可進行例如CMP的平坦化製程以將第二ILD 108的表面平坦化。在一些實施例中,第二ILD 108可形成為具有在約10nm至約30nm之間的厚度T1,儘管其他厚度為可能的。
根據一些實施例,在沉積第二ILD 108之前,在結構上方沉積硬遮罩96。硬遮罩96可包括一層或多層介電材料,例如氮化矽、氮氧化矽等,且硬遮罩96具有與上方的第二ILD 108的材料不同的蝕刻速率。在一些實施例中,硬遮罩96可形成為具有在約2nm至約4nm之間的厚度。在一些實施例中,硬遮罩96是由與CESL 87相同的材料所形成,或者形成為具有與CESL 87約相同的厚度。後續形成的源極/汲極接觸件118(參照第20圖)穿過硬遮罩96及CESL 87,以接觸磊晶源極/汲極區82的頂表面,且閘極接觸件132(參照第27A圖)穿過硬遮罩96以接觸閘極電極94的頂表面。
第16圖至第22圖係根據一些實施例,繪示出形成具有氣隙120的源極/汲極接觸件118(參照第22圖)的中間步驟。源極/汲極接觸件118實體及電性接觸磊晶源極/汲極區82。源極/汲極接觸件118也可被稱作「接觸件118」或「接
觸插塞118」。為了清楚起參照,第16圖至第22圖被繪示為第15B圖的區域111的詳細視圖。第16圖繪示出與第15B圖所示的結構相同的區域111。
第17圖係根據一些實施例,係在第一ILD 88及第二ILD 108中形成開口110,以露出磊晶源極/汲極區82。使用可接受的光學微影及蝕刻技術來形成開口110。舉例而言,可在第二ILD 108上方形成光阻(例如,單層或多層光阻結構)。然後可對光阻進行圖案化以在與開口110相對應的區中露出第二ILD 108。然後,使用圖案化的光阻作為蝕刻遮罩,可進行一個或多個適合的蝕刻製程以蝕刻開口110。一個或多個蝕刻製程可包括濕式蝕刻製程及/或乾式蝕刻製程。在一些實施例中,當形成開口110時,可將CESL 87及/或硬遮罩96用作蝕刻停止層。在一些實施例中,也可移除延伸於磊晶源極/汲極區82上方的CESL 87的部分。在其中開口延伸穿過CESL 87的一些實施例中,開口110可延伸於磊晶源極/汲極區82的頂表面下方並延伸至磊晶源極/汲極區82中。在一些實施例中,一個或多個蝕刻製程可移除第一ILD 88的材料以露出CESL 87,並且也可在磊晶源極/汲極區82上方部分地蝕刻CESL 87的部分。開口110可具有如第17圖所示的漸縮(tapered)側壁、或者可具有不同的輪廓(例如,垂直側壁)的側壁。在一些實施例中,開口110可具有在約10nm至約30nm之間的寬度W1,但是其他寬度也是可能的。可橫跨開口110的頂部、橫跨開口110的底部、或橫跨開口110在任何其他位置測量寬度W1。在一些情況下,控制寬度W1可控制源極/汲極接觸件118的尺寸及/或後續形成之氣隙120的尺寸(參照第22圖)。
第18圖係根據一些實施例,在開口110上方形成虛設間隔層112。在一些實施例中,首先進行蝕刻製程以移除位於磊晶源極/汲極區82上方的CESL 87。蝕刻製程可包括例如非等向性乾式蝕刻製程。蝕刻製程可將開口110延伸至
磊晶源極/汲極區82的頂表面下方並延伸至磊晶源極/汲極區82中。然後,可將虛設間隔層112形成為毯覆(blanket)層,毯覆層延伸於第二ILD 108、CESL 87及磊晶源極/汲極區82的上方。在一些實施例中,虛設間隔層112可包括例如矽、多晶矽、非晶矽等、或其組合的材料。在一些實施例中,虛設間隔層112可為相對於例如第二ILD 108、CESL 87、或接觸間隔層114(如後文所述)的其他層而言,以高選擇性蝕刻的材料。虛設間隔層112可藉由PVD、CVD、ALD等來沉積。在一些實施例中,虛設間隔層112可形成為具有在約3nm至約9nm之間的厚度,儘管其他厚度也是可能的。在一些實施例中,虛設間隔層112的厚度約等於後續形成的氣隙120的寬度W2(參照第22圖)。
第19圖係根據一些實施例,在虛設間隔層112上形成接觸間隔層114。在形成接觸間隔層114之前,可進行適合的非等向性乾式蝕刻製程,以移除橫向延伸於第二ILD 108及磊晶源極/汲極區82上方的虛設間隔層112的區。由於乾式蝕刻製程的非等向性,虛設間隔層112沿著開口110之側壁延伸的區域得以保留。在一些實施例中,非等向性乾式蝕刻製程也可蝕刻磊晶源極/汲極區82的材料,並因此將開口110進一步延伸至磊晶源極/汲極區82中。
在一些實施例中,接觸間隔層114可形成為毯覆層,毯覆層延伸於第二ILD 108、虛設間隔層112、及磊晶源極/汲極區82上方。接觸間隔層114可包括例如下列一層或多層材料:氧化矽、氮化矽、氮氧化矽、碳氮化矽等、或其組合。接觸間隔層114可藉由PVD、CVD、ALD等來沉積。在一些實施例中,接觸間隔層114可形成為具有約2nm至約5nm之間的厚度,例如約3nm,但是其他厚度也是可能的。在形成接觸間隔層114之後,可進行適當的非等向性乾式蝕刻製程以移除橫向延伸於第二ILD 108、虛設間隔層112、及磊晶源極/汲極區82
上方的接觸間隔層114的區域。由於乾式蝕刻製程的非等向性,沿著開口110之側壁延伸(例如,沿著虛設間隔層112延伸)的接觸間隔層114的區域得以保留。在一些情況下,控制接觸間隔層114的厚度可控制源極/汲極接觸件118的尺寸及/或後續形成之氣隙120的尺寸(參照第22圖)。
繼續參照第20圖,係根據一些實施例,將一種或多種導電材料沉積於開口110中,形成源極/汲極接觸件118。在一些實施例中,源極/汲極接觸件118的導電材料包括保形沉積於開口110的表面上(例如,在接觸間隔層114上)的襯層(未單獨繪示)及沉積在襯層上以填充開口110的導電填充材料。在一些實施例中,襯層包括鈦、鈷、鎳、氮化鈦、氧化鈦、氮化鉭、氧化鉭等、或其組合。在一些實施例中,導電填充材料包括鈷、鎢、銅、鋁、金、銀、其合金等、或其組合。可使用例如下列一種或多種合適的製程來沉積襯層或導電填充材料:CVD、PVD、ALD、濺鍍、電鍍等。
在一些實施例中,矽化物區116也可形成在磊晶源極/汲極區82的上部上,以改善磊晶源極/汲極區82與源極/汲極接觸件118之間的電性連接。在一些實施例中,可藉由使磊晶源極/汲極區82的上部與襯層反應來形成矽化物區116。在一些實施例中,可在磊晶源極/汲極區82上沉積分開的材料,以與磊晶源極/汲極區82反應以形成矽化物區116。矽化物區116可包括矽化鈦、矽化鎳等、或其組合。在一些實施例中,進行一個或多個退火製程以促進矽化物形成反應。在沉積用於源極/汲極接觸件118的導電填充材料之後,可藉由使用例如CMP的平坦化製程移除多餘的材料,以形成與第二ILD 108的頂表面共平面的源極/汲極接觸件118的頂面。
繼續參照第21圖,係根據一些實施例,將虛設間隔層112的材料
移除,以形成初始氣隙120’。可使用例如乾式蝕刻製程等的適當蝕刻製程來移除虛設間隔層112的材料。蝕刻製程可對位於第二ILD 108、CESL 87、或接觸間隔層114的材料上方的虛設間隔層112的材料具有選擇性。舉例而言,在虛設間隔層112包括矽且接觸間隔層114包括氮化矽的實施例中,蝕刻製程可包括在選擇性蝕刻虛設間隔層112的矽的電漿蝕刻製程中使用HBr、O2、He、CH3F、H2等、或其組合作為製程氣體,其他材料或蝕刻製程也是可能的。
在一些實施例中,初始氣隙120’可形成為具有在約0.5nm至約4nm之間的寬度W2,但是其他寬度也是可能的。在一些情況下,形成具有較大寬度W2的初始氣隙120’可導致降低的電容及改善的裝置性能,這將在後文更詳細地描述。初始氣隙120’可具有實質上均勻的寬度,或者寬度可沿著其垂直長度(例如,遠離基板50延伸的長度)變化。舉例而言,初始氣隙120’的寬度可漸縮,例如在底部附近(例如,在磊晶源極/汲極區82附近)的寬度小於頂部附近(例如,在第二ILD 108附近)的寬度。在一些實施例中,初始氣隙120’的底部可延伸至磊晶源極/汲極區82中(如第21圖所示),或者初始氣隙120’可在磊晶源極/汲極區82頂表面處或上方具有底部。如第21圖所示,初始氣隙120’可相對於縱軸成一定角度延伸,或者可實質上沿著縱軸延伸。在一些實施例中,初始氣隙120’可延伸約15nm至約80nm之間的垂直高度H1(例如,沿著縱軸的距離H1),但是其他高度也是可能的。
在一些情況下,藉由在源極/汲極接觸件118及閘極堆疊92/94之間形成初始氣隙120’(以及如第22圖所示後續形成的氣隙120),源極/汲極接觸件118及閘極堆疊層92/94之間的電容可降低。相對於例如氧化物、氮化物等的其他間隔物材料,由於空氣的介電常數(k值)較低,約為k=1,因此可以這種方式
降低電容。藉由使用氣隙120降低電容,FinFET裝置可在較高頻率的操作下具有更快的響應速度(response speed)及改善的性能。
繼續參照第22圖,在第二ILD 108上方、源極/汲極接觸件118上方、以及初始氣隙120’上方形成蝕刻停止層(etch stop layer,ESL)122。ESL 122可形成為橫跨初始氣隙120’延伸的毯覆層,使得初始氣隙120’被封閉(enclosed)並形成氣隙120。在一些實施例中,ESL 122的一些材料部分地延伸至初始氣隙120’中。如後文針對第26A圖至第26B圖及第27A圖至第27B圖所述,ESL 122可隨後在源極/汲極接觸件118上形成導電部件136的期間用作蝕刻停止層。
ESL 122可包括一層或多層材料,例如氮化矽、氮氧化矽、氮碳化矽、氮碳氧化矽等、或其組合,並且可使用例如ALD製程(例如,熱ALD製程或電漿增強ALD(plasma-enhanced atomic layer deposition,PEALD)製程)來沉積。在一些實施例中,可形成具有在第二ILD 108上方的厚度T2的ESL 122,上述厚度T2在約3nm至約30nm之間,但是其他厚度也是可能的。在一些實施例中,可沉積ESL 122,使得將ESL 122的材料形成為延伸至初始氣隙120’中並密封初始氣隙120’。ESL 122延伸至初始氣隙120’中的部分在第22圖及後續圖中表示為密封區123’。在一些實施例中,密封區123’可以約2nm至約20nm之間的垂直距離D1延伸至初始氣隙120’中,儘管其他距離也是可能的。在一些情況下,距離D1可小於、約相同、或大於第二ILD 108的厚度T1。在一些實施例中,如後文更詳細地討論,可藉由控制ESL 122材料沉積製程的參數來控制距離D1。
由密封區123’密封的初始氣隙120’的剩餘部分在第22圖及後續圖式中表示為氣隙120。在一些實施例中,氣隙120可延伸約10nm至約80nm之間的垂直高度H2,儘管其他距離是可能的。藉由控制ESL 122的沉積使得密封區
123’延伸至初始氣隙120’中,可阻止隨後沉積的導電部件136的導電材料(參照第27B圖)填充或部分填充初始氣隙120’。因此可維持氣隙的電容的益處,且也減少了導電部件136及閘極堆疊92/94之間的滲漏機會。舉例而言,在FinFET裝置的源極/汲極接觸件118及閘極堆疊92/94之間形成氣隙120可降低源極/汲極接觸件118及閘極堆疊92/94之間的寄生電容,這可改善FinFET的高速操作。此外,氣隙120的存在減少了源極/汲極接觸件118與閘極堆疊92/94之間或後續形成之導電部件136(參照第27B圖)與閘極堆疊92/94之間的滲漏機會。藉由控制密封區123’的距離D1,可控制後續形成之氣隙120的尺寸。舉例而言,在一些情況下,較小的距離D1可允許較大的氣隙120,這可進一步降低寄生電容或滲漏。
在使用ALD製程沉積ESL 122的材料的一些實施例中,可控制ALD製程的參數以控制密封區123’延伸進入初始氣隙120’的距離D1。在一些實施例中,可藉由控制ALD製程的一種或多種前驅物的劑量(例如,壓力及/或脈衝持續時間)來控制距離D1。舉例而言,較大劑量的前驅物可允許前驅物到達並與初始氣隙120’內更深的表面反應。以這種方式,更大劑量的前驅物可允許ESL 122的材料生長於更延伸進入初始氣隙120’的表面上。因此,較小劑量的前驅物可將ESL 122的材料的生長限製到初始氣隙120’頂部附近的表面。以這種方式,藉由控制一種或多種前驅物的劑量,可控制生長ESL 122的材料成長進入初始氣隙120’的距離,因此可控制密封區123’延伸進入初始氣隙120’的距離D1。
在一些實施例中,藉由使用較小劑量的前驅物,前驅物可能無法在ALD半循環期間到達初始氣隙120’的所有表面(例如,底部),因此並非所有潛在的表面反應位點在ALD半循環期間與前驅物反應。以這種方式,ALD製程不受表面反應位點飽和的限制,而是受到前驅物劑量的限制,並且本文所述之
ALD製程可被認為是「非飽和」或「低劑量」的ALD製程。此外,藉由使用較小的前驅物劑量,可控制ESL 122的材料,不填充初始氣隙120’而是在初始氣隙120’的上表面上生長,以形成被密封區123’密封的氣隙120。以這種方式,本文描述的非飽和ALD製程可減小用材料填充初始氣隙120’的風險來密封初始氣隙120’。
第23A圖及第23B圖繪示出類似於第22圖所示的結構,但是第23A圖繪示出密封區123’形成為具有較小距離D1的實施例,且第23B圖繪示出密封區123’形成為具有較大距離D1的實施例。在一些實施例中,可控制本文所述之非飽和ALD製程的參數以控制密封區123’的距離D1。舉例而言,可控制半循環的前驅物的劑量(例如,壓力及/或脈衝持續時間)以控制密封區123’的形成。類似於第23A圖所示的密封區123’,使用較小的前驅物劑量(例如,較小的前驅物壓力及/或較短的脈衝持續時間)可將密封區123’形成為以較小的距離D1延伸進入初始氣隙120’。類似於第23B圖所示的密封區123’,使用較大的前驅物劑量(例如,較大的前驅物壓力及/或較長的脈衝持續時間)可形成以較大的距離D1延伸進入初始氣隙120’的密封區123’,以這種方式,控制前驅物劑量可控制密封區123’延伸進入初始氣隙120’的距離D1。
作為另一示例,對於ALD製程為PEALD製程的實施例,可控制以半循環施加RF功率的持續時間以控制密封區123’的形成。隨著RF持續時間的減少而減少了所生成的反應性前驅物物質(species)的數量,較短的RF功率持續時間可形成以較小距離D1延伸的密封區123’,類似於第23A圖所示的密封區123’。更長的RF功率持續時間可形成以較大距離D1延伸的密封區123’,類似於第23B圖所示的密封區123’。在一些實施例中,相較於結合較長的前驅物脈衝持
續時間與較長的RF功率持續時間而言,結合較短的前驅物脈衝持續時間與較短的RF功率持續時間可形成具有較小距離D1的密封區123’。這些為示例,並且可以其他組合或其他變型形式控制前驅物壓力、脈衝持續時間、RF功率持續時間、及/或其他參數,以控制密封區123’的形成。可以這種方式控制ALD循環的不同部分的參數或前驅物,並且在一些實施例中,沉積製程的不同ALD循環的相同部分可具有不同的參數。第22圖、第23A圖、及第23B圖中所示的密封區123’及各自的距離D1為說明性示例,並且密封區123’可形成為具有與所示的距離D1不同的距離。
作為說明性示例,可使用PEALD製程來沉積包括氮化矽的ESL 122(及密封區123’)。形成矽(Silicon-forming)的前驅物可用於形成矽的半循環(silicon-forming half-cycle),並且在產生電漿之形成氮的半循環期間(nitrogen-forming half-cycle)可使用形成氮的前驅物例如N2、NH3等、或其組合,上述前驅物例如SiH4、SiH2Cl2、SiH2I2等、或其組合。在其他實施例中可使用除了這些以外的其他前驅物。可在約250℃至約400℃之間的製程溫度下在處理腔室中進行沉積,儘管可使用其他溫度。在一些實施例中,在形成矽的半循環中,可將形成矽的前驅物以介於約5sccm至約100sccm之間的流速脈衝進入處理腔室中,脈衝持續時間介於約0.1秒至0.5秒之間。形成矽的半循環的壓力可在約10Torr至約30Torr之間。在將形成矽的前驅物脈衝(pulsing)之後,可進行吹掃(purge)約0.1秒至約5秒。在一些實施例中,在形成氮的半循環中,可將形成氮的前驅物以約10sccm至約500sccm之間的流速脈衝進入處理腔室中,脈衝持續時間為約0.1秒至1秒。氮形成半循環的壓力可在約10Torr至約30Torr之間。可藉由RF功率在約0.1秒至約1秒之間來產生電漿。可藉由介於約100Watts
至約800Watts之間的RF功率來產生電漿。在將形成氮的前驅物脈衝之後,可進行吹掃約0.1秒至約1秒。這些為例示性參數值,並且在其他實施例中可使用除了這些示例以外的其他參數值或參數值的組合。
第24A圖至第27B圖係根據一些實施例,係在FinFETs的製造中額外階段的剖面圖。第24A圖至第27B圖繪示出第15A圖及第15B圖所示的結構的相同剖面圖。第24A圖及第24B圖繪示出在沉積ESL 122之後的結構,類似於第22圖所示的結構。
繼續參照第25A圖及第25B圖,係根據一些實施例,可在ESL 122上方形成介電層134。介電層134可由例如低k介電材料等合適的介電材料、例如聚酰亞胺的聚合物、氧化矽、氮化矽、碳化矽、氮碳化矽、氮碳氧化矽等或其組合所形成。可使用例如旋塗、CVD、PVD、ALD等合適的製程來形成介電層134。在一些實施例中,介電層134可以類似於先前描述的第一ILD 88或第二ILD 108的方式來形成。
第26A圖及第26B圖係根據一些實施例,可形成開口138及凹槽139。開口138延伸穿過介電層134及ESL 122,以露出源極/汲極接觸件118。第26B圖繪示出一實施例,其中單一開口138露出了兩個鄰近的源極/汲極接觸件118,但是在其他實施例中,單一開口138可露出單個源極/汲極接觸件118、或兩個以上的源極/汲極接觸件118。可使用適當的光學微影及蝕刻技術來形成開口138及凹槽139。舉例而言,可在介電層134上方形成光阻(例如,單層或多層光阻結構)。然後可對光阻進行圖案化以在與開口138相對應的區域中露出介電層134。然後,使用圖案化的光阻作為蝕刻遮罩,可進行適合的蝕刻製程以蝕刻開口138。一個或多個蝕刻製程可包括濕式蝕刻製程及/或乾式蝕刻製程。在一些實施
例中,當形成開口138時,可將ESL 122用作蝕刻停止層。開口138可具有如第26B圖所示的漸縮的側壁,或者可具有具有不同輪廓的側壁(例如,垂直側壁)。
繼續參照第26B圖,密封區123’的部分也可藉由(多個)蝕刻製程來移除,形成延伸至初始氣隙120’中的凹槽139(參照第21圖)。可控制(多個)蝕刻製程,使得在形成開口138之後繼續藉由密封區123’的剩餘部分來密封氣隙120。可將密封區123’的剩餘部分稱作「密封件(seals)123」。由於形成密封件123的密封區123’的剩餘部分,使用密封區123’密封氣隙120可防止在形成開口138時露出氣隙120。在一些實施例中,凹槽139可以垂直距離D2延伸至初始氣隙120’中,上述垂直距離D2在約0nm至約15nm之間,但是其他距離也是可能的。密封件123的可能尺寸在後文針對第28圖更詳細地描述。
此外,密封件123的存在保護了氣隙120並且阻止後續形成的導電材料進入氣隙120,這可減少後續形成的導電部件136(參照第27B圖)及閘極堆疊92/94之間滲漏的機會。舉例而言,儘管第26B圖繪示出被圖案化以在氣隙120上方延伸的開口138,但是在其他情況下,由於例如光學微影未對準,可能不期望地形成了在氣隙120上延伸的開口138。因此,藉由密封件123防止了隨後沉積的材料進入氣隙120。通過控制凹槽139相對於密封區123’的垂直距離D1(參照第22圖)的深度D2,可減小密封件123的深度,密封件123的位置及尺寸可被控制,這可取決於特定的應用或期望的結構。舉例而言,具有較大尺寸的密封件123可提供更多的防止滲漏的保護,或者具有較小尺寸的密封件123可允許更大的氣隙120,因此進一步降低寄生電容。這些為示例,並且其他配置或考慮因素也是可能的。
第27A圖及第27B圖係根據一些實施例,將導電部件136形成為接
觸源極/汲極接觸件118。第28圖繪示出第27B圖的區域135的詳細視圖。導電部件136可包括與源極/汲極接觸件118實體及電性接觸的一個或多個金屬線及/或導孔。導電部件136可為例如重分佈層(redistribution layers)。可使用任何合適的技術來形成導電部件136。
在一些實施例中,可使用單及/或雙金屬鑲嵌製程、導孔先製製程(via-first process)、或金屬先製製程(metal-first process)形成導電部件136的材料。在一些實施例中,在開口138及凹槽139中形成例如擴散阻擋層、黏著層等的襯層137(未繪示)。襯層可包括鈦、氮化鈦、鉭、氮化鉭等,可使用例如CVD、ALD等的沉積製程來形成襯層。然後,可在襯層137上方形成導電材料。導電材料可為銅、銅合金、銀、金、鎢、鈷、鋁、鎳等、或其組合。導電材料可藉由例如化學電鍍製程(electro-chemical plating process)、CVD、ALD、PVD等、或其組合在開口138及凹槽139中的襯層137上方形成。襯層137的材料及/或導電材料被密封件123阻止進入氣隙120。可進行例如CMP的平坦化製程以從介電層134的表面移除多餘的材料。剩餘的襯層137及導電材料形成導電部件136。在其他實施例中,可使用其他技術來形成導電部件136。如第28圖所示,密封件123可藉由導電部件136與ESL 122的剩餘部分(例如,第二ILD 108上的一部分)間隔開。
第27A圖也繪示出實體及電性耦合至閘極電極94的閘極接觸件132。可藉由例如下列製程來形成閘極接觸件132:藉由使用合適的光學微影及蝕刻製程藉由形成露出閘極電極94的開口,然後在開口內沉積可選的襯層及導電材料。閘極接觸件132可在形成介電層134之前或之後形成。源極/汲極接觸件118及閘極接觸件132可以不同的製程形成、或者可以相同的製程形成。在一些
實施例中,也可形成與閘極接觸件132接觸的一些導電部件136(第27A圖中未繪示)。
參照第28圖,每個密封件123可形成為具有與先前描述的初始氣隙120’的寬度W2大致相同的寬度。密封件123的寬度可實質上不變,或者密封件123可具有凹形、凸形、漸縮的、或不規則形的側壁輪廓。如第28圖所示,密封件123可具有實質上垂直的側壁或可具有至少部分斜角的側壁。在一些實施例中,密封件123可延伸約1nm至約15nm之間的垂直高度H3,儘管其他高度也是可能的。在一些實施例中,密封件123的高度H3可在第二ILD 108的厚度T1的約1%至約150%之間,但是其他分率(fraction)也是可能的。在一些情況下,更大的高度H3可提供對氣隙120之改善的密封並且改善防止電子短路或滲漏。在一些實施例中,密封件123的頂表面可在閘極堆疊上方(例如,在閘極介電層92及閘極電極94上方)的垂直距離D4,上述垂直距離D4在約0nm至約35nm之間,但是其他距離也是可能的。密封件123的頂表面可在閘極堆疊上方、在閘極堆疊下方、或與閘極堆疊約齊平。在一些情況下,密封件123的頂表面與閘極堆疊之間較大的垂直距離D4可允許改善防止導電部件136與閘極堆疊之間的滲漏或短路。在一些實施例中,密封件123可具有在約4:1至約1:30之間的深寬比(寬度:高度),儘管其他深寬比也是可能的。在一些情況下,具有相對較寬的深寬比的密封件123可允許較大的氣隙120,這可改善電容降低。在一些實施例中,密封件123可具有實質上平坦的頂表面、及/或實質上平坦的底表面,其可為實質上水平的(例如,平行於基板50的平面)、或可相對於水平成一角度。第28圖繪示出一實施例,其中密封件123的頂表面及底表面實質上為平坦的並且實質上為水平的。在其他實施例中,密封件123的頂表面、及/或底表面可為凸的、凹的、
圓形的、不規則的、或具有另一種形狀。
參照第28圖,填充凹槽139的導電部件136的部分可具有在約0.5nm及約4nm之間的寬度W3,儘管其他寬度也是可能的。寬度W3可與先前描述的初始氣隙120’的寬度W2大致相同。凹槽139內的導電部件136的寬度可為實質上不變、或者可具有凹形、凸形、漸縮的、或不規則形的側壁輪廓。如第28圖所示,凹槽139內的導電部件136可具有實質上垂直的側壁、或可具有至少部分成角度的側壁。在一些實施例中,凹槽139內的導電部件136可以垂直距離D3延伸於第二ILD 108的頂表面下方,上述垂直距離D3在約0nm至約15nm之間,儘管其他距離也是可能的。垂直距離D3可與針對第26B圖描述的凹槽139的垂直距離D2約相同。在一些實施例中,垂直距離D3可在第二ILD 108的厚度T1的約0%至約150%之間,儘管其他分率也是可能的。在一些情況下,較小的垂直距離D3可允許形成較大的氣隙120,並且因此可允許改善電容降低。在一些實施例中,凹槽139內的導電部件136可具有在約10:1至約1:30之間的深寬比(寬度:高度),儘管其他深寬比也是可能的。在一些情況下,相對較寬的深寬比可允許更大的氣隙120,這可改善電容降低。在一些實施例中,凹槽139內的導電部件136可具有實質上平坦的底表面,底表面可為實質上水平的(例如,平行於基板50的平面)、或可相對於水平成一角度。第28圖繪示出一實施例,其中凹槽139內的導電部件136的底表面為實質上平坦的並且是實質上水平的。在其他實施例中,凹槽139內的導電部件136的底表面可為凸的、凹的、圓形的、不規則的、或具有另一種形狀。
實施例可實現優點。藉由在FinFET裝置的源極/汲極接觸件與閘極堆疊之間形成氣隙,可降低源極/汲極接觸件與閘極堆疊之間的電容。電容降
低可提高FinFET裝置的速度或高頻操作。此外,氣隙的頂部是由上方介電層的剩餘部分所密封,介電層可為蝕刻停止層。藉由密封氣隙,可阻止不需要的材料進入氣隙並降低裝置性能或導致製程缺陷。舉例而言,介電層的密封部分可改善FinFET的源極/汲極接觸件及閘極之間的隔離。在一些情況下,控制用於形成介電層的ALD製程的劑量及/或PEALD製程的RF時間可控制氣隙內介電層的剩餘部分的尺寸或深度。
在一些實施例中,一種半導體裝置,包括:鰭片,從半導體基板延伸;閘極堆疊,位於鰭片上方;間隔物,位於閘極堆疊的側壁上;源極/汲極區,位於鄰近於間隔物的鰭片中;層間介電層(inter-layer dielectric,ILD),延伸於閘極堆疊、間隔物、及源極/汲極區上方;接觸插塞,延伸穿過ILD並接觸源極/汲極區;介電層,包括位於ILD的頂表面上的第一部分及延伸於ILD及接觸插塞之間的第二部分,其中第二部分的頂表面相較於ILD的頂表面更靠近基板;及氣隙,位於間隔物及接觸插塞之間,其中介電層的第二部分密封氣隙的頂部。在一實施例中,半導體裝置包括導電材料,延伸於ILD、第二部分、及接觸插塞上。在一實施例中,導電材料藉由第二部分與氣隙間隔開。在一實施例中,第一部分藉由導電材料與第二部分間隔開。在一實施例中,介電層包括氮化矽。在一實施例中,第二部分的頂表面在ILD的頂表面下方的0nm至15nm之間的範圍內。在一實施例中,第二部分具有在1nm至15nm之間的範圍內的垂直厚度。在一實施例中,第二部分具有在0.5nm及4nm之間的範圍內的寬度。在一實施例中,第一部分具有在3nm至30nm之間的範圍內的垂直厚度。在一實施例中,第二部分的底表面相較於ILD的底表面更遠離基板。
在一些實施例中,一種半導體裝置的形成方法,包括:形成從基
板突出的鰭片;形成閘極結構於鰭片的通道區上方;沿著閘極結構的側壁形成閘極間隔物;形成磊晶區於鄰近於通道區的鰭片中;沉積第一介電層於閘極結構及閘極間隔物上方,第一介電層包括第一介電材料;形成延伸穿過第一介電層並接觸磊晶區的接觸插塞,其中氣隙將接觸插塞及閘極間隔物間隔開;沉積第二介電層於第一介電層上方及接觸插塞上方,包括用第二介電層密封氣隙的下部區,其中第二介電層包括不同於第一介電材料的第二介電材料;蝕刻第二介電層以露出接觸插塞,其中在蝕刻第二介電層之後,第二介電層的剩餘部分密封氣隙的下部區;及沉積導電材料於接觸插塞上,包括沉積導電材料於接觸插塞及第一介電材料之間、以及於第二介電層的剩餘部分上。在一實施例中,氣隙的上部區將第一介電層及接觸插塞間隔開。在一實施例中,第二介電層的剩餘部分的厚度小於第一介電層的厚度。在一實施例中,第二介電層的剩餘部分相較於第一介電層的頂表面更靠近基板。在一實施例中,沉積導電材料的步驟包括沉積導電材料於第一介電層的頂表面上。在一實施例中,第二介電層的剩餘部分從第一介電層延伸至接觸插塞上的間隔層。
在一些實施例中,一種半導體裝置的形成方法,包括:形成閘極堆疊於半導體鰭片上方;形成磊晶源極/汲極區於鄰近於閘極堆疊層的半導體鰭片中;沉積第一介電層於閘極堆疊上方及磊晶源極/汲極區上方;形成開口於第一介電層中,以露出磊晶源極/汲極區;沉積犧牲材料於開口內;沉積第一導電材料於開口內的犧牲材料上方;移除犧牲材料,以形成間隙;沉積第二介電層於第一介電層上方、第一導電材料上方、以及間隙上方,其中第二介電層延伸第一距離進間隙中;及蝕刻第二介電層,以露出第一導電材料,其中第二介電層的多個第一部分在蝕刻之後保留在間隙內。在一實施例中,沉積第二介電層
的步驟包括使用電漿增強原子層沉積(plasma-enhanced atomic layer deposition,PEALD)製程來沉積氮化矽。在一實施例中,蝕刻第二介電層的步驟包括蝕刻位於間隙內的第二介電層的多個第二部分。在一實施例中,半導體裝置的形成方法包括沉積第二導電材料於第一導電材料上及第二介電層的該些第一部分上。
以上概述數個實施例之特徵,以使本發明所屬技術領域中具有通常知識者可更加理解本發明實施例的觀點。本發明所屬技術領域中具有通常知識者應理解,可輕易地以本發明實施例為基礎,設計或修改其他製程及結構,以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解,此類等效的結構並無悖離本發明的精神與範圍,且可在不違背本發明之精神及範圍下,做各式各樣的改變、取代及替換。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。
50:基板
52:鰭片
58:通道區
80:閘極密封間隔物
82:磊晶源極/汲極區
86:閘極間隔物
87:接觸蝕刻停止層
92:閘極介電層
94:閘極電極
96:硬遮罩
108:第二ILD
114:接觸間隔層
116:矽化物區
118:源極/汲極接觸件
120:氣隙
122:蝕刻停止層
123’:密封區
T1:厚度
T2:厚度
W2:寬度
H2:高度
D1:距離
Claims (13)
- 一種半導體裝置,包括:一鰭片,從一半導體基板延伸;一閘極堆疊,位於該鰭片上方;一間隔物,位於該閘極堆疊的側壁上;一源極/汲極區,位於鄰近於該間隔物的該鰭片中;一層間介電層(inter-layer dielectric,ILD),延伸於該閘極堆疊、該間隔物、及該源極/汲極區上方;一接觸插塞,延伸穿過該ILD並接觸該源極/汲極區;一介電層,包括位於該ILD的一頂表面上的一第一部分及延伸於該ILD及該接觸插塞之間的一第二部分,其中該第二部分的一頂表面相較於該ILD的該頂表面更靠近該基板;及一氣隙,位於該間隔物及該接觸插塞之間,其中該介電層的該第二部分密封該氣隙的頂部。
- 如請求項1所述之半導體裝置,更包括一導電材料,延伸於該ILD、該第二部分、及該接觸插塞上。
- 如請求項2所述之半導體裝置,其中該導電材料藉由該第二部分與該氣隙間隔開,其中該第一部分藉由該導電材料與該第二部分間隔開。
- 如請求項1所述之半導體裝置,其中該第二部分的該頂表面在該ILD的該頂表面下方的0nm至15nm之間的範圍內,其中該第二部分的一底表面相較於該ILD的一底表面更遠離該基板。
- 如請求項1所述之半導體裝置,其中該第二部分具有在1nm 至15nm之間的範圍內的垂直厚度,其中該第二部分具有在0.5nm及4nm之間的範圍內的寬度。
- 如請求項1至5中任一項所述之半導體裝置,其中該第一部分具有在3nm至30nm之間的範圍內的垂直厚度。
- 一種半導體裝置的形成方法,包括:形成從一基板突出的一鰭片;形成一閘極結構於該鰭片的一通道區上方;沿著該閘極結構的側壁形成一閘極間隔物;形成一磊晶區於鄰近於一通道區的該鰭片中;沉積第一介電層於該閘極結構及該閘極間隔物上方,該第一介電層包括一第一介電材料;形成延伸穿過該第一介電層並接觸該磊晶區的一接觸插塞,其中一氣隙將該接觸插塞及該閘極間隔物間隔開;沉積一第二介電層於該第一介電層上方及該接觸插塞上方,包括用該第二介電層密封該氣隙的一下部區,其中該第二介電層包括不同於該第一介電材料的一第二介電材料;蝕刻該第二介電層以露出該接觸插塞,其中在蝕刻該第二介電層之後,該第二介電層的一剩餘部分密封該氣隙的該下部區;及沉積一導電材料於該接觸插塞上,包括沉積該導電材料於該接觸插塞及該第一介電材料之間、以及於該第二介電層的該剩餘部分上。
- 如請求項7所述之半導體裝置的形成方法,其中該氣隙的一上部區將該第一介電層及該接觸插塞間隔開。
- 如請求項7所述之半導體裝置的形成方法,其中該第二介電層的該剩餘部分的厚度小於該第一介電層的厚度,其中該第二介電層的該剩餘部分相較於該第一介電層的一頂表面更靠近該基板,其中該第二介電層的該剩餘部分從該第一介電層延伸至該接觸插塞上的一間隔層。
- 如請求項7至9中任一項所述之半導體裝置的形成方法,其中沉積該導電材料的步驟包括沉積該導電材料於該第一介電層的一頂表面上。
- 一種半導體裝置的形成方法,包括:形成一閘極堆疊於一半導體鰭片上方;形成一磊晶源極/汲極區於鄰近於該閘極堆疊層的該半導體鰭片中;沉積一第一介電層於該閘極堆疊上方及該磊晶源極/汲極區上方;形成一開口於該第一介電層中,以露出該磊晶源極/汲極區;沉積一犧牲材料於該開口內;沉積一第一導電材料於該開口內的該犧牲材料上方;移除該犧牲材料,以形成一間隙;沉積一第二介電層於該第一介電層上方、該第一導電材料上方、以及該間隙上方,其中該第二介電層延伸一第一距離進該間隙中;及蝕刻該第二介電層,以露出該第一導電材料,其中該第二介電層的多個第一部分在蝕刻之後保留在該間隙內。
- 如請求項11所述之半導體裝置的形成方法,其中蝕刻該第二介電層的步驟包括蝕刻位於該間隙內的該第二介電層的多個第二部分。
- 如請求項11至12中任一項所述之半導體裝置的形成方法,更包括沉積一第二導電材料於該第一導電材料上及該第二介電層的該些第一部分 上。
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2021
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- 2021-01-18 DE DE102021100840.9A patent/DE102021100840B4/de active Active
- 2021-02-25 KR KR1020210025706A patent/KR102546906B1/ko active IP Right Grant
- 2021-03-23 CN CN202110307154.5A patent/CN114551400A/zh active Pending
- 2021-08-06 TW TW110129094A patent/TWI808458B/zh active
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2023
- 2023-08-01 US US18/363,554 patent/US20240021619A1/en active Pending
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TW202230610A (zh) | 2022-08-01 |
US20220231023A1 (en) | 2022-07-21 |
DE102021100840A1 (de) | 2022-07-21 |
US20240021619A1 (en) | 2024-01-18 |
KR102546906B1 (ko) | 2023-06-22 |
DE102021100840B4 (de) | 2023-01-12 |
KR20220103579A (ko) | 2022-07-22 |
CN114551400A (zh) | 2022-05-27 |
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