CN114551352A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN114551352A
CN114551352A CN202210084499.3A CN202210084499A CN114551352A CN 114551352 A CN114551352 A CN 114551352A CN 202210084499 A CN202210084499 A CN 202210084499A CN 114551352 A CN114551352 A CN 114551352A
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layer
type epitaxial
epitaxial layer
bottommost
region
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江国诚
陈燕铭
郑嵘健
王志豪
程冠伦
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

公开了一种半导体结构、半导体器件及其制造方法。一种示例性制造方法包括：在半导体衬底的正面形成第一类型外延层与第二类型外延层的堆叠件；对堆叠进行图案化以形成鳍状结构；在鳍状结构的侧壁上沉积介电层；以及使介电层凹陷以暴露鳍状结构的顶部部分。该凹陷介电层的顶面位于堆叠件的底面上方。该示例性制造方法还包括：在鳍状结构的顶部部分上方形成栅极结构；从半导体衬底的背面蚀刻半导体衬底；以及穿过沟槽蚀刻至少最底第一类型外延层和最底第二类型外延层。

Description

半导体器件及其制造方法
技术领域
本发明的实施例涉及半导体器件及其制造方法。
背景技术
半导体集成电路(IC)行业经历了指数式增长。IC材料和设计的技术进步已生产出几代IC，其中，每一代具有都比上一代更小、更复杂的电路。在IC的发展过程中，功能密度(即每个芯片区互连器件的数量)普遍增加，而其几何尺寸(即使用制造工艺中可制造的最小元件(或线路))则在减小。这种按比例缩小工艺一般通过提高生产效率和降低相关成本带来效益。这种按比例缩小也增加了加工和制造IC的复杂度。
例如，随着IC技术朝着更小的技术节点发展，已经引入了多栅极金属氧化物半导体场效应晶体管(多栅极MOSFET或多栅极器件)，以通过增加栅极-沟道耦合、减小截止状态电流和减小短沟道效应(SCE)改进栅极控制。多栅极器件通常是指使栅极结构(也称为栅极堆叠件)或其一部分设置在沟道区的多个侧上方的器件。鳍式场效应晶体管(FinFET)和多桥沟道(MBC)晶体管是多栅极器件的示例，这些器件已成为高性能和低泄漏应用的流行和有希望的候选者。FinFET的高边沟道在多个侧的上方被栅极结构环绕(例如，栅极环绕从衬底延伸的半导体材料“鳍”的顶部和侧壁)。MBC晶体管的栅极结构可部分或全部围绕沟道区延伸，以提供对两侧或更多侧沟道区的访问。由于MBC晶体管的栅极结构围绕沟道区，因此MBC晶体管也可被称为环绕栅极晶体管(SGT)或全环绕栅极(GAA)晶体管。
IC芯片不同区或电路不同部分的MBC晶体管具有不同的功能，诸如输入/输出(I/O)功能和核心功能。这些不同的功能要求晶体管具有不同的结构。同时，具有类似的工艺和类似的工艺窗口来制造这些不同的晶体管以降低成本和提高产量是有利的。例如，IC芯片可包括用于高性能计算(HPC)单元或中央处理单元(CPU)的高功率区，这需要具有强大电流驱动能力的MBC晶体管来实现高运行速度，并且IC芯片可包括用于I/O或片上系统(SoC)单元的低功率区，这需要具有较小电流驱动能力的MBC晶体管来实现低电容和低泄漏性能。因此，在一个IC芯片中，不同区的MBC晶体管的沟道构件的数量需求可能不同。通常，具有更多沟道构件的MBC晶体管提供更强的电流驱动能力，反之亦然。因此，在IC演进的过程中，如何在一个IC芯片上实现适合不同应用的不同沟道构件的数量是半导体行业面临的挑战。同时，具有类似的工艺和类似的工艺窗口来制造这些不同的晶体管以降低成本和提高产量是有利的。因此，尽管现有的半导体器件通常足以满足其预期目的，但它们并非在所有方面令人满意。
发明内容
根据本发明实施例的一个方面，提供了一种制造半导体器件的方法，包括：在半导体衬底的正面形成第一类型外延层与第二类型外延层的堆叠件，第一类型外延层与第二类型外延层具有不同的材料组分，第一类型外延层与第二类型外延层在竖直方向上交替设置；对堆叠件进行图案化以形成鳍状结构；在鳍状结构的侧壁上沉积介电层；使介电层凹陷以暴露鳍状结构的顶部部分，其中，凹陷介电层的顶面位于堆叠件的底面上方；在鳍状结构的顶部部分上方形成栅极结构；从半导体衬底的背面蚀刻半导体衬底，从而在介电层之间形成沟槽，沟槽暴露堆叠件的底面；以及穿过沟槽蚀刻至少最底第一类型外延层和最底第二类型外延层。
根据本发明实施例的另一个方面，提供了一种制造半导体器件的方法，包括：在衬底的第一区上方形成第一多个沟道构件，第一多个沟道构件竖直堆叠；在衬底的第二区上方形成第二多个沟道构件，第二多个沟道构件竖直堆叠；在第一区和第二区中形成隔离部件，其中，隔离部件的顶面在第二区中高于在第一区中，使得第二多个沟道部件的一部分在第二区中位于隔离部件的顶面下方；形成与第一多个沟道构件接合的第一栅极结构，从而在第一区中形成第一晶体管；形成与第二多个沟道构件接合的第二栅极结构，从而在第二区中形成第二晶体管；以及从第二区去除第二多个沟道构件的部分，使得第一晶体管中的第一多个沟道构件的数量大于第二晶体管中的第二多个沟道构件的数量。
根据本发明实施例的又一个方面，提供了一种半导体器件，包括：第一栅极结构，与第一多个沟道构件接合；第二栅极结构，与第二多个沟道构件接合；第一背面介电部件，设置在第一栅极结构正下方；以及第二背面介电部件，设置在第二栅极结构正下方，其中，第一多个沟道构件的数量大于第二多个沟道构件的数量。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A和图1B示出根据本发明的一个或多个方面的用于制造半导体器件的示例方法的流程图。
图2示出根据本发明的一个或多个方面的半导体器件的透视图。
图3A、图3B、图3C、图3D、图4A、图4B、图4C、图4D、图5A、图5B、图5C、图5D、图6A、图6B、图6C、图6D、图7A、图7B、图7C、图7D、图8A、图8B、图8C、图8D、图9A、图9B、图9C、图9D、图10A、图10B、图10C、图10D、图11A、图11B、图11C、图11D、图12A、图12B、图12C、图12D、图13A、图13B、图13C、图13D、图14A、图14B、图14C、图14D、图15A、图15B、图15C、图15D、图16A、图16B、图16C、图16D、图17A、图17B、图17C、图17D、图18A、图18B、图18C、图18D、图19A、图19B、图19C、图19D、图20A、图20B、图20C、图20D、图21A、图21B、图21C、图21D、图21E、图21F、图22A、图22B、图22C、图22D、图23A、图23B、图23C、图23D、图24A、图24B、图24C、图24D、图25A、图25B、图25C、图25D、图25E、图25F、图26A、图26B、图26C、图26D、图26E、图26F、图27A、图27B、图27C、图27D、图28A、图28B、图28C和图28D示出根据本发明的一个或多个方面的在图1A和图1B中的方法的各个制造阶段期间的图2中的半导体器件的局部截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或示例。下面描述了组件和布置的具体示例以简化本发明。当然，这些仅仅是示例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个示例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，本发明可在各个示例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。此外，在随后的本发明中的另一部件上、连接至和/或耦合至另一部件的部件的形成可包括与部件直接接触的实施例，也可包括形成为插入部件的附加部件，使得部件不直接接触的实施例。此外，为了便于描述本发明，空间相对术语，例如“下”、“上”、“水平”、“竖直”、“以上”、“上方”、“下方”、“以下”、“向上”、“向下”、“下方”、“顶部”、“底部”等及其派生词(例如，“水平地”、“向下地”、“向上地”等)用于描述一个部件与另一部件的关系。空间相对术语旨在覆盖包括部件的器件的不同取向。更进一步，用“约”、“近似”等描述数值或数值范围时，该术语旨在涵盖在包括所描述的数字在内的合理范围内的数字，诸如所描述的数字或如本领域技术人员理解的其他值的+/-10％内。例如，术语“约5nm”涵盖从4.5nm至5.5nm的尺寸范围。
本发明总体上涉及半导体器件及其制造，并且更具体地涉及具有晶体管的集成电路(IC)芯片，该晶体管在不同区中具有不同数量的沟道构件以适合在一个芯片上的不同应用。在各种实施例中，在同一衬底上具有不同(变化)数量的沟道构件的多桥沟道(MBC)晶体管分别放置在一个IC芯片内的第一区(例如，用于高功率应用的核心区)和第二区(例如，一个用于低泄漏应用的I/O区)中。根据本发明的各个方面，可从半导体结构的背面实现不同数量的沟道构件。尽管包括纳米线或纳米片形式的堆叠半导体沟道层的实施例在图中被示出为沟道构件，但本发明不限于此并且可适用于其他多栅极器件，诸如其他类型的MBC晶体管或FinFET。
现在将参考附图更详细地描述本发明的各个方面。图1A和图1B共同示出形成半导体器件的方法100的流程图。方法100仅是一个示例，并不旨在将本发明限制为方法100中明确示出的内容。可在这些方法之前、期间和之后提供附加步骤，并且对于方法100的附加实施例，可替换、消除或移动所描述的一些步骤。为了简单起见，本文未详细描述所有步骤。下面结合图2至图28D描述方法100，图2至图28D示出根据方法100的实施例的不同制造阶段的工件200的局部透视图和截面图。因为半导体器件将由工件200形成，所以如上下文需要，工件200可被称为半导体器件200或器件200。
在一些实施例中，工件200是IC芯片、片上系统(SoC)或其部分的一部分，包括各种无源和有源微电子器件，诸如电阻器、电容器、电感器、二极管、p型场效应晶体管(PFET)、n型场效应晶体管(NFET)、FinFET、纳米片FET、纳米线FET、其他类型的多栅极FET、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、横向扩散MOS(LDMOS)晶体管、高压晶体管、高频晶体管、存储器件、其他合适的元件或其组合。为了清楚起见，已经简化图2至图28D以更好地理解本发明的发明构思。可在工件200中添加附加部件，并且在工件200的其他实施例中可替换、修改或消除下文描述的某些部件。工件200包括用于大功率和/或高速应用的第一区(也表示为区I)，诸如需要较强电流驱动能力的核心区域、以及用于低电容和/或低泄漏应用的第二区(也表示为区II)，诸如需要较弱电流驱动能力的I/O区域。区I可包括高性能计算(HPC)单元、中央处理器(CPU)逻辑电路、存储器电路和其他核心电路。区II可包括I/O单元、ESD单元和其他电路。
图2示出工件200的透视图，并且图3A至图28D分别部分地示出沿着图2中的A-A线、B-B线、C-C线、D-D线、E-E线和F-F线的工件200的截面图。具体地，A-A线和B-B线分别是区I和II中的待形成晶体管的沟道区中的局部截面图(即沿着栅极结构长度方向并垂直于沟道构件的长度方向的沟道区中的中Y-Z平面中的切面)；C-C线和D-D线分别是沿着区I和II中的待形成晶体管中的沟道构件的长度方向的局部截面图(即沿着沟道构件的长度方向并穿过沟道区和邻接的源极/漏极区的X-Z平面中的切面)；E-E和F-F线分别是区I和II中的待形成晶体管的源极/漏极区的局部截面图(即垂直于沟道构件的纵向方向的源极区或漏极区中的Y-Z平面中的切口)。在本发明中，源极与漏极可互换使用。
参考图2和图3A至图3D，方法100包括接纳工件200的框102(图1A)。工件200包括衬底202和设置在衬底202上的堆叠件204。在一个实施例中，衬底202可以是硅(Si)衬底。在一些其他实施例中，衬底202可包括其他半导体材料，诸如锗(Ge)、硅锗(SiGe)或III-V半导体材料。示例III-V半导体材料可包括砷化镓(GaAs)、磷化铟(InP)、磷化镓(GaP)、氮化镓(GaN)、磷化砷化镓(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、磷化铟镓镓(GaInP)和砷化铟镓(InGaAs)。在各种实施例中，衬底202是从区I连续延伸至区II的一个衬底。
堆叠件204可包括在衬底202上方的交替的沟道层208和牺牲层206以及在牺牲层206和沟道层208上方的顶牺牲层206T。可使用外延工艺来沉积牺牲层206、沟道层208和顶牺牲层206T。示例外延工艺可包括气相外延(VPE)、超高真空CVD(UHV-CVD)、分子束外延(MBE)和/或其他合适的工艺。沟道层208与牺牲层206可具有不同的半导体组分。在一些实现方式中，沟道层208由硅(Si)形成并且牺牲层206由硅锗(SiGe)形成。牺牲层206中的附加锗(Ge)含量允许选择性地去除或凹陷牺牲层206而不会对沟道层208造成实质性损坏。牺牲层206与沟道层208交替设置，使得牺牲层206与沟道层208交错。图2示出交替且竖直布置的牺牲层206中的三(3)个层与沟道层208中的三(3)个层，这仅用于说明性目的，并且不旨在超出权利要求书中具体阐述的内容的限制。层数取决于半导体器件200的沟道层208的期望数量。在一些实施例中，沟道层208的数量介于2与7之间。
与牺牲层206一样，顶牺牲层206T可由硅锗(SiGe)形成。在一些示例中，牺牲层206与顶牺牲层206T的组分基本相同。顶牺牲层206T可比牺牲层206厚，并起到保护堆叠件204在制造工艺期间免受损坏的作用。在一些示例中，顶牺牲层206T的厚度可介于约20nm与约40nm之间，而牺牲层206的厚度可介于约4nm与约15nm之间。
参考图4A至图4C，方法100包括框104(图1A)，其中，对堆叠件204和衬底202进行图案化以形成被鳍沟槽212分离的鳍状结构210。为了对进行堆叠件204和衬底202图案化，硬掩模层214沉积在顶牺牲层206T上方。然后对硬掩模层214进行图案化以用作蚀刻掩模以对顶牺牲层206T、堆叠件204和衬底202的顶部部分进行图案化。在一些实施例中，可使用CVD、等离子增强CVD(PECVD、原子层沉积(ALD)、等离子增强ALD(PEALD)或合适的沉积方法)来沉积硬掩模层214。硬掩模层214可以是单层或多层。当硬掩模层214是多层时，硬掩模层214可包括衬垫氧化物和衬垫氮化物层。在可选的实施例中，硬掩模层214可包括硅(Si)。鳍状结构210可使用合适的工艺来图案化，包括双重图案化或多重图案化工艺。通常，双重图案化或多重图案化工艺将光刻与自对准工艺相结合，从而允许创建例如间距小于可使用单种直接光刻工艺获得的间距的图案。例如，在一个实施例中，材料层形成在衬底上方并使用光刻工艺来图案化。使用自对准工艺来在图案化材料层旁边形成间隔件。然后去除材料层，然后可使用剩余的间隔件或心轴来对硬掩模层214进行图案化，然后可将图案化的硬掩模层214用作蚀刻掩模来蚀刻堆叠件204和衬底202，以形成鳍状结构210。蚀刻工艺可包括干蚀刻、湿蚀刻、反应性离子蚀刻(RIE)和/或其他合适的工艺。
仍然参考图4A至图4D，鳍状结构210中的每个包括由衬底202的部分形成的底座部分210B和由堆叠件204形成的顶部部分210T。顶部部分210T设置在底座部分210B上方。鳍状结构210从衬底202沿着X方向纵向延伸并沿着Z方向竖直延伸。沿着Y方向，鳍状结构210被鳍状沟槽212分离。在一些示例中，鳍沟槽212具有在约20nm至约50nm范围内的宽度，从而限定相邻鳍状结构210之间的间距。
参考图5A至图5D，方法100包括框106(图1A)，其中，在鳍沟槽212中形成隔离部件216。隔离部件216可被称为浅槽隔离(STI)部件216。在形成隔离部件216的示例工艺中，在工件200上方沉积介电材料，同时用介电材料填充鳍沟槽212。在一些实施例中，介电材料可包括四乙基正硅酸盐(TEOS)氧化物、非掺杂硅酸盐玻璃或掺杂的氧化硅，诸如硼磷硅玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅玻璃(PSG)、硼掺杂的硅玻璃(BSG)和/或其他合适的介电材料。在各种示例中，在框106处，可通过可流动CVD(FCVD)、旋涂和/或其他合适的工艺沉积介电材料。然后例如通过化学机械抛光(CMP)工艺将沉积的介电材料减薄和平坦化，直至暴露硬掩模层214为止。
在平坦化之后，使沉积的介电材料在回蚀刻工艺中凹陷，直至位于鳍状结构210的顶部部分中的一些牺牲层206和沟道层208上升到高于隔离部件216为止。作为比较，底座部分210B保持被隔离部件216以及牺牲层206和沟道层208的位于鳍状结构210的底部中的其余部分完全覆盖。如下文将进一步详细讨论，尽管沟道层208的数量在区I和II中看起来相同，但在区II中被隔离部件216完全或部分覆盖的沟道层208稍后将从工件200的背面去除。具体地，在所示出的实施例中，最底牺牲层206被隔离部件216完全覆盖并且最底沟道层208被隔离部件216部分地覆盖，并且最底沟道层208将被去除，使得区II中的沟道层208的数量将比区I中的沟道层数减少一个。在各种实施例中，通过使更多底部沟道层208不完全升高到高于隔离部件216，区II中的沟道层208的数量将是进一步减少，诸如比区I中少一到四层。换句话说，如下所示，隔离部件216的高度用于控制将从区II去除的沟道层208的数量。区I和II中的沟道层的差由器件性能需求决定。框106处的回蚀刻工艺可包括例如湿蚀刻、干蚀刻、反应性离子蚀刻或其他合适的蚀刻方法。也可在回蚀刻工艺中去除硬掩模层214。
参考图6A至图6D，方法100包括框108(图1A)，其中，在回蚀刻工艺中使区I中的隔离部件216进一步凹陷，直至堆叠件204完全上升到高于隔离部件216为止。如所示出的实施例所示，也可部分地暴露区I中的底座部分210B。回蚀刻工艺可包括例如湿蚀刻、干蚀刻、反应性离子蚀刻或其他合适的蚀刻方法。进一步凹陷的距离ΔH可介于约5nm至约30nm的范围内。为了限制区I中的回蚀刻工艺，可首先沉积(例如，通过旋涂)掩模层214以覆盖区II。在一些实施例中，掩模层214是光刻胶层，诸如底抗反射涂(BARC)层。在使区I中的隔离部件216进一步凹陷之后，可在蚀刻工艺或诸如灰化或抗蚀剂剥离等其他合适的工艺中去除掩模层214。
参考图7A至图7D、图8A至图8D和图9A至图9D，方法100包括形成介电鳍218的框110(图1A)。在所示出的实施例中，在框110处，在鳍沟槽212中形成介电鳍218。形成介电鳍218的示例工艺包括共形地沉积包覆层220(如图7A至图7D所示)、共形地沉积第一介电层222并在鳍沟槽212中沉积第二介电层224(如图8A至图8D所示)，以及在第一介电层222和第二介电层224的顶部沉积高k介电层226(如图9A至图9D所示)。
在工件200上方沉积包覆层220，包括在区I中的堆叠件204的侧壁和底座部分210B的顶部部分上方以及部分地在区II中的堆叠件204的侧壁上方。在一些实施例中，包覆层220可具有类似于牺牲层206或顶牺牲层206T的组分。在一个示例中，包覆层220可由硅锗(SiGe)形成。它们的共同组分允许在后续的蚀刻工艺中选择性地同时去除牺牲层206和包覆层220。在一些实施例中，包覆层220可使用气相外延(VPE)或分子束外延(MBE)来共形且外延地生长。如图7A至图7D所示，包覆层220选择性地设置在鳍沟槽212中暴露的侧壁表面上。根据包覆层220的选择性生长的程度，可执行回蚀刻工艺以暴露隔离部件216。
形成介电鳍218的示例工艺还包括依次在工件200上方共形地沉积第一介电层222和第二介电层224。第二介电层224被第一介电层222围绕。可使用CVD、ALD或合适的方法来共形地沉积第一介电层222。第一介电层222加衬鳍沟槽212的侧壁和底面。然后使用CVD、高密度等离子CVD(HDPCVD)、可流动CVD(FCVD)和/或其他合适的工艺来在第一介电层222上方共形地沉积第二介电层224。在一些示例中，第二介电层224的介电常数小于第一介电层222的介电常数。第一介电层222可包括硅、氮化硅、碳化硅、碳氮化硅、碳氮氧化硅、氧化铝、氮化铝、氧氮化铝、氧化锆、氮化锆、氧化铝锆、氧化铪或合适的介电材料。在一个实施例中，第一介电层222包括氧化铝。第二介电层224可包括氧化硅、碳化硅、氮氧化硅、碳氮氧化硅或合适的介电材料。在一个实施例中，第二介电层224包括氧化硅。在一些示例中，如图8A至图8D所示，在沉积介电层222和224之后，可执行CMP工艺以去除过多的材料部分并将工件200的顶面平坦化，使得顶牺牲层206T暴露。
形成介电鳍218的示例工艺可还包括沉积高k介电层226。在一些示例中，执行凹陷工艺以去除介电层222和224的顶部部分。凹陷工艺可包括干蚀刻工艺、湿蚀刻工艺和/或其组合。在一些实施例中，控制凹陷深度(例如，通过控制蚀刻时间)以产生期望的凹陷深度。在执行凹陷工艺之后，在通过凹陷工艺形成的沟槽内沉积高K介电层226。在一些实施例中，高K介电层226可包括HfO2、ZrO2、HfAlOx、HfSiOx、Y2O3、Al2O3或另一种高K材料。高K介电层226可通过CVD工艺、ALD工艺、PVD工艺和/或其他合适的工艺沉积。如图9A至图9D所示，在沉积高K介电层226之后，执行CMP工艺以去除过多的材料部分并将工件200的顶面平坦化。在框110结束时，介电鳍218被定义为具有包括介电层222、224的凹陷部分的下部分和包括高K介电层226的上部分。介电鳍218也称为复合鳍218。区I和II中的介电鳍218具有不平坦的底面，使得区I中的底面比区II中的底面低ΔH。如上所述，ΔH的范围可介于约5nm至约30nm。
参考图10A至图10D，方法100包括框112(图1A)，其中，去除鳍状结构210中的顶牺牲层206T。在框112处，蚀刻工件200以选择性地去除顶牺牲层206T和包覆层220的部分以暴露最顶沟道层208，而基本不损坏介电鳍218。在一些示例中，因为顶牺牲层206T和包覆层220由硅锗(SiGe)形成，所以框112处的蚀刻工艺可对硅锗(SiGe)具有选择性。例如，可使用包括氢氧化铵(NH4OH)、氟化氢(HF)、过氧化氢(H2O2)或其组合的选择性湿蚀刻工艺来蚀刻包覆层220和顶牺牲层206T。在去除顶牺牲层206T以及包覆层220的部分之后，介电鳍218上升到高于最顶沟道层208。
参考图11A至图11D，方法100包括框114(图1A)，其中，在鳍状结构210的沟道区上方形成伪栅极堆叠件240。在一些实施例中，采用栅极替换工艺(或后栅极工艺)，其中，伪栅极堆叠件240用作功能栅极结构的占位器。其他工艺和配置也是可能的。在所示出的实施例中，伪栅极堆叠件240包括伪介电层242和设置在伪介电层242上方的伪电极244。出于图案化的目的，栅极顶硬掩模246沉积在伪栅极堆叠件240上方。栅极顶硬掩模246可以是多层的，并包括氮化硅掩模层248和氮化硅掩模层248上方的氧化硅掩模层250。位于伪栅极堆叠件240下面的鳍状结构210的区可被称为沟道区。鳍状结构210中的每个沟道区夹在两个源极/漏极区之间以形成源极/漏极。在示例工艺中，伪介电层242通过CVD坦覆地沉积在工件200上方。然后将用于伪电极244的材料层坦覆地沉积在伪介电层242上方。然后使用光刻工艺以对伪介电层242和伪电极244的材料层进行图案化来形成伪栅极堆叠件240。在一些实施例中，伪介电层242可包括氧化硅，并且伪电极244可包括多晶硅(polysilicon)。
仍然参考图11A至图11D，方法100包括框116(图1A)，其中，沿着伪栅极堆叠件240的侧壁形成栅极间隔件252。栅极间隔件252可包括两个或更多个栅极间隔件层。可选择用于栅极间隔件252的介电材料以允许选择性地去除伪栅极堆叠件240。合适的介电材料可包括氮化硅、氮氧化硅、碳氮化硅、氧化硅、碳氧化硅、碳化硅、氮氧化硅和/或其组合。在示例工艺中，栅极间隔件252可使用CVD、亚大气压CVD(SACVD)或ALD来共形地沉积在工件200上方，然后被各向异性蚀刻以去除水平部分，而栅极间隔件252的竖直部分保留在伪栅极堆叠件240的侧壁上。
参考图12A至图12D，方法100包括框118(图1A)，其中，使鳍状结构210的源极/漏极区凹陷以形成源极凹槽和漏极凹槽，共同作为源极/漏极凹槽254(或源极/漏极沟槽254)。以伪栅极堆叠件240和栅极间隔件252充当蚀刻掩模，各向异性蚀刻工件200以在鳍状结构210的源极/漏极区上方形成源极/漏极凹槽254。在所示出的实施例中，框118处的操作从区I和II中的源极/漏极区去除牺牲层206和沟道层208，从而暴露底座部分210B，并且从区II去除包覆层220以及隔离部件216的部分，从而暴露隔离部件216(图12B)。作为比较，因为包覆层220在区I中的最底牺牲层206下方延伸，所以包覆层220的最底部分保留并覆盖区I中的隔离部件216(图12A)。框118处的各向异性蚀刻可包括干蚀刻工艺。例如，干蚀刻工艺可实现氢气、含氧气体、含氟气体(例如，CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如，Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如，HBr和/或CHBr3)、含碘气体、其他合适的气体和/或等离子体和/或其组合。在框118结束时，区I和II中的底座部分210B的暴露顶面是水平的，如图12A和图12B中的虚线所示。
参考图13A至图13D，方法100包括框120，其中，通过蚀刻工艺使区I中的源极/漏极凹槽254进一步延伸至底座部分210B中以形成更深的源极/漏极凹槽254D并去除区I中的包覆层220的剩余部分。为了限制区I中的蚀刻工艺，可首先沉积(例如，通过旋涂)掩模层256以覆盖区II。在一些实施例中，掩模层256是光刻胶层，诸如底抗反射涂(BARC)层。在使区I中更深的源极/漏极凹槽254D延伸之后，可在蚀刻工艺或诸如灰化或抗蚀剂剥离等其他合适的工艺中去除掩模层256。进一步凹陷的距离ΔH’可介于约5nm至约10nm的范围内。
参考图14A至图14D，方法100包括框122，其中，形成内间隔件部件258。在一些实施例中，在框122处，首先使暴露在源极/漏极凹槽254和更深的源极/漏极凹槽254D中的牺牲层206选择性地部分凹陷以形成内间隔件凹槽，而基本不蚀刻暴露的沟道层208。在沟道层208基本由硅(Si)组成并且牺牲层206基本由硅锗(SiGe)组成的实施例中，牺牲层206的选择性和部分凹陷可包括SiGe氧化工艺，然后是SiGe氧化物去除。在那些实施例中，SiGe氧化工艺可包括使用臭氧。在其他一些实施例中，部分凹陷可包括选择性蚀刻工艺(例如，选择性干蚀刻工艺或选择性湿蚀刻工艺)，并且牺牲层206凹陷的程度受蚀刻工艺的持续时间控制。选择性干蚀刻工艺可包括使用一种或多种氟基蚀刻剂，诸如氟气或氢氟烃。选择性湿蚀刻工艺可包括氢氧化铵(NH4OH)、氟化氢(HF)、过氧化氢(H2O2)或其组合(例如，包括氢氧化氨-过氧化氢-水混合物的APM蚀刻)。在形成内间隔件凹槽之后，然后使用CVD或ALD来在工件200上方(包括在内间隔件凹槽上方和进入其中)共形地沉积内间隔材料层。内间隔材料可包括氮化硅、碳氮氧化硅、碳氮化硅、氧化硅、碳氧化硅、碳化硅或氮氧化硅。在沉积内间隔材料层之后，回蚀刻内间隔材料层以形成内间隔件部件258，如图14A至图14D所示。
仍然参考图14A至图14D，方法100包括形成源极/漏极部件260的框124。源极/漏极部件260选择性地且外延地沉积在源极/漏极凹槽254和更深的源极/漏极凹槽254D中的沟道层208和底座部分210B的暴露的半导体表面上。使用外延工艺，诸如气相外延(VPE)、超高真空CVD(UHV-CVD)、分子束外延(MBE)和/或其他合适的工艺等，可沉积源极/漏极部件260。在一些示例中，源极/漏极部件260包括非掺杂外延层262和重掺杂外延层264。非掺杂外延层262用于防止重掺杂外延层264与阱区之间的漏电流。在一些示例中，非掺杂外延层262具有约5nm至约15nm的厚度。由于更深的源极/漏极凹槽254D的更大深度，非掺杂外延层262位于最底沟道层208下方的区I中(图14C)和位于最底沟道层208上方的区II中(图14D)。取决于晶体管的期望配置，重掺杂外延层264可掺杂有p型掺杂剂或n型掺杂剂。当源极/漏极部件260是n型时，重掺杂外延层264可包括掺杂有诸如磷(P)或砷(As)等n型掺杂剂的硅(Si)。当源极/漏极部件260是p型时，重掺杂外延层264可包括掺杂有诸如硼(B)或镓(Ga)等p型掺杂剂的硅锗(SiGe)。重掺杂外延层264的掺杂可通过它们的沉积原位地或使用诸如结注入工艺等注入工艺来非原位地执行。同样如图14A和图14B所示，在源极/漏极凹槽254和更深的源极/漏极凹槽254D的侧壁的台阶区处，源极/漏极部件260的小面可在源极/漏极部件260与介电部件之间(诸如介电鳍218与隔离部件216)捕获空隙267。随后，在蚀刻工艺中选择性地去除源极/漏极区中的介电鳍218的高k介电层226，如图15A至图15D所示。蚀刻工艺可包括干蚀刻、湿蚀刻、反应性离子蚀刻(RIE)和/或其他合适的工艺。
参考图16A至图16D，方法100包括框126(图1A)，其中，在工件200的正面上沉积接触蚀刻停止层(CESL)270和层间介电(ILD)层272。在示例工艺中，CESL 270首先共形地沉积在工件200上方，然后ILD层272坦覆地沉积在CESL 270上方。CESL 270可包括氮化硅、氧化硅、氮氧化硅和/或本领域已知的其他材料。CESL 270可使用ALD、等离子增强化学气相沉积(PECVD)工艺和/或其他合适的沉积或氧化工艺等来沉积。在一些实施例中，ILD层272包括四乙基正硅酸盐(TEOS)氧化物、非掺杂硅酸盐玻璃或掺杂的氧化硅，诸如硼磷硅玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅玻璃(PSG)、硼掺杂的硅玻璃(BSG)等材料和/或其他合适的介电材料。ILD层272可通过旋涂、FCVD工艺或其他合适的沉积技术来沉积。在一些实施例中，在形成ILD层272之后，可对工件200执行退火以提高ILD层272的完整性。为了去除过多的材料(包括栅极顶硬掩模246)并暴露伪栅极堆叠件240的伪电极244的顶面，可对工件200执行平坦化工艺(诸如CMP工艺)以提供平坦顶面。
参考图17A至图17D，方法100包括框128(图1A)，其中，选择性地去除伪栅极堆叠件240。通过选择性蚀刻工艺从工件200去除在框126结束时暴露的伪栅极堆叠件240。选择性蚀刻工艺可以是选择性湿蚀刻工艺、选择性干蚀刻工艺或其组合。在所描绘的实施例中，选择性蚀刻工艺选择性地去除伪介电层242和伪电极244而基本不损坏沟道层208和栅极间隔件252。去除伪栅极堆叠件240产生沟道区上方的栅极沟槽266。在去除伪栅极堆叠件240之后，沟道区中的沟道层208、牺牲层206和包覆层220暴露在栅极沟槽266中。
参考图18A至图18D，方法100包括框130(图1A)，其中，从栅极沟槽266去除牺牲层206和包覆层220以释放沟道层208。应注意，尽管区I中的牺牲层206都被去除，但至少区II(图18B)中的最底牺牲层206保留，因为它在最底沟道层208和隔离部件216下受到保护。在框130结束时释放的沟道层208也表示为沟道构件208。在沟道构件208类似于片或纳米片的所描绘的实施例中，沟道构件释放工艺也可被称为片形成工艺。沟道构件208沿着Z方向竖直堆叠。所有沟道构件208与介电鳍218横向间隔开由包覆层220保留的一段距离。牺牲层206和包覆层220的选择性去除可通过选择性干蚀刻、选择性湿蚀刻或其他选择性蚀刻工艺来实现。在一些实施例中，选择性湿蚀刻包括氢氧化铵(NH4OH)、氟化氢(HF)、过氧化氢(H2O2)或其组合(例如，包括氢氧化氨-过氧化氢-水混合物的APM蚀刻)。在一些可选的实施例中，选择性去除包括硅锗氧化，然后是硅锗氧化物去除。例如，可通过臭氧清洁提供氧化，然后通过诸如NH4OH等蚀刻剂去除硅锗氧化物。
参考图19A至图19D，方法100包括框132(图1A)，其中，在栅极沟槽266中形成栅极结构274(也称为功能栅极结构274或金属栅极结构274)以与沟道构件208接合。在区I中，沟道构件208中的每个被相应栅极结构274环绕。作为比较，在区II中，最底沟道层208具有沉积有栅极结构274的顶面，但该顶面不在其保持与最底牺牲层206交接的底面上沉积。栅极结构274中的每个包括设置在沟道构件208上的栅极介电层276和位于栅极介电层276上方的栅极电极层278。在一些实施例中，栅极介电层276包括界面层和高k介电层。界面层可包括氧化硅并且作为预清洁工艺的结果而形成。示例预清洁工艺可包括使用RCA SC-1(氨、过氧化氢和水)和/或RCA SC-2(盐酸、过氧化氢和水)。预清洁工艺氧化沟道构件208的暴露表面以形成界面层。然后使用ALD、CVD和/或其他合适的方法来在界面层上方沉积高k介电层。高k介电层包括高k介电材料。在一个实施例中，高k介电层可包括氧化铪。可选地，高k介电层可包括其他高K介电质，诸如氧化钛(TiO2)、氧化铪锆(HfZrO)、氧化钽(Ta2O5)、氧化铪硅(HfSiO4)、氧化锆(ZrO2)、氧化锆(ZrSiO2)、氧化镧(La2O3)、氧化铝(Al2O3)、氧化锆(ZrO)、氧化钇(Y2O3)、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、氧化铪镧(HfLaO)、氧化镧硅(LaSiO)、氧化铝硅(AlSiO)、氧化铪钽(HfTaO)、氧化铪钛(HfTiO)、(Ba,Sr)TiO3(BST)、氮化硅(SiN)、氮氧化硅(SiON)、其组合或其他合适的材料。在形成栅极介电层276之后，在栅极介电层276上方沉积栅极电极层278。栅极电极层278可以是包括至少一个功函数层和金属填充层的多层结构。例如，至少一个功函数层可包括氮化钛(TiN)、钛铝(TiAl)、氮化钛铝(TiAlN)、氮化钽(TaN)、钽铝(TaAl)、氮化钽铝(TaAlN)、碳化钽铝(TaAlC)、碳氮化钽(TaCN)或碳化钽(TaC)。金属填充层可包括铝(Al)、钨(W)、镍(Ni)、钛(Ti)、钌(Ru)、钴(Co)、铂(Pt)、氮化钽硅(TaSiN)、铜(Cu)、其他难熔金属或其他合适的金属材料或其组合。在各种实施例中，栅极电极层278可通过ALD、PVD、CVD、电子束蒸发或其他合适的工艺形成。尽管图中未明确示出，但栅极结构274被沉积为联合栅极结构，然后被回蚀刻直至介电鳍218将联合栅极结构分成彼此分离的栅极结构274为止。介电鳍218还在相邻的栅极结构274之间提供电气隔离。栅极结构274的回蚀刻可包括使用硝酸、盐酸、硫酸、氢氧化铵、过氧化氢或其组合的选择性湿蚀刻工艺。尽管在所示出的实施例中，回蚀刻工艺之后的栅极结构274的顶面与高k介电层226的底面齐平，但在可选的实施例中，回蚀刻之后的栅极结构274的顶面工艺可位于高k介电层226的底面下方。栅极结构274的回蚀刻可还包括回蚀刻沟道区中的介电鳍218的高k介电层226。
参考图20A至图20D，方法100包括框134(图1B)，其中，在工件200的正面中形成金属保护层280、自对准保护(SAC)层282和栅极切割部件284。在一些实施例中，金属保护层280可包括钛(Ti)、氮化钛(TiN)、氮化钽(TaN)、钨(W)、钌(Ru)、钴(Co)或镍(Ni)，并可使用PVD、CVD或金属有机化学气相沉积(MOCVD)来进行沉积。在一个实施例中，金属保护层280包括钨(W)，诸如无氟钨(FFW)，并通过PVD沉积。在金属保护层280通过MOCVD沉积的一些可选的实施例中，金属保护层280的沉积可选择性地沉积在栅极结构274上。在沉积金属保护层280之后，通过CVD、PECVD或合适的沉积工艺在工件200上方沉积SAC层282。SAC层282可包括氧化硅、氮化硅、碳化硅、碳氮化硅、氧氮化硅、氧碳氮化硅、氧化铝、氮化铝、氧氮化铝、氧化锆、氮化锆、氧化铝锆、氧化铪或合适的介电材料。然后执行光刻工艺和蚀刻工艺以蚀刻沉积的SAC层282，以形成栅极切割开口来暴露介电鳍218的顶面。此后，通过CMP工艺沉积并平坦化介电材料以在栅极切割开口中形成栅极切割部件284。可使用HDPCVD、CVD、ALD或合适的沉积技术来沉积用于栅极切割部件284的介电材料。在一些示例中，栅极切割部件284可包括氧化硅、氮化硅、碳化硅、碳氮化硅、氧氮化硅、氧碳氮化硅、氧化铝、氮化铝、氧氮化铝、氧化锆、氮化锆、氧化铝锆、氧化铪或合适的介电材料。在一些实施例中，栅极切割部件284和SAC层282可具有不同的组分以引入蚀刻选择比。
参考图21A至图21F，方法100包括框136(图1B)，其中，执行一个或多个正面中道工序(MEOL)和正面后道工序(BEOL)工艺以形成一个或多个互连层，该等互连层具有嵌入介电层中的接触件、通孔和金属线(也称为金属布线层)。在一些实施例中，框136处的操作包括形成源极/漏极接触286、栅极接触288、附加ILD层290和金属布线层292。工件200可还包括建立在工件200正面上的钝化层和/或其他层。这些层和一个或多个互连层连接各种晶体管的栅极、源极和漏极以及工件200中的其他电路，以部分或完整地形成集成电路。
参考图22A至图22D，方法100包括框138(图1B)，其中，将载体294附接至工件200的正面。在一些实施例中，载体294可以是硅晶圆。框138处的操作可使用任何合适的附着工艺，诸如直接接合、复合接合、使用粘合剂或其他结合方法。在所示出的实施例中，接合氧化物层296和粘合剂层298形成在工件200的正面上，并将载体294邻接至工件200的正面。框138处的操作可还包括对准、退火和/或其他工艺。载体294的附接允许工件200被上下翻转，如图23A至图23D所示。这使得可从工件200的背面接近工件200以进行进一步处理。应注意，工件200在以下附图(即图24A至图26D)中也被上下翻转。
参考图24A至图24D，方法100包括框140(图1B)，其中，从工件200的背面减薄工件200。示例减薄工艺可包括在选择性蚀刻工艺中去除衬底202以在工件背面上方形成沟槽300。在一些示例中，栅极结构274(特别是栅极介电层276)暴露在区I中的沟槽300中，并且最底牺牲层206暴露在区II中的沟槽300中。可选地，在区II中，如在所示出的实施例中，衬底202的薄层可保持覆盖最底牺牲层206，诸如受蚀刻工艺的持续时间控制的蚀刻工艺。非掺杂外延层262也在区I和II中暴露并部分地凹陷。在一些实施例中，控制非掺杂外延层262的凹陷深度(例如，通过控制蚀刻时间)以产生期望的凹陷深度。区I和II中的非掺杂外延层262的暴露表面甚至可产生于框140结束时，如图24C和图24D所示。在一些实施例中，减薄工艺的第一阶段包括机械研磨工艺以去除大量衬底202，而隔离部件216用作机械研磨停止层。之后，化学减薄工艺可将蚀刻化学剂施加至工件的背面以去除衬底202，而最底牺牲层206可用作蚀刻停止层。类似地，在一些实施例中，化学减薄工艺可受计时器控制，使得衬底202的薄层仍可保留在最底牺牲层206上。
参考图25A至图25F，方法100包括框142(图1B)，其中，从区II中的沟槽300蚀刻选择性地牺牲层206和邻接牺牲层206并且未被栅极结构274环绕的沟道层208。为了限制区I中的蚀刻工艺，可首先沉积(例如，通过旋涂)掩模层302以覆盖区I。在一些实施例中，掩模层302是光刻胶层，诸如底抗反射涂(BARC)层。在所示出的实施例中，蚀刻一个牺牲层206(最底层)和一个沟道层208(最底层)，从而暴露区II中的栅极结构274(尤其是栅极介电层276)。在一个示例中，进一步蚀刻栅极介电层276中的界面层，并且在沟槽300中暴露栅极介电层276中的高k介电层。如上文结合图5A至图5D所讨论，区II中的隔离部件216的高度用于确定要去除的沟道层208的数量，使得只有完全上升到高于隔离部件216的沟道层208保留。换句话说，根据器件性能需要，可能存在多个沟道层208未被选择性蚀刻的栅极结构274换套，诸如沟道层208中的一个层至四个层。
框142处的操作应用一种或多种蚀刻工艺，这些蚀刻工艺被调谐为对牺牲层206和沟道层208的半导体材料具有选择性，并且对内间隔件部件258和栅极介电层276的介电材料没有蚀刻(或蚀刻最少)。此外，非掺杂外延层262也可凹陷于沟槽300中但并未完全去除，以保护重掺杂外延层264免受蚀刻工艺的损坏。选择性蚀刻工艺可以是干蚀刻、湿蚀刻、反应性离子蚀刻或其他合适的蚀刻方法。如图25D所示，牺牲层206的去除和非掺杂外延层262的凹陷使得内间隔件部件258从工件200的背面突出。直接位于内间隔件部件258下方的沟道层208的端部(表示为端部208E)可从各向异性蚀刻工艺中保留，并且也从工件200的背面突出。取决于凹陷深度，非掺杂外延层262的暴露表面可完全位于端部208E或端部208E的接口侧壁下方。在一些示例中，非掺杂外延层262的暴露表面与栅极介电层276的暴露表面齐平。在一些可选的示例中，非掺杂外延层262的暴露表面位于栅极介电层276的暴露表面下方。然而在一些示例中，非掺杂外延层262的凹陷是可选的并且可被跳过，使得非掺杂外延层262保持其厚度，并在Y-Z平面中朝向工件200的背面位于介电鳍218上方。在框142处的选择性蚀刻工艺之后，可在蚀刻工艺或诸如灰化或抗蚀剂剥离等其他合适的工艺中去除掩模层302。此外，由于区I中的隔离部件216被掩模层302保护免于附加的选择性蚀刻工艺，因此与区II中可能具有圆角的隔离部件相比，区I中的隔离部件216可具有更成形的边缘，如图25B和图25F中的虚线所示。
参考图26A至图26F，方法100包括框144(图1B)，其中，在工件200的背面上方沉积背面介电层304，并且该背面介电层填充沟槽300。背面介电层304大大减少源极与漏极部件之间的阱隔离泄漏和衬底泄漏。在一些实施例中，背面介电层304的沉积材料包括SiN、SiOCN、SiOC、SiCN、其组合或其他合适的材料。背面介电层304可通过CVD、PVD、PE-CVD、F-CVD、涂覆工艺或其他合适的沉积技术来沉积。在沉积背面介电层304之后，最底内间隔件258和端部208E突出到背面介电层304中，如图26D所示。框144处的操作还包括执行平坦化工艺，诸如CMP工艺，以从工件200的背面去除过多的介电材料并暴露隔离部件216。
参考图27A至图27D，方法100包括框146(图1B)，其中，将载体308附接至工件200的背面。在一些实施例中，载体308可以是硅晶圆。框146处的操作可使用任何合适的附着工艺，诸如直接接合、复合接合、使用粘合剂或其他结合方法。在所示出的实施例中，接合氧化物层306形成在工件200的背面上并且将载体308邻接至工件200的背面。框146处的操作可还包括对准、退火和/或其他工艺。载体308的附接允许工件200被后翻转。这使得可从工件200的正面再次接近工件200以进行进一步加工。框146处的操作还包括执行正面减薄工艺，诸如CMP工艺，以从工件200的正面去除正面载体294和粘合剂层298并暴露正面接合氧化物层296。
参考图28A至图28D，方法100包括框148(图1B)，其中，对工件200执行另外的制造工艺。例如，它可执行其他BEOL工艺以在工件200的正面上形成更多互连层，诸如正面电源轨。在实施例中，可使用镶嵌工艺、双镶嵌工艺、金属图案化工艺或其他合适的工艺来来形成正面电源轨。正面电源轨可包括钨(W)、钴(Co)、钼(Mo)、钌(Ru)、铜(Cu)、镍(Ni)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)或其他金属，并且可通过CVD、PVD、ALD、镀覆或其他合适的工艺沉积。框148处的操作可还包括在工件200的正面上形成钝化层、执行其他BEOL工艺以及去除背面载体308。
仍参考图28A至图28D，在方法100结束时，分别在区I和区II中形成多个MBC晶体管。每个MBC晶体管包括与一个或多个沟道构件208的栅极结构274接合。相邻的MBC晶体管被介电鳍218和落着在介电鳍218上的栅极切割部件284电气分离。具体地，区I中的MBC晶体管比区II中的MBC晶体管具有更多的堆叠沟道构件208，提从而供更强的电流驱动能力。这有利于满足一个IC芯片的不同区的不同电流驱动能力的需求。此外，背面介电层304取代原始半导体衬底并结合隔离部件216以在栅极结构和源极/漏极部件下方限定大介电层。这种实现方式有效地减少井隔离泄漏和衬底泄漏。由于区II中较少的沟道构件208所节省的空间，背面介电层304在区II中具有比在区I中更大的厚度。相比下方，区II中的源极/漏极部件260的厚度小于区I中的厚度。此外，区I和区II中最底内间隔件部件258可以是水平的，而区II中的间隔件部件突出向下进入背面介电层304，并可由于在区II中接纳的额外选择性蚀刻工艺而具有圆形边缘。在区II中，部分去除的最底沟道构件208的端部208E也向下突出至背面介电层304中。
在一个示例性方面中，本发明涉及一种方法。方法包括：在半导体衬底的正面形成第一类型外延层与第二类型外延层的堆叠件，第一类型外延层与第二类型外延层具有不同的材料组分，第一类型外延层与第二类型外延层在竖直方向上交替设置；对堆叠件进行图案化以形成鳍状结构；在鳍状结构的侧壁上沉积介电层；使介电层凹陷以暴露鳍状结构的顶部部分，凹陷介电层的顶面位于堆叠件的底面上方；在鳍状结构的顶部部分上方形成栅极结构；从半导体衬底的背面蚀刻半导体衬底，从而在介电层之间形成沟槽，沟槽暴露堆叠件的底面；以及穿过沟槽蚀刻至少最底第一类型外延层和最底第二类型外延层。在一些实施例中，最底第一类型外延层位于最底第二类型外延层下方，并且凹陷介电层的顶面位于最底第一类型外延层的顶面上方。在一些实施例中，凹陷介电层的顶面位于最底第二类型外延层的顶面下方。在一些实施例中，栅极结构是金属栅极结构，并且蚀刻至少最底第一类型外延层和最底第二类型外延层在形成栅极结构之后发生。在一些实施例中，方法还包括：在形成栅极结构之前，从鳍状结构的顶部部分去除第一类型外延层，并且在形成栅极结构之后，栅极结构在鳍状结构的顶部部分中环绕第二类型外延层。在一些实施例中，在形成栅极结构之后，最底第二类型外延层具有与栅极结构交接的顶面和与最底第一类型外延层交接的底面。在一些实施例中，蚀刻至少最底第一类型外延层和最底第二类型外延层包括从沟槽完全去除最底第一类型外延层并部分去除最底第二类型外延层。在一些实施例中，蚀刻至少最底第一类型外延层和最底第二类型外延层包括蚀刻多个第二类型外延层。在一些实施例中，方法还包括：在沟槽中沉积介电材料，并且最底第二类型外延层的部分突出至介电材料中。
在另一示例性方面中，本发明涉及一种制造多栅极器件的方法。方法包括：在衬底的第一区上方形成第一多个沟道构件，第一多个沟道构件竖直堆叠；在衬底的第二区上方形成第二多个沟道构件，第二多个沟道构件竖直堆叠；在第一区和第二区中形成隔离部件，隔离部件的顶面在第二区中高于在第一区中，使得第二多个沟道部件的部分在第二区中位于隔离部件的顶面下方；形成与第一多个沟道构件接合的第一栅极结构，从而在第一区中形成第一晶体管；形成与第二多个沟道构件接合的第二栅极结构，从而在第二区中形成第二晶体管；以及从第二区去除第二多个沟道构件的部分，使得第一晶体管中的第一多个沟道构件的数量大于第二晶体管中的第二多个沟道构件的数量。在一些实施例中，形成隔离部件包括：在第一多个沟道构件和第二多个沟道构件的侧壁上方沉积介电材料；使介电材料在第一区和第二区中凹陷，从而暴露第一多个沟道构件和第二多个沟道构件的顶部部分；以及使介电材料第一区中进一步凹陷，使得第一多个沟道构件完全位于介电材料上方。在一些实施例中，方法还包括：在第一区和第二区中蚀刻衬底，从而在第一区和第二区中形成沟槽，并且去除第二多个沟道构件的部分在第二区中的沟槽中暴露第二栅极结构。在一些实施例中，蚀刻衬底在第一区中的沟槽中暴露第一栅极结构。在一些实施例中，方法还包括：形成邻接第一多个沟道构件的第一源极/漏极部件；以及形成邻接第二多个沟道构件的第二源极/漏极部件，其中，第二源极/漏极部件的厚度小于第一源极/漏极部件的厚度。在一些实施例中，方法还包括：形成介于第一源极/漏极部件与第一栅极结构之间的第一内间隔件部件；形成介于第二源极/漏极部件与第二栅极结构之间的第二内间隔件部件；以及使第二源极/漏极部件凹陷，使得最底第二内间隔件部件与第二源极/漏极部件间隔开。在一些实施例中，第一栅极结构在第一区中环绕第一多个沟道构件中的每个，并且第二栅极结构在第二区中环绕多个第二沟道构件的顶部部分中的每个。
在另一示例性方面中，本发明涉及一种半导体器件。半导体器件包括：第一栅极结构，与第一多个沟道构件接合；第二栅极结构，与第二多个沟道构件接合；第一背面介电部件，直接设置在第一栅极结构下方；以及第二背面介电部件，直接设置在第二栅极结构下方。第一多个沟道构件的数量大于第二多个沟道构件的数量。在一些实施例中，第一栅极结构的高度大于第二栅极结构的高度。在一些实施例中，第一背面介电部件的厚度小于第二背面介电部件的厚度。在一些实施例中，半导体器件还包括：第一内间隔件部件，与第一栅极结构邻接；以及第二内间隔件部件，与第二栅极结构邻接。第二内间隔件部件的底部延伸至第二背面介电部件中。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种制造半导体器件的方法，包括：
在半导体衬底的正面形成第一类型外延层与第二类型外延层的堆叠件，所述第一类型外延层与所述第二类型外延层具有不同的材料组分，所述第一类型外延层与第二类型外延层在竖直方向上交替设置；
对所述堆叠件进行图案化以形成鳍状结构；
在所述鳍状结构的侧壁上沉积介电层；
使所述介电层凹陷以暴露所述鳍状结构的顶部部分，其中，凹陷的所述介电层的顶面位于所述堆叠件的底面上方；
在所述鳍状结构的所述顶部部分上方形成栅极结构；
从所述半导体衬底的背面蚀刻所述半导体衬底，从而在所述介电层之间形成沟槽，所述沟槽暴露所述堆叠件的所述底面；以及
穿过所述沟槽蚀刻至少最底第一类型外延层和最底第二类型外延层。
2.根据权利要求1所述的方法，其中，所述最底第一类型外延层位于所述最底第二类型外延层下方，并且其中，凹陷的所述介电层的所述顶面位于所述最底第一类型外延层的顶面上方。
3.根据权利要求2所述的方法，其中，凹陷的所述介电层的所述顶面位于所述最底第二类型外延层的顶面下方。
4.根据权利要求1所述的方法，其中，所述栅极结构是金属栅极结构，并且其中，所述蚀刻至少所述最底第一类型外延层和所述最底第二类型外延层在所述形成所述栅极结构之后发生。
5.根据权利要求1所述的方法，还包括：
在所述形成所述栅极结构之前，从所述鳍状结构的所述顶部部分去除所述第一类型外延层，
其中，在所述形成所述栅极结构之后，所述栅极结构在所述鳍状结构的所述顶部部分中环绕所述第二类型外延层。
6.根据权利要求1所述的方法，其中，在所述形成所述栅极结构之后，所述最底第二类型外延层具有与所述栅极结构交接的顶面和与所述最底第一类型外延层交接的底面。
7.根据权利要求1所述的方法，其中，所述蚀刻至少所述最底第一类型外延层和所述最底第二类型外延层包括从所述沟槽完全去除所述最底第一类型外延层并部分去除所述最底第二类型外延层。
8.根据权利要求1所述的方法，其中，所述蚀刻至少所述最底第一类型外延层和所述最底第二类型外延层包括蚀刻多个第二类型外延层。
9.一种制造半导体器件的方法，包括：
在衬底的第一区上方形成第一多个沟道构件，所述第一多个沟道构件竖直堆叠；
在衬底的第二区上方形成第二多个沟道构件，所述第二多个沟道构件竖直堆叠；
在所述第一区和所述第二区中形成隔离部件，其中，所述隔离部件的顶面在所述第二区中高于在所述第一区中，使得所述第二多个沟道部件的部分在所述第二区中位于所述隔离部件的所述顶面下方；
形成与所述第一多个沟道构件接合的第一栅极结构，从而在所述第一区中形成第一晶体管；
形成与所述第二多个沟道构件接合的第二栅极结构，从而在所述第二区中形成第二晶体管；以及
从所述第二区去除所述第二多个沟道构件的所述部分，使得所述第一晶体管中的所述第一多个沟道构件的数量大于所述第二晶体管中的所述第二多个沟道构件的数量。
10.一种半导体器件，包括：
第一栅极结构，与第一多个沟道构件接合；
第二栅极结构，与第二多个沟道构件接合；
第一背面介电部件，直接设置在所述第一栅极结构下方；以及
第二背面介电部件，直接设置在所述第二栅极结构下方，
其中，所述第一多个沟道构件的数量大于所述第二多个沟道构件的数量。
CN202210084499.3A 2021-01-28 2022-01-25 半导体器件及其制造方法 Pending CN114551352A (zh)

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