TWI818404B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

Info

Publication number
TWI818404B
TWI818404B TW111100314A TW111100314A TWI818404B TW I818404 B TWI818404 B TW I818404B TW 111100314 A TW111100314 A TW 111100314A TW 111100314 A TW111100314 A TW 111100314A TW I818404 B TWI818404 B TW I818404B
Authority
TW
Taiwan
Prior art keywords
layer
gate structure
region
channel members
dielectric
Prior art date
Application number
TW111100314A
Other languages
English (en)
Other versions
TW202230463A (zh
Inventor
江國誠
陳燕銘
鄭嶸健
王志豪
程冠倫
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202230463A publication Critical patent/TW202230463A/zh
Application granted granted Critical
Publication of TWI818404B publication Critical patent/TWI818404B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)

Abstract

提供一種半導體結構及其製造方法。一示例性的製造方法包括：形成第一類型及第二類型的磊晶層的一堆疊於一半導體基底的一前側；圖案化堆疊，以形成一鰭形結構；沉積一介電層於鰭形結構的側壁上，以及凹陷介電層，以露出鰭形結構的一頂層部。凹陷的介電層的上表面位於堆疊的下表面之上。此示例性的製造方法也包括：於鰭形結構的頂部上形成一閘極結構；從半導體基底的背側蝕刻半導體基底，以及經由溝槽至少蝕刻最底層的第一類型磊晶層及最底層的第二類型磊晶層。

Description

半導體裝置及其製造方法
本發明實施例係關於一種半導體技術，且特別為關於一種半導體裝置及其製造方法。
半導體積體電路(IC)行業經歷了快速的增長。積體電路材料及設計方面的技術進展已經產生了一代又一代的積體電路，每一世代都比上一世代具有更小更複雜的電路。在積體電路的發展過程中，功能密度(例如，每個晶片面積上的內連接裝置的數量)普遍增加，而幾何尺寸(例如，使用製造製程可形成的最小的部件(或接線))卻減少。這種微縮化製程通常因提高生產效率及降低相關成本而帶來許多好處。這種微縮化也增加了製作及製造積體電路(IC)的複雜性。
舉例來說，隨著積體電路(IC)技術向更小的技術世代發展，導入了多閘極裝置，以透過增加閘極-通道耦合、降低截止狀態電流及減少短通道效應(short-channel effect, SCE)來改善閘極控制。多閘極裝置一般是指具有閘極結構，或其部分位於通道區的一側以上。鰭式場效電晶體(Fin-like field effect transistor, FinFET)及多橋通道(multi-bridge-channel, MBC)電晶體為多閘極裝置的示例，其已成為高效能及低漏電應用的普及又具前景的備選裝置。鰭式場效電晶體(FinFET)具有一上升通道，其多面包覆閘極(例如，閘極包覆從基底延伸出來的半導體材料“鰭部”的頂部及側壁)。多橋通道(MBC)電晶體的閘極結構可局部或全部延伸圍繞通道區，以提供對通道區的兩個或多個側面的存取。由於其閘極結構環繞通道區，多橋通道(MBC)電晶體也可稱作環繞式閘極電晶體(surrounding gate transistor, SGT)或閘極全繞式(gate-all-around、 GAA)電晶體。
位於積體電路晶片不同區域或電路不同區域的多橋通道(MBC)電晶體具有不同的功能，如輸入/輸出(I/O)功能及核心功能。這些不同的功能要求電晶體具有不同的結構。同時，擁有相似的製程及相似的製程容許度來製造這些不同的電晶體是很有利的，可降低成本及提高產量。舉例來說，積體電路晶片可包括用於高效能能計算(high performance computing, HPC)單元或中央處理單元(central processing unit, CPU)的大功率區域(其需要具有強大的電流驅動能力的多橋通道(MBC)電晶體來實現高操作速度)，以及用於輸入/輸出(I/O)或系統晶片(system-on-a-chip, SoC)單元的低功耗區域(其需要具有較小的電流驅動能力的多橋通道(MBC)電晶體來實現低電容及低漏電效能)。因此，在一積體電路晶片中，不同區域的多橋通道(MBC)電晶體對通道構件數量的需求是不同的。一般來說，具有較大數量的通道構件的多橋通道(MBC)電晶體提供更強的電流驅動能力，反之亦然。因此，在積體電路的發展過程中，如何在一積體電路晶片上實現適合不同應用的不同數量的通道構件是半導體行業面臨的挑戰。同時，在製造這些不同的電晶體時，擁有相似的製程及相似的製作容許度對降低成本及提高良率是有利的。因此，雖然現有的半導體裝置通常足以滿足其預期性目的，但其在所有方面並非都能令人滿意。
在一些實施例中，一種半導體裝置之製造方法包括：形成由一第一類型及一第二類型磊晶層構成的一堆疊於一半導體基底的一前側，第一類型及第二類型磊晶層具有不同的材料組成，第一類型及第二類型磊晶層在一垂直方向上交替設置；圖案化堆疊，以形成一鰭形結構；沉積一介電層於鰭形結構的側壁上；凹陷介電層，以露出鰭形結構的一頂層部，凹陷的介電層的上表面位於堆疊的下表面之上；形成一閘極結構於鰭形結構的頂層部上；從半導體基底的背側蝕刻半導體基底，以形成一溝槽於介電層之間，此溝槽露出堆疊的下表面；以及經由溝槽來蝕刻至少一最底層的第一類型磊晶層及一最底層的第二類型磊晶層。
在一些實施例中，一種半導體裝置之製造方法包括：形成多個第一通道構件於一基底的一第一區域上，多個第一通道構件為垂直堆疊的；形成多個第二通道構件於基底的一第二區域上，多個第二通道構件為垂直堆疊的；形成一隔離特徵部件於第一及第二區域中，隔離特徵部件的上表面在第二區域高於在第一區域，使得在第二區域中多個第二通道構件的一部分低於隔離特徵部件的上表面；形成與多個第一通道構件嚙合的一第一閘極結構，以在第一區域形成一第一電晶體；形成與多個第二通道構件嚙合的一第二閘極結構，以在第二區域形成一第二電晶體；以及從第二區域移除多個第二通道構件的上述部分，使第一電晶體中的多個第一通道構件的數量大於第二電晶體中的多個第二通道構件的數量。
在一些實施例中，一種半導體裝置包括：一第一閘極結構，與多個第一條通道構件嚙合；一第二閘極結構，與多個第二條通道構件嚙合；一第一背側介電特徵部件，設置於第一閘極結構正下方；以及一第二背側介電特徵部件，設置於第二閘極結構正下方。多個第一通道構件的數量大於多個第二組通道構件的數量。
以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵部件。而以下的揭露內容為敘述各個部件及其排列方式的特定範例，以求簡化本揭露內容。當然，這些僅為範例說明並非用以限定本發明。舉例來說，若為以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方，即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件為直接接觸的實施例，亦包含了尚可將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。
另外，本揭露於各個不同範例中會重複標號及/或文字。重複為為了達到簡化及明確目的，而非自列指定所探討的各個不同實施例及/或配置之間的關係。再者，在本文後續中形成一特徵部件於另一特徵部件上、連接至另一特徵部件上及/或耦接至另一特徵部件上可包括所述特徵部件形成為直接接觸的實施例，並且也可包括另外的特徵部件插入特徵部件之間的實施例，使得特徵部件可不直接接觸。另外，使用了空間上相對性用語，例如“下”、“上”、“水準”、“垂直”、“之上”、“上方”、“之下”、“下方”、“向上”、“向下”、“下方”、 “頂部”、“底部”等及其派生詞(例如，“水準”、“朝下”、“朝上”等)，使本文實施例容易說明一特徵部件與另一特徵部件的關係。空間相對性用語意在涵蓋具有特徵部件的裝置的不同方位。更進一步，當使用“約”、“近似”等描述數值或數值範圍時，此用語旨在涵蓋包括所述數值的合理範圍內的數值，例如所述的數值的+/-10%，或任何所屬技術領域中具有通常知識者所理解的其他數值。舉例來說，用語“約5nm”涵蓋從4.5nm至5.5nm的範圍。
本揭露內容通常有關於一種半導體裝置及其製造，特別是關於一種積體電路(IC)晶片，此晶片在不同區域具有不同數量的通道構件的電晶體，適合於同一晶片上的不同應用。在不同的實施例中，在同一基底上具有不同數量的通道構件的多橋通道(MBC)電晶體分別放置於一積體電路(IC)晶片內部的第一區域(例如，用於高功率應用的核心區域)及第二區域(例如，用於低漏電應用的輸入/輸出(I/O)區域)。根據本揭露內容的各個型態，不同數量的通道構件可實現於半導體結構的背側。儘管堆疊的半導體通道層(包括奈米線或奈米片形式)的實施例於圖式中繪示為通道構件，但本揭露的內容並未受限於此，且可適用於其他多閘極裝置(例如，其他類型的多橋通道(MBC)電晶體或鰭式場效電晶體(FinFET))。
現在將參照圖式詳細說明本揭露的各個型態。第1A及1B圖共同繪示出半導體裝置的製造方法100流程圖。方法100僅為一示例，並未將本揭露內容局限於方法100中具體說明的內容。在方法100之前、期間及之後可提供額外的操作步驟，所說明的一些操作步驟可在上述方法的其他實施例中進行替換、取消或移動。為了簡化起見，此處並未詳細說明所有的操作步驟。以下配合第2至28D圖來說明方法100，圖式中繪示出根據方法100的實施例，工作部件200在不同製造階段的片段式立體示意圖及剖面示意圖。由於半導體裝置將由工作部件200所形成，依內文需要，工作部件200可稱為半導體裝置200或裝置200。
在一些實施例中，工作部件200為一部分的積體電路(IC)晶片、一系統晶片(SoC)或其一部分，包括各種被動及主動的微電子裝置，例如電阻、電容器、電感器、二極體、p型場效電晶體(PFET)、n型場效電晶體(NFET)、鰭式場效電晶體(FinFET)、奈米片場效電晶體 (FET)、奈米線場效電晶體 (FET)、其他類型的多閘極場效電晶體 (FET)、金屬氧化物半導體場效電晶體(MOSFET)、互補式金屬氧化物半導體(CMOS)電晶體、雙極接面電晶體(BJT)。橫向擴散金屬氧化物半導體(LDMOS)電晶體、高電壓電晶體、高頻電晶體、記憶體裝置、其他合適的元件，或其組合。已簡化第2至28D圖，以更好地理解本揭露的發明概念。在工作部件200中可加入額外的特徵部件，並且在工作部件200的其他實施例中可進行替換、修改或取消以下所述的一些特徵部件。工作部件200包括用於高功率及/或高速應用的第一區域(也表示為區域I)，例如要求較強電流驅動能力的核心區域，以及包括用於低電容及/或低漏電應用的第二區域(也表示為區域II)，例如要求較弱的電流驅動能力的輸入/輸出(I/O)區域。區域I可包括高效能計算(HPC)單元、中央處理單元(CPU)邏輯電路、記憶體電路及其他核心電路。區域II可包括輸入/輸出(I/O)單元、ESD單元及其他電路。
第2圖繪示出工作部件200的立體示意圖，第3A至28D圖繪示出工作部件200的局部剖面示意圖，分別沿第2圖的A-A線、B-B線、C-C線、D-D線、E-E線以及F-F線。具體來說，A-A線及B-B線分別為區域I及區域II中待形成的電晶體的通道區域的片段式剖面示意圖(亦即，沿閘極結構的長度方向且垂直於通道構件的長度方向的通道區域內於Y-Z平面的截面)；C-C線及D-D線分別為沿區域I及區域II中待形成的電晶體的通道構件長度方向的片段式剖面示意圖(亦即，沿通道構件的長度方向且穿過通道區域並鄰接源極/汲極區域於Y-Z平面的截面)；E-E及F-F線分別為區域I及區域II中待形成的電晶體的源極區或汲極區的片段式剖面示意圖 (亦即，垂直於通道構件的長度方向的源極區或汲極區於Y-Z平面的截面)。在本揭露中，源極及汲極可互相交換使用。
請參照第2及3A-3D圖，方法100包括步驟區塊102(第1A圖)，接收一工作部件200。工作部件200包括一基底202及設置於基底202上的一堆疊204。在一實施例中，基底202可為一矽(Si)基底。在其他一些實施例中，基底202可包括其他半導體材料，例如鍺(Ge)、矽鍺(SiGe)或III-V族半導體材料。III-V族半導體材料的示例可包括砷化鎵(GaAs)、磷化銦(InP)、磷化鎵(GaP)、氮化鎵(GaN)、磷化砷鎵(GaAsP)、砷化銦鋁(AlInAs)、砷化鎵鋁(AlGaAs)、磷化銦鎵(GaInP)及砷化鎵銦(InGaAs)。在各種實施例中，基底202為從區域I連續延伸至區域II的一基底。
堆疊204可包括在基底202上的交替的通道層208及 犧牲層206，以及位於犧牲層206及通道層208上的頂層犧牲層206T。犧牲層206、通道層208及頂層犧牲層206T可使用磊晶製程進行沉積。示例的磊晶製程可包括氣相磊晶(vapor-phase epitaxy, VPE)、超高真空化學氣相沉積(ultra-high vacuum, CVD UHV-CVD))、分子束磊晶(molecular beam epitaxy, MBE)及/或其他合適的製程。通道層208及犧牲層206可具有不同的半導體組成。在一些實施例中，通道層208由矽(Si)所形成，而犧牲層206由矽鍺(SiGe)所形成。犧牲層206內額外的鍺(Ge)含量允許選擇性去除或凹陷犧牲層206，而不會對通道層208造成實質性的損害。犧牲層206及通道層208交替排列，使犧牲層206與通道層208交錯排列。第2圖繪示出三層犧牲層206及三層通道層208交替及垂直排列，其僅為說明性目的，並未限制申請專利範圍中具體記載的內容。層數取決於半導體裝置200的通道層208的所需數量。在一些實施例中，通道層208的數量在2至7之間。
如同犧牲層206，頂部的犧牲層206T可由矽鍺(SiGe)形成。在某些情況下，犧牲層206及頂層犧牲層206T的組成實際上是相同的。頂層犧牲層206可厚於犧牲層206，其功能為保護堆疊204在製造過程中免於遭受損壞。在某些情況下，頂層犧牲層206T的厚度可約在20nm至40nm之間，而犧牲層206的厚度可約在4nm至15nm之間。
請參照第4A至4C圖，方法100包括步驟區塊104(第1A圖)，圖案化堆疊204及基底202，以形成由鰭狀溝槽212分隔的鰭形結構210。為了圖案化堆疊204及基底202，沉積一硬式罩幕層214於頂部的犧牲層206T上。然後，圖案化硬式罩幕層214以作為蝕刻罩幕來圖案化頂層犧牲層206T、堆疊204及基底202的頂部。在一些實施例中，硬式罩幕層214可使用化學氣相沉積(CVD)、電漿增強化學氣相沉積(plasma-enhanced CVD, PECVD)、原子層沉積(atomic layer deposition, ALD)、電漿增強原子層沉積(plasma-enhanced ALD, PEALD)或合適的沉積方法進行沉積。硬式罩幕層214可為單層或多層。當硬式罩幕層214為多層時，硬式罩幕層214可包括氧化墊層及氮化墊層。在另一實施例中，硬式罩幕層214可包括矽(Si)。鰭形結構210可使用合適的製程，包括雙重圖案化製程或多重圖案化製程。般來說，雙重圖案或多重圖案製程結合了微影及自對準製程，容許形成的圖案的間距小於使用單一直接微影製程可獲得的間距。舉例來說，在一實施例中，一材料層形成於一基底上，並使用微影製程進行圖案化。使用自對準製程形成間隔層於圖案化的材料層旁側。之後，去除材料層，餘留的間隔層或芯軸可接著用於圖案化硬式罩幕層214，然後圖案化的硬式罩幕層214可作為蝕刻罩幕來蝕刻堆疊204及基底202，以形成鰭形結構210。蝕刻製程可包括乾式蝕刻、溼式蝕刻、反應離子蝕刻(reactive ion etching, RIE)及/或其他合適的製程。
仍然請參照第4A至4D圖，每個鰭形結構210包括由基底202的一部分形成的基體部210B及由堆疊204形成的頂層部210T。頂層部210T設置於基體部210B上。鰭形結構210沿X方向縱向延伸，並從基底202沿Z方向垂直延伸。沿Y方向，鰭狀溝槽212隔開鰭形結構210。在某些情況下，鰭狀溝槽212的寬度約在20nm至50nm，其定義出相鄰鰭形結構210之間的間距。
請參照第5A至5D圖，方法100包括步驟區塊106(第1A圖)，其中在鰭狀溝槽212中形成一隔離特徵部件216。隔離特徵部件216可稱為淺溝槽隔離(shallow trench isolation, STI)特徵部件216。在一示例中，為了形成隔離特徵部件216，在工作部件200上沉積介電材料，用介電材料填滿鰭狀溝槽212。在一些實施例中，介電材料可包括四乙基正矽酸鹽(tetraethylorthosilicate, TEOS)氧化物、未摻雜的矽酸鹽玻璃或摻雜的矽氧化物(例如，硼磷矽酸鹽玻璃(borophosphosilicate glass, BPSG)、熔融石英玻璃(fused silica glass, FSG)、磷矽酸鹽玻璃(phosphosilicate glass, PSG)、硼摻雜矽玻璃(boron doped silicon glass, BSG)及/或其他合適的介電材料。 在各種的示例中，在步驟區塊106，介電材料可透過流動式化學氣相沉積(FCVD)、旋轉塗佈及/或其他合適的製程進行沉積。然後，薄化及平坦化沉積的介電材料，例如透過化學機械研磨(chemical mechanical polishing, CMP)製程，直至露出硬式罩幕層214。
在進行平坦化之後，在回蝕刻製程中凹陷沉積的介電材料，直至位於鰭形結構210的頂層部的一些犧牲層206及通道層208升高於隔離的特徵部件216之上。相較之下，隔離特徵部件216仍然完全覆蓋基體部210B以及其他位於鰭形結構210的底層部的 犧牲層206及通道層208。如以下將進一步詳細說明般，儘管在區域I及區域II中通道層208的數量看起來是相同的，然而區域II中完全或局部由隔離特徵部件216所覆蓋的通道層208後續將從工作部件200的背側移除。具體來說，在繪示的實施例中，最底層的犧牲層206由隔離特徵部件216所完全覆蓋，而最底層的通道層208則由隔離特徵部件216所局部覆蓋，且將移除最底層的通道層208，使得位於區域II中的通道層208將比位於區域I中的減少一個數量。在各種實施例中，透過使更多的底層通道層208未完全高於隔離特徵部件216，區域II中的通道層208的數量將進一步減少，例如比區域I中的通道層少1至4層。換句話說，如以下所述，隔離特徵部件216的高度係用以控制將從區域II中移除的通道層208數量。區域I及區域II中的通道層的差異是由裝置效能需求所決定的。步驟區塊106的回蝕刻製程可包括，例如，溼式蝕刻、乾式蝕刻、反應離子蝕刻，或其他適當的蝕刻方法。硬式罩幕層214也可在回蝕刻製程中移除。
請參照第6A至6D圖，方法100包括步驟區塊108(第1A圖)，其中區域I中的隔離特徵部件216在回蝕刻製程中進一步凹陷，直至堆疊204完全升高至隔離特徵部件216之上。如所繪示的實施例，也可局部露出位於區域I中的基體部210B。回蝕刻製程可包括，例如，溼式蝕刻、乾式蝕刻、反應離子蝕刻或其他合適的蝕刻方法。進一步的凹陷的距離ΔH可約在5nm至30nm。為了限制區域I中的回蝕刻製程，可先沉積一罩幕層214(例如，透過旋轉塗佈)以覆蓋區域II。在一些實施例中，罩幕層214為一光阻層，如底部抗反射 (bottom antireflective coating, BARC)層。在進一步凹陷位於區域I中的隔離特徵部件216之後，罩幕層214可在蝕刻製程或其他合適的製程中移除，例如灰化或光阻剝離。
請參照第7A至7D、8A至8D及9A至9D圖，方法100包括步驟區塊110(第1A圖)，其中形成介電鰭部218。在繪示的實施例中，在步驟區塊110，介電鰭部218形成於鰭狀溝槽212內。形成介電鰭部218的示例性製程包括順應性沉積一包覆層220(如第7A至7D圖所示)、順應性沉積一第一介電層222及沉積一第二介電層224於鰭狀溝槽212內(如第8A至8D圖所示)，以及沉積一高k值介電層226於第一介電層222及第二介電層224的頂部上 (如第9A至9D圖所示)。
包覆層220沉積於工作部件200上，包括位於區域I中的堆疊204的側壁及基體部210B的頂部上，以及位於區域II中的堆疊204的局部側壁上。在一些實施例中，包覆層220可具有相似於 犧牲層206或頂層犧牲層206T的組成。在一示例中，包覆層220可由矽鍺(SiGe)形成。共同的組成容許在後續的蝕刻製程中，選擇性及同時性去除犧牲層206及包覆層220。在一些實施例中，包覆層220可使用氣相磊晶(VPE)或分子束磊晶(MBE)進行順應性磊晶生長。如第7A至7D圖所示，包覆層220選擇性設置於鰭狀溝槽212的露出側壁表面上。根據包覆層220選擇性生長的程度，可進行回蝕刻製程，以露出隔離特徵部件216。
形成介電層218的一示例性製程進一步包括在工作部件200上依序順應性沉積第一介電層222及第二介電層224。第一介電層222包圍第二介電層224。第一介電層222可使用化學氣相沉積(CVD)、原子層沉積(ALD)或合適的方法進行順應性沉積。第一介電層222形成了位於鰭狀溝槽212的側壁及下表面上的襯層。接著第二介電層224透過使用化學氣相沉積(CVD)、高密度電漿化學氣相沉積(high density plasma CVD, HDPCVD)、流動式化學氣相沉積(FCVD)及/或其他合適的製程順應性沉積於第一介電層222上。在某些情況下，第二介電層224的介電常數小於第一介電層222的介電常數。第一介電層222可包括矽、氮化矽、碳化矽、氮碳化矽、氮碳氧化矽、氧化鋁、氮化鋁、氮氧化鋁、氧化鋁、氧化鋯、氮化鋯、氮化鋯鋁、氧化鉿或合適的介電材料。在一實施例中，第一介電層222可包括氧化鋁。第二介電層224可包括氧化矽、碳化矽、氮氧化矽、氮碳氧化矽或合適的介電材料。在一實施例中，第二介電層224包括氧化矽。在某些情況下，如第8A至8D圖所示，在沉積介電層222及224之後，可進行化學機械研磨(CMP)製程，以去除多餘的材料部分，並平坦化工作部件200的上表面，以露出頂層犧牲層206T。
形成介電層218的示例性製程可進一步包括沉積高k值介電層226。在某些情況下，進行凹陷製程以移除介電層222及224的頂部。凹陷製程可包括乾式蝕刻製程、溼式蝕刻製程及/或其組合。在一些實施例中，控制凹陷深度(例如，透過控制蝕刻時間)以形成所需的凹陷深度。在一些實施例中，高k值介電層226可包括HfO 2、ZrO 2、HfAlO x、HfSiO x、Y 2O 3、Al 2O 3或其他高k值材料。高k值介電層226可透過化學氣相沉積(CVD)製程、原子層沉積(ALD)製程、物理氣相沉積(PVD)製程及/或其他合適的製程進行沉積。如第9A至9D圖所示，在高k值介電層226的沉積之後，進行化學機械研磨(CMP)製程，以去除多餘的材料部分，並平坦化工作部件200的上表面。結束步驟區塊110之後，介電層218定義為具有一下部(包括介電層222、224的凹陷部分)及一上部(包括高k值介電層226)。介電鰭部218也稱為混合式鰭部218。位於區域I及區域II的介電鰭部218具有不一致的下表面，例如位於區域I的下表面比位於區域II的下表面低ΔH。如上所述，ΔH可約在5nm至30nm。
請參照第10A至10D圖，方法100包括步驟區塊112(第1A圖)，其中移除鰭形結構210中的頂層犧牲層206T。在步驟區塊112，蝕刻工作部件200，以選擇性去除頂層犧牲層206T及局部的包覆層220，以露出最頂層的通道層208，而不實質性損壞介電層218。在某些情況下，由於頂層犧牲層206T及包覆層220是由矽鍺(SiGe)形成的，在步驟區塊112的蝕刻製程可能對矽鍺(SiGe)具有選擇性。舉例來說，包覆層220及頂部的犧牲層206T可使用選擇性的溼式蝕刻製程進行蝕刻，包括氫氧化銨(NH 4OH)、氟化氫(HF)、過氧化氫(H 2O 2)或其組合。在去除頂層犧牲層206T及局部的包覆層220之後，介電層218升高至最頂層的通道層208之上。
請參照第11A至11D圖，方法100包括步驟區塊114(第1A圖)，其中形成虛置閘極堆疊240於鰭形結構210的通道區域上。在一些實施例中，採用了閘極取代製程(或後閘極製程)，其中虛置閘極堆疊240作為功能性閘極結構的預留位置。也可能採用其他製程及配置。在繪示的實施例中，虛置閘極堆疊240包括一虛置介電層242及設置於虛置介電層242上的一虛置電極244。基於圖案化的目的，於虛置閘極堆疊240上沉積一閘極頂部硬式罩幕246。閘極頂部硬式罩幕246可為多層的，包括一氮化矽罩幕層248及位於氮化矽罩幕層248上的一氧化矽罩幕層250。位於虛置閘極堆疊240下方的鰭形結構210的區域可稱為通道區域。鰭形結構210中的每個通道區域夾設於兩個源極/汲極區域之間，以形成源極/汲極。在一示例中，虛置介電層242透過化學氣相沉積(CVD) 毯覆式沉積於工作部件200上。接著，用於虛置電極244的材料層毯覆式沉積於虛置介電層242上。虛置介電層242及用於虛置電極244的材料層透過微影製程進行圖案化，形成虛置閘極堆疊240。在一些實施例中，虛置介電層242可包括氧化矽，而虛置電極244可包括多晶矽(polysilicon)。
仍然請參照第11A至11D圖，方法100包括步驟區塊116(第1A圖)，其中閘極間隙壁252沿著虛置閘極堆疊240的側壁形成。閘極間隙壁252可包括二或更多個閘極間隙壁層。可選擇閘極間隙壁252的介電材料，以容許選擇性去除虛置閘極堆疊240。合適的介電材料可包括氮化矽、氮碳氧化矽、氮碳化矽、氧化矽、碳氧化矽、碳化矽、氮氧化矽及/或其組合。在一示例的製程中，可使用化學氣相沉積(CVD)、次常壓化學氣相沉積(subatmospheric CVD, SACVD)或原子層沉積(ALD) 順應性沉積閘極間隙壁252於工作部件200上，然後進行異向性蝕刻。然後進行異向性蝕刻，以去除水平部分，同時閘極間隙壁252的垂直部分餘留於虛置閘極堆疊240的側壁上。
請參照第12A至12D圖，方法100包括步驟區塊118(第1A圖)，其中凹陷鰭形結構210的源極/汲極區域，以形成源極凹槽及汲極凹槽，其統稱為源極/汲極凹槽254(或源極/汲極溝槽254)。以虛置閘極堆疊240及閘極間隙壁252作為蝕刻罩幕，異向性蝕刻工作部件200，以在鰭形結構210的源極/汲極區域形成源極/汲極凹槽254。在繪示的實施例中，步驟區塊118的操作從區域I及區域II的源極/汲極區域移除犧牲層206及通道層208，藉以露出基體部210B，且從區域II中移除包覆層220及局部的隔離特徵部件216，藉以露出隔離特徵部件216(第12B圖)。相較之下，由於包覆層220延伸至區域I中最底層的犧牲層206以下，因此仍然餘留包覆層220的最底層部分並覆蓋區域I中的隔離特徵部件216(第12A圖)。步驟區塊118的異向性蝕刻可包括乾式蝕刻製程。舉例來說，乾式蝕刻製程可實施於氫氣、含氟氣體(例如CF 4、SF 6、CH 2F 2、CHF 3及/或C 2F 6)、含氯氣體(例如，Cl 2、CHCl 3、CCl 4及/或BCl 3)，含溴氣體(如HBr及/或CHBr3)、含溴氣體(例如，HBr及/或CHBr 3)、含碘氣體、其他合適的氣體及/或電漿，及/或其組合。結束步驟區塊118之後，位於區域I及II的基體部210B所露出的上表面為平坦的，如第12A及12B圖中的虛線所示。
請參照第13A至13D圖，方法100包括步驟區塊120，其中透過蝕刻製程，使位於區域I的源極/汲極凹槽254進一步延伸至基體部210B內，以形成較深的源極/汲極凹槽254D，並去除位於區域I的包覆層220的餘留部分。為了限制區域I中的蝕刻製程，可先沉積(例如，透過旋轉塗佈)一罩幕層256來覆蓋區域II。在一些實施例中，罩幕層256為一光阻層，如底部抗反射(BARC)層。在延伸位於區域I的較深的源極/汲極凹槽254D之後，罩幕層256可在蝕刻製程或其他合適的製程(例如，灰化或光阻剝離)中移除。進一步凹陷的距離ΔH’可約在5nm至10nm。
請參照第14A至14D圖，方法100包括步驟區塊122，其中形成內間隔特徵部件258。在一些實施例中，在步驟區塊122中，先選擇性局部凹陷源極/汲極凹槽254及較深的源極/汲極凹槽254D內所露出的犧牲層206，以形成內間隔凹槽，而露出的通道層208則實質上未受蝕刻。在一實施例中，通道層208實質上由矽(Si)組成，而犧牲層206實質上由矽鍺(SiGe)組成，犧牲層206的選擇性及局部凹陷可包括SiGe氧化製程並接著去除SiGe氧化物。在上述實施例中，SiGe氧化製程可包括使用臭氧。在其他一些實施例中，局部凹陷可包括選擇性蝕刻製程(例如，選擇性乾式蝕刻製程或選擇性溼式蝕刻製程)，而犧牲層206的凹陷程度由蝕刻製程的進行時間來控制。選擇性乾式蝕刻製程可包括使用一或多種氟基蝕刻劑，例如氟氣或氫氟碳化物。選擇性溼式蝕刻製程可包括氫氧化銨(NH 4OH)、氟化氫(HF)、過氧化氫(H 2O 2)或其組合(例如，包括氫氧化銨-過氧化氫-水混合物的APM蝕刻)。在形成內間隔凹槽之後，使用化學氣相沉積(CVD)或原子層沉積(ALD) 順應性沉積內間隔材料層於工作部件200上，包括於內間隔凹槽上方及內部。內間隔材料可包括氮化矽、氮碳氧化矽、氮碳化矽、氧化矽、碳氧化矽、碳化矽或氮氧化矽。在沉積內間隔材料層之後，回蝕刻內間隔材料層，以形成內間隔特徵部件258，如第14A至14D圖所示。
仍然請參照第14A至14D圖，方法100包括步驟區塊124，其中形成源極/汲極特徵部件260。選擇性磊晶沉積源極/汲極特徵部件260於源極/汲極凹槽254及較深的源極/汲極凹槽254D內的通道層208及基體部210B的露出的半導體表面上。源極/汲極特徵部件260可使用磊晶製程進行沉積，例如氣相磊晶(VPE)、超高真空化學氣相沉積(UHV-CVD)、分子束磊晶(MBE)及/或其他合適的製程。在某些情況下，源極/汲極特徵部件260包括一未摻雜的磊晶層262及一重摻雜的磊晶層264。未摻雜的磊晶層262是為了防止重摻雜的磊晶層264與井區之間的漏電流。在某些情況下，未摻雜的磊晶層262的厚度約在5nm至15nm。於較深的源極/汲極凹槽254D的深度較大，未摻雜的磊晶層262在區域I中位於最底層的通道層208下方(第14C圖)，而在區域II中則位於最底層的通道層208上方(第14D圖)。重摻雜的磊晶層264可摻雜p型摻雜物或n型摻雜物，取決於電晶體的所需配置。當源極/汲極特徵部件260為n型時，重摻雜的磊晶層264可包括摻雜有n型摻雜劑(例如，磷(P)或砷(As))的矽(Si)。當源極/汲極特徵部件260為p型時，重摻雜的磊晶層264可包括摻雜有p型摻雜劑(例如，硼(B)或鎵(Ga))的矽鍺(SiGe)。重摻雜的磊晶層264的摻雜可透過於沉積時原位(in-situ)進行，也可透過使用佈植製程(例如，接面佈植製程)非原位進行。另外，如第14A及14B圖所示，在源極/汲極凹槽254的側壁的階梯區域及較深的源極/汲極凹槽254D處，源極/汲極特徵部件260的刻面(facet)可捕獲位於源極/汲極特徵部件260與介電特徵部件(例如，介電鰭部218及隔離特徵部件216)之間空孔267。隨後，在蝕刻製程中選擇性移除位於源極/汲極區域的介電鰭部218的高k值介電層226，如第15A至15D圖所示。蝕刻製程可包括乾式蝕刻、溼式蝕刻、反應離子蝕刻(RIE)及/或其他合適的製程。
請參照第16A至16D圖，方法100包括步驟區塊126(第1A圖)，其中沉積一接觸蝕刻停止層(contact etch stop layer, CESL)270及一層間介電(interlayer dielectric, ILD) 272層於工作部件200的前側。在一示例中，先順應性沉積接觸蝕刻停止層(CESL)270於工作部件200上，然後毯覆式沉積層間介電(ILD)層272於接觸蝕刻停止層(CESL)270上。接觸蝕刻停止層(CESL)270可包括氮化矽、氧化矽、氮氧化矽及/或本領域內已知的其他材料。接觸蝕刻停止層(CESL)270可使用原子層沉積(ALD)、電漿增強化學氣相沉積(PECVD)製程及/或其他合適的沉積或氧化製程進行沉積。在一些實施例中，層間介電(ILD)層272包括乙基正矽酸鹽(TEOS)氧化物、未摻雜的矽酸鹽玻璃等材料或摻雜的氧化矽(例如，硼磷矽酸鹽玻璃(BPSG)、熔融石英玻璃(FSG)、磷矽酸鹽玻璃(PSG)、硼摻雜矽玻璃(BSG)及/或其他合適的介電材料。層間介電(ILD)層272可透過旋轉塗佈、流動式化學氣相沉積(FCVD)製程或其他合適的沉積技術進行沉積。在一些實施例中，在形成層間介電(ILD)層272之後，可對工作部件200進行退火，以改善層間介電(ILD)層272的完整性。為了去除多餘的材料(包括閘極頂部硬式罩幕246)，並露出虛置閘極堆疊240的虛置電極244的上表面。可對工作部件200進行平坦化製程(例如，化學機械研磨(CMP)製程)，以提供平面的上表面。
請參照第17A至17D圖，方法100包括步驟區塊128(第1A圖)，其中選擇性移除虛置閘極堆疊240。結束步驟區塊126時，透過選擇性蝕刻製程從工作部件200中移除露出的虛置閘極堆疊240。選擇性蝕刻製程可為選擇性溼式蝕刻製程、選擇性乾式蝕刻製程或其組合。 在繪示的實施例中，選擇性蝕刻製程可選擇性去除虛置介電層242及虛置電極244，而並未實質上損壞通道層208及閘極間隙壁252。移除虛置閘極堆疊240導致閘極溝槽266位於通道區域上方。在移除虛置閘極堆疊240之後，閘極溝槽266內露出通道區域的通道層208、犧牲層206及包覆層220。
請參照第18A至18D圖，方法100包括步驟區塊130(第1A圖)，其中從閘極溝槽266內移除犧牲層206及包覆層220以釋出通道層208。需要注意的是，儘管全部移除了位於區域I的犧牲層206，然而區域II(第18B圖)中至少最底層的犧牲層206仍然存在，因為其在最底層的通道層208及隔離特徵部件216的保護之下。結束步驟區塊130時，釋出的通道層208也稱為通道構件208。在繪示的實施例中，通道構件208相似於薄片或奈米片，釋出通道構件的製程也可稱為薄片形成製程。通道構件208為沿Z方向垂直堆積。所有的通道構件208都經由包覆層220與介電鰭部218橫向隔開一距離。選擇性去除犧牲層206及包覆層220的可透過選擇性乾式蝕刻、選擇性溼式蝕刻或其他選擇性蝕刻製程來進行。在一些實施例中，選擇性溼式蝕刻包括氫氧化銨(NH 4OH)、氟化氫(HF)、過氧化氫(H 2O 2)或其組合(例如，包括氫氧化銨-過氧化氫-水混合物的APM蝕刻)。在一些其他的實施例中，選擇性去除包括矽鍺氧化，接著再去除矽鍺氧化物。舉例來說，可透過臭氧清潔進行氧化，然後再透過蝕刻劑(例如，氫氧化銨(NH 4OH))去除氧化矽。
請參照第19A至19D圖，方法100包括步驟區塊132(第1A圖)，其中形成閘極結構274(功能閘極結構274或金屬閘極結構274)於閘極溝槽266內，以與通道構件208嚙合。在區域I中，每個通道構件208由各自的閘極結構274所包圍。相較之下，在區域II中，最底層的通道層208的上表面沉積有閘極結構274，但在其下表面則未有沉積，而下表面仍與最底層的犧牲層206相接觸。每一閘極結構274包括設置於通道構件208上的閘極介電層276及位於閘極介電層276上的閘極電極層278。在一些實施例中，閘極介電層276包括一界面層及一高k值介電層。界面層可包括氧化矽，並由預清潔製程形成。預清潔製程的示例可包括使用RCA SC-1(氨、過氧化氫及水)及/或RCA SC-2(鹽酸、過氧化氫及水)。預先清洗的製程會氧化通道構件208的露出表面而形成界面層。然後使用原子層沉積(ALD)、化學氣相沉積(CVD)及/或其他合適的方法沉積高k值介電層於界面層上。高k值介電層包括高k值介電材料。在一實施例中，高k值介電層可包括氧化鉿。或者，高k值介電層也可包括其他高k值介電材料，如氧化鈦(TiO 2)、氧化鋯鉿(HfZrO)、氧化鉭(Ta 2O 5)、氧化鉿矽(HfSiO 4) 、氧化鋯(ZrO2) 、氧化鋯矽(ZrSiO2) 、氧化鑭(La2O3) 、氧化鋁(Al2O3) 、氧化鋯(ZrO 2)、氧化鋯矽(ZrSiO 2)、氧化鑭(La 2O 3)、氧化鋁(Al 2O 3)、氧化鋯(ZrO)。氧化釔(Y 2O 3)、SrTiO 3(STO)、BaTiO 3(BTO)、BaZrO、氧化鑭鉿(HfLaO)、氧化鑭矽(LaSiO)、氧化鋁矽(AlSiO)、氧化鉿鉭(HfTaO)、氧化鉿鈦(HfTiO)、(Ba,Sr)TiO 3(BST)、氮化矽(SiN)、氮氧化矽(SiON)、其組合或其他合適的材料。在形成閘極介電層276之後，閘極電極層278沉積於閘極介電層276上。閘極電極層278可為多層結構，包括至少一功函數層及一金屬填充層。舉例來說，至少一功函數層可包括氮化鈦(TiN)、鈦鋁(TiAl)、氮化鈦鋁(TiAlN)、氮化鉭(TaN)、鉭鋁(TaAl)、氮化鉭鋁(TaAlN)、碳化鉭鋁(TaAlC)、碳化鉭(TaCN)，或碳化鉭(TaC)。金屬填充層可包括鋁(Al)、鎢(W)、鎳(Ni)、鈦(Ti)、釕(Ru)、鈷(Co)、鉑(Pt)、鉭氮化矽(TaSiN)、銅(Cu)、其他耐火金屬或其他合適的金屬材料或其組合。在各種的實施例中，閘極電極層278可透過原子層沉積(ALD)、物理氣相沉積(PVD) 、化學氣相沉積(CVD)、電子束蒸鍍或其他合適的製程形成。雖然圖式中未明確繪示，然而閘極結構274沉積為一連接的閘極結構，然後回蝕刻直至介電鰭部218將連接的閘極結構分離成彼此隔開的閘極結構274。介電鰭部218也於相鄰的閘極結構274之間提供電性隔離。閘極結構274的回蝕刻可包括使用硝酸、鹽酸、硫酸、氫氧化銨、過氧化氫或其組合的選擇性溼式蝕刻製程。雖然在繪示實施例中，閘極結構274的上表面在回蝕刻製程之後與高k值介電層226的下表面齊平，然而在其他實施例中，閘極結構274的上表面在回蝕刻製程之後可能低於高k值介電層226的下表面。閘極結構274的回蝕刻也可包括回蝕刻通道區域中高介電鰭部218的高k值介電層226。
請參照第20A至20D圖，方法100包括步驟區塊134(第1B圖)，其中在工作部件200的前側形成金屬蓋層280、自對準蓋(self-aligned cap, SAC)層282及閘極切割特徵部件284。1B)，其中形成金屬蓋層280、自對準蓋(SAC)層282及閘極切割特徵部件284於工作部件200的前側。在一些實施例中，金屬蓋層280可包括鈦(Ti)、氮化鈦(TiN)、氮化鉭(TaN)、鎢(W)、釕(Ru)、鈷(Co)或鎳(Ni)，並且可使用物理氣相沉積(PVD) 、化學氣相沉積(CVD)或金屬有機化學氣相沉積(metal organic chemical vapor deposition, MOCVD)進行沉積。在一實施例中，金屬蓋層280包括鎢(W)(例如，無氟鎢(fluorine-free tungsten, FFW))，並透過物理氣相沉積(PVD)進行沉積。在一些其他實施例中，金屬蓋層280透過金屬有機化學氣相沉積(MOCVD)進行沉積，金屬蓋層280的沉積可選擇性沉積於閘極結構 274上。在沉積金屬蓋層280之後，自對準蓋(SAC)層282透過化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)或合適的沉積製程而沉積於工作部件200上。自對準蓋(SAC)層282可包括氧化矽、氮化矽、碳化矽、氮碳化矽、氮氧化矽、氮碳氧化矽、氧化鋁、氮化鋁、氧氮化鋁、氧化鋯、氮化鋯、氧化鋯鋁、氧化鉿或合適的介電材料。然後進行微影製程及蝕刻製程來蝕刻沉積的自對準蓋(SAC)層282，以形成閘極切割開口而露出介電鰭部218的上表面。之後，沉積介電材料並透過化學機械研磨(CMP)製程進行平坦化，以在閘極切割開口處形成閘極切割的特徵部件284。閘極切割特徵部件284的介電材料可使用高密度電漿化學氣相沉積(HDPCVD)、化學氣相沉積(CVD)、原子層沉積(ALD)或合適的沉積技術進行沉積。在某些情況下，閘極切割特徵部件284可包括氧化矽、氮化矽、碳化矽、氮碳化矽、氮氧化矽、氮碳氧化矽、氧化鋁、氮化鋁、氧氮化鋁、氧化鋯、氮化鋯、氧化鋯鋁、氧化鉿或合適的介電材料。在一些實施例中，閘極切割特徵部件284及自對準蓋(SAC)層282可具有不同的組成，以導入蝕刻選擇性。
請參照第21A至21F圖，方法100包括步驟區塊136(第1B圖)，其中進行一或多個前側中段(middle-end-of-line, MEOL)及前側後段(back-end-of-line, BEOL)製程，以形成一或多個內連接層，其具有埋入於介電層的接點(contact)、介層連接窗(via)及金屬線(也稱為金屬接線層)。在一些實施例中，在步驟區塊136的操作包括形成源極/汲極接點286、閘極接點288、額外的層間介電(ILD)層290以及金屬接線層292。工作部件200可進一步包括鈍化護層及/或其他建於工作部件200的前側的膜層。這些膜層及一或多個內連接層連接各個電晶體的閘極電極、源極電極及汲極電極以及工作部件200中的其他電路，以形成局部或全部的積體電路。
請參照第22A至22D圖，方法100包括步驟區塊138(第1B圖)，其中承載體294黏合於工作部件200的前側。在一些實施例中，承載體294可為一矽晶圓。步驟區塊138的操作可使用任何合適的黏合製程，例如直接接合、混合接合、使用黏合劑或其他接合方法。在繪示的實施例中，形成一接合氧化物層296及一黏著層298於工作部件200的前側，並將承載體294與工作部件200的前側相連接。步驟區塊138的操作可進一步包括對準、退火及/或其他製程。如第23A至23D圖所示，黏合承載體294容許工作部件200翻面向下。如此可從工作部件200的背側接觸工作部件200，以便進一步進行製作。值得注意的是，工作部件200在後續圖式中也翻面向下，即第24A至26F圖。
請參照第24A至24D圖，方法100包括步驟區塊140(第1B圖)，其中從工作部件200的背側薄化工作部件200。一示例的薄化製程可包括在選擇性蝕刻製程中去除基底202，以在工作部件的背側形成溝槽300。在某些情況下，在區域I中，溝槽300內露出閘極結構274(特別是閘極介電層276)，在區域II中，溝槽300內露出最底層的犧牲層206。或者，如繪圖示的實施例，在區域II中，基底202的一薄層維持覆蓋最底層的犧牲層206，例如由於控制蝕刻製程的進行時間的蝕刻製程。未摻雜的磊晶層262也露出於區域I及II中，並局部凹陷。在一些實施例中，控制未摻雜的磊晶層262的凹陷深度(例如，透過控制蝕刻時間)，以得到所需的凹陷深度。結束步驟區塊140時，區域I及II中的未摻雜的磊晶層262的露出表面可為平坦的，如第24C及24D圖所示。在一些實施例中，第一階段的薄化製程包括一機械磨削製程，以去除大量的基底202，而隔離特徵部件216作為機械磨削停止層。之後，化學薄化製程可施加蝕刻化學劑於工作部件的背側，以去除基底202，而最底層的犧牲層206可作為蝕刻停止層。相似地，在一些實施例中，化學薄化製程可由計時器來控制，使得基底202的薄層仍可餘留於最底層的犧牲層206上。
請參照第25A至25F圖，方法100包括步驟區塊142(第1B圖)，其中在區域II中從溝槽300內選擇性蝕刻犧牲層206以及與犧牲層206鄰接且未被閘極結構274包圍的通道層208。在一些實施例中，罩幕層302為一光阻層，例如底部抗反射 (BARC)層。在繪示的實施例中，蝕刻一個犧牲層206(最底層)及一個通道層208(最底層)，藉以露出位於區域II的閘極結構274(特別是閘極介電層276)。在一示例中，進一步蝕刻閘極介電層276內的界面層，且溝槽300內露出閘極介電層276內的高k值介電層。如上文配合第5A至5D圖所說明，位於區域II的隔離特徵部件216的高度用於決定待去除的通道層208的數量，使得只有完全高於隔離特徵部件216的通道層208會保留下來。換句話說，取決於裝置效能的需要，可選擇性蝕刻多個未被閘極結構274包圍的通道層208，例如一到四層的通道層208。
步驟區塊142的操作實施一或多道蝕刻製程，其調整為對犧牲層206及通道層208的半導體材料具有選擇性，而對內間隔特徵部件258及閘極介電層276的介電材料沒有(或極少)受到蝕刻。再者，未摻雜的磊晶層262也可於溝槽300內凹陷，但未完全去除，以保護重摻雜的磊晶層264不受蝕刻製程所破壞。選擇性蝕刻製程可為乾式蝕刻、溼式蝕刻、反應離子蝕刻，或其他合適的蝕刻方法。如第25D圖所示，去除犧牲層206及凹陷未摻雜的磊晶層262會使得內間隔特徵部件258突出於工作部件200的背側。位於內間隔特徵部件258正下方的通道層208的端部(表示為端部208E)可在異向性蝕刻製程中保留下來，且也突出於工作部件200的背側。取決於凹槽深度，未摻雜的磊晶層262的露出表面可完全未於端部208E之下或接觸端部208E的側壁。在某些情況下，未摻雜的磊晶層262的露出表面與閘極介電層276的露出表面齊平。在另一些情況下，未摻雜的磊晶層262的露出表面位於閘極介電層276的露出表面之下。然而，在某些情況下，凹陷未摻雜的磊晶層262為選擇性的，可略過，使得未摻雜的磊晶層262維持其厚度，並在Y-Z平面內朝向工作部件200的背側位於介電鰭部218之上。在步驟區塊142的選擇性蝕刻製程後，罩幕層302可在蝕刻製程或其他合適的製程中移除，例如灰化或光阻剝離。再者，由於區域I中的隔離特徵部件216受到罩幕層302的保護，不受額外的選擇性蝕刻製程的影響，因此區域I中的隔離特徵部件216相較於區域II中具有圓角(如第25B及25F圖中的虛線所示)的隔離特徵部件216，可具有較尖銳的邊緣。
請參照第26A至26F圖，方法100包括步驟區塊144(第1B圖)，其中沉積背側介電層304於工作部件200的背側，並填滿溝槽300。背側介電層304實質上減少了井區隔離漏電流及源極與汲極特徵部件之間的基底漏電流。在一些實施例中，背側介電層304的沉積材料包括SiN、SiOCN、SiOC、SiCN、其組合或其他合適的材料。背側介電層304可透過化學氣相沉積(CVD)、物理氣相沉積(PVD)、電漿增強化學氣相沉積(PE-CVD)、流動式化學氣相沉積(F-CVD)、塗佈製程或其他合適的沉積技術進行沉積。在沉積背側介電層304之後，最底層的內間隔258及端部208E突出至背側介電層304內，如第26D圖所示。步驟區塊144的操作也包括進行平坦化製程(例如，化學機械研磨(CMP)製程)，以從工作部件200的背側去除多餘的介電材料，並露出隔離特徵部件216。
請參照第27A至27D圖，方法100包括步驟區塊146(第1B圖)，其中承載體308黏合於工作部件200的背側。在一些實施例中，承載體308可為一矽晶圓。步驟區塊146的操作可使用任何合適的黏合製程，例如直接接合、混合接合、使用黏合劑或其他接合方法。在繪示的實施例中，形成一接合氧化物層306於工作部件200的背側，並將承載體308工作部件200的背側相連接。步驟區塊146的操作可進一步包括對準、退火及/或其他製程。黏合承載體308容許工作部件200翻面向下。如此可從工作部件200的前側再次接觸工作部件200，以便進一步進行製作。步驟區塊146的操作也包括進行前側薄化製程(例如，化學機械研磨(CMP)製程)，將前側承載體294及黏著層298從工作部件200的前側移除，並露出前側接合氧化層296。
請參照第28A至28F圖，方法100包括步驟區塊148(第1B圖)，其中對工作部件200進行進一步製程。舉例來說，它可進行其他後段(BEOL)製程，以在工作部件200的前側形成更多的內連接層，例如前側電源軌。在一實施例中，前側電源軌可使用鑲嵌製程、雙鑲嵌製程、金屬圖案化製程或其他合適的製程形成。前側電源軌可包括鎢(W)、鈷(Co)、鉬(Mo)、釕(Ru)、銅(Cu)、鎳(Ni)、鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、氮化鉭(TaN)或其他金屬，並可通過化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、電鍍或其他合適的製程進行沉積。步驟區塊148的操作也可包括形成一鈍化護層於工作部件200的前側、進行其他後段(BEOL)製程以及移除背側承載體308。
仍請參照第28A至28D圖，在結束方法100後，在區域I及區域II中分別形成多個多橋通道(MBC)電晶體。每個多橋通道(MBC)電晶體包括一閘極結構274，其與一或多個通道構件208嚙合。相鄰的多橋通道(MBC)電晶體經由介電鰭部218及座落於介電鰭部218上的閘極切割特徵部件284電性隔離。特別是，區域I的多橋通道(MBC)電晶體相較於區域II的多橋通道(MBC)電晶體具有更多的堆疊通道構件208，以提供更強的電流驅動能力。此有利地滿足了在一積體電路(IC)晶片的不同區域的不同電流驅動能力的要求。再者，背側介電層304取代了原來的半導體基底，並與隔離特徵部件216一起於閘極結構及源極/汲極特徵部件下方定義一大的介電層。此方式有效地降低井區隔離漏電流及基底漏電流。背側介電層304在區域II的厚度大於在區域I的厚度，這是因為在區域II中具有較少的通道構件208而節省了空間。相較之下，源極/汲極特徵部件260在區域II的厚度小於在區域I的厚度。再者，區域I及區域II中最底層的內間隔特徵部件258可能是齊平的，然而區域II中的內間隔特徵部件向下突出至背側介電層304內，並且由於區域II中受到額外選擇性蝕刻製程而可能具有圓化邊緣。在區域II中，局部移除的最底層的通道構件208的端部208E也向下突出至背側介電層304內。
在一示例性型態中，本揭露提供一種半導體裝置之製造方法。上述方法包括：形成由一第一類型及一第二類型磊晶層構成的一堆疊於一半導體基底的一前側，第一類型及第二類型磊晶層具有不同的材料組成，第一類型及第二類型磊晶層在一垂直方向上交替設置；圖案化堆疊，以形成一鰭形結構；沉積一介電層於鰭形結構的側壁上；凹陷介電層，以露出鰭形結構的一頂層部，凹陷的介電層的上表面位於堆疊的下表面之上；形成一閘極結構於鰭形結構的頂層部上；從半導體基底的背側蝕刻半導體基底，以形成一溝槽於介電層之間，此溝槽露出堆疊的下表面；以及經由溝槽來蝕刻至少一最底層的第一類型磊晶層及一最底層的第二類型磊晶層。在一些實施例中，最底層的第一類型磊晶層位於最底層的第二類型磊晶層之下，而凹陷的介電層的上表面位於最底層的第一類型磊晶層的上表面之上。在一些實施例中，凹陷的介電層的上表面低於最底層的第二類型磊晶層的上表面。在一些實施例中，閘極結構為一金屬閘極結構，而蝕刻至少最底層的第一類型磊晶層及最底層的第二類型磊晶層是在形成閘極結構之後進行。在一些實施例中，上述方法也包括在形成閘極結構之前，從鰭形結構的頂層部移除第一類型磊晶層，且在形成閘極結構之後，閘極結構包圍鰭形結構的頂層部內的第二類型磊晶層。在一些實施例中，在形成閘極結構之後，最底層的第二類型磊晶層具有一上表面與閘極結構相接觸，且具有一下表面與最底層的第一類型磊晶層相接觸。在一些實施例中。蝕刻至少最底層的第一類型磊晶層及最底層的第二類型磊晶層包括從溝槽完全去除最底層的第一類型磊晶層及局部去除最底層的第二類型磊晶層。在一些實施例中，蝕刻至少最底層的第一類型磊晶層及最底層的第二類型磊晶層包括蝕刻多個第二類型磊晶層。在一些實施例中，上述方法也包括沉積一介電材料於溝槽內，而最底層的第二類型磊晶層的一部分突出進入介電材料內。
在另一示例性型態中，本揭露提供一種多閘極裝置之製造方法。上述方法包括：形成多個第一通道構件於一基底的一第一區域上，多個第一通道構件為垂直堆疊的；形成多個第二通道構件於基底的一第二區域上，多個第二通道構件為垂直堆疊的；形成一隔離特徵部件於第一及第二區域中，隔離特徵部件的上表面在第二區域高於在第一區域，使得在第二區域中多個第二通道構件的一部分低於隔離特徵部件的上表面；形成與多個第一通道構件嚙合的一第一閘極結構，以在第一區域形成一第一電晶體；形成與多個第二通道構件嚙合的一第二閘極結構，以在第二區域形成一第二電晶體；以及從第二區域移除多個第二通道構件的上述部分，使第一電晶體中的多個第一通道構件的數量大於第二電晶體中的多個第二通道構件的數量。在一些實施例中，形成隔離特徵部件包括：沉積一介電材料於多個第一及第二通道構件的側壁上；凹陷位於第一及第二區域的介電材料，以露出多個第一及第二通道構件的頂部；以及進一步凹陷位於第一區域的介電材料，以使多個第一通道構件完全位於介電材料之上。在一些實施例中，上述方法也包括蝕刻位於第一及第二區域的基底，以形成多個溝槽於第一及第二區域中，而去除多個第二通道構件的上述部分則露出位於第二區域的溝槽內的第二閘極結構。在一些實施例中，蝕刻基底露出了位於第一區域的溝槽內的第一閘極結構。在一些實施例中，上述方法也包括：形成多個第一源極/汲極特徵部件，與多個第一通道構件相接；以及形成多個第二源極/汲極特徵部件，與多個第二通道構件相接，其中第二源極/汲極特徵部件的厚度小於第一源極/汲極特徵部件的厚度。在一些實施例中，上述方法也包括：形成多個第一內間隔特徵部件，插入於第一源極/汲極特徵部件與第一閘極結構之間；形成多個第二內間隔特徵部件，插入於第二源極/汲極特徵部件與第二閘極結構之間；以及凹陷第二源極/汲極特徵部件，使最底層的第二內間隔特徵部件與第二源極/汲極特徵部件隔開。在一些實施例中，第一閘極結構包圍位於第一區域的多個第一通道構件中的每一者，且第二閘極結構包圍位於第二區域的多個第二通道構件的頂部中的每一者。
在另一示例性型態中，本揭露提供一種半導體裝置。半導體裝置包括：一第一閘極結構，與多個第一條通道構件嚙合；一第二閘極結構，與多個第二條通道構件嚙合；一第一背側介電特徵部件，設置於第一閘極結構正下方；以及一第二背側介電特徵部件，設置於第二閘極結構正下方。多個第一通道構件的數量大於多個第二組通道構件的數量。在一些實施例中，第一閘極結構的高度大於第二閘極結構的高度。在一些實施例中，第一背側介電特徵部件的厚度小於第二背側介電特徵部件的厚度。在一些實施例中，半導體裝置也包括：多個第一內間隔特徵部件，與第一閘極結構相接；以及多個第二內間隔特徵部件，與第二閘極結構相接。第二內間隔特徵部件的底部延伸至第二背側介電特徵部件內。
以上概略說明瞭本發明數個實施例的特徵部件，使所屬技術領域中具有通常知識者對於本揭露的型態可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到可輕易利用本揭露作為其它製程或結構的變更或設計基礎，以進行相同於此處所述實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構並未脫離本揭露之精神及保護範圍，且可於不脫離本揭露之精神及範圍，當可作更動、替代與潤飾。
100:方法 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 146, 148:步驟區塊 200:工作部件 202:基底 204:堆疊 206:犧牲層 206T:頂層犧牲層 208:通道層/通道構件 208E:端部 210:鰭形結構 210B:基體部 210T:頂層部 212:鰭狀溝槽 214:硬式罩幕層 216:(淺溝槽)隔離特徵部件 218:介電鰭部/混合式鰭部 220:包覆層 222:第一介電層 224:第二介電層224 226:高k值介電層 240:虛置閘極堆疊 242:虛置介電層 244:虛置電極 246:閘極頂部硬式罩幕 248:氮化矽罩幕層 250:氧化矽罩幕層 252:閘極間隙壁 254:源極/汲極凹槽 254D:較深的源極/汲極凹槽 256, 302:罩幕層 258:內間隔特徵部件 260:源極/汲極特徵部件 262:未摻雜的磊晶層 264:重摻雜的磊晶層 266:閘極溝槽 267:空孔 270:接觸蝕刻停止層(CESL) 272:層間介電(ILD)層 274:閘極結構/功能閘極結構/金屬閘極結構 276:閘極介電層 278:閘極電極層 280:金屬蓋層 282:自對準蓋(SAC)層 284:閘極切割特徵部件 286:源極/汲極接點 288:閘極接點 290:額外的層間介電(ILD)層 292:金屬接線層 294, 308:承載體 296:前側接合氧化層 298:黏著層 300:溝槽 304:背側介電層 306:接合氧化物層 ΔH, ΔH’:距離 I, II:區域
第1A及1B圖繪示出根據本揭露的一或多個型態，用於製造半導體裝置的示例方法流程圖。 第2圖繪示出根據本揭露的一或多個型態的半導體裝置立體示意圖。 第3A、3B、3C、3D、4A、4B、4C、4D、5A、5B、5C、5D、6A、6B、6C、6D、7A、7B、7C、7D、8A、8B、8C、8D、9A、9B、9C、9D、10A、10B、10C、10D、11A、11B、11C、11D、12A、12B、12C、12D、13A、13B、13C、13D、14A、14B、14C、14D 、15A、15B、15C、15D、16A、16B、16C、16D、17A、17B、17C、17D、18A、18B、18C、18D、19A、19B、19C、19D、20A、20B、20C、20D、21A、21B、21C、21D、21E、21F、22A、22B、22C、22D、23A、23B、23C、23D、24A、24B、24C、24D、25A、25B、25C、25D、25E、25F、26A、26B、26C、26D、26E、26F、27A、27B、27C、27D、28A、28B、28C及28D圖繪示出根據本揭露的一或多個型態在第1A及1B圖的方法的各個製造階段期間，第2圖的半導體裝置於不同製造階段的片段式剖面示意圖。
無
132,134,136,138,140,142,144,146,148:步驟區塊

Claims (15)

  1. 一種半導體裝置之製造方法，包括：形成由一第一類型及一第二類型磊晶層構成的一堆疊於一半導體基底的一前側，該等第一類型及第二類型磊晶層具有不同的材料組成，該等第一類型及第二類型磊晶層在一垂直方向上交替設置；圖案化該堆疊，以形成一鰭形結構；沉積一介電層於該鰭形結構的複數個側壁上；凹陷該介電層，以露出該鰭形結構的一頂層部，凹陷的該介電層的一上表面位於該堆疊的一下表面之上；形成一功能閘極結構於該鰭形結構的該頂層部上；從該半導體基底的一背側蝕刻該半導體基底，以形成一溝槽於該介電層之間，該溝槽露出該堆疊的該下表面；以及經由該溝槽來蝕刻至少一最底層的第一類型磊晶層及一最底層的第二類型磊晶層。
  2. 如請求項1之半導體裝置之製造方法，其中該最底層的第一類型磊晶層位於該最底層的第二類型磊晶層之下，而凹陷的該介電層的該上表面位於該最底層的第一類型磊晶層的一上表面之上，且於該最底層的第二類型磊晶層的一上表面之下。
  3. 如請求項1或2之半導體裝置之製造方法，其中該功能閘極結構為一金屬閘極結構，且其中蝕刻至少該最底層的第一類型磊晶層及該最底層的第二類型磊晶層是在形成該功能閘極結構之後進行。
  4. 如請求項1或2之半導體裝置之製造方法，更包括： 在形成該功能閘極結構之前，從該鰭形結構的該頂層部移除該等第一類型磊晶層；其中在形成該功能閘極結構之後，該閘極結構包圍該鰭形結構的該頂層部內的該等第二類型磊晶層。
  5. 如請求項1或2之半導體裝置之製造方法，其中在形成該功能閘極結構之後，該最底層的第二類型磊晶層具有一上表面與該功能閘極結構相接觸，且具有一下表面與該最底層的第一類型磊晶層相接觸。
  6. 如請求項1或2之半導體裝置之製造方法，其中蝕刻至少該最底層的第一類型磊晶層及該最底層的第二類型磊晶層包括：從該溝槽完全去除該最底層的第一類型磊晶層及局部去除該最底層的第二類型磊晶層。
  7. 如請求項1或2之半導體裝置之製造方法，更包括：沉積一介電材料於該溝槽內，其中該最底層的第二類型磊晶層的一部分突出進入該介電材料內。
  8. 一種半導體裝置之製造方法，包括：形成複數個第一通道構件於一基底的一第一區域上，該等第一通道構件為垂直堆疊的；形成複數個第二通道構件於該基底的一第二區域上，該等第二通道構件為垂直堆疊的；形成一隔離特徵部件於該第一及該第二區域中，該隔離特徵部件的一上表面在該第二區域高於在該第一區域，使得在該第二區域中該等第二通道構件的一部分低於該隔離特徵部件的該上表面；形成與該等第一通道構件嚙合的一第一閘極結構，以在該第一區域形成一第 一電晶體；形成與該等第二通道構件嚙合的一第二閘極結構，以在該第二區域形成一第二電晶體；以及從該第二區域移除該等第二通道構件的該部分，使該第一電晶體中的該等第一通道構件的數量大於該第二電晶體中的該等第二通道構件的數量。
  9. 如請求項8之半導體裝置之製造方法，其中形成該隔離特徵部件包括：沉積一介電材料於該等第一及第二通道構件的側壁上；凹陷位於該第一及該第二區域的該介電材料，以露出該等第一及第二通道構件的一頂部；以及進一步凹陷位於該第一區域的該介電材料，以使該等第一通道構件完全位於該介電材料之上。
  10. 如請求項8之半導體裝置之製造方法，更包括：蝕刻位於該第一及該第二區域的該基底，以形成複數個溝槽於該第一及該第二區域中，其中去除該等第二通道構件的該部分，露出位於該第二區域的該等溝槽內的該第二閘極結構，且露出位於該第一區域的該等溝槽內的該第一閘極結構。
  11. 如請求項8、9或10之半導體裝置之製造方法，更包括：形成複數個第一源極/汲極特徵部件，與該等第一通道構件相接；以及形成複數個第二源極/汲極特徵部件，與該等第二通道構件相接，其中該等第二源極/汲極特徵部件的厚度小於該等第一源極/汲極特徵部件的厚度。
  12. 一種半導體裝置，包括：一第一閘極結構，與多個第一條通道構件嚙合； 一第二閘極結構，與多個第二條通道構件嚙合；一第一背側介電特徵部件，設置於該第一閘極結構與該等第一條通道構件正下方；以及一第二背側介電特徵部件，設置於該第二閘極結構與該等第二條通道構件正下方；其中該等第一通道構件的數量大於該等第二組通道構件的數量。
  13. 如請求項12之半導體裝置，其中該第一閘極結構的一高度大於該第二閘極結構的一高度。
  14. 如請求項12或13之半導體裝置，其中該第一背側介電特徵部件的一厚度小於該第二背側介電特徵部件的一厚度。
  15. 如請求項12或13之半導體裝置，更包括：複數個第一內間隔特徵部件，與該第一閘極結構相接；以及複數個第二內間隔特徵部件，與該第二閘極結構相接，其中該等第二內間隔特徵部件的一底部延伸至該第二背側介電特徵部件內。
TW111100314A 2021-01-28 2022-01-05 半導體裝置及其製造方法 TWI818404B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202163142532P 2021-01-28 2021-01-28
US63/142,532 2021-01-28
US17/336,673 2021-06-02
US17/336,673 US11538927B2 (en) 2021-01-28 2021-06-02 Nanostructures and method for manufacturing the same

Publications (2)

Publication Number Publication Date
TW202230463A TW202230463A (zh) 2022-08-01
TWI818404B true TWI818404B (zh) 2023-10-11

Family

ID=81671917

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111100314A TWI818404B (zh) 2021-01-28 2022-01-05 半導體裝置及其製造方法

Country Status (5)

Country Link
US (2) US11538927B2 (zh)
KR (1) KR102626687B1 (zh)
CN (1) CN114551352A (zh)
DE (2) DE102021114489A1 (zh)
TW (1) TWI818404B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230010541A1 (en) * 2021-07-08 2023-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Gate all around device and method of forming the same
CN117476640B (zh) * 2023-10-08 2024-05-17 北京大学 半导体制备方法、半导体结构和芯片

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170009678A (ko) * 2015-07-16 2017-01-25 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US20200058800A1 (en) * 2018-08-14 2020-02-20 Semiconductor Manufacturing International (Beijing) Corporation Semiconductor structure and method for forming same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US10998234B2 (en) * 2019-05-14 2021-05-04 International Business Machines Corporation Nanosheet bottom isolation and source or drain epitaxial growth

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170009678A (ko) * 2015-07-16 2017-01-25 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US20200058800A1 (en) * 2018-08-14 2020-02-20 Semiconductor Manufacturing International (Beijing) Corporation Semiconductor structure and method for forming same

Also Published As

Publication number Publication date
TW202230463A (zh) 2022-08-01
US11538927B2 (en) 2022-12-27
US12094950B2 (en) 2024-09-17
DE102021115012A1 (de) 2022-07-28
US20230114351A1 (en) 2023-04-13
US20220238699A1 (en) 2022-07-28
KR102626687B1 (ko) 2024-01-17
KR20220109283A (ko) 2022-08-04
DE102021114489A1 (de) 2022-07-28
CN114551352A (zh) 2022-05-27

Similar Documents

Publication Publication Date Title
US10749014B2 (en) Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features
CN113380706B (zh) 具有前侧和后侧的半导体结构及其形成方法
KR102647010B1 (ko) 게이트 격리 구조물을 갖는 반도체 디바이스 및 그 형성 방법
US12094950B2 (en) Nanostructures and method for manufacturing the same
TWI793675B (zh) 半導體裝置及其形成方法
TW202205449A (zh) 半導體裝置及其形成方法
TWI783606B (zh) 半導體裝置及其形成方法
TWI835314B (zh) 半導體裝置及其製造方法
US11152475B2 (en) Method for forming source/drain contacts utilizing an inhibitor
TW202205393A (zh) 半導體裝置的製造方法
US20230395686A1 (en) Semiconductor device with gate isolation features and fabrication method of the same
US20230326983A1 (en) Method for forming source/drain contacts utilizing an inhibitor
US20230010541A1 (en) Gate all around device and method of forming the same
TWI843395B (zh) 半導體結構及其形成方法
US20230141523A1 (en) Semiconductor structure with dielectric fin structure and method for manufacturing the same
US20240178302A1 (en) Semiconductor device with protective gate structure and methods of fabrication thereof
US20240113201A1 (en) Multi-gate device inner spacer and methods thereof
TW202431384A (zh) 半導體裝置及其製造方法
TW202418473A (zh) 半導體結構及其製造方法