CN109004925B - 具有后栅极偏置的开关的电路 - Google Patents
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Abstract
本发明涉及具有后栅极偏置的开关的电路,其揭露具有开关的电子电路以及操作电子电路中的开关的方法。第一放大器通过第一路径与天线耦接。第二放大器通过第二路径与该天线耦接。晶体管在一节点与该第一路径耦接。该第一晶体管包括后栅极。后栅极偏置电路与该第一晶体管的该后栅极耦接。该后栅极偏置电路经配置成向该第一晶体管的该后栅极供应偏置电压,从而降低该晶体管的阈值电压。
Description
技术领域
本发明通常涉及电子电路,尤其涉及具有开关的电子电路以及用于操作电子电路中的开关的方法。
背景技术
射频集成电路(Radio-frequency integrated circuit;RFIC)存在于许多类型的装置中,例如移动电话。RFIC通常需要开关来选择并控制天线、发送器电路(例如,功率放大器)与接收器电路(例如,低噪声放大器)之间的连接。通过使用半导体装置(通常为单个场效应晶体管(field-effect transistor;FET)或堆叠的多个FET)在RFIC中可实施开关。这样的开关可能引入插入损耗,其可能影响发送器电路的效率及接收器电路的噪声系数。
需要改进的具有开关的电子电路以及用于操作电子电路中的开关的方法。
发明内容
在本发明的一个实施例中,电子电路包括通过第一路径与天线耦接的第一放大器,通过第二路径与该天线耦接的第二放大器,以及在一节点与该第一路径耦接的晶体管。后栅极偏置电路与该晶体管的后栅极耦接。该后栅极偏置电路经配置成向该晶体管的该后栅极供应偏置电压,从而降低该晶体管的阈值电压。
在本发明的一个实施例中,一种操作电子电路的方法包括向晶体管的后栅极施加偏置电压,该晶体管在第一节点与位于天线与第一放大器之间的第一路径耦接。响应施加该偏置电压,通过第二路径自第二放大器向该天线发送信号。向该晶体管的该后栅极供应的该偏置电压降低该晶体管的阈值电压。
附图说明
包含于并构成本说明书的一部分的附图说明本发明的各种实施例,并与上面所作的概括说明以及下面所作的实施例的详细说明一起用以解释本发明的实施例。
图1显示依据本发明的实施例的电子电路的示意图。
图2显示依据本发明的实施例用以生成后栅极偏置电压的后栅极偏置电路的示意图。
图3显示依据本发明的实施例用以生成后栅极偏置电压的后栅极偏置电路的示意图。
图4显示具有后栅极的场效应晶体管的剖视图,该场效应晶体管可用于构建图1的RF开关的场效应晶体管。
具体实施方式
请参照图1并依据本发明的实施例,电子电路10包括天线12、功率放大器(poweramplifier;PA)14、将PA 14与天线12连接的发送器(TX)支路或路径16、低噪声放大器(low-noise amplifier;LNA)18、以及将LNA 18与天线12连接的接收器(RX)支路或路径20。天线12、TX路径16及RX路径20共同连接于节点21。电子电路10还包括场效应晶体管22,其在节点25与RX路径20耦接并充当电子电路10中的开关。电子电路10还包括场效应晶体管24,其具有在节点27与RX路径20耦接的漏极以及与地耦接的源极。场效应晶体管24提供功率降低功能,以于LNA 18关闭时提供发送信号的额外衰减。
电子电路10可为例如移动电话或其它类型移动装置中的射频集成电路(RFIC)的组件。PA 14经配置成以高信噪比自该RFIC的其它电路接受较强的可预测信号并提高其功率以通过TX路径16发送至天线12。LNA 18经配置成通过RX路径20自天线12接收不可预测的低功率、低电压信号以及所带来的相关随机噪声并提高其功率至可用的水平。
场效应晶体管22包括后栅极36,其可供电性偏置以调节场效应晶体管22的阈值电压。类似地,场效应晶体管24包括后栅极38,其可供电性偏置以调节场效应晶体管24的阈值电压。阈值电压(Vt)表示为将场效应晶体管22、24置于开启状态而在场效应晶体管22、24的栅极电极所需的最小施加电压。通过向场效应晶体管22、24的各后栅极36、38施加后栅极偏置电压,可降低场效应晶体管22、24的相应阈值电压(也就是,降低至较小的值)。
在一个实施例中,场效应晶体管22、24可为超低阈值电压场效应晶体管(超低Vt(super low Vt;SLVT))。除其它参数外,通过使用栅极电极的功函数金属、晶体管类型(也就是,n型或p型)以及/或者后栅极36、38的半导体材料的导电类型可选择场效应晶体管22、24的阈值电压。在一个实施例中,场效应晶体管22、24可都包括n型场效应晶体管。
电子电路10还包括位于节点25与天线12之间的RX路径20中的电容器28,位于场效应晶体管22与节点25之间的电容器30,以及位于节点25与节点27之间的RX路径20中的匹配网络(matching network;MN)32。匹配网络32可包括一个或多个反应元件,例如一个或多个电感器及/或一个或多个电容器,其经配置成通过阻抗匹配来优化从天线12至LNA 18的信号传递。变压器33及匹配电容器34位于天线12与PA 14的输入之间的TX路径16中。
场效应晶体管22具有接地的漏极,以及通过电容器30与节点25连接的源极。电容器28、30可经尺寸设定以使电容器30的电容(C2)显着大于电容器28的电容(C1)。电容器28、30的电容比可经选择成至少部分衰减所发送的RF信号的任意高摆幅值,从而保护LNA 18的输入。场效应晶体管22的漏极上的电压是其导通电阻相对电容器30的阻抗的函数。场效应晶体管22的导通电阻的降低值(通过向其后栅极36施加偏置电压可有助于这种情况)可确保将场效应晶体管22的漏极上的电压摆幅保持于低于其可靠性等级。场效应晶体管24的导通电阻的降低值可改进衰减,从而可限制C2与C1的比不会过高。
后栅极偏置电路(例如后栅极偏置电路40(图2)或后栅极偏置电路46(图3))可充当直接至场效应晶体管22、24的各后栅极36、38的后栅极偏置电压源或供应(VBBN)。为此,后栅极偏置电路40或后栅极偏置电路46可与场效应晶体管22的后栅极36耦接且还可与场效应晶体管24的后栅极38耦接。后栅极偏置电路40、46分别经配置成向场效应晶体管22、24的后栅极36、38供应偏置电压(VH)或者向场效应晶体管22、24的后栅极36、38供应低电压(例如,地)。向场效应晶体管22、24的后栅极36、38同时施加等于VH的VBBN(其发生于TX模式操作期间)允许使用以小尺寸为特征的场效应晶体管22、24,其可改进RX模式期间,场效应晶体管22、24对噪声系数的影响。VH的值可依赖于该RFIC的高逻辑要求,且VH可由电池供应。
当电子电路10操作于接收(RX)模式时,LNA 18与天线12连接以自天线12接收信号,且TX路径16上的输入阻抗高,用以隔离PA 14。在RX模式期间,该高阻抗防止RF信号沿TX路径16传播。在RX模式下,LNA 18开启,PA 14关闭且其输出为浮置,场效应晶体管22、24关闭,VBBN被设为低电压(例如,0伏或地)。因为场效应晶体管22、24各自的后栅极36、38接地且未偏置,所以场效应晶体管22、24的阈值电压未被降低,这在电子电路10操作于RX模式时会改进该场效应晶体管的隔离。
当电子电路10操作于发送(TX)模式时,PA 14与天线12连接,且RX路径20呈现高输入阻抗,以阻断RX路径20并隔离LNA 18。在TX模式下,PA 14开启,LNA 18关闭,场效应晶体管22、24开启,且等于VH的VBBN被施加于场效应晶体管22、24的后栅极36、38。在场效应晶体管22、24的开启状态期间的后栅极偏置导致场效应晶体管22、24的阈值电压降低,从而与关闭状态相比,场效应晶体管22、24的导通电阻及有效开关尺寸降低。当电子电路10操作于TX模式时,该有效开关尺寸的缩小降低场效应晶体管22、24的漏极寄生电容。
当电子电路10操作于TX模式时,场效应晶体管22的漏极寄生电容可因后栅极36可偏置而降低。因此,可降低在节点25的总电容,其为节点27处的等效电容器。也可因在TX模式下后栅极38可偏置而降低场效应晶体管24的漏极寄生电容。因此,在节点27的总电容得以降低。在节点25及27的降低电容可减少对噪声系数的影响。
请参照图2并依据本发明的实施例,可自与充当电子电路10的输出的节点43并行耦接的场效应晶体管42及场效应晶体管44构建后栅极偏置电路40。节点43与场效应晶体管22的后栅极36(图1)及场效应晶体管24的后栅极38(图1)连接。场效应晶体管42具有与供应电压(VH)的电源供应耦接的源极以及与节点43耦接的漏极。场效应晶体管44具有与地耦接的漏极以及与节点43耦接的源极。共同控制信号(common control signal;CTL)可同时施加于场效应晶体管42、44的栅极,以用于开关目的。
具有互补类型(也就是,p型及n型)的场效应晶体管42、44可为包括漂移区的横向扩散金属氧化物半导体(laterally-diffused metal-oxide-semiconductor;LDMOS)装置或包括厚栅极介电质的输入/输出(I/O)装置。在一个实施例中,场效应晶体管42可为p型场效应晶体管且场效应晶体管44可为n型场效应晶体管。场效应晶体管42、44的装置选择可依赖于RFIC可用的供应电压。在一个实施例中,若将I/O装置用作场效应晶体管42、44,则VH的值可小于或等于两(2)伏。向两个场效应晶体管42、44的栅极同时施加同一控制信号(CTL)导致一个打开而另一个关闭,从而向节点43提供二元输出。
在TX模式期间,当场效应晶体管42被施加于其栅极的等于低或逻辑0的控制信号(CTL)开启时,该场效应晶体管便配置成将等于VH的VBBN供应给节点43并随后从节点43供应到达场效应晶体管22、24的后栅极36、38。向场效应晶体管22、24的后栅极36、38施加等于VH的VBBN会降低该场效应晶体管的相应阈值电压。场效应晶体管44通过施加于其栅极的低逻辑控制信号而关闭,从而将节点43与地隔离。
在RX模式期间,当场效应晶体管44被施加于其栅极的等于高或逻辑1的控制信号开启时,该场效应晶体管便配置成将等于地(也就是,0伏)的VBBN供应给节点43并随后从节点43供应到达场效应晶体管22、24的后栅极36、38。场效应晶体管42在该高控制信号施加于其栅极时关闭,从而将节点43与电源供应隔离。
由于场效应晶体管42、44具有互补类型,因此可向两个装置的栅极施加同一控制信号,以在RX模式及TX模式期间提供后栅极偏置电路40的两种不同状态。例如,若场效应晶体管42为p型场效应晶体管且场效应晶体管44为n型场效应晶体管,则在TX模式期间,该控制信号可为低,且在RX模式期间,该控制信号可为高。
请参照图3且依据本发明的实施例,可将后栅极偏置电路46用作VBBN源来替代后栅极偏置电路40(图2)。后栅极偏置电路46可由场效应晶体管50、52、54及电阻器56、58构建,且可包括与场效应晶体管22、24(图1)的后栅极36、38耦接的节点55。后栅极偏置电路46的节点55可通过电阻器56与该RFIC的相关电源供应所供应的电压(VH)耦接。场效应晶体管50具有与节点60连接的源极以及通过电阻器58与节点55连接的漏极。场效应晶体管52具有在节点60与场效应晶体管50的漏极连接的源极以及接地的漏极。
场效应晶体管50、52及电阻器58串联耦接至电性地。场效应晶体管50的栅极与电源供应耦接,该电源供应不同于供应VH的电源供应。例如,该不同的电源供应可供应较低的偏置电压(VL),例如该RFIC用于I/O操作的偏置电压(例如,1.8伏)。场效应晶体管54经配置成开关自该较低电压电源供应供应给位于场效应晶体管50与场效应晶体管52之间的节点60的电压VL。场效应晶体管52的栅极及场效应晶体管54的栅极与用以提供该开关动作的共用控制信号(CTL)耦接。滤波电容器62可与节点60连接,以过滤并降低源自供应VH的该电源供应的噪声。
后栅极偏置电路46可替代后栅极偏置电路40,例如,若VH的值为约3伏且LDMOS装置不可用作场效应晶体管50、52时。场效应晶体管52与场效应晶体管54具有互补类型,且在一个实施例中,场效应晶体管54可为p型场效应晶体管而场效应晶体管54可为n型场效应晶体管。场效应晶体管50具有与场效应晶体管52相同的类型(也就是,p型或n型)。电阻器56、58的尺寸设定成使电阻器56的电阻(R1)显着高于电阻器58的电阻(R2)。在一个实施例中,电阻器56的电阻(R1)可为50kΩ,而电阻器58的电阻(R2)可为1kΩ。
在TX模式期间,施加于场效应晶体管52及场效应晶体管54的栅极的控制信号(CTL)为低或逻辑0。场效应晶体管54通过该控制信号开启,因此,该较低电源供应电压(例如,VL=1.8伏)被供应至节点60。场效应晶体管52及54关闭,从而将节点60与地隔离。结果是后栅极偏置电路46在节点55供应等于VH的VBBN,在TX模式期间,将VBBN自节点55供应给场效应晶体管22、24的后栅极36、38。向场效应晶体管22、24的后栅极36、38施加等于VH的VBBN降低该场效应晶体管的相应阈值电压。
在RX模式期间,施加于场效应晶体管52及场效应晶体管54的栅极的控制信号(CTL)为高或逻辑1。场效应晶体管54通过该控制信号关闭,因此,自节点60阻断该较低电源供应电压(例如,VL=1.8伏)。场效应晶体管50及52开启,从而将节点60与地连接。因此,后栅极偏置电路46表现类似电阻式分压器(resistive divider),因为两个场效应晶体管50、52都开启。在节点55的VBBN的值等于输入电压VH乘以电阻器58的电阻R2除以电阻器56的电阻R1与电阻器58的电阻R2之和的比。因为电阻器56的电阻R1显着大于电阻器58的电阻R2,因此在RX模式期间,VBBN有效等于零(0)伏。
请参照图4,其中相同的附图标记表示图1中类似的特征,显示场效应晶体管100,可将其用作场效应晶体管22、24的装置结构。可在前端工艺(front-end-of-line;FEOL)制程期间通过互补金属氧化物半导体(CMOS)制程利用绝缘体上半导体(semiconductor-on-insulator;SOI)衬底制造场效应晶体管100。该SOI衬底包括装置层102、由硅的氧化物(例如,SiO2)组成的埋置氧化物(burield oxide;BOX)层104形式的埋置介电层,以及操作晶圆106。装置层102通过中间BOX层104与操作晶圆106隔开且远薄于操作晶圆106。装置层102及操作晶圆106可由单晶半导体材料组成,例如单晶硅。装置层102通过BOX层104与操作晶圆106电性隔离。在一个实施例中,该SOI衬底可为极薄绝缘体上半导体(extremely thinsemiconductor-on-insulator;ETSOI)衬底且可被用以通过CMOS FEOL制程制造场效应晶体管22、24作为全耗尽SOI装置(fully-depleted SOI;FDSOI)。
场效应晶体管100包括栅极介电质108以及通过栅极介电质108与装置层102隔开的栅极电极110。栅极电极110可由导体组成,例如掺杂多晶硅或一种或多种金属,且栅极介电质108可由介电或绝缘材料组成。在栅极电极110的垂直侧壁可设置不导电间隙壁112。
场效应晶体管100包括抬升式源/漏区114、116,其设置于栅极电极110的相对侧上并通过不导电间隙壁112与栅极电极110隔开。本文中所使用的术语“源/漏区”是指可充当场效应晶体管100的源极或漏极的半导体材料掺杂区。源/漏区114、116的半导体材料可包括有效赋予n型导电性的选自周期表的第V族的n型掺杂物(例如,磷(P)或砷(As))。或者,源/漏区114、116的半导体材料可包括有效赋予p型导电性的选自周期表的第III族的p型掺杂物(例如,硼(B))。
位于源/漏区114、116之间并垂直位于栅极电极110下方的装置层102的部分构成晶体管本体118,通过该晶体管本体118,切换栅控电流流过沟道。形成浅沟槽隔离122,其结合BOX层104限制晶体管本体118。场效应晶体管100还包括位于操作晶圆106中的后栅极120,其与栅极电极110对齐并通过BOX层104与晶体管本体118隔开。晶体管本体118垂直设置于后栅极120与栅极电极110之间。高掺杂接触119提供与后栅极120的连接。后栅极120的半导体材料可经掺杂以具有与源/漏区114、116的半导体材料相同的导电类型(也就是,极性),或者,后栅极120的半导体材料可经掺杂以具有与源/漏区114、116的半导体材料相反的导电类型(也就是,极性)。除其它参数以外,通过向后栅极120施加偏置电位(例如,VBBN)可调节场效应晶体管100的阈值电压。
当被超过阈值电压的给定电压偏置时,栅极电极110向晶体管本体118施加电场,以将场效应晶体管100在开状态(其中,该场效应晶体管的沟道变为导电)与关状态之间切换。在该开状态,电荷载流子自充当场效应晶体管100的源极的源/漏区114、116的其中之一向充当场效应晶体管100的漏极的的源/漏区114、116的另一个穿过晶体管本体118在沟道中流动。在该关状态,可将场效应晶体管100的晶体管本体118视为全耗尽,因为在晶体管本体118的整个高度上基本没有自由电荷载流子。在场效应晶体管100具有FDSOI装置结构的实施例中,此耗尽层在装置层102的整个厚度上的晶体管本体118中垂直延伸。
在一个实施例中,场效应晶体管22、24可为被实施为具有n型后栅极120的n型场效应晶体管的超低阈值电压场效应晶体管。
后栅极偏置电路40的场效应晶体管42、44及后栅极偏置电路46的场效应晶体管50、52、54可具有与场效应晶体管100类似的构造,除了略去后栅极120以外。
如上所述的方法可用于集成电路芯片的制造中。制造者可以原始晶圆形式(也就是,作为具有多个未封装芯片的单个晶圆)、作为裸芯片,或者以封装形式分配所得的集成电路芯片。在后一种情况中,该芯片设于单芯片封装中(例如塑料承载件,其具有附着至母板或其它更高层次承载件的引脚)或者多芯片封装中(例如陶瓷承载件,其具有单面或双面互连或嵌埋互连)。在任何情况下,接着将该芯片与其它芯片、分立电路元件和/或其它信号处理装置集成,作为(a)中间产品例如母板的部分,或者作为(b)最终产品的部分。该最终产品可为包括集成电路芯片的任意产品,涉及范围从玩具及其它低端应用直至具有显示器、键盘或其它输入装置以及中央处理器的先进电脑产品。
与另一个元件“连接”或“耦接”的特征可与该另一个元件直接连接或耦接,或者可存在一个或多个中间元件。如果不存在中间元件,则特征可与另一个元件“直接连接”或“直接耦接”。如存在至少一个中间元件,则特征可与另一个元件“非直接连接”或“非直接耦接”。
对本发明的各种实施例所作的说明是出于说明目的,而非意图详尽无遗或限于所揭露的实施例。许多修改及变更对于本领域的普通技术人员将显而易见,而不背离所述实施例的范围及精神。本文中所使用的术语经选择以最佳解释实施例的原理、实际应用或在市场已知技术上的技术改进,或者使本领域的普通技术人员能够理解本文中所揭露的实施例。
Claims (18)
1.一种用于天线的电子电路,该电子电路包括:
第一放大器,通过第一路径与该天线耦接;
第二放大器,通过第二路径与该天线耦接;
第一晶体管,在第一节点与该第一路径耦接,该第一晶体管具有后栅极;以及
后栅极偏置电路,在第二节点与该第一晶体管的该后栅极耦接,该后栅极偏置电路经配置成向该第一晶体管的该后栅极供应偏置电压,从而降低该第一晶体管的阈值电压,其中,该后栅极偏置电路包括:将该第二节点与经配置成供应该偏置电压的第一电源供应耦接的第一电阻器,以及与地耦接的第二电阻器。
2.如权利要求1所述的电子电路,还包括:
衬底,包括装置层、操作晶圆、以及设置于该装置层与该操作晶圆之间的埋置介电层,
其中,该第一晶体管的该后栅极位于该操作晶圆中,该第一晶体管包括栅极电极、源极、漏极、以及位于该源极与该漏极之间的该装置层中的本体,且该埋置介电层垂直设置于该第一晶体管的该本体与该第一晶体管的该后栅极之间。
3.如权利要求1所述的电子电路,还包括:
第三晶体管,在第三节点与该第一路径耦接,该第三晶体管具有后栅极,
其中,该后栅极偏置电路的该第二节点还与该第三晶体管的该后栅极耦接,且该后栅极偏置电路经配置成向该第三晶体管的该后栅极供应该偏置电压,从而降低该第三晶体管的阈值电压。
4.如权利要求3所述的电子电路,其中,该后栅极偏置电路经配置成向该第一晶体管的该后栅极及该第三晶体管的该后栅极同时供应该偏置电压。
5.如权利要求3所述的电子电路,其中,该第一晶体管具有与地连接的漏极及与该第一节点连接的源极,且还包括:
第一电容器,位于该第一晶体管的该源极与该第一节点之间。
6.如权利要求5所述的电子电路,其中,该第三晶体管具有与该第三节点连接的漏极以及与地连接的源极。
7.如权利要求5所述的电子电路,还包括:
第二电容器,位于该第一节点与该天线之间的该第一路径中。
8.如权利要求1所述的电子电路,其中,该第一放大器及该第二放大器经配置成操作于将第一信号自该第一放大器传输至该天线的发送模式以及将第二信号自该天线传输至该第一放大器的接收模式,且在该发送模式中,该后栅极偏置电路向该第一晶体管的该后栅极供应该偏置电压。
9.如权利要求1所述的电子电路,其中,该后栅极偏置电路还包括第二晶体管及第三晶体管,该第二晶体管具有通过该第二电阻器与该第二节点耦接的漏极以及源极,且该第三晶体管具有在第三节点与该第二晶体管的该源极耦接的漏极以及与地耦接的源极。
10.如权利要求9所述的电子电路,其中,该后栅极偏置电路还包括:第四晶体管,将该第三节点与第二电源供应耦接,该第二电源供应经配置成向该第二节点选择性供应小于该偏置电压的低电压。
11.如权利要求1所述的电子电路,其中,该第一路径为接收路径,且该第一放大器为低噪声放大器。
12.如权利要求1所述的电子电路,其中,该第二路径为发送路径,且该第二放大器为功率放大器。
13.如权利要求1所述的电子电路,其中,该第一晶体管是通过使用互补金属氧化物半导体制程制造的全耗尽绝缘体上硅装置结构。
14.如权利要求1所述的电子电路,其中,该第一晶体管为n型场效应晶体管。
15.如权利要求1所述的电子电路,其中,该第一晶体管为超低电压场效应晶体管。
16.一种操作电子电路的方法,该方法包括:
向第一晶体管的后栅极施加偏置电压,该第一晶体管在第一节点与位于天线与第一放大器之间的第一路径耦接;以及
响应施加该偏置电压,通过第二路径自第二放大器向该天线发送第一信号,
其中,该偏置电压降低该第一晶体管的阈值电压,且向该第一晶体管的该后栅极施加该偏置电压还包括:
通过第一电阻器自电源向与该第一晶体管的该后栅极耦接的第二节点供应该偏置电压;以及
切换第二晶体管以将与该第二节点连接的第二电阻器与地隔离。
17.如权利要求16所述的方法,还包括:
通过该第一路径自该天线接收第二信号于该第一放大器,
其中,响应接收该第二信号,自该后栅极移除该偏置电压。
18.如权利要求16所述的方法,其中,第三晶体管在第三节点与位于该天线与该第一放大器之间的该第一路径耦接,且还包括:
响应自该第二放大器发送该第一信号,向该第三晶体管的后栅极施加该偏置电压。
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