TWI681532B - 具有背閘極偏壓之開關的電路 - Google Patents

具有背閘極偏壓之開關的電路 Download PDF

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TWI681532B
TWI681532B TW107113835A TW107113835A TWI681532B TW I681532 B TWI681532 B TW I681532B TW 107113835 A TW107113835 A TW 107113835A TW 107113835 A TW107113835 A TW 107113835A TW I681532 B TWI681532 B TW I681532B
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transistor
back gate
node
field effect
coupled
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阿貝拉特 貝拉爾
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美商格芯(美國)集成電路科技有限公司
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Abstract

本發明揭露具有開關的電子電路以及操作電子電路中的開關的方法。第一放大器通過第一路徑與天線耦接。第二放大器通過第二路徑與該天線耦接。電晶體在一節點與該第一路徑耦接。該第一電晶體包括背閘極。背閘極偏壓電路與該第一電晶體的該背閘極耦接。該背閘極偏壓電路經配置成向該第一電晶體的該背閘極供應偏壓電壓,從而降低該電晶體的閾值電壓。

Description

具有背閘極偏壓之開關的電路
本發明大致係關於電子電路,尤其關於具有開關的電子電路以及用於操作電子電路中的開關的方法。
射頻積體電路(Radio-frequency integrated circuit;RFIC)存在於許多類型的裝置中,例如行動電話。RFIC通常需要開關來選擇並控制天線、發送器電路(例如,功率放大器)與接收器電路(例如,低噪聲放大器)之間的連接。通過使用半導體裝置(通常為單個場效電晶體(field-effect transistor;FET)或堆疊的多個FET)在RFIC中可實施開關。這樣的開關可能引入插入損耗,其可能影響發送器電路的效率及接收器電路的噪聲係數。
需要改進的具有開關的電子電路以及用於操作電子電路中的開關的方法。
在本發明的一個實施例中,電子電路包括通過第一路徑與天線耦接的第一放大器,通過第二路徑與該天線耦接的第二放大器,以及在一節點與該第一路徑耦接 的電晶體。背閘極偏壓電路與該電晶體的背閘極耦接。該背閘極偏壓電路經配置成向該電晶體的該背閘極供應偏壓電壓,從而降低該電晶體的閾值電壓。
在本發明的一個實施例中,一種操作電子電路的方法包括向電晶體的背閘極施加偏壓電壓,該電晶體在第一節點與位於天線與第一放大器之間的第一路徑耦接。響應施加該偏壓電壓,通過第二路徑自第二放大器向該天線發送信號。向該電晶體的該背閘極供應的該偏壓電壓降低該電晶體的閾值電壓。
10‧‧‧電子電路
12‧‧‧天線
14‧‧‧功率放大器、PA
16‧‧‧發送器(TX)支路或路徑、TX路徑
18‧‧‧低噪聲放大器、LNA
20‧‧‧接收器(RX)支路或路徑、RX路徑
21‧‧‧節點
22‧‧‧場效電晶體
24‧‧‧場效電晶體
25‧‧‧節點
27‧‧‧節點
28‧‧‧電容器
30‧‧‧電容器
32‧‧‧匹配網路
33‧‧‧變壓器
34‧‧‧匹配電容器
36‧‧‧背閘極
38‧‧‧背閘極
40‧‧‧背閘極偏壓電路
42‧‧‧場效電晶體
43‧‧‧節點
44‧‧‧場效電晶體
46‧‧‧背閘極偏壓電路
50‧‧‧場效電晶體
52‧‧‧場效電晶體
54‧‧‧場效電晶體
55‧‧‧節點
56‧‧‧電阻器
58‧‧‧電阻器
60‧‧‧節點
62‧‧‧濾波電容器
100‧‧‧場效電晶體
102‧‧‧裝置層
104‧‧‧埋置氧化物層、BOX層
106‧‧‧操作晶圓
108‧‧‧閘極介電質
110‧‧‧閘極電極
112‧‧‧不導電間隔物
114‧‧‧抬升式源/汲區、源/汲區
116‧‧‧抬升式源/汲區、源/汲區
118‧‧‧電晶體本體
119‧‧‧高摻雜接觸
120‧‧‧背閘極
122‧‧‧淺溝槽隔離
包含於並構成本說明書的一部分的附圖說明本發明的各種實施例,並與上面所作的概括說明以及下面所作的實施例的詳細說明一起用以解釋本發明的實施例。
第1圖顯示依據本發明的實施例的電子電路的示意圖。
第2圖顯示依據本發明的實施例用以生成背閘極偏壓電壓的背閘極偏壓電路的示意圖。
第3圖顯示依據本發明的實施例用以生成背閘極偏壓電壓的背閘極偏壓電路的示意圖。
第4圖顯示具有背閘極的場效電晶體的剖視圖,該場效電晶體可用於構建第1圖的RF開關的場效電晶體。
請參照第1圖並依據本發明的實施例,電子 電路10包括天線12、功率放大器(power amplifier;PA)14、將PA 14與天線12連接的發送器(TX)支路或路徑16、低噪聲放大器(low-noise amplifier;LNA)18、以及將LNA 18與天線12連接的接收器(RX)支路或路徑20。天線12、TX路徑16及RX路徑20共同連接於節點21。電子電路10進一步包括場效電晶體22,其在節點25與RX路徑20耦接並充當電子電路10中的開關。電子電路10進一步包括場效電晶體24,其具有在節點27與RX路徑20耦接的汲極以及與地耦接的源極。場效電晶體24提供功率降低功能,以於LNA 18關閉時提供發送信號的額外衰減。
電子電路10可為例如移動電話或其它類型移動裝置中的射頻積體電路(RFIC)的組件。PA 14經配置成以高信噪比自該RFIC的其它電路接受較強的可預測信號並提高其功率以通過TX路徑16發送至天線12。LNA 18經配置成通過RX路徑20自天線12接收不可預測的低功率、低電壓信號以及所帶來的相關隨機噪聲並提高其功率至可用的水平。
場效電晶體22包括背閘極36,其可供電性偏壓以調節場效電晶體22的閾值電壓。類似地,場效電晶體24包括背閘極38,其可供電性偏壓以調節場效電晶體24的閾值電壓。閾值電壓(Vt)表示為將場效電晶體22、24置於開啟狀態而在場效電晶體22、24的閘極電極所需的最小施加電壓。通過向場效電晶體22、24的各背閘極36、38施加背閘極偏壓電壓,可降低場效電晶體22、24 的相應閾值電壓(也就是,降低至較小的值)。
在一個實施例中,場效電晶體22、24可為超低閾值電壓場效電晶體(超低Vt(super low Vt;SLVT))。除其它參數外,通過使用閘極電極的功函數金屬、電晶體類型(也就是,n型或p型)以及/或者背閘極36、38的半導體材料的導電類型可選擇場效電晶體22、24的閾值電壓。在一個實施例中,場效電晶體22、24可都包括n型場效電晶體。
電子電路10進一步包括位於節點25與天線12之間的RX路徑20中的電容器28,位於場效電晶體22與節點25之間的電容器30,以及位於節點25與節點27之間的RX路徑20中的匹配網路(matching network;MN)32。匹配網路32可包括一個或多個反應元件,例如一個或多個電感器及/或一個或多個電容器,其經配置成通過阻抗匹配來優化從天線12至LNA 18的信號傳遞。變壓器33及匹配電容器34位於天線12與PA 14的輸入之間的TX路徑16中。
場效電晶體22具有接地的汲極,以及通過電容器30與節點25連接的源極。電容器28、30可經尺寸設定以使電容器30的電容(C2)顯著大於電容器28的電容(C1)。電容器28、30的電容比可經選擇成至少部分衰減所發送的RF信號的任意高擺幅值,從而保護LNA 18的輸入。場效電晶體22的汲極上的電壓是其導通電阻相對電容器30的阻抗的函數。場效電晶體22的導通電阻的降低值 (通過向其背閘極36施加偏壓電壓可有助於這種情況)可確保將場效電晶體22的汲極上的電壓擺幅保持於低於其可靠性等級。場效電晶體24的導通電阻的降低值可改進衰減,從而可限制C2與C1的比不會過高。
背閘極偏壓電路(例如背閘極偏壓電路40(第2圖)或背閘極偏壓電路46(第3圖))可充當直接至場效電晶體22、24的各背閘極36、38的背閘極偏壓電壓源或供應(VBBN)。為此,背閘極偏壓電路40或背閘極偏壓電路46可與場效電晶體22的背閘極36耦接且還可與場效電晶體24的背閘極38耦接。背閘極偏壓電路40、46分別經配置成向場效電晶體22、24的背閘極36、38供應偏壓電壓(VH)或者向場效電晶體22、24的背閘極36、38供應低電壓(例如,地)。向場效電晶體22、24的背閘極36、38同時施加等於VH的VBBN(其發生於TX模式操作期間)允許使用以小尺寸為特徵的場效電晶體22、24,其可改進RX模式期間,場效電晶體22、24對噪聲係數的影響。VH的值可依賴於該RFIC的高邏輯要求,且VH可由電池供應。
當電子電路10操作於接收(RX)模式時,LNA 18與天線12連接以自天線12接收信號,且TX路徑16上的輸入阻抗高,用以隔離PA 14。在RX模式期間,該高阻抗防止RF信號沿TX路徑16傳播。在RX模式下,LNA 18開啟,PA 14關閉且其輸出為浮置,場效電晶體22、24關閉,VBBN被設為低電壓(例如,0伏或地)。因為場 效電晶體22、24各自的背閘極36、38接地且未偏壓,所以場效電晶體22、24的閾值電壓未被降低,這在電子電路10操作於RX模式時會改進該場效電晶體的隔離。
當電子電路10操作於發送(TX)模式時,PA 14與天線12連接,且RX路徑20呈現高輸入阻抗,以阻斷RX路徑20並隔離LNA 18。在TX模式下,PA 14開啟,LNA 18關閉,場效電晶體22、24開啟,且等於VH的VBBN被施加於場效電晶體22、24的背閘極36、38。在場效電晶體22、24的開啟狀態期間的背閘極偏壓導致場效電晶體22、24的閾值電壓降低,從而與關閉狀態相比,場效電晶體22、24的導通電阻及有效開關尺寸降低。當電子電路10操作于TX模式時,該有效開關尺寸的縮小降低場效電晶體22、24的汲極寄生電容。
當電子電路10操作于TX模式時,場效電晶體22的汲極寄生電容可因背閘極36可偏壓而降低。因此,可降低在節點25的總電容,其為節點27處的等效電容器。也可因在TX模式下背閘極38可偏壓而降低場效電晶體24的汲極寄生電容。因此,在節點27的總電容得以降低。在節點25及27的降低電容可減少對噪聲係數的影響。
請參照第2圖並依據本發明的實施例,可自與充當電子電路10的輸出的節點43並行耦接的場效電晶體42及場效電晶體44構建背閘極偏壓電路40。節點43與場效電晶體22的背閘極36(第1圖)及場效電晶體24的背閘極38(第1圖)連接。場效電晶體42具有與供應 電壓(VH)的電源供應耦接的源極以及與節點43耦接的汲極。場效電晶體44具有與地耦接的汲極以及與節點43耦接的源極。共同控制信號(common control signal;CTL)可同時施加於場效電晶體42、44的閘極,以用於開關目的。
具有互補類型(也就是,p型及n型)的場效電晶體42、44可為包括漂移區的橫向擴散金屬氧化物半導體(laterally-diffused metal-oxide-semiconductor;LDMOS)裝置或包括厚閘極介電質的輸入/輸出(I/O)裝置。在一個實施例中,場效電晶體42可為p型場效電晶體且場效電晶體44可為n型場效電晶體。場效電晶體42、44的裝置選擇可依賴於RFIC可用的供應電壓。在一個實施例中,若將I/O裝置用作場效電晶體42、44,則VH的值可小於或等於兩(2)伏。向兩個場效電晶體42、44的閘極同時施加同一控制信號(CTL)導致一個打開而另一個關閉,從而向節點43提供二元輸出。
在TX模式期間,當場效電晶體42被施加於其閘極的等於低或邏輯0的控制信號(CTL)開啟時,該場效電晶體便配置成將等於VH的VBBN供應給節點43並隨後從節點43供應到達場效電晶體22、24的背閘極36、38。向場效電晶體22、24的背閘極36、38施加等於VH的VBBN會降低該場效電晶體的相應閾值電壓。場效電晶體44通過施加於其閘極的低邏輯控制信號而關閉,從而將節點43與地隔離。
在RX模式期間,當場效電晶體44被施加於其閘極的等於高或邏輯1的控制信號開啟時,該場效電晶體便配置成將等於地(也就是,0伏)的VBBN供應給節點43並隨後從節點43供應到達場效電晶體22、24的背閘極36、38。場效電晶體42在該高控制信號施加于其閘極時關閉,從而將節點43與電源供應隔離。
由於場效電晶體42、44具有互補類型,因此可向兩個裝置的閘極施加同一控制信號,以在RX模式及TX模式期間提供背閘極偏壓電路40的兩種不同狀態。例如,若場效電晶體42為p型場效電晶體且場效電晶體44為n型場效電晶體,則在TX模式期間,該控制信號可為低,且在RX模式期間,該控制信號可為高。
請參照第3圖且依據本發明的實施例,可將背閘極偏壓電路46用作VBBN源來替代背閘極偏壓電路40(第2圖)。背閘極偏壓電路46可由場效電晶體50、52、54及電阻器56、58構建,且可包括與場效電晶體22、24(第1圖)的背閘極36、38耦接的節點55。背閘極偏壓電路46的節點55可通過電阻器56與該RFIC的相關電源供應所供應的電壓(VH)耦接。場效電晶體50具有與節點60連接的源極以及通過電阻器58與節點55連接的汲極。場效電晶體52具有在節點60與場效電晶體50的汲極連接的源極以及接地的汲極。
場效電晶體50、52及電阻器58串聯耦接至電性地。場效電晶體50的閘極與電源供應耦接,該電源供應不同於供應VH的電源供應。例如,該不同的電源供應可供應較低的偏壓電壓(VL),例如該RFIC用於I/O操作的偏壓電壓(例如,1.8伏)。場效電晶體54經配置成開關自該較低電壓電源供應供應給位於場效電晶體50與場效電晶體52之間的節點60的電壓VL。場效電晶體52的閘極及場效電晶體54的閘極與用以提供該開關動作的共用控制信號(CTL)耦接。濾波電容器62可與節點60連接,以過濾並降低源自供應VH的該電源供應的噪聲。
背閘極偏壓電路46可替代背閘極偏壓電路40,例如,若VH的值為約3伏且LDMOS裝置不可用作場效電晶體50、52時。場效電晶體52與場效電晶體54具有互補類型,且在一個實施例中,場效電晶體54可為p型場效電晶體而場效電晶體54可為n型場效電晶體。場效電晶體50具有與場效電晶體52相同的類型(也就是,p型或n型)。電阻器56、58的尺寸設定成使電阻器56的電阻(R1)顯著高於電阻器58的電阻(R2)。在一個實施例中,電阻器56的電阻(R1)可為50kΩ,而電阻器58的電阻(R2)可為1kΩ。
在TX模式期間,施加於場效電晶體52及場效電晶體54的閘極的控制信號(CTL)為低或邏輯0。場效電晶體54通過該控制信號開啟,因此,該較低電源供應電壓(例如,VL=1.8伏)被供應至節點60。場效電晶體52及54關閉,從而將節點60與地隔離。結果是背閘極偏壓電路46在節點55供應等於VH的VBBN,在TX模式 期間,將VBBN自節點55供應給場效電晶體22、24的背閘極36、38。向場效電晶體22、24的背閘極36、38施加等於VH的VBBN降低該場效電晶體的相應閾值電壓。
在RX模式期間,施加於場效電晶體52及場效電晶體54的閘極的控制信號(CTL)為高或邏輯1。場效電晶體54通過該控制信號關閉,因此,自節點60阻斷該較低電源供應電壓(例如,VL=1.8伏)。場效電晶體50及52開啟,從而將節點60與地連接。因此,背閘極偏壓電路46表現類似電阻式分壓器(resistive divider),因為兩個場效電晶體50、52都開啟。在節點55的VBBN的值等於輸入電壓VH乘以電阻器58的電阻R2除以電阻器56的電阻R1與電阻器58的電阻R2之和的比。因為電阻器56的電阻R1顯著大於電阻器58的電阻R2,因此在RX模式期間,VBBN有效等於零(0)伏。
請參照第4圖,其中相同的附圖標記表示第1圖中類似的特徵,顯示場效電晶體100,可將其用作場效電晶體22、24的裝置結構。可在前端工藝(front-end-of-line;FEOL)製程期間通過互補金屬氧化物半導體(CMOS)製程利用絕緣體上半導體(semiconductor-on-insulator;SOI)基板製造場效電晶體100。該SOI基板包括裝置層102、由矽的氧化物(例如,SiO2)組成的埋置氧化物(burield oxide;BOX)層104形式的埋置介電層,以及操作晶圓106。裝置層102通過中間BOX層104與操作晶圓106隔開且遠薄於操作晶圓106。裝置層102及操作晶圓106可 由單晶半導體材料組成,例如單晶矽。裝置層102通過BOX層104與操作晶圓106電性隔離。在一個實施例中,該SOI基板可為極薄絕緣體上半導體(extremely thin semiconductor-on-insulator;ETSOI)基板且可被用以通過CMOS FEOL製程製造場效電晶體22、24作為全耗盡SOI裝置(fully-depleted SOI;FDSOI)。
場效電晶體100包括閘極介電質108以及通過閘極介電質108與裝置層102隔開的閘極電極110。閘極電極110可由導體組成,例如摻雜多晶矽或一種或多種金屬,且閘極介電質108可由介電或絕緣材料組成。在閘極電極110的垂直側壁可設置不導電間隔物112。
場效電晶體100包括抬升式源/汲區114、116,其設置於閘極電極110的相對側上並通過不導電間隔物112與閘極電極110隔開。本文中所使用的術語“源/汲區”是指可充當場效電晶體100的源極或汲極的半導體材料摻雜區。源/汲區114、116的半導體材料可包括有效賦予n型導電性的選自週期表的第V族的n型摻雜物(例如,磷(P)或砷(As))。或者,源/汲區114、116的半導體材料可包括有效賦予p型導電性的選自週期表的第III族的p型摻雜物(例如,硼(B))。
位於源/汲區114、116之間並垂直位於閘極電極110下方的裝置層102的部分構成電晶體本體118,通過該電晶體本體118,切換閘控電流流過通道。形成淺溝槽隔離122,其結合BOX層104限制電晶體本體118。 場效電晶體100進一步包括位於操作晶圓106中的背閘極120,其與閘極電極110對齊並通過BOX層104與電晶體本體118隔開。電晶體本體118垂直設置於背閘極120與閘極電極110之間。高摻雜接觸119提供與背閘極120的連接。背閘極120的半導體材料可經摻雜以具有與源/汲區114、116的半導體材料相同的導電類型(也就是,極性),或者,背閘極120的半導體材料可經摻雜以具有與源/汲區114、116的半導體材料相反的導電類型(也就是,極性)。除其它參數以外,通過向背閘極120施加偏壓電位(例如,VBBN)可調節場效電晶體100的閾值電壓。
當被超過閾值電壓的給定電壓偏壓時,閘極電極110向電晶體本體118施加電場,以將場效電晶體100在開狀態(其中,該場效電晶體的通道變為導電)與關狀態之間切換。在該開狀態,電荷載流子自充當場效電晶體100的源極的源/汲區114、116的其中之一向充當場效電晶體100的汲極的的源/汲區114、116的另一個穿過電晶體本體118在通道中流動。在該關狀態,可將場效電晶體100的電晶體本體118視為全耗盡,因為在電晶體本體118的整個高度上基本沒有自由電荷載流子。在場效電晶體100具有FDSOI裝置結構的實施例中,此耗盡層在裝置層102的整個厚度上的電晶體本體118中垂直延伸。
在一個實施例中,場效電晶體22、24可為被實施為具有n型背閘極120的n型場效電晶體的超低閾值電壓場效電晶體。
背閘極偏壓電路40的場效電晶體42、44及背閘極偏壓電路46的場效電晶體50、52、54可具有與場效電晶體100類似的構造,除了略去背閘極120以外。
如上所述的方法可用於積體電路晶片的製造中。製造者可以原始晶圓形式(也就是,作為具有多個未封裝晶片的單個晶圓)、作為裸晶片,或者以封裝形式分配所得的積體電路晶片。在後一種情況中,該晶片設于單晶片封裝中(例如塑料承載件,其具有附著至母板或其它更高層次承載件的引腳)或者多晶片封裝中(例如陶瓷承載件,其具有單面或雙面互連或嵌埋互連)。在任何情況下,接著將該晶片與其它晶片、分立電路元件和/或其它信號處理裝置集成,作為(a)中間產品例如母板的部分,或者作為(b)最終產品的部分。該最終產品可為包括積體電路晶片的任意產品,涉及範圍從玩具及其它低端應用直至具有顯示器、鍵盤或其它輸入裝置以及中央處理器的先進電腦產品。
與另一個元件“連接”或“耦接”的特徵可與該另一個元件直接連接或耦接,或者可存在一個或多個中間元件。如果不存在中間元件,則特徵可與另一個元件“直接連接”或“直接耦接”。如存在至少一個中間元件,則特徵可與另一個元件“非直接連接”或“非直接耦接”。
對本發明的各種實施例所作的說明是出於說明目的,而非意圖詳盡無遺或限於所揭露的實施例。許多修改及變更對於本領域的普通技術人員將顯而易見,而不 背離所述實施例的範圍及精神。本文中所使用的術語經選擇以最佳解釋實施例的原理、實際應用或在市場已知技術上的技術改進,或者使本領域的普通技術人員能夠理解本文中所揭露的實施例。
10‧‧‧電子電路
12‧‧‧天線
14‧‧‧功率放大器、PA
16‧‧‧發送器(TX)支路或路徑、TX路徑
18‧‧‧低噪聲放大器、LNA
20‧‧‧接收器(RX)支路或路徑、RX路徑
21‧‧‧節點
22‧‧‧場效電晶體
24‧‧‧場效電晶體
25‧‧‧節點
27‧‧‧節點
28‧‧‧電容器
30‧‧‧電容器
32‧‧‧匹配網路
33‧‧‧變壓器
34‧‧‧匹配電容器
36‧‧‧背閘極
38‧‧‧背閘極

Claims (19)

  1. 一種用於天線的電子電路,該電子電路包括:第一放大器,通過第一路徑與該天線耦接;第二放大器,通過第二路徑與該天線耦接;第一電晶體,在第一節點與該第一路徑耦接,該第一電晶體具有背閘極;以及背閘極偏壓電路,在第二節點與該第一電晶體的該背閘極耦接,該背閘極偏壓電路經配置成向該第一電晶體的該背閘極供應偏壓電壓,從而降低該第一電晶體的閾值電壓,第一電阻器耦接該第二節點與經配置成供應該偏壓電壓的第一電源供應,以及第二電阻器與地耦接。
  2. 如申請專利範圍第1項所述的電子電路,進一步包括:基板,包括裝置層、操作晶圓、以及設置於該裝置層與該操作晶圓之間的埋置介電層,其中,該第一電晶體的該背閘極位於該操作晶圓中,該第一電晶體包括閘極電極、源極、汲極、以及位於該源極與該汲極之間的該裝置層中的本體,且該埋置介電層垂直設置於該第一電晶體的該本體與該第一電晶體的該背閘極之間。
  3. 如申請專利範圍第1項所述的電子電路,進一步包括:第二電晶體,在第三節點與該第一路徑耦接,該第二電晶體具有背閘極,其中,該背閘極偏壓電路的該第二節點與該第二 電晶體的該背閘極進一步耦接,且該背閘極偏壓電路經配置成向該第二電晶體的該背閘極供應該偏壓電壓,從而降低該第二電晶體的閾值電壓。
  4. 如申請專利範圍第3項所述的電子電路,其中,該背閘極偏壓電路經配置成向該第一電晶體的該背閘極及該第二電晶體的該背閘極同時供應該偏壓電壓。
  5. 如申請專利範圍第3項所述的電子電路,其中,該第一電晶體具有與地連接的汲極及與該第一節點連接的源極,且進一步包括:第一電容器,位於該第一電晶體的該源極與該第一節點之間。
  6. 如申請專利範圍第5項所述的電子電路,其中,該第二電晶體具有與該第三節點連接的汲極以及與地連接的源極。
  7. 如申請專利範圍第5項所述的電子電路,進一步包括:第二電容器,位於該第一節點與該天線之間的該第一路徑中。
  8. 如申請專利範圍第1項所述的電子電路,其中,該第一放大器及該第二放大器經配置成操作於將第一信號自該第一放大器傳輸至該天線的發送模式以及將第二信號自該天線傳輸至該第一放大器的接收模式,且在該發送模式中,該背閘極偏壓電路向該第一電晶體的該背閘極供應該偏壓電壓。
  9. 如申請專利範圍第1項所述的電子電路,其中,該背閘 極偏壓電路進一步包括第二電晶體及第三電晶體,該第二電晶體具有通過該第二電阻器與該第二節點耦接的汲極以及源極,且該第三電晶體具有在第三節點與該第二電晶體的該源極耦接的汲極以及與地耦接的源極。
  10. 如申請專利範圍第9項所述的電子電路,其中,該背閘極偏壓電路進一步包括:第四電晶體,將該第三節點與第二電源供應耦接,該第二電源供應經配置成向該第二節點選擇性供應小於該偏壓電壓的低電壓。
  11. 如申請專利範圍第1項所述的電子電路,其中,該第一路徑為接收路徑,且該第一放大器為低噪聲放大器。
  12. 如申請專利範圍第1項所述的電子電路,其中,該第二路徑為發送路徑,且該第二放大器為功率放大器。
  13. 如申請專利範圍第1項所述的電子電路,其中,該第一電晶體是通過使用互補金屬氧化物半導體製程製造的全耗盡絕緣體上矽裝置結構。
  14. 如申請專利範圍第1項所述的電子電路,其中,該第一電晶體為n型場效電晶體。
  15. 如申請專利範圍第1項所述的電子電路,其中,該第一電晶體為超低電壓場效電晶體。
  16. 一種操作電子電路的方法,該方法包括:向第一電晶體的背閘極施加偏壓電壓,該第一電晶體在第一節點與位於天線與第一放大器之間的第一路徑耦接;以及響應施加該偏壓電壓,通過第二路徑自第二放大 器向該天線發送第一信號,其中,該偏壓電壓降低該第一電晶體的閾值電壓。
  17. 如申請專利範圍第16項所述的方法,進一步包括:通過該第一路徑自該天線接收第二信號於該第一放大器,其中,響應接收該第二信號,自該背閘極移除該偏壓電壓。
  18. 如申請專利範圍第16項所述的方法,其中,第二電晶體在第二節點與位於該天線與該第一放大器之間的該第一路徑耦接,且進一步包括:響應自該第二放大器發送該第一信號,向該第二電晶體的背閘極施加該偏壓電壓。
  19. 如申請專利範圍第16項所述的方法,其中,向該第一電晶體的該背閘極施加該偏壓電壓包括:通過第一電阻器自電源向與該第一電晶體的該背閘極耦接的第二節點供應該偏壓電壓;以及切換第二電晶體以將與該第二節點連接的第二電阻器與地隔離。
TW107113835A 2017-06-07 2018-04-24 具有背閘極偏壓之開關的電路 TWI681532B (zh)

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