CN103928335A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103928335A
CN103928335A CN201310014886.0A CN201310014886A CN103928335A CN 103928335 A CN103928335 A CN 103928335A CN 201310014886 A CN201310014886 A CN 201310014886A CN 103928335 A CN103928335 A CN 103928335A
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fin
grid
stacking
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substrate
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CN103928335B (zh
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朱慧珑
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Institute of Microelectronics of CAS
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Abstract

本申请公开了一种半导体器件及其制造方法。一示例器件可以包括：在衬底上形成的鳍；在衬底上形成的与鳍相交的栅堆叠，栅堆叠经由隔离层与衬底隔离；以及在鳍下方的区域中形成的穿通阻挡部，该穿通阻挡部包括位于鳍与栅堆叠相交部分下方的第一部分以及位于第一部分两侧的第二部分，其中穿通阻挡部的第二部分的掺杂浓度低于穿通阻挡部的第一部分的掺杂浓度。

Description

半导体器件及其制造方法
技术领域
本公开涉及半导体领域，更具体地，涉及一种半导体器件及其制造方法。 
背景技术
随着平面型半导体器件的尺寸越来越小，短沟道效应愈加明显。为此，提出了立体型半导体器件如FinFET(鳍式场效应晶体管)。一般而言，FinFET包括在衬底上竖直形成的鳍以及与鳍相交的栅堆叠。另外，衬底上形成有隔离层，以隔离栅堆叠与衬底。因此，鳍的底部被隔离层所包围，从而栅难以有效控制鳍的底部。结果，易于出现源和漏之间经由鳍底部的漏电流。 
通常，可以采用穿通阻挡部(PTS)来减小这种漏电流。但是，这种PTS的引入增大了结泄漏和结电容。 
发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法。 
根据本公开的一个方面，提供了一种制造半导体器件的方法，包括：在衬底上形成鳍状结构；在衬底上形成隔离层，隔离层露出鳍状结构的一部分，鳍状结构的露出部分用作该半导体器件的鳍；进行第一离子注入，以在鳍下方的区域中形成穿通阻挡部；在隔离层上形成与鳍状结构相交的栅堆叠；以及进行第二离子注入，以对穿通阻挡部进行补偿。 
根据本公开的另一方面，提供了一种半导体器件，包括：在衬底上形成的鳍；在衬底上形成的与鳍相交的栅堆叠，栅堆叠经由隔离层 与衬底隔离；以及在鳍下方的区域中形成的穿通阻挡部，该穿通阻挡部包括位于鳍与栅堆叠相交部分下方的第一部分以及位于第一部分两侧的第二部分，其中穿通阻挡部的第二部分的掺杂浓度低于穿通阻挡部的第一部分的掺杂浓度。 
根据本发明的示例性实施例，在鳍的下方形成PTS。通过上述第一离子注入和第二离子注入，PTS中掺杂浓度高的第一部分自对准于沟道区下方，从而可以有效降低源和漏之间的漏电流。另外，PTS中掺杂浓度低的第二部分自对准于源、漏区下方，从而可以降低源、漏与衬底之间的结电容。 
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中： 
图1-12是示出了根据本公开实施例的制造半导体器件流程的示意图。 
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。 
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。 
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件 “上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。 
根据本公开的实施例，提供了一种半导体器件，该半导体器件可以包括衬底、在衬底上形成的鳍以及与鳍相交的栅堆叠。栅堆叠可以通过隔离层与衬底相隔离。 
为防止源漏区之间经由鳍底部的泄漏，该半导体器件可以包括在鳍下方的穿通阻挡部(PTS)。另外，为了在防止泄漏同时降低源/漏区与衬底之间的结电容和结泄漏，PTS可以包括位于沟道区下方的掺杂浓度相对较高的第一部分以及位于源/漏区下方的掺杂浓度相对较低的第二部分。这种PTS例如可以通过本文所述的自对准技术来形成。 
根据本公开的实施例，这种自对准技术可以如下实现。例如，在衬底上形成鳍状结构并形成露出鳍状结构一部分的隔离层(其中，鳍状结构的露出部分可以用作该半导体器件的真正鳍)之后，可以进行第一离子注入，以在鳍下方的区域中形成穿通阻挡部(PTS)。之后，可以在隔离层上形成栅堆叠(例如，包括栅介质层、栅导体层和栅侧墙)。栅堆叠与鳍相交，从而在鳍中限定了沟道区以及源/漏区(具体地，鳍与栅堆叠相交的部分可以成为沟道区，而鳍中位于沟道区两侧的部分可以成为源/漏区)。可以进行第二离子注入。由于栅堆叠的存在，第二离子注入进入到源/漏区下方的区域中，而基本不会进入沟道区下方的区域中。该第二离子注入的掺杂剂类型可以与第一离子注入的掺杂剂类型相反，从而对源/漏区下方的PTS进行补偿(例如，通过降低其掺杂浓度)。于是，PTS包括掺杂浓度相对较高的第一部分(掺杂浓度基本上由第一离子注入决定)以及位于第一部分两侧的第二部分(掺杂浓度基本上由第一离子注入和第二离子注入的效果总和来决定)。由于栅堆叠，第一部分自对准于栅堆叠(或者沟道区)下方，而第二部分自对准于源/漏区下方。 
根据本公开的其他实施例，还可以应用应变源/漏技术。例如，在形成栅堆叠之后，可以栅堆叠为掩模，对鳍状结构进行选择性刻蚀。然后，可以通过外延生长形成一半导体层，用以形成源、漏区。这种源、漏区可以向沟道区施加应力(例如，对于p型器件，施加压应力；而对于n型器件，施加拉应力)，以增强器件性能。 
根据本公开的其他实施例，还可以结合替代栅工艺。例如，上述形成的栅堆叠为牺牲栅堆叠(例如，包括牺牲栅介质层、牺牲栅导体层和栅侧墙)。根据替代栅工艺，在进行源/漏注入之后(或者，在如上所述应用应变源/漏技术的情况下，在生长源/漏区之后)，可以选择性去除牺牲栅导体层和牺牲栅介质层，在栅侧墙内形成栅槽(或孔)。然后，在栅槽(或孔)内形成栅介质层(例如，高K栅介质)和栅导体层(例如，金属栅导体)，从而形成器件的真正栅堆叠。 
本公开可以各种形式呈现，以下将描述其中一些示例。 
如图1所示，提供衬底1000。该衬底1000可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。 
根据本公开的一些示例，可以在衬底1000中形成阱区1000-1。例如，对于p型器件，可以形成n型阱区；而对于n型器件，可以形成p型阱区。例如，n型阱区可以通过在衬底1000中注入n型杂质如P或As来形成，p型阱区可以通过在衬底1000中注入p型杂质如B来形成。如果需要，在注入之后还可以进行退火。本领域技术人员能够想到多种方式来形成n型阱、p型阱，在此不再赘述。 
接下来，可以对衬底1000进行构图，以形成鳍状结构。例如，这可以如下进行。具体地，在衬底1000上按设计形成构图的光刻胶1002。通常，光刻胶1002被构图为一系列平行的等间距线条。然后，如图2所示，以构图的光刻胶1002为掩模，对衬底1000进行刻蚀例如反应离子刻蚀(RIE)，从而形成鳍状结构1004。在此，对衬底1000的刻蚀进行到阱区1000-1中。之后，可以去除光刻胶1002。 
这里需要指出的是，通过刻蚀所形成的(鳍状结构1004之间的)沟槽的形状不一定是图2中所示的规则矩形形状，可以是例如从上到下逐渐变小的锥台形。另外，所形成的鳍状结构的位置和数目不限于图2所示的示例。 
另外，鳍状结构不限于通过直接对衬底进行构图来形成。例如，可以在衬底上外延生长另外的半导体层，对该另外的半导体层进行构 图来形成鳍状结构。如果该另外的半导体层与衬底之间具有足够的刻蚀选择性，则在对鳍状结构进行构图时，可以使构图基本上停止于衬底，从而实现对鳍状结构高度的较精确控制。 
因此，在本公开中，表述“在衬底上形成鳍状结构”包括以任何适当的方式在衬底上形成鳍状结构。 
在通过上述处理形成鳍状结构之后，可以在衬底上形成隔离层。例如，如图3所示，可以在衬底上例如通过淀积形成电介质层(例如，可以包括氧化物如氧化硅)，然后对淀积的电介质层进行回蚀，来形成隔离层1006。通常，淀积的电介质层可以完全覆盖鳍状结构1004，并且在回蚀之前可以对淀积的电介质进行平坦化，如化学机械抛光(CMP)。根据一优选示例，可以通过溅射来对淀积的电介质层进行平坦化处理。例如，溅射可以使用等离子体，如Ar或N等离子体。在衬底1000中形成阱区1000-1的情况下，隔离层1006优选稍稍露出阱区。即，隔离层1006的顶面略低于阱区1000-1的顶面(附图中没有示出它们之间的高度差)。 
为改善器件性能，特别是降低源漏泄漏，根据本公开的一示例，如图4中的箭头所示，通过注入(以下称作“第一离子注入”)来形成穿通阻挡部(PTS)1020。例如，对于n型器件而言，可以注入p型杂质，如B、BF2或In；对于p型器件，可以注入n型杂质，如As或P。第一离子注入可以垂直于衬底表面。控制第一离子注入的参数，使得PTS形成于鳍状结构1004位于隔离层1006表面之下的部分中，并且具有期望的掺杂浓度，例如约5E17-2E19cm-3，并且掺杂浓度应高于衬底中阱区1000-1的掺杂浓度。应当注意，由于鳍状结构1004的形状因子(细长形)，一部分掺杂剂(离子或元素)可能从鳍状结构的露出部分散射出去，从而有利于在深度方向上形成陡峭的掺杂分布。可以进行退火如尖峰退火、激光退火和/或快速退火，以激活注入的掺杂剂。这种PTS有助于减小源漏泄漏。 
随后，可以在隔离层1006上形成与鳍相交的栅堆叠。例如，这可以如下进行。具体地，如图5所示，例如通过淀积，形成栅介质层1008。例如，栅介质层1008可以包括氧化物，厚度为约0.8-1.5nm。 在图7所示的示例中，仅示出了“П”形的栅介质层1008。但是，栅介质层1008也可以包括在隔离层1006的顶面上延伸的部分。然后，例如通过淀积，形成栅导体层1010。例如，栅导体层1010可以包括多晶硅。栅导体层1010可以填充鳍之间的间隙，并可以进行平坦化处理例如CMP。 
如图6(图6(b)示出了沿图6(a)中BB′线的截面图)所示，对栅导体层1010进行构图。在图6的示例中，栅导体层1010被构图为与鳍状结构相交的条形。根据另一实施例，还可以构图后的栅导体层1010为掩模，进一步对栅介质层1008进行构图。 
在形成构图的栅导体之后，例如可以栅导体为掩模，进行晕圈(halo)注入和延伸区(extension)注入。 
接下来，如图7(图7(b)示出了沿图7(a)中CC′线的截面图)所示，可以在栅导体层1010的侧壁上形成栅侧墙1012。例如，可以通过淀积形成厚度约为5-20nm的氮化物(如氮化硅)，然后对氮化物进行RIE，来形成栅侧墙1012。本领域技术人员知道多种方式来形成这种侧墙，在此不再赘述。在鳍之间的沟槽为从上到下逐渐变小的锥台形时(由于刻蚀的特性，通常为这样的情况)，栅侧墙1012基本上不会形成于鳍的侧壁上。 
为改善器件性能，特别是降低源/漏区与衬底之间的结电容，根据本公开的一示例，在如上所述形成栅堆叠(例如，包括栅介质层、栅导体层和栅侧墙)之后，可以对源/漏区下方的PTS进行补偿。例如，如图8(图8(a)示出了沿图7(a)中B1B1′线的截面图，图8(b)示出了沿图7(a)中B2B2′线的截面图，图8(c)示出了沿图7(a)中CC′线的截面图)中的箭头所示，进行离子注入(以下称作“第二离子注入”)，以降低PTS 1020中的掺杂浓度。具体地，第二离子注入的掺杂剂导电类型可以与第一离子注入的掺杂剂导电类型相反。例如，对于n型器件，由于第一离子注入利用p型掺杂剂，则第二离子注入可以使用n型掺杂剂，如As或P；对于p型器件，由于第一离子注入利用n型掺杂剂，则第二离子注入可以使用p型掺杂剂，如B、BF2或In。第二离子注入可以垂直于衬底表面。控制第二离子注入的参数， 使得其能够注入到PTS 1020中，以对PTS 1020进行有效补偿，例如将PTS 1020中的掺杂剂浓度降低到约5E16-1E19cm-3。 
如图8(a)所示，由于栅堆叠的存在，鳍状结构1004与栅堆叠相交部分(沟道区将在其中形成)下方的区域基本上不会受到第二离子注入的影响。相反，如图8(b)所示，在鳍状结构1004位于栅堆叠两侧的部分下方，由于鳍状结构1004的形状因子(细长形)，同以上第一离子注入类似，能够形成陡峭的掺杂分布。结果，如图8(c)所示，PTS 1020位于栅堆叠下方的部分保留原有掺杂浓度，而其余部分则掺杂浓度降低(图8(c)中示出为1020′)。PTS的高浓度部分1020和低浓度部分1020′的分布是根据栅堆叠(例如，栅介质层1008、栅导体层1010和栅侧墙1012)得到的。因此，高浓度部分1020自对准于沟道区下方，而低浓度部分1020′自对准于源/漏区下方。 
在形成侧墙之后，可以栅导体及侧墙为掩模，进行源/漏(S/D)注入。随后，可以通过退火，激活注入的离子，以形成源/漏区，得到FinFET。 
为改善器件性能，根据本公开的一示例，可以利用应变源/漏技术。具体地，如图9所示，首先选择性去除(例如，RIE)暴露在外的栅介质层1008。在栅介质层1008和隔离层1006均包括氧化物的情况下，由于栅介质层1008较薄，因此对栅介质层1008的RIE基本上不会影响隔离层1006。在以上形成栅堆叠的过程中，以栅导体为掩模进一步构图栅介质层的情况下，不再需要该操作。 
然后，可以选择性去除(例如，RIE)由于栅介质层1008的去除而露出的鳍状结构1004的部分。对鳍状结构1004该部分的刻蚀可以进行至到达阱区1000-1。由于栅堆叠的存在，鳍状结构1004可以留于栅堆叠下方。这里需要指出的是，尽管在图9中将刻蚀后鳍状结构1004的边缘示出为与栅侧墙1012的边缘完全对准，但是本公开不限于此。例如，由于刻蚀的横向作用(可能很小)，从而刻蚀后鳍状结构1004的边缘相对于栅侧墙1012的边缘向里缩进。 
接下来，如图10所示，例如可以通过外延，在露出的鳍状结构部分上形成半导体层1014。随后可以在该半导体层1014中形成源/漏 区。根据本公开的一实施例，可以在生长半导体层1014的同时，对其进行原位掺杂。例如，对于n型器件，可以进行n型原位掺杂；而对于p型器件，可以进行p型原位掺杂。另外，为了进一步提升性能，半导体层1014可以包括不同于鳍状结构1004的材料，以便能够向鳍1004(其中将形成器件的沟道区)施加应力。例如，在鳍状结构1004包括Si的情况下，对于n型器件，半导体层1014可以包括Si:C(C的原子百分比例如为约0.2-2％)，以施加拉应力；对于p型器件，半导体层1014可以包括SiGe(例如，Ge的原子百分比为约15-75％)，以施加压应力。 
尽管在附图中将半导体层1014示出为与鳍状结构1004相对应的鳍状(例如，图11(a)、12(a)中的虚线所示部位)，但是本公开不限于此。例如，为了方便制造与源/漏区的接触，可以将半导体层1014生长为在横向上展宽一定程度。 
在栅导体层1010包括多晶硅的情况下，半导体层1014的生长可能也会发生在牺牲栅导体层1010的顶面上。这在附图中并未示出。 
在上述实施例中，在形成鳍之后，直接形成了栅堆叠。本公开不限于此。例如，替代栅工艺同样适用于本公开。 
根据本公开的另一实施例，在图5中形成的栅介质层1008和栅导体层1010为牺牲栅介质层和牺牲栅导体层(这样，通过结合图6、7描述的操作得到的栅堆叠为牺牲栅堆叠)。接下来，可以同样按以上结合图8描述的操作来对PTS进行补偿。另外，同样可以按以上结合图9-10描述的操作，来应用应变源/漏技术。 
接下来，可以根据替代栅工艺，对牺牲栅堆叠进行处理，以形成器件的真正栅堆叠。例如，这可以如下进行。 
具体地，如图11(图11(b)示出了沿图11(a)中CC′线的截面图)所示，例如通过淀积，形成电介质层1016。该电介质层1016例如可以包括氧化物。随后，对该电介质层1016进行平坦化处理例如CMP。该CMP可以停止于栅侧墙1012，从而露出牺牲栅导体层1010。 
随后，如图12(图12(b)示出了沿图12(a)中CC′线的截面图)所示，例如通过TMAH溶液，选择性去除牺牲栅导体1010，从 而在栅侧墙1012内侧形成了栅槽。根据另一示例，还可以进一步去除牺牲栅介质层1008。然后，通过在栅槽中形成栅介质层1022和栅导体层1024，形成最终的栅堆叠。栅介质层1022可以包括高K栅介质例如HfO2，厚度为约1-5nm。栅导体层1024可以包括金属栅导体。优选地，在栅介质层1022和栅导体层1024之间还可以形成功函数调节层(未示出)。 
这样，就得到了根据本公开实施例的半导体器件。如图12所示，该半导体器件可以包括在衬底1000上形成的鳍1004以及与鳍1004相交的栅堆叠。在该实施例中，栅堆叠可以包括栅介质层1022和栅导体层1024(以及栅侧墙1022)，且通过隔离层1006与衬底隔离开。该半导体器件还包括在鳍下方的区域中形成的PTS，该PTS包括自对准于沟道区(对应于鳍1004与栅堆叠相交的部分)下方的高掺杂浓度部分1020以及自对准于源/漏区(对应于鳍1004中位于沟道区两侧的部分)下方的低掺杂浓度部分1020′。例如，对于n型器件而言，PTS的掺杂可以为p型杂质，如B、BF2或In；对于p型器件，PTS的掺杂可以为n型杂质，如As或P。 
衬底1000中可以形成有阱区1000-1。自对准于沟道区下方的高掺杂浓度部分1020的掺杂浓度高于衬底中阱区1000-1的掺杂浓度。 
另外，在应用应变源漏技术的情况下，鳍状结构1004被隔离层1006露出的部分(上述“鳍”)留于栅堆叠下方，且在鳍的相对侧面上形成有半导体层1014，用以形成源/漏区。半导体层1014可以形成为鳍状。 
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。 
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附 权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。 

Claims (13)

1.一种制造半导体器件的方法，包括：
在衬底上形成鳍状结构；
在衬底上形成隔离层，隔离层露出鳍状结构的一部分，鳍状结构的露出部分用作该半导体器件的鳍；
进行第一离子注入，以在鳍下方的区域中形成穿通阻挡部；
在隔离层上形成与鳍状结构相交的栅堆叠；以及
进行第二离子注入，以对穿通阻挡部进行补偿。
2.根据权利要求1所述的方法，其中，
进行第一离子注入包括：对于n型器件，注入p型掺杂剂；和/或对于p型器件，注入n型掺杂剂；
进行第二离子注入包括：注入与第一离子注入的掺杂剂导电类型相反的掺杂剂。
3.根据权利要求2所述的方法，其中，在第二离子注入之前穿通阻挡部中的掺杂剂浓度为约5E17-2E19cm-3，在第二离子注入之后穿通阻挡部中受到补偿的区域的掺杂剂浓度为约5E16-1E19cm-3。
4.根据权利要求1所述的方法，其中，在第二离子注入之后，该方法还包括：
以栅堆叠为掩模，对鳍状结构进行选择性刻蚀；以及
外延生长半导体层，用以形成源、漏区。
5.根据权利要求4所述的方法，还包括：在外延生长半导体层同时，对该半导体层进行原位掺杂。
6.根据权利要求4所述的方法，其中，对于p型器件，半导体层带压应力；而对于n型器件，半导体层带拉应力。
7.根据权利要求1所述的方法，其中，形成的栅堆叠为牺牲栅堆叠，
该方法还包括：根据替代栅工艺，对牺牲栅堆叠进行处理，以形成器件栅堆叠。
8.一种半导体器件，包括：
在衬底上形成的鳍；
在衬底上形成的与鳍相交的栅堆叠，栅堆叠经由隔离层与衬底隔离；以及
在鳍下方的区域中形成的穿通阻挡部，该穿通阻挡部包括位于鳍与栅堆叠相交部分下方的第一部分以及位于第一部分两侧的第二部分，其中穿通阻挡部的第二部分的掺杂浓度低于穿通阻挡部的第一部分的掺杂浓度。
9.根据权利要求8所述的半导体器件，其中，鳍位于栅堆叠下方，且该半导体器件还包括在鳍的相对侧面上形成的半导体层，用以形成半导体器件的源/漏区。
10.根据权利要求9所述的半导体器件，其中，对于p型器件，半导体层带压应力；而对于n型器件，半导体层带拉应力。
11.根据权利要求10所述的半导体器件，其中，衬底包括Si，鳍与衬底一体，半导体层包括SiGe或Si:C。
12.根据权利要求9所述的半导体器件，其中，穿通阻挡部的第一部分自对准于栅堆叠，且穿通阻挡部的第二部分自对准于源/漏区。
13.根据权利要求8所述的半导体器件，其中，穿通阻挡部的第一部分中掺杂剂浓度为约5E17-2E19cm-3，穿通阻挡部的第二部分中掺杂剂浓度为约5E16-1E19cm-3。
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