CN103811320B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103811320B
CN103811320B CN201210447292.4A CN201210447292A CN103811320B CN 103811320 B CN103811320 B CN 103811320B CN 201210447292 A CN201210447292 A CN 201210447292A CN 103811320 B CN103811320 B CN 103811320B
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dielectric layer
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CN103811320A (zh
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朱慧珑
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Institute of Microelectronics of CAS
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Priority to PCT/CN2012/084816 priority patent/WO2014071651A1/zh
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Abstract

本申请公开了一种半导体器件及其制造方法。一示例方法可以包括：在衬底上依次形成第一半导体层和第二半导体层，其中第一半导体层是掺杂的；对第二半导体层、第一半导体层进行构图，以形成初始鳍；在衬底上形成电介质层，使得电介质层实质上覆盖初始鳍，其中位于初始鳍顶部的电介质层厚度充分小于位于衬底上的电介质层厚度；对电介质层进行回蚀以形成隔离层，隔离层露出第一半导体层的一部分，从而限定出位于隔离层上的鳍；以及在隔离层上形成横跨鳍的栅堆叠。

Description

半导体器件及其制造方法
技术领域
本公开涉及半导体领域，更具体地，涉及一种半导体器件及其制造方法。
背景技术
随着平面型半导体器件的尺寸越来越小，短沟道效应愈加明显。为此，提出了立体型半导体器件如FinFET(鳍式场效应晶体管)。一般而言，FinFET包括在衬底上竖直形成的鳍以及与鳍相交的栅极。因此，沟道区形成于鳍中，且其宽度主要由鳍的高度决定。然而，在集成电路制造工艺中，难以控制晶片上形成的鳍的高度相同，从而导致晶片上器件性能的不一致性。
发明内容
本公开的目的至少部分地在于提供一种半导体器件及其制造方法。
根据本公开的一个方面，提供了一种制造半导体器件的方法，包括：在衬底上依次形成第一半导体层和第二半导体层，其中第一半导体层是掺杂的；对第二半导体层、第一半导体层进行构图，以形成初始鳍；在衬底上形成电介质层，使得电介质层实质上覆盖初始鳍，其中位于初始鳍顶部的电介质层厚度充分小于位于衬底上的电介质层厚度；对电介质层进行回蚀以形成隔离层，隔离层露出第一半导体层的一部分，从而限定出位于隔离层上方的鳍；以及在隔离层上形成横跨鳍的栅堆叠。
根据本公开的另一方面，提供了一种半导体器件，包括：衬底；在衬底上依次形成的构图的第一半导体层和第二半导体层，其中第一半导体层是掺杂的；在衬底上形成的隔离层，所述隔离层露出第一半导体层的一部分，从而限定出位于隔离层上方的鳍；以及在隔离层上形成的横跨鳍的栅堆叠，其中，每一鳍的顶面大致持平，隔离层的顶面大致持平。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1-11是示出了根据本公开实施例的制造半导体器件流程的示意图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
为控制鳍的高度，常规的思想是控制鳍构图工艺中的参数。例如，在通过刻蚀衬底形成鳍的情况下，可以通过刻蚀参数来控制刻蚀深度，并因此控制所形成的鳍的高度。与此不同，根据本公开的一些实施例，并不刻意去精确控制鳍构图工艺，而是在通过构图在衬底上形成初始鳍之后，再在衬底上形成电介质层以基本上覆盖初始鳍。然后，可以对电介质层进行回蚀以形成隔离层，隔离层露出初始鳍的一部分。这样，以初始鳍的露出部分作为最终器件的鳍，其高度基本上由其顶面到隔离层的顶面的距离决定。
根据本公开的一个实施例，可以如此形成电介质层，使得电介质层基本上覆盖初始鳍时(即，在多个初始鳍的情况下基本上填充初始鳍之间的间隙时)，位于初始鳍顶部的电介质层厚度充分小于位于衬底上的电介质层厚度，例如初始鳍顶部的电介质层厚度可以小于位于衬底上的电介质层厚度的三分之一，优选为四分之一。例如，这可以通过高密度等离子体(HDP)淀积来实现。另外，在形成多个初始鳍的情况下，位于每一鳍的顶面之上的电介质材料的厚度可以小于与其相邻的鳍之间间距的二分之一。这样，在随后的回蚀中，可以减少刻蚀深度，从而能够增加刻蚀控制精度。
根据本公开的实施例，还可以在衬底上例如通过外延形成至少一个半导体层。这样，在例如通过刻蚀来构图初始鳍时，为形成相同高度的初始鳍，刻蚀进入衬底中的深度相对于常规技术可以减小(甚至可以为零，这种情况下，完全通过所述至少一个半导体层来形成初始鳍)，从而可以更加容易控制刻蚀深度的一致性。此外，外延层的厚度一致性可以相对容易地控制，结果，可以改善最终形成的鳍的厚度的一致性。
根本公开的优选实施例，所述至少一个半导体层可以包括两个或更多的半导体层。在这些半导体层中，相邻的半导体层可以相对于彼此具有刻蚀选择性，从而可以选择性刻蚀每一半导体层。
本公开可以各种形式呈现，以下将描述其中一些示例。
如图1所示，提供衬底1000。该衬底1000可以是各种形式的衬底，例如但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底1000中，可以形成n型阱1000-1和p型阱1000-2，以供随后在其中分别形成p型器件和n型器件。例如，n型阱1000-1可以通过在衬底1000中注入n型杂质如P或As来形成，p型阱1000-2可以通过在衬底1000中注入p型杂质如B来形成。如果需要，在注入之后还可以进行退火。本领域技术人员能够想到多种方式来形成n型阱、p型阱，在此不再赘述。
这里需要指出的是，尽管在以下描述了分别在n型阱和p型阱中形成互补器件的工艺，但是本公开不限于此。例如，本公开同样适用于非互补工艺。而且，以下涉及互补器件的一些处理，在某些实现方式中并非是必须的。
在衬底1000上，例如通过外延生长，形成第一半导体层1002。例如，第一半导体层1002可以包括Si，厚度为约10-50nm。在外延生长第一半导体层的过程中，可以对其进行原位掺杂，例如通过B而掺杂为p型。第一半导体层的掺杂浓度可以高于之下的p型阱的掺杂浓度，例如可为1E18-2E19cm-3。根据一示例，为降低B扩散，可以在p型第一半导体层1002中注入C。
然后，可以通过光刻胶(未示出)遮挡p型阱区上的第一半导体层，并向n型阱区上的第一半导体层注入杂质如As或P，以将该部分第一半导体层转换为n型，且其掺杂浓度可以高于之下的n型阱的掺杂浓度。注入浓度例如可以是2E18-4E19cm-3。之后可以去除光刻胶。于是，形成了n型第一半导体层1002-1和p型第一半导体层1002-2。
根据本公开的另一示例，第一半导体层也可以包括SiGe(Ge原子百分比例如为约5-20％)。在这种情况下，SiGe的第一半导体层同样可以如上所述进行掺杂。这种SiGe层能够在随后的鳍构图处理中提供充分的刻蚀选择性，以进一步提升对鳍构图处理的控制。
接下来，在第一半导体层1002(包括1002-1和1002-2)上，例如通过外延生长，形成第二半导体层1004。例如，第二半导体层1004可以包括Si，厚度为约20-100nm。
随后，可以对如此形成的第二半导体层1004、第一半导体层1002和衬底进行构图，以形成初始鳍。例如，这可以如下进行。具体地，在第二半导体层1004上按设计形成构图的光刻胶1006。通常，光刻胶1006可以被构图为一系列平行的等间距线条。然后，如图2所示，以构图的光刻胶1006为掩模，依次刻蚀例如反应离子刻蚀(RIE)第二半导体层1004、第一半导体层1002和衬底1000，从而形成初始鳍。
在互补工艺的情况下，还可以如图3所示，来在n型区域和p型区域之间形成隔离。具体地，可以在衬底上形成光刻胶1008，并对光刻胶1008进行构图，以露出n型区域和p型区域之间界面周围的一定区域。然后，通过选择性刻蚀例如RIE，去除该区域存在的第二半导体层、第一半导体层。优选地，还进一步选择性刻蚀如RIE衬底。从而在n型区域和p型区域之间形成隔离地带，该隔离地带随后被电介质材料所填充。然后，可以去除光刻胶1008。
可以看到，在图2的操作中，形成初始鳍的刻蚀步骤进入到衬底1000中；然后，通过图3中的操作，可以使得p型阱和n型阱之间的接触面积(即，形成的pn结的面积)较小。但是，本公开不限于此。例如，在非互补工艺，或者在单一类型(p型或n型)器件的局部区域，图2中对第一半导体层1002的刻蚀可以停止于衬底1000，并且随后不再对衬底1000进行刻蚀也是可行的；图3所示的操作可能也并非是必须的。通过刻蚀所形成的(初始鳍之间的)沟槽的形状不一定是图2中所示的规则矩形形状，可以是例如从上到下逐渐变小的锥台形。另外，所形成的初始鳍的位置和数目不限于图2所示的示例。
在图2所示的示例中，在n型阱1000-1和p型阱1000-2之间的界面处，也形成了初始鳍。由于图3所示的隔离形成工艺，该初始鳍也被去除。于是，得到了图4所示的结构。如图4所示，刻蚀深度在衬底上可能有变化。
在通过上述处理形成初始鳍之后，可以在衬底上形成用于隔离栅堆叠和衬底的隔离层，并在隔离层上形成横跨鳍的栅堆叠，从而形成最终的半导体器件。
在此，为了改善隔离层(顶面的)高度的一致性，并因此改善最终形成的鳍的高度的一致性，如图5所示，淀积电介质层1010，使得电介质层1010基本上覆盖初始鳍(在多个初始鳍的情况下，基本上填充初始鳍之间的间隙)。根据本公开的实施例，可以如此淀积，使得初始鳍顶部的电介质层厚度充分小于位于衬底上的电介质层厚度，并且一般来说初始鳍顶部的电介质层厚度都小于位于衬底上的电介质层厚度的三分之一，优选为四分之一。例如，每一初始鳍顶部的电介质层厚度一般不大于20nm，而位于衬底上的电介质层厚度可达100nm左右。
根据本公开的一示例，电介质层1010可以包括通过高密度等离子体(HDP)淀积形成的氧化物(例如，氧化硅)。由于HDP的特性，在淀积过程中可以使得初始鳍顶部的电介质层(沿垂直于衬底方向的)厚度和初始鳍侧面的电介质层(沿平行于衬底的方向，即横向的)厚度要小于初始鳍之间衬底上的电介质层(沿垂直于衬底方向的)厚度。因为HDP的这种特性，在常规技术中通常并不采用HDP淀积来制作氧化隔离。
在此，例如可以通过控制淀积条件，使得电介质层1010在基本上覆盖初始鳍时(或者，基本上填充初始鳍之间的空隙时)，位于每一初始鳍顶部上的厚度可以小于与其相邻的初始鳍之间间距的二分之一。如果初始鳍之间的间距并不相同，则可以使电介质层1010位于每一初始鳍顶部的厚度小于与其相邻的初始鳍之间间距中较小间距的二分之一。
随后，如图6所示，对电介质层1010进行回蚀，得到隔离层。隔离层露出第一半导体层1002的一部分(即，隔离层的顶面位于第一半导体层1002的顶面和底面之间)。这样，隔离层就限定了位于其上的鳍。在该示例中，第一半导体层1002-1和1002-2如上所述是掺杂的，其对应的阈值电压要高于第二半导体层1004对应的阈值电压。因此，通过控制栅极控制电压，可以使得第二半导体层导通而第一半导体层并不能导通。这样，最终用作器件的鳍可以仅包括第二半导体层1004，且第一半导体层可以充当穿通阻挡层，防止源漏之间的穿通。
由于电介质层1010的回蚀深度相对较小，从而对该刻蚀的控制相对容易，并因此可以更加精确地控制从初始鳍的顶面(在该示例中，第二半导体层1004的顶面)到隔离层1010的顶面的距离(至少部分地决定最终器件的鳍高度并因此决定最终器件的沟道宽度)，使得该距离在衬底上基本保持一致。这样，每一鳍的顶面大致持平，而鳍之间的间隙中填充的隔离层1010的顶面也大致持平，从而使得每一鳍的高度大致相同。
随后，可以在隔离层1010上形成横跨鳍的栅堆叠。例如，这可以如下进行。具体地，如图7(图7(b)示出了沿图7(a)中BB′线的截面图)所示，例如通过淀积，形成栅介质层1012。例如，栅介质层1012可以包括氧化物，厚度为约0.8-1.5nm。在图8所示的示例中，仅示出了“∏”形的栅介质层1012。但是，栅介质层1012也可以包括在隔离层1010的顶面上延伸的部分。然后，例如通过淀积，形成栅导体层1014。例如，栅导体层1014可以包括多晶硅。栅导体层1014可以填充鳍之间的间隙，并可以进行平坦化处理例如化学机械抛光(CMP)。之后，对栅导体层1014进行构图，以形成栅堆叠。在图7的示例中，栅导体层1014被构图为与鳍相交的条形。根据另一实施例，还可以构图后的栅导体层1014为掩模，进一步对栅介质层1012进行构图。
在形成构图的栅导体之后，例如可以栅导体为掩模，进行晕圈(halo)注入和延伸区(extension)注入。
接下来，如图8(图8(b)示出了沿图8(a)中BB′线的截面图)所示，可以在栅导体层1014的侧壁上形成侧墙1016。例如，可以通过淀积形成厚度约为5-30nm的氮化物，然后对氮化物进行RIE，来形成侧墙1016。本领域技术人员知道多种方式来形成这种侧墙，在此不再赘述。
在图8所示的示例中，将栅导体的高度形成为露出的鳍高度的至少两倍。这样，在形成侧墙1016的工艺中，可以使得鳍的侧壁上基本上不会形成侧墙。
在形成侧墙之后，可以栅导体及侧墙为掩模，进行源/漏(S/D)注入。随后，可以通过退火，激活注入的离子，以形成源/漏区。这样，就得到了根据该实施例的半导体器件。如图8所示，该半导体器件可以包括：衬底；在衬底上依次形成的构图的第一半导体层和第二半导体层，其中第一半导体层是掺杂的；在衬底上形成的隔离层，所述隔离层露出第一半导体层的一部分，从而限定出位于隔离层上方的鳍；以及在隔离层上形成的横跨鳍的栅堆叠，其中，每一鳍的顶面大致持平，隔离层的顶面大致持平。第一半导体层的掺杂浓度例如可以高于之下衬底的掺杂浓度，并可以用作穿通阻挡层。在第一半导体层充当穿通阻挡层的情况下，该器件的鳍可以包括构图的第二半导体层。
在上述实施例中，在形成鳍之后，直接形成了栅堆叠。本公开不限于此。例如，替代栅工艺同样适用于本公开。
根据本公开的另一实施例，在图7中形成的栅介质层1012和栅导体层1014为牺牲栅介质层和牺牲栅导体层。接下来，可以同样按以上结合图7、8描述的方法来进行处理。
接下来，如图9(图9(b)示出了沿图9(a)中BB′线的截面图)所示，例如通过淀积，形成另一电介质层1018。该电介质层1018例如可以包括氧化物。随后，对该电介质层1018进行平坦化处理例如CMP。该CMP可以停止于侧墙1016，从而露出牺牲栅导体1014。
随后，如图10(图10(b)示出了沿图10(a)中BB′线的截面图，图10(c)示出了沿图10(a)中CC′线的截面图)所示，例如通过TMAH溶液，选择性去除牺牲栅导体1014，从而在侧墙1016内侧形成了空隙1020。根据另一示例，还可以进一步去除牺牲栅介质层1012。
然后，如图11(图11(b)示出了沿图11(a)中BB′线的截面图，图11(c)示出了沿图11(a)中CC′线的截面图)所示，通过在空隙1020中形成栅介质层1022和栅导体层1024，形成最终的栅堆叠。栅介质层1022可以包括高K栅介质例如HfO2，厚度为约1-5nm。栅导体层1024可以包括金属栅导体。优选地，在栅介质层1022和栅导体层1024之间还可以形成功函数调节层(未示出)。在图11的示例中，将栅介质层1022示出为仅形成于空隙1020的底面上。事实上，栅介质层1022还可以形成在空隙1020的侧面上，从而包围栅导体层1024的底面和侧面。
这样，就得到了根据该实施例的半导体器件。该半导体器件与图8所示的半导体器件在结构上基本相同，除了栅堆叠按不同方式形成之外。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (9)

1.一种制造半导体器件的方法，包括：
在衬底上依次形成第一半导体层和第二半导体层，其中第一半导体层是掺杂的；
对第二半导体层、第一半导体层进行构图，以形成初始鳍；
在衬底上淀积电介质层，使得电介质层实质上覆盖初始鳍，其中位于初始鳍顶部的电介质层厚度充分小于位于衬底上的电介质层厚度，所淀积的电介质层具有第一表面，所述第一表面的最低处超出初始鳍的顶面；
在同一刻蚀步骤中从第一表面开始对电介质层进行回蚀，使电介质层具有低于第一表面的第二表面以形成隔离层，隔离层露出第一半导体层的一部分，从而限定出位于隔离层上方的鳍，其中隔离层位于鳍相对两侧的部分各自的第二表面实质上持平；以及
在隔离层上形成横跨鳍的栅堆叠。
2.根据权利要求1所述的方法，其中，位于初始鳍顶部的电介质层厚度小于位于衬底上的电介质层厚度的三分之一。
3.根据权利要求1所述的方法，其中，通过高密度等离子体(HDP)淀积形成电介质层。
4.根据权利要求1所述的方法，其中，在衬底上形成多个初始鳍，且位于每一初始鳍顶部的电介质层厚度小于与其相邻的初始鳍之间间距的二分之一。
5.根据权利要求1所述的方法，其中，对于p型器件，第一半导体层中掺杂n型杂质；对于n型器件，第一半导体层中掺杂p型杂质。
6.根据权利要求1所述的方法，其中，在形成初始鳍的操作中，还进一步对衬底进行构图。
7.根据权利要求1所述的方法，其中，形成栅堆叠包括：
形成横跨鳍的牺牲栅堆叠；
在牺牲栅堆叠的侧壁上形成侧墙；
在衬底上形成另一电介质层，并平坦化，以露出牺牲栅堆叠；
选择性去除牺牲栅堆叠，从而侧墙限定空隙；以及
在所述空隙中形成栅堆叠。
8.根据权利要求7所述的方法，其中，形成牺牲栅堆叠包括：
在衬底上淀积牺牲栅介质层和牺牲栅导体层；以及
对牺牲栅导体层进行构图，以形成牺牲栅堆叠。
9.根据权利要求8所述的方法，其中，选择性去除牺牲栅堆叠包括：
选择性去除牺牲栅导体层；以及
进一步选择性去除牺牲栅介质层。
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