CN106449388A - 具有自对准源极接触和漏极接触的晶体管及其制造方法 - Google Patents

具有自对准源极接触和漏极接触的晶体管及其制造方法 Download PDF

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CN106449388A
CN106449388A CN201511017723.3A CN201511017723A CN106449388A CN 106449388 A CN106449388 A CN 106449388A CN 201511017723 A CN201511017723 A CN 201511017723A CN 106449388 A CN106449388 A CN 106449388A
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J·H·张
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STMicroelectronics lnc USA
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Abstract

本发明涉及具有自对准源极接触和漏极接触的晶体管及其制造方法。一种晶体管包括有源区，该有源区由衬底支撑并且具有源极区、沟道区和漏极区。栅叠层在该沟道区之上延伸，并且第一侧壁包围该栅叠层。分别在该有源区的该源极区和该漏极区之上邻近该第一侧壁提供升高的源极区和升高的漏极区。第二侧壁周向地包围该升高的源极区和该升高的漏极区中的每一者。该第二侧壁在该升高的源极区和该升高的漏极区的顶表面上方延伸以限定由该第一侧壁和该第二侧壁横向地界定的多个区。导电材料填充这些区以分别形成到该升高的源极区和该升高的漏极区的源极接触和漏极接触。

Description

具有自对准源极接触和漏极接触的晶体管及其制造方法
技术领域
本发明涉及制造集成电路，并且更具体地涉及形成具有自对准的源极接触和漏极接触的集成电路晶体管器件的工艺。
背景技术
由于技术节点继续缩小以生产越来越小的集成电路晶体管器件，制造每个晶体管器件的端子并且与其电接触变得越来越有挑战性。一个关心的问题是防止当使用升高的源-漏外延区时在晶体管栅极区与晶体管源-漏区之间无意中形成短路。另一个关心的问题是防止在相邻的有源区之间无意中形成短路。电路设计者必须在器件之间包括足够的间隔以避免短路的风险，但是这种解决方案是以增加表面面积为代价。这种面积代价在针对相邻晶体管器件利用未合并的源-漏结构的设计中会尤其有问题。
因此，在本领域中存在对制造晶体管器件的改进工艺的需求，其可以解决以下问题：源-漏外延短路、当维持减小的接触电阻时源-漏接触的自对准、以及形成自对准于栅极的源-漏接触。
发明内容
在实施例中，一种方法包括：形成有源区，该有源区由衬底支撑并且包括源极区、沟道区和漏极区；在该沟道区之上形成栅叠层；分别在该有源区的该源极区和该漏极区之上外延地生长升高的源极区和升高的漏极区；分别在该升高的源极区和该升高的漏极区之上沉积牺牲层以形成源叠层和漏叠层；形成侧壁间隔物，该侧壁间隔物周向地包围该栅叠层、该源叠层和该漏叠层中的每一个；选择性地去除该牺牲层以在该升高的源极区和该升高的漏极区上方形成各自由该侧壁间隔物界定的多个开口；并且用导电材料填充所述多个开口以分别形成到该升高的源极区和该升高的漏极区的源极接触和漏极接触。
在实施例中，一种方法包括：形成有源区，该有源区由衬底支撑并且包括源极区、沟道区和漏极区；在该沟道区之上形成栅叠层；在该栅叠层上形成第一侧壁间隔物；分别在该有源区的该源极区和该漏极区之上邻近该第一侧壁间隔物外延地生长升高的源极区和升高的漏极区；在该升高的源极区和该升高的漏极区之上沉积牺牲层；在该栅叠层之上形成第一掩模；在该牺牲层和该升高的源极区和该升高的漏极区之上在与该第一掩模相同的水平面形成第二掩模；使用该第一和第二掩模进行蚀刻以限定由所述第二掩模覆盖的源叠层和漏叠层；在该源叠层和该漏叠层上形成第二侧壁间隔物；去除该第二掩模；使用该第一掩模进行蚀刻以去除该牺牲层并且在该升高的源极区和该升高的漏极区上方形成由该第一和第二侧壁间隔物界定的多个开口；并且用导电材料填充所述多个开口以分别形成到该升高的源极区和该升高的漏极区的源极接触和漏极接触。
在实施例中，一种集成电路包括：有源区，该有源区由衬底支撑并且包括源极区、沟道区和漏极区；在该沟道区之上延伸的栅叠层；包围该栅叠层的第一侧壁；分别在该有源区的该源极区和该漏极区之上邻近该第一侧壁的升高的源极区和升高的漏极区；周向地包围该升高的源极区和该升高的漏极区中的每一者的第二侧壁，所述第二侧壁在该升高的源极区和该升高的漏极区的顶表面之上延伸以限定由该第一和第二侧壁横向地界定的多个区；以及导电材料，该导电材料填充所述多个区以分别形成到该升高的源极区和该升高的漏极区的源极接触和漏极接触。
附图说明
为了更好地理解实施例，现在将仅以示例方式参照附图，在附图中：
图1至图15示出了用于形成集成电路晶体管器件的工艺步骤。
具体实施方式
现在参照示出了用于形成集成电路晶体管器件的工艺步骤的图1至图15。将理解的是，所提供的视图不一定示出按比例绘制的特征。
工艺从常规类型的绝缘体上硅(SOI)衬底10晶片开始(包括例如对本领域的技术人员是已知的极薄绝缘体上硅(ETSOI)或者超薄本体和掩埋氧化物(UTBB)绝缘体上硅(SOI))。SOI衬底10的顶部半导体层12(厚1nm至80nm)可以是针对集成电路应用被适当掺杂的硅。在实施例中，顶部半导体层可以是完全耗尽(FD)构型。顶部半导体层12由掩埋氧化物层14支撑(厚2nm至200nm)，而掩埋氧化物层由半导体衬底层16支撑。
图1示出了晶片的一部分的俯视图，而图1A示出了沿线A-A截取的横截面并且图1B示出了沿线B-B截取的横截面。在这些附图中，俯视图与横截面视图之间的这种关系是一致的。
使用本领域中公知的图案化蚀刻和填充技术，在顶部半导体层12中形成浅沟槽隔离(STI)结构20以对由顶部半导体层12的半导体材料形成的有源区22进行界定。有源区22可以例如具有5nm至40nm的宽度并且以10nm至80nm的间距被安排。可以支持有源区的取决于应用的任何合适的长度。在替代性实施例中，有源区22可以包括如在本领域中已知的那些用于制造鳍式FET晶体管的鳍结构。STI结构可以使鳍结构彼此分开，但是此类鳍结构将典型地具有在STI结构的顶表面上方延伸的高度。
高K电介质材料层(厚2nm至20nm)和多晶硅材料层(厚5nm至120nm)沉积于晶片之上。使用常规的光刻工艺技术对这些层进行图案化以形成包括栅极电介质32和栅极电极34的栅叠层30，该栅叠层在沟道区(C)的位置处横跨有源区22以形成晶体管。在有源区22中在沟道区的任一侧上提供晶体管的源极区(S)和漏极区(D)。尽管多晶硅被示出为栅极电极34的材料，将理解的是这仅是示例性的并且栅极电极可以包括其他导电材料或半导体材料并且可以由多层导电材料或半导体材料形成。栅叠层30可以例如具有跨多个有源区22延伸的宽度和5nm至40nm的长度。
在栅叠层30是在替换金属栅极制造技术中使用的已知类型的“假”栅极的情况中，层32和层34可以由多晶硅或其他合适的被图案化以限定栅极区的材料的单层替换。
在有源区22被形成为鳍结构的情况下，栅叠层30将在如图1C和图1D中示出的沟道区处在其三侧上跨坐于有源区之上，而不仅仅在如图1A和图1B中示出的顶侧上。在此示出的剩余工艺步骤同样适用于形成平面型MOSFET器件(如所示)或鳍式FET器件，并且因此有源区应包括如平面型有源区(图1A和图1B)或者鳍式结构有源区(图1C和图1D)的构型。在图1A和图1B中示出的这些结构的上下文中进行进一步的阐明和描述，而所有进一步的步骤同样适用于在图1C和图1D中示出的这些结构。
在此上下文中，将理解的是术语“宽度”和“长度”是相对于所形成的晶体管器件的沟道的宽度和长度而采取的。
然后，在栅叠层30的侧壁上形成侧壁间隔物38。例如，侧壁间隔物38可以由绝缘材料在晶片上的共形沉积接着进行蚀刻而形成，该蚀刻优先去除晶片的水平表面上的材料而留下晶片的竖直表面上的材料。针对侧壁间隔物38的绝缘材料可以包括：SiN、SiBCN或SiOCN。侧壁间隔物38可以具有1nm至20nm的厚度。形成间隔物的工艺可以例如使用Lam混合模式脉冲(MMP)沉积/蚀刻/O2闪蒸方法。在图2、图2A和图2B中示出了结果。在此上下文中，在栅叠层30的第一相反侧上形成侧壁间隔物38。
然后使用外延工艺来在晶片上生长半导体材料的外延层40。例如，层40可以具有20nm至60nm的厚度，其中，那个厚度优选地小于栅叠层30的高度，并且更优选地大约为栅叠层30的高度的30-40％。在图3、图3A和图3B中示出了结果。如果所生产的这些晶体管是nMOS型的，那么外延层40的材料可以例如包括具有磷掺杂浓度为1×1019at/cm3至1×1021at/cm3的SiP/Si。该材料可以包括0.5％至5％的替代碳。如果所生产的这些晶体管是pMOS型的，那么外延层40的材料可以例如包括具有硼掺杂浓度为1×1019at/cm3至2×1021at/cm3的SiGeB。该材料可以包括25％至75％的替代锗。
然后在晶片上共形地沉积电介质材料的牺牲层44(厚400nm至600nm)直到足够覆盖栅叠层30的厚度。然后执行化学机械抛光以去除层44在栅叠层30的顶部上方的这些部分。在图4、图4A和图4B中示出了结果。层44的电介质材料可以例如包括使用化学气相沉积(CVD)或等离子增强型化学气相沉积(PECVD)沉积的低温氧化物或可流动的氧化物。
然后在晶片之上沉积一层硬掩模材料。例如，该硬掩模材料可以包括使用PECVD沉积的SiON。使用常规光刻技术，该层硬掩模材料被图案化以在晶片的每个区之上留下栅极掩模50，其中，栅叠层30与有源区22交叉(相交)。在图5、图5A和图5B中示出了结果。
然后在晶片上共形地沉积硬掩模材料的附加层52(厚大约80nm)直到足够覆盖栅叠层50的厚度。然后执行化学机械抛光以去除层52在栅极掩模50的顶部上方的这些部分。在图6、图6A和图6B中示出了结果。例如，附加硬掩模材料可以包括非晶碳。
使用本领域中已知的光刻技术，附加层52被图案化以限定掩模54，该掩模覆盖有源区22和晶片与有源区相邻的区域。在图7、图7A和图7B中示出了结果。
然后使用掩模50和54执行蚀刻以阻止材料去除。蚀刻延伸通过不同的层40和44到达STI结构20的顶部并形成多个开口56。在图8、图8A和图8B中示出了结果。该蚀刻工艺可以例如包括被添加至氧气作为对反应离子蚀刻(RIE)中的SiON具有选择性的非晶碳层的添加蚀刻气体蚀刻的硫化羰(COS)。基于费罗林的各向异性的RIE可以被用于在STI结构20上停止。蚀刻的结果留下在每个有源区22之上的分开的栅叠层60以及在该分开的栅叠层60的任一侧上的在每个有源区22之上的源-漏叠层62。
然后在分开的栅叠层60的侧壁和每个分开的源-漏叠层62的新暴露的侧壁上形成侧壁间隔物68。例如，侧壁间隔物68可以由绝缘材料在晶片上的共形沉积接着进行蚀刻而形成，该蚀刻优先去除水平表面上的材料而留下竖直表面上的材料。针对侧壁间隔物68的绝缘材料可以包括：SiN、SiBCN或SiOCN。侧壁间隔物68可以具有1nm至20nm的厚度。形成间隔物的工艺可以例如使用Lam混合模式脉冲(MMP)沉积/蚀刻/O2闪蒸方法。在图9、图9A和图9B中示出了结果(其中，图9C是沿图9中的线C-C截取的横截面)。在此上下文中，在分开的栅叠层60的第二相反侧上形成侧壁间隔物68，而在栅叠层30的第一相反侧上形成侧壁间隔物38，并且侧壁间隔物38和68周向地包围该分开的栅叠层60和每个源-漏叠层62。
然后在开口56之内在晶片上共形地沉积电介质材料的层70(厚400nm至600nm)直到足够覆盖掩模50和54的厚度。然后执行化学机械抛光以去除层70在掩模50和54的顶部上方的这些部分。在图10、图10A和图10B中示出了结果。层70的电介质材料可以例如包括使用化学气相沉积(CVD)或等离子增强型化学气相沉积(PECVD)沉积的氧化物。
然后选择性地去除掩模54并且通过由去除掩模54留下的开口执行蚀刻以去除在外延层40上停止的氧化层44并形成多个开口58，这些开口由栅叠层30上的侧壁间隔物38和包围源-漏叠层62的侧壁间隔物68横向地界定。在图11、图11A、图11B和图11C中示出了结果(其中，图11C是沿图11中的线C-C截取的横截面)。该蚀刻工艺可以例如包括被添加至氧气作为对反应离子蚀刻(RIE)中的SiON具有选择性的非晶碳层的添加蚀刻气体蚀刻的硫化羰(COS)。蚀刻的结果留下在每个有源区22之上的分开的栅叠层60以及在该分开的栅叠层60的任一侧上的在每个有源区22之上的源-漏叠层62的外延层40。就此而言，在分开的栅叠层60的一侧上提供源极区66s并且在分开的栅叠层60的另一侧上提供漏极区66d。
然后在每个开口58中的源极区66s和漏极区66d的顶表面转换成硅化物70。在图12、图12A和图12B中示出了结果。用于形成硅化物的技术对于本领域技术人员而言是公知的。在针对相对大的(大于或等于20nm)临界尺寸工艺的实施例中，可以使用以下硅化物工艺：SiCoNi预清洁、使用RFPVD沉积NiPt层、以及在380℃中退火30秒。针对相对小的(小于20nm)临界尺寸工艺，针对nMOS晶体管器件可以使用以下硅化物工艺：气体团簇离子束(GCIB)/dHF预清洁、具有磷非晶态注入(1×1019at/cm3至1×1021at/cm3)和退火的SiP沟道外延层、通过PVD沉积Ti层、以及激光退火。针对相对小的(小于20nm)临界尺寸工艺，针对pMOS晶体管器件可以使用以下硅化物工艺：气体团簇离子束(GCIB)/dHF预清洁、具有硼非晶态注入(1×1019at/cm3至2×1021at/cm3)和退火的GeB沟道外延层、通过PVD沉积Ti层、以及激光退火。
然后在硅化物70之上在开口58之内形成针对源极和漏极的每一者的金属接触74。金属接触74优选地由势垒层(Ti的3-5nmALD)、内衬(TiN的2-4nm ALD)和金属填充物(W、Co、Cu、Al或其合金的200nm CVD)形成。然后执行化学机械抛光以去除金属接触74的层、内衬和填充物在分开的栅叠层60的顶部上方的这些部分。栅极掩模50也被去除。在图13、图13A和图13B中示出了结果。
然后可以使用常规的中段制程(MOL)和后段制程(BEOL)工艺以形成针对源极和漏极的金属接触74以及针对栅极的金属接触76的延伸物。在图14和图15中示出了针对MOL/BEOL结构的结构构型的示例。
在以上所描述的实施例中，栅叠层30可以以与“栅极优先”制造技术一致的方式包括针对晶体管器件的完全形成的栅极电极。在替代性实施例中，栅叠层可以以与“栅极最后”(或替换金属栅极)制造技术一致的方式代替地包括“假”栅极结构。在栅极最后工艺中，在图13、13A和13B的步骤之后，工艺将接下来包括去除假栅极结构的材料32/34以形成由包围假栅叠层30的侧壁间隔物38和侧壁间隔物68所界定的开口。在这之后，通过例如沉积高K电介质材料以覆盖沟道区、沉积功函数金属以及沉积多晶硅或金属电极材料而在开口中制造栅极电极。在或者栅极优先技术或者栅极最后技术中，栅极电极可以进一步包括硅化物区。
虽然已在附图和前述描述中具体示出和描述的本发明，但是这些示出和描述被认为是示意性或示例性，而非限制性。本发明不限于所公开的具体实施例。在实践本发明的过程中，本领域技术人员根据对附图、公开内容和权利要求书的研究可以理解和实现对所公开的实施例的其它变化。

Claims (24)

1.一种方法，包括：
形成有源区，所述有源区由衬底支撑并且包括源极区、沟道区和漏极区；
在所述沟道区之上形成栅叠层；
分别在所述有源区的所述源极区和所述漏极区之上外延地生长升高的源极区和升高的漏极区；
分别在所述升高的源极区和所述升高的漏极区之上沉积牺牲层以形成源叠层和漏叠层；
形成侧壁间隔物，所述侧壁间隔物周向地包围所述栅叠层、所述源叠层和所述漏叠层中的每一个；
选择性地去除所述牺牲层以在所述升高的源极区和所述升高的漏极区上方形成各自由所述侧壁间隔物界定的多个开口；并且
用导电材料填充所述多个开口以分别形成到所述升高的源极区和所述升高的漏极区的源极接触和漏极接触。
2.如权利要求1所述的方法，其中，形成所述有源区包括限定鳍结构并且在所述鳍结构的三侧上形成所述栅叠层。
3.如权利要求1所述的方法，其中，所述衬底是绝缘体上硅(SOI)衬底。
4.如权利要求1所述的方法，其中，所述栅叠层是假栅叠层，并且所述方法进一步包括：
去除所述假栅叠层以形成由所述第一侧壁间隔物和所述第二侧壁间隔物界定的另一个开口；并且
在所述另一个开口中制造绝缘栅极电极结构。
5.如权利要求1所述的方法，其中，形成所述侧壁间隔物包括：
在所述栅叠层的多个侧壁上形成第一侧壁间隔物；并且
在所述源叠层和所述漏叠层的多个侧壁上形成第二侧壁间隔物。
6.如权利要求5所述的方法，其中，所述第一侧壁间隔物进一步被提供在所述源叠层和所述漏叠层中的每一者的侧壁上。
7.如权利要求5所述的方法，其中，形成所述第一侧壁间隔物包括在所述栅叠层的第一相反侧壁上形成所述第一侧壁间隔物，并且其中，形成所述第二侧壁间隔物进一步包括在所述栅叠层的第二相反侧壁上形成所述第二侧壁间隔物。
8.如权利要求1所述的方法，进一步包括：
在所述栅叠层之上沉积第一掩模；
在所述升高的源极区和所述升高的漏极区之上沉积第二掩模；并且
使用所述第一掩模和所述第二掩模进行蚀刻以限定所述源叠层和所述漏叠层。
9.如权利要求8所述的方法，其中，蚀刻进一步限定了所述栅叠层。
10.如权利要求8所述的方法，其中，选择性地去除所述牺牲层包括：
去除所述第二掩模；并且
使用所述第一掩模进行蚀刻以去除所述牺牲层。
11.如权利要求8所述的方法，其中，所述第一掩模和所述第二掩模形成在同一水平面上。
12.如权利要求1所述的方法，其中，形成所述有源区包括形成通过绝缘材料而彼此分开的多个有源区，并且其中，形成所述栅叠层包括将所述栅叠层形成为在所述多个有源区之上延伸。
13.如权利要求12所述的方法，其中，形成所述侧壁间隔物包括：
在所述栅叠层的第一相反侧壁上形成第一侧壁间隔物；
去除所述栅叠层在所述多个有源区中的相邻有源区之间的多个部分以限定相应的多个分开的栅叠层；并且
在每个分开的栅叠层的第二相反侧壁上形成第二侧壁间隔物。
14.如权利要求13所述的方法，其中，形成所述侧壁间隔物进一步包括同样在所述源叠层和所述漏叠层的多个侧壁上形成所述第二侧壁间隔物。
15.如权利要求1所述的方法，其中，填充所述多个开口包括形成硅化物。
16.一种方法，包括：
形成有源区，所述有源区由衬底支撑并且包括源极区、沟道区和漏极区；
在所述沟道区之上形成栅叠层；
在所述栅叠层上形成第一侧壁间隔物；
分别在所述有源区的所述源极区和所述漏极区之上邻近所述第一侧壁间隔物外延地生长升高的源极区和升高的漏极区；
在所述升高的源极区和所述升高的漏极区之上沉积牺牲层；
在所述栅叠层之上形成第一掩模；
在所述牺牲层和所述升高的源极区和所述升高的漏极区之上在与所述第一掩模相同的水平面上形成第二掩模；
使用所述第一掩模和所述第二掩模进行蚀刻以限定由所述第二掩模覆盖的源叠层和漏叠层；
在所述源叠层和所述漏叠层上形成第二侧壁间隔物；
去除所述第二掩模；
使用所述第一掩模进行蚀刻以去除所述牺牲层并且在所述升高的源极区和所述升高的漏极区上方形成由所述第一侧壁间隔物和所述第二侧壁间隔物界定的多个开口；并且
用导电材料填充所述多个开口以分别形成到所述升高的源极区和所述升高的漏极区的源极接触和漏极接触。
17.如权利要求16所述的方法，其中，形成所述有源区包括限定鳍结构并且在所述鳍结构的三侧上形成所述栅叠层。
18.如权利要求16所述的方法，其中，所述衬底是绝缘体上硅(SOI)衬底。
19.如权利要求16所述的方法，其中，所述栅叠层是假栅叠层，并且所述方法进一步包括：
去除所述假栅叠层以形成由所述第一侧壁间隔物和所述第二侧壁间隔物界定的另一个开口；并且
在所述另一个开口中制造绝缘栅极电极结构。
20.一种集成电路，包括：
有源区，所述有源区由衬底支撑并且包括源极区、沟道区和漏极区；
在所述沟道区之上延伸的栅叠层；
包围所述栅叠层的第一侧壁；
分别在所述有源区的所述源极区和所述漏极区之上邻近所述第一侧壁的升高的源极区和升高的漏极区；
周向地包围所述升高的源极区和所述升高的漏极区中的每一者的第二侧壁，所述第二侧壁在所述升高的源极区和所述升高的漏极区的顶表面上方延伸以限定由所述第一侧壁和所述第二侧壁横向地界定的多个区；以及
导电材料，所述导电材料填充所述多个区以分别形成到所述升高的源极区和所述升高的漏极区的源极接触和漏极接触。
21.如权利要求20所述的集成电路，其中，所述第一侧壁和所述第二侧壁周向地包围所述栅叠层。
22.如权利要求20所述的集成电路，其中，所述栅叠层是替换金属栅极。
23.如权利要求20所述的集成电路，其中，所述有源区包括鳍结构并且所述栅叠层在三侧上包围所述鳍结构。
24.如权利要求20所述的集成电路，其中，所述衬底是绝缘体上硅(SOI)衬底。
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