WO2021213115A1 - 具有u形结构的半导体器件及其制造方法及电子设备 - Google Patents

具有u形结构的半导体器件及其制造方法及电子设备 Download PDF

Info

Publication number
WO2021213115A1
WO2021213115A1 PCT/CN2021/082400 CN2021082400W WO2021213115A1 WO 2021213115 A1 WO2021213115 A1 WO 2021213115A1 CN 2021082400 W CN2021082400 W CN 2021082400W WO 2021213115 A1 WO2021213115 A1 WO 2021213115A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
trench
sacrificial
semiconductor
substrate
Prior art date
Application number
PCT/CN2021/082400
Other languages
English (en)
French (fr)
Inventor
朱慧珑
李晨
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US17/919,652 priority Critical patent/US20230163204A1/en
Publication of WO2021213115A1 publication Critical patent/WO2021213115A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device having a U-shaped structure and a manufacturing method thereof, and electronic equipment including such a semiconductor device.
  • FinFET fin field effect transistors
  • MBCFET multi-bridge channel field effect transistors
  • the purpose of the present disclosure is at least partly to provide a semiconductor device having a U-shaped structure, a method of manufacturing the same, and an electronic device including such a semiconductor device.
  • a semiconductor device including: a first fin and a second fin extending in a vertical direction relative to a substrate and facing each other; connecting the nanosheets, and connecting the first fin The sheet and the bottom end of the second fin are connected to form a U-shaped structure, wherein the connecting nano sheet is spaced apart from the top surface of the substrate.
  • a method of manufacturing a semiconductor device including: forming a first trench extending in a first direction in a substrate, and the first trench includes opposing trenches extending in the first direction. The sidewalls and the bottom surface connecting the sidewalls; the semiconductor layer extending along the sidewalls and the bottom surface is formed in the first trench; the first sacrificial layer is filled in the first trench where the semiconductor layer is formed; the first sacrificial layer is filled in The first trench of the layer is on the first side in the second direction intersecting the first direction, forming a second trench that enters the substrate and extends in the first direction, and the second trench extends in the second direction to Below the bottom surface of the first trench, but the semiconductor layer and the first sacrificial layer in the first trench remain on the second side of the first trench opposite to the first side in the second direction, and are still connected to the substrate; A second sacrificial layer is formed in the second trench; on the second side of the first trench filled with
  • the third trench is Extend in the second direction below the bottom surface of the first trench to the second sacrificial layer; fill the third sacrificial layer in the third trench, so that the semiconductor layer is surrounded by the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer ,
  • the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer can be selectively etched with respect to the semiconductor layer.
  • an electronic device including the above-mentioned semiconductor device.
  • the semiconductor device may have two fins, and thus form a dual fin field effect transistor (DFFET).
  • DFFET dual fin field effect transistor
  • the two fins can be connected to each other by connecting nanosheets, thereby forming a U-shaped structure. This can provide high performance and high integration.
  • 1 to 29(b) show schematic diagrams of some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure
  • Figures 1 to 18, 28(a), 29(a) are cross-sectional views along the line AA';
  • Figures 19, 20(b), 28(d), 29(b) are top views, and the top view of Figure 19 shows the positions of lines AA', BB', and CC';
  • Figures 20(a), 21, 22(a), 23, 24(a), 25(a), 26(a), 27(a), 28(b) are cross-sectional views along the line BB';
  • Figures 22(b), 24(b), 25(b), 26(b), 27(b), 28(c) are cross-sectional views along the CC' line.
  • a layer/element when a layer/element is referred to as being “on” another layer/element, the layer/element may be directly on the other layer/element, or there may be an intermediate layer/element between them. element.
  • the layer/element may be located "under” the other layer/element when the orientation is reversed.
  • a semiconductor device may have a U-shaped structure.
  • the U-shaped structure may include two fins extending in a vertical direction relative to the substrate (for example, a direction substantially perpendicular to the surface of the substrate) and a connecting nanosheet connecting the bottom ends of the two fins to each other.
  • the connecting nanosheets can be spaced apart from the substrate.
  • this U-shaped structure can be fabricated using trenches in the substrate as a template.
  • the U-shaped structure can be formed by epitaxially growing a semiconductor layer on the sidewall and bottom surface of the trench.
  • the U-shaped structure may be integrated and may have a substantially uniform thickness.
  • the bottom surface of the trench may be substantially parallel to the top surface of the substrate, so the connecting nanosheets formed on the bottom surface of the trench may be substantially parallel to the top surface of the substrate.
  • the semiconductor layer formed in the same trench can be separated into several parts in the longitudinal extension direction of the trench ("first direction"), and used for corresponding semiconductor devices respectively.
  • first direction the respective U-shaped structures of the semiconductor devices adjacent in the first direction
  • the respective vertical fins may be substantially coplanar
  • the respective connection nanosheets may be substantially coplanar.
  • This U-shaped structure can be used as a channel portion, so the semiconductor device can be a dual fin field effect transistor (DFFET).
  • the semiconductor device may further include source/drain portions located on opposite sides of the U-shaped structure in the first direction.
  • the U-shaped structure is connected between the source/drain portions on opposite sides, and a conductive channel between the source/drain portions can be formed.
  • the source/drain portion may include the same material as the channel portion, or may include a different material so as to, for example, apply stress to the channel portion to enhance device performance.
  • the U-shaped structure may include a single crystal semiconductor material to improve device performance.
  • the source/drain portion may also include a single crystal semiconductor material.
  • the semiconductor device may further include a gate stack intersecting the channel portion.
  • the gate stack may extend in a second direction that intersects (e.g., perpendicularly) to the first direction. As described above, since the U-shaped structure is spaced apart from the substrate, the gate stack can surround the U-shaped structure and define a channel region therein.
  • Gate sidewall spacers may be formed on the sidewalls of the gate stack on opposite sides in the first direction.
  • the gate stack can be separated from the source/drain part by a gate sidewall.
  • the outer wall of the gate side wall facing each source/drain portion may be substantially coplanar in the vertical direction, and may be substantially coplanar with the sidewall of the U-shaped structure.
  • the gate side wall surface and the inner side wall of the gate stack may be substantially coplanar in the vertical direction, so that the gate stack may have a substantially uniform gate length.
  • the gate spacer may have a substantially uniform thickness.
  • Such a semiconductor device can be manufactured as follows, for example.
  • a first trench extending in the first direction may be formed in the substrate and used as a template for forming the semiconductor layer as described above. More specifically, the first trench may include sidewalls facing each other and extending in the first direction and a bottom surface connecting the sidewalls.
  • a semiconductor layer may be formed on the sidewall and bottom surface of the first trench, and the semiconductor layer may include a portion (vertical fin) extending along the sidewall of the first trench and a portion extending along the bottom surface of the first trench ( Connect the nanosheets).
  • the first sacrificial layer may be filled in the first trench to cover the semiconductor layer, thereby substantially defining the sacrificial gate above the semiconductor layer.
  • a second trench extending in the first direction may be formed,
  • the second groove may extend below the bottom surface of the first groove in the second direction.
  • the second sacrificial layer may be filled in the second trench, so that the sacrificial gate may be defined on this side of the semiconductor layer and below the bottom surface.
  • a third trench extending in the first direction may be formed, and the third trench may be in the second direction. It extends in two directions below the bottom surface of the first trench to the second sacrificial layer.
  • the third sacrificial layer may be filled in the third trench, so that the sacrificial gate may be defined on the other side and under the bottom surface of the semiconductor layer. Since the third trench extends to the second sacrificial layer, the third sacrificial layer filled in the third trench may be connected to the second sacrificial layer.
  • the second trench and the third trench may be formed along the sidewalls of the first trench, so the second sacrificial layer in the second trench and the third sacrificial layer in the third trench may be the same as the first trench.
  • the first sacrificial layer in the groove is connected.
  • the first sacrificial layer, the second sacrificial layer, and the third sacrificial layer may be connected to each other to surround the semiconductor layer, and thus may become a sacrificial gate.
  • the sacrificial gate may have an etching selectivity with respect to the semiconductor layer so as to be replaced with a gate stack later.
  • an isolation layer may be provided between the sacrificial gate and the substrate.
  • an isolation layer with a certain thickness may be formed first.
  • the second trench and the isolation layer formed in the second trench may be connected to each other so as to be interposed between the sacrificial gate and the substrate.
  • the sacrificial gate may be patterned into a bar shape extending in the second direction.
  • the sacrificial gate can be used as a mask to pattern the semiconductor layer, leaving it under the sacrificial gate to be used as a channel part.
  • source/drain portions connected to the semiconductor layer can be formed by, for example, epitaxial growth.
  • the sacrificial gate can be replaced with a real gate stack through a replacement gate process.
  • the present disclosure can be presented in various forms, some examples of which will be described below.
  • the selection of various materials is involved.
  • the selection of materials also considers etching selectivity.
  • the required etching selectivity may or may not be indicated. It should be clear to those skilled in the art that when etching a certain material layer is mentioned below, if it is not mentioned that other layers are also etched or the figure does not show that other layers are also etched, then this kind of etching It may be selective, and the material layer may have etching selectivity relative to other layers exposed to the same etching recipe.
  • 1 to 29(b) show schematic diagrams of some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure.
  • a substrate 1001 is provided.
  • the substrate 1001 may be in various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk Si substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • SOI semiconductor-on-insulator
  • a trench may be formed in the substrate 1001 to serve as a template for forming a U-shaped structure.
  • a hard mask layer may be formed on the substrate 1001 and an opening may be defined in the hard mask layer, and the opening in the hard mask layer may be used to define the trench in the substrate 1001.
  • it is necessary to form processing channels on each of the opposite sides of the U-shaped structure when processing is performed on one side through the corresponding processing channel). , The other side remains connected to the substrate to avoid collapse of the U-shaped structure).
  • different materials having etch selectivity with respect to each other may be used to form portions of the hard mask layer located on opposite sides of the opening, respectively.
  • a hard mask layer that meets the above conditions can be provided in combination with a spacer forming process.
  • the sidewall spacers may be formed on the sidewalls of the mandrel pattern.
  • one side of the sidewall is the core mold pattern (as part of the hard mask layer), and the other side of the sidewall can be formed with a material with etch selectivity relative to the core mold pattern (as another part of the hard mask layer). Part).
  • the core mold pattern plus the material can form a hard mask layer, and an opening can be defined in such a hard mask layer by removing the side wall, and the hard mask layer portions on both sides of the opening can have engravings relative to each other. Eclipse selectivity.
  • the width of the opening and the width of the groove obtained thereby can be better controlled.
  • the etch stop layer 1003 and the core mold layer 1005 can be sequentially formed on the substrate by, for example, deposition.
  • the etch stop layer 1003 may have an etch selectivity with respect to the substrate 1001 and the core layer 1005, for example, includes oxide (for example, silicon oxide), and has a thickness of, for example, about 2 nm-10 nm.
  • the core mold layer 1005 may include polysilicon to achieve good etching quality, and the thickness is, for example, about 50 nm-150 nm.
  • a photoresist (not shown) may be used to selectively etch the core layer 1005, such as reactive ion etching (RIE), to form a core pattern (still labeled 1005).
  • RIE reactive ion etching
  • the RIE may be along a vertical direction (for example, a direction substantially perpendicular to the surface of the substrate 1001), so that the core pattern 1005 may have vertical sidewalls.
  • the core pattern 1005 may have a strip shape extending in the first direction (the direction entering the paper surface in the figure). Therefore, the side wall can extend in the first direction.
  • the RIE can be stopped at the etch stop layer 1003. After that, the photoresist can be removed.
  • sidewalls 1007 may be formed on the sidewalls of the core pattern 1005.
  • the formation of sidewall spacers may include substantially conformal formation, for example, deposition of a sidewall spacer material layer, and anisotropic etching of the formed sidewall material layer, such as RIE in the vertical direction (can be stopped at the etching stop layer 1003) .
  • the thickness of the sidewall 1007 (the scale in the horizontal direction in the figure) or the thickness of the deposited sidewall material layer can be determined according to the width of the trench to be formed (the scale in the horizontal direction in the figure). As an example, the thickness of the deposited sidewall material layer may be about 10nm-25nm.
  • the sidewall spacer 1007 may include a material having etch selectivity with respect to the core pattern 1005 (and the etch stop layer 1003), such as SiC.
  • a first sub-hard mask layer 1009 may be formed on the substrate 1001.
  • the first sub hard mask layer 1009 may define the hard mask layer together with the core pattern 1005 (which is subsequently replaced by the second sub hard mask layer 1011, see FIG. 5).
  • the first sub-hard mask layer 1009 may include a material having etching selectivity with respect to the sidewall spacer 1009 and the core pattern 1005 (or the second sub-hard mask layer 1011 to be replaced later), for example Nitride (for example, silicon nitride).
  • the nitride layer can be formed by depositing about 50nm-150nm of silicon nitride, and performing planarization treatments such as chemical mechanical polishing (CMP) on the deposited silicon nitride until the sidewalls 1007 and the core pattern 1005 are exposed. 1009.
  • CMP chemical mechanical polishing
  • the core pattern 1005 polysilicon in this example
  • the substrate 1001 in this example, Si
  • the core mold pattern 1005 of polysilicon can be replaced by a second sub-hard mask layer 1011 such as an oxide by etching, deposition and then planarization, which is together with the first sub-hard mask layer 1009 Define the hard mask layer.
  • the replacement process for the core mold pattern 1005 can be omitted in some cases, for example, in the case of using oxide as the core mold pattern 1005 (polysilicon is used as the core mold pattern 1005 to achieve better etching quality).
  • the first sub-hard mask layer 1009 and the second sub-hard mask layer 1011 together constitute a hard mask layer, and sidewall spacers 1007 are embedded therein.
  • This form of hard mask layer can save the number of masking steps, and can realize a self-aligned mask to save area, which will be described in further detail below.
  • the sidewalls 1007 can be removed by selective etching, so openings are formed in the hard mask layer 1009+1011.
  • the width of these openings (the horizontal dimension in the figure) is determined by the sidewalls 1007 Width limit.
  • the etching stop layer 1003 and the substrate 1001 are sequentially selectively etched, such as RIE along the vertical direction, to form trenches in the substrate 1001 T1.
  • the height of the second sub-hard mask layer 1011 in this example, the same oxide as the etch stop layer 1003 can be reduced.
  • the width of the trench T1 (the scale in the horizontal direction in the figure) may be defined by the width of the opening in the hard mask layer or the sidewall spacer 1007.
  • the sidewall and bottom surface of the trench T1 provide a template for forming a U-shaped structure.
  • a semiconductor layer 1015 may be formed on the sidewall and bottom surface of the trench T1, for example, by epitaxial growth, to obtain a U-shaped nanosheet.
  • a silicon process is taken as an example for description, that is, the semiconductor layer 1015 includes Si.
  • an etch stop layer may be formed on the sidewall and bottom surface of the trench T1, for example, by epitaxial growth 1013, the semiconductor layer 1015 may grow on the surface of the etch stop layer 1013.
  • the etch stop layer 1013 may include a material having etch selectivity with respect to the semiconductor layer 1015 and the substrate 1001, such as SiGe (for example, Ge atomic percentage is about 20%-50%), and the thickness is, for example, about 1 nm-3 nm.
  • the etching stop layer 1013 may also be omitted.
  • the top end of the semiconductor layer 1015 may have a small bent portion.
  • a bent portion at the top of the semiconductor layer 1015 can be removed.
  • the trench T formed with the etch stop layer 1013 and the semiconductor layer 1015 may be filled with the first sacrificial layer 1017 to shield the lower portion of the semiconductor layer 1015 and expose the top portion thereof. This filling can be done by deposition, planarization such as CMP and then etch back.
  • the first sacrificial layer 1017 may include a material similar to or the same as that of the etch stop layer 1013, so that the same etching recipe can have similar or similar materials.
  • the same etch selectivity For example, the first sacrificial layer 1017 may include SiGe, where the atomic percentage of Ge is substantially the same as or close to that of the etch stop layer 1013, which is about 20%-50%.
  • the portion of the semiconductor layer 1015 exposed by the first sacrificial layer 1017 can be removed by selective etching such as RIE.
  • the semiconductor layer 1015 is U-shaped. In the case where the top surface of the first sacrificial layer 1017 is substantially flat, the top of the U-shaped semiconductor layer 1015 may be at substantially the same height.
  • Such a U-shaped semiconductor layer 1015 can be used as a channel portion of a semiconductor device.
  • the two vertically extending portions (the portions extending on the sidewalls of the trench T1) of the U-shaped semiconductor layer 1015 can be used as active fins of the device, and the resulting semiconductor device can be called a dual-fin field Effect transistor (DFFET).
  • the two active fins may be connected to each other through the laterally extending portion (the portion extending on the bottom surface of the trench T1) of the U-shaped semiconductor layer 1015, and the laterally extending portion may also be referred to as connecting nanosheets, and It can also be used as a channel part of a semiconductor device.
  • a gate stack surrounding the U-shaped semiconductor layer 1015 may be formed.
  • the gate stack may be formed by a replacement gate process.
  • a sacrificial gate surrounding the U-shaped semiconductor layer 1015 may be formed. That is, sacrificial gates may be formed on the left and right sides and above and below the U-shaped semiconductor layer 1015.
  • a sacrificial layer 1019 may be further filled. Likewise, this filling can be performed by deposition, planarization such as CMP and then etch back.
  • the sacrificial layer 1019 may include a material similar to or the same as that of the first sacrificial layer 1017, so as to subsequently have similar or the same etching selectivity for the same etching recipe.
  • the sacrificial layer 1019 may include SiGe, where the atomic percentage of Ge is substantially the same as or close to that of the first sacrificial layer 1017, which is about 20%-50%.
  • the sacrificial layer 1019 in the trench T1 and the first sacrificial layer 1017 together may substantially define the sacrificial gate above the U-shaped semiconductor layer 1015, and they may be processed together (for example, removed together) in a subsequent process, so that in the following drawings They are shown as a whole in, and they are collectively referred to as the first sacrificial layer.
  • the sacrificial gates formed on the left and right sides and above and below the U-shaped semiconductor layer 1015 may include the same or similar materials, And can use the same etching recipe to remove.
  • a protective plug may be formed on the top of the first sacrificial layer in the trench T1.
  • a protective material layer 1021 may be formed on the substrate by, for example, deposition.
  • the protective material layer 1021 may include a material having an etch selectivity with respect to the hard mask layer 1009+1011 (and the first sacrificial layer), such as SiC.
  • the protective material layer 1021 is formed to fill the trench T1, but there are undulations on its top surface due to the contours of the layers below it.
  • the present disclosure is not limited to this.
  • the protective material layer 1021 may be formed thick enough so that its top surface is substantially flat. Then, as shown in FIG.
  • the protective material layer 1021 can be etched back to remove the parts located on the top surfaces of the first sub-hard mask layer 1009 and the second sub-hard mask layer 1011, and the portions located in the trench T1 A part can be retained to form a protective plug (still marked as 1021). Likewise, there may be undulations on the top surface of the protective plug 1021, but the present disclosure is not limited thereto.
  • the U-shaped semiconductor layer 1015 (or trench T1) can be located on opposite sides of the U-shaped semiconductor layer 1015 (or trench T1) in the second direction (the horizontal direction on the paper in the figure) intersecting (for example, vertical) with the first direction, respectively.
  • Form a processing channel
  • the second sub-hard mask layer 1011 and the etching stop layer 1003 below it can be removed by selective etching such as RIE, and the substrate 1001 exposed thereby can be selectively etched. Etch such as RIE to form trench T2. Therefore, for each U-shaped semiconductor layer 1015, one side thereof is exposed in the trench T2, while the other side is still connected to the substrate 1001, thereby maintaining mechanical stability.
  • a photoresist can be formed on the hard mask layer, and the photoresist can be patterned to shield the hard mask layer.
  • the first sub-hard mask layer 1009 is located And expose the position of the second sub-hard mask layer 1011 in this embodiment in the hard mask layer, and use the photoresist patterned in this way as a mask to selectively etch the hard mask layer, To expose the underlying substrate. It can be seen that a mask step has been added.
  • the substrate 1001 can be further selectively etched, and the etching formula used can have lateral etching characteristics, for example, isotropic etching such as wet etching using TMAH solution to make
  • the trench T2 extends below the U-shaped semiconductor layer 1015 (or trench T1) in the second direction to form an undercut.
  • the degree of undercut (or the degree to which the trench T2 laterally expands from one side wall of the trench T1 to the other side wall of the trench T1) may be smaller than the width w of the trench T1 (so that the width w of the trench T1 is formed therein)
  • the bottom surface of the trench T1 with the etch stop layer 1013, the semiconductor layer 1015 and the first sacrificial layer will not be completely suspended, thereby maintaining mechanical stability), and may be greater than w/2 (so that when the trench is formed on the other side, The semiconductor layer 1015 can be fully supported).
  • sacrificial gates can be formed on one side (and below) of each trench T1.
  • an isolation layer 1023 may be formed at the bottom of the trench T2.
  • the isolation layer 1023 may include a suitable dielectric material, such as oxide.
  • the isolation layer 1023 may be formed by deposition, planarization such as CMP and then etch back.
  • the etching recipe used in the etch back may have lateral etching characteristics such as isotropic etching, so that under the trench T1, the top surface of the isolation layer 1023 can be at a certain distance from the bottom surface of the trench T1, so that the trench T1
  • the bottom surface of the trench T1 is not covered by the isolation layer 1023 (but is covered by a second sacrificial layer formed later).
  • the second sacrificial layer 1025 may be further filled. Likewise, this filling can be done by deposition, planarization such as CMP and then etch back.
  • the second sacrificial layer 1025 may substantially define one side of the U-shaped semiconductor layer 1015 and the sacrificial gate below a part of the bottom surface, and may include materials similar to or the same as the first sacrificial layer, so that subsequent etching recipes may have similar or similar materials. The same etch selectivity.
  • the second sacrificial layer 1025 may include SiGe, where the atomic percentage of Ge is substantially the same as or close to that of the first sacrificial layer, and is about 20%-50%.
  • the etch stop layer 1013, the first sacrificial layer, and the second sacrificial layer 1025 of similar or the same material can be processed together. '.
  • each U-shaped semiconductor layer 1015 in the second direction Similar processing can be performed.
  • the first sub-hard mask layer 1009 and the etching stop layer 1003 below it can be removed by selective etching such as RIE, and the substrate 1001 exposed thereby can be selectively etched. Etch such as RIE to form trench T3.
  • the sidewalls of the first sacrificial layer in the trench T1 and the second sacrificial layer (marked as 1025′ in FIG. 15) and the sidewalls of the isolation layer 1023 may be exposed. Since the undercut> w/2 as described above, most of the bottom surface of the structure in the trench T1 can be supported, thereby enhancing the mechanical stability.
  • a photoresist can be formed on the hard mask layer, and the photoresist can be patterned to shield the hard mask layer where the second sub-hard mask layer 1011 is located in this embodiment. And expose the position of the first sub-hard mask layer 1009 in this embodiment in the hard mask layer, and use the photoresist patterned in this way as a mask to selectively etch the hard mask layer, To expose the underlying substrate. It can be seen that a mask step has been added.
  • an isolation layer such as oxide may be formed at the bottom of the trench T3.
  • the formation of the isolation layer can refer to the previous description in conjunction with FIG. 14.
  • the isolation layer formed here and the previously formed isolation layer 1023 may be connected to each other, and they are shown as one body here, and are collectively designated as 1023'.
  • the top surface of the exposed portion of the isolation layer 1023' may be substantially at the same height, but the present disclosure is not limited thereto.
  • the protective plug 1021 may become substantially coplanar with the sacrificial layer 1025'.
  • the third sacrificial layer 1027 can be further filled. Likewise, this filling can be done by deposition, planarization such as CMP and then etch back.
  • the third sacrificial layer 1027 may substantially define the other side of the U-shaped semiconductor layer 1015 and the sacrificial gate below the bottom surface of the remaining part, and may include materials similar to or the same as those of the first sacrificial layer and the second sacrificial layer, so that the same
  • the etching recipe can have similar or the same etching selectivity.
  • the third sacrificial layer 1027 may include SiGe, where the atomic percentage of Ge is substantially the same as or close to that of the first sacrificial layer and the second sacrificial layer, and is about 20%-50%.
  • the sacrificial layer 1025' may also be etched back to a certain extent, and its top surface may be substantially coplanar with the top surface of the third sacrificial layer 1027.
  • the third sacrificial layer 1027 and the previously formed sacrificial layer 1025 ′ surround the U-shaped semiconductor layer to form a sacrificial gate, and the sacrificial gate is electrically isolated from the substrate 1001 by the isolation layer 1023 ′.
  • the third sacrificial layer 1027 and the previously formed sacrificial layer 1025' are shown as one body, and are labeled as 1027' together.
  • the protective plug 1021 can be removed by selective etching such as RIE.
  • a planarization process such as CMP may be performed to make its top surface flat.
  • a material having an etching selectivity similar to or the same as that of the sacrificial gate 1027' (for example, SiGe with similar or the same Ge atomic percentage) may be deposited to increase the height of the sacrificial gate 1027'.
  • a hard mask layer 1029 may be formed by, for example, deposition to facilitate subsequent patterning of the sacrificial gate 1027'.
  • the hard mask layer 1029 may include nitride, and the thickness is, for example, about 50 nm-150 nm.
  • the sacrificial gate 1027' may be patterned into a strip shape extending in the second direction, thereby forming the sacrificial gate.
  • a photoresist 1031 may be formed on the hard mask layer 1029 and patterned into a stripe shape extending in the second direction. Then, as shown in FIGS.
  • the photoresist 1031 can be used as a mask, and the hard mask layer 1029, the sacrificial gate 1027', and the semiconductor layer 1015 can be selected in sequence by selective etching such as RIE. ⁇ etching.
  • the sacrificial gate 1027' may be patterned into a strip shape extending in the second direction. The etching can stop at the isolation layer 1023' of oxide. After that, the photoresist 1031 may be removed.
  • Gate sidewall spacers can be formed on the sidewalls of the sacrificial gate 1027'.
  • the sacrificial gate 1027' (relative to the semiconductor layer 1015) can be recessed to a certain depth in the lateral direction by selective etching.
  • atomic layer etching ALE
  • a dielectric material may be filled to form a gate spacer 1033.
  • Such filling can be formed, for example, by depositing a nitride with a thickness of about 2 nm-5 nm, and then performing RIE on the deposited nitride (until the surface of the semiconductor layer 1015 is exposed).
  • the hard mask layer 1029 which is also nitride, and the gate spacers on the sidewalls of the sacrificial gate 1027' can be integrated, and are therefore marked as 1029'.
  • the gate spacer 1033 can be formed on the sidewall of the sacrificial gate 1027 ′ in a self-aligned manner, instead of being formed on the sidewall of the semiconductor layer 1015.
  • the gate spacer 1033 may have a substantially uniform thickness, which thickness depends on the depth of the above-mentioned recess, for example.
  • the outer sidewalls of the gate sidewall spacer 1033 and the outer sidewalls of the semiconductor layer 1015 can be substantially vertically aligned, and the inner sidewalls of the gate sidewall 1033 can be substantially aligned in the vertical direction (by controlling various locations when forming the recesses).
  • the etching depth is basically the same to achieve).
  • source/drain portions connected to the sidewalls of the semiconductor layer 1015 may be formed on both sides of the sacrificial gate 1027'.
  • the source/drain portion 1035 can be formed by, for example, epitaxial growth.
  • the source/drain portion 1035 may be grown from the sidewall of the exposed semiconductor layer 1015.
  • the grown source/drain portion 1035 is in contact with the sidewall of the semiconductor layer 1015.
  • the source/drain portion 1035 can be doped in situ to the conductivity type corresponding to the device to be formed during growth, for example, n-type for n-type devices, p-type for p-type devices, and the doping concentration may be about 1E19- 1E21cm-3.
  • the grown source/drain portion 1035 may have a different material from the semiconductor layer 1015 (for example, have a different lattice constant) in order to apply stress to the semiconductor layer 1015.
  • the source/drain portion 1035 may include Si:C (the atomic percentage of C is, for example, about 0.1%-5%); for a p-type device, the source/drain portion 1049 may include SiGe (atomic percentage of Ge is, for example, About 20%-75%).
  • the source/drain portions can be grown separately for the n-type device and the p-type device.
  • the area of another type of device can be shielded by a shielding layer such as photoresist.
  • an interlayer dielectric layer can be formed by, for example, deposition and then planarization (until the sacrificial gate 1027' is exposed).
  • the interlayer dielectric layer may include an oxide, so the isolation layer 1023 ′ of the oxide formed before may be shown as a single body and designated as 1037 together.
  • the same source/drain portion 1035 is connected to the semiconductor layer 1015 on opposite sides. That is, the devices on these two sides are currently electrically connected together. According to the design layout, electrical isolation between devices can be performed.
  • a photoresist 1039 can be formed on the isolation layer 1037 and patterned to shield one or more sacrificial gates 1027' and expose other sacrificial gates 1027' .
  • the sacrificial gate 1027' in the middle is shielded, and the sacrificial gates 1027' on both sides are exposed.
  • the exposed sacrificial gate 1027 ′ and the semiconductor layer 1015 underneath it can be selectively etched by, for example, RIE (which can be stopped at the isolation layer 1037), thereby leaving a space between the gate spacers 1033.
  • the photoresist 1039 may be removed. As shown in FIGS.
  • the remaining space may be filled with a dielectric material such as oxide to form an isolation portion between devices.
  • This filling may include deposition and then planarization.
  • the isolation part may extend between the side walls 1033.
  • the sidewall spacers 1033 on both sides of the isolation part are no longer used to define the gate stack, and thus can be referred to as dummy gate sidewall spacers.
  • the formed isolation portion and the previously formed isolation layer 1037 both include oxide, so they can be shown as one body, and are labeled 1037' together.
  • the sacrificial gate 1027' can be replaced with a gate stack to complete the device manufacturing.
  • the sacrificial gate 1027' can be removed by selective etching (as described above, the different parts formed in the sacrificial gate 1027' are the same as the above-mentioned first sacrificial layer ,
  • the second sacrificial layer and the third sacrificial layer may include similar or identical materials, and may be etched by the same etching recipe), thereby forming a gate trench T4 inside the gate spacer 1033, which may be formed in the gate trench T4 Grid stack.
  • a gate dielectric layer 1041 and a gate conductor layer 1043 can be deposited in the gate trench T4 in sequence.
  • the gate dielectric layer 1041 may be formed in a substantially conformal manner, with a thickness of, for example, about 2 nm-5 nm, and may include a high-k gate dielectric such as HfO 2 .
  • an interface layer may also be formed, for example, an oxide formed by an oxidation process or deposition such as atomic layer deposition (ALD), with a thickness of about 0.2-2 nm.
  • the gate conductor layer 1043 may include a work function adjusting metal such as TiN, TaN, etc. and a gate conductive metal such as W, etc.
  • the deposited gate dielectric layer 1041 and the gate conductor layer 1043 may be planarized, such as CMP, to remain in the gate trench T4.
  • a p-type device and an n-type device are formed on the substrate at the same time, different gate stacks can be formed for the p-type device and the n-type device, for example, they have different work functions.
  • the device area of this type can be masked by a masking layer such as photoresist, and the first gate stack existing in the other type of device area can be removed (only the gate conductor layer can be removed). ), and then form a second gate stack for the other type of device.
  • the gate stack is located inside the gate spacer 1033 and surrounds each semiconductor layer 1015.
  • the semiconductor layer 1015 is respectively connected to the source/drain portions 1035 on both sides, and a channel is formed between the source/drain portions 1035, similar to a fin in a FinFET.
  • the mechanical stability can be improved, and the fins can be prevented from collapsing or sticking, which is beneficial to improve the yield rate.
  • the fins are connected to each other by connecting nanosheets, and the connecting nanosheets are also used as a channel part, so that the device area can be fully utilized.
  • the semiconductor layer 1015 serving as the channel portion is formed by epitaxial growth, so its thickness can be well controlled.
  • a different semiconductor material for example, a semiconductor material different from the substrate 1001
  • the epitaxially grown semiconductor layer 1015 is very thin, which is caused by lattice mismatch. Fewer defects.
  • the gate stacks of the current devices are continuous with each other, so that the respective gates of these devices are electrically connected to each other. According to the design layout, electrical isolation between devices can be performed.
  • a photoresist (not shown) may be formed on the isolation layer 1037' to expose the gate stack between the device regions that need to be isolated, while shielding the rest of the gate stack .
  • the exposed gate stack (especially the gate conductor layer) may be selectively etched such as RIE, and the etching may be stopped at the gate dielectric layer (or at the isolation layer 1037' below).
  • a dielectric material 1045 such as oxide may be filled. The filling of the dielectric material 1045 may include deposition and then planarization.
  • the semiconductor device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, it is possible to form an integrated circuit (IC) based on such a semiconductor device, and thereby construct an electronic device. Therefore, the present disclosure also provides an electronic device including the above-mentioned semiconductor device.
  • the electronic device may also include components such as a display screen matched with an integrated circuit and a wireless transceiver matched with an integrated circuit.
  • Such electronic devices are for example smart phones, computers, tablet computers (PCs), artificial intelligence devices, wearable devices, mobile power supplies, and so on.
  • a manufacturing method of a system on chip is also provided.
  • the method may include the method described above.
  • a variety of devices can be integrated on the chip, at least some of which are manufactured according to the method of the present disclosure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

公开了一种具有U形结构的半导体器件及其制造方法以及包括这种半导体器件的电子设备。根据实施例，半导体器件可以包括：沿相对于衬底的竖直方向延伸、且彼此对置的第一鳍片和第二鳍片；连接纳米片，将第一鳍片和第二鳍片的底端相连接，从而形成U形结构，其中，连接纳米片与衬底的顶面间隔开。

Description

具有U形结构的半导体器件及其制造方法及电子设备
相关申请的引用
本申请要求于2020年4月23日递交的题为“具有U形结构的半导体器件及其制造方法及电子设备”的中国专利申请202010329915.2的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，更具体地，涉及具有U形结构的半导体器件及其制造方法以及包括这种半导体器件的电子设备。
背景技术
提出了各种不同的结构来应对半导体器件进一步小型化的挑战，例如鳍式场效应晶体管(FinFET)以及多桥沟道场效应晶体管(MBCFET)。但是FinFET和MBCFET的进一步缩小受限。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种具有U形结构的半导体器件及其制造方法以及包括这种半导体器件的电子设备。
根据本公开的一个方面，提供了一种半导体器件，包括：沿相对于衬底的竖直方向延伸、且彼此对置的第一鳍片和第二鳍片；连接纳米片，将第一鳍片和第二鳍片的底端相连接，从而形成U形结构，其中，连接纳米片与衬底的顶面间隔开。
根据本公开的另一方面，提供了一种制造半导体器件的方法，包括：在衬底中形成沿第一方向延伸的第一沟槽，第一沟槽包括彼此相对的、沿第一方向延伸的侧壁和连接侧壁的底面；在第一沟槽中形成沿侧壁和底面延伸的半导体层；在形成有半导体层的第一沟槽中填充第一牺牲层；在填充有第一牺牲层的第一沟槽在与第一方向相交的第二方向上的第一侧，形成进入衬底中、沿第一方向延伸的第二沟槽，第二沟槽在第二方向上延伸到第一沟槽的底面下方，但 第一沟槽中的半导体层和第一牺牲层保持在第一沟槽的在第二方向上与第一侧相对的第二侧仍然连接至衬底；在第二沟槽中形成第二牺牲层；在填充有第一牺牲层的第一沟槽的第二侧，形成进入衬底中、沿第一方向延伸的第三沟槽，第三沟槽在第二方向上延伸到第一沟槽的底面下方直至第二牺牲层；在第三沟槽中填充第三牺牲层，从而半导体层被第一牺牲层、第二牺牲层和第三牺牲层围绕，第一牺牲层、第二牺牲层和第三牺牲层能够相对于半导体层被选择性刻蚀。
根据本公开的另一方面，提供了一种电子设备，包括上述半导体器件。
根据本公开的实施例，半导体器件可以具有两个鳍片，且因此形成双鳍场效应晶体管(DFFET)。另外，两个鳍片之间可以通过连接纳米片彼此连接，由此形成U形结构。这可以提供高性能和高集成度。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至29(b)示出了根据本公开实施例的制造半导体器件的流程中部分阶段的示意图，
其中，图1至18、28(a)、29(a)是沿AA′线的截面图；
图19、20(b)、28(d)、29(b)是俯视图，图19的俯视图中示出了AA′线、BB′线、CC′线的位置；
图20(a)、21、22(a)、23、24(a)、25(a)、26(a)、27(a)、28(b)是沿BB′线的截面图；
图22(b)、24(b)、25(b)、26(b)、27(b)、28(c)是沿CC′线的截面图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，提出了一种半导体器件。该半导体器件可以具有U形结构。U形结构可以包括沿相对于衬底的竖直方向(例如，大致垂直于衬底面的方向)延伸的两个鳍片以及将这两个鳍片的底端彼此连接的连接纳米片。连接纳米片可以与衬底间隔开。于是，当这样的U形结构用作沟道部时，可以形成环绕栅。
如下所述，这种U形结构可以利用衬底中的沟槽为模板来制作。例如，可以通过在沟槽的侧壁和底面上外延生长半导体层，来形成这种U形结构。于是，U形结构可以是一体的，并且可以具有实质上均匀的厚度。沟槽的底面可以实质上平行于衬底的顶面，于是在沟槽的底面上形成的连接纳米片可以实质上平行于衬底的顶面。在同一沟槽中形成的半导体层可以在沟槽的纵向延伸方向(“第一方向”)上分离为若干部分，并分别用于相应的半导体器件。于是，在第一方向上相邻的半导体器件各自的U形结构可以彼此对准，例如各自的竖直鳍片可以实质上共面，各自的连接纳米片可以实质上共面。
这种U形结构可以用作沟道部，于是该半导体器件可以成为双鳍场效应晶体管(DFFET)。这种情况下，该半导体器件还可以包括在第一方向上处于U形结构相对两侧的源/漏部。U形结构连接在相对两侧的源/漏部之间，其中可以形成源/漏部之间的导电沟道。源/漏部可以包括与沟道部相同的材料，也可以包括不同的材料从而例如向沟道部施加应力以增强器件性能。
U形结构可以包括单晶半导体材料，以改善器件性能。当然，源/漏部也 可以包括单晶半导体材料。
该半导体器件还可以包括与沟道部相交的栅堆叠。栅堆叠可以沿与第一方向相交(例如垂直)的第二方向延伸。如上所述，由于U形结构与衬底间隔开，于是栅堆叠可以围绕U形结构，并在其中限定沟道区。
栅堆叠在第一方向上的相对两侧的侧壁上可以形成有栅侧墙。栅堆叠可以通过栅侧墙与源/漏部相隔。栅侧墙面向各源/漏部的外侧壁在竖直方向上可以实质上共面，并可以与U形结构的侧壁实质上共面。栅侧墙面向栅堆叠的内侧壁在竖直方向上可以实质上共面，从而栅堆叠可以具有实质上均匀的栅长。栅侧墙可以具有实质上均匀的厚度。
这种半导体器件例如可以如下制造。
可以在衬底中形成沿第一方向延伸的第一沟槽，用作如上所述的用于形成半导体层的模板。更具体地，第一沟槽可以包括彼此相对、沿第一方向延伸的侧壁和连接侧壁的底面。可以在第一沟槽的侧壁和底面上形成半导体层，于是半导体层可以包括沿第一沟槽的侧壁延伸的部分(竖直鳍片)和沿第一沟槽的底面延伸的部分(连接纳米片)。可以在第一沟槽中填充第一牺牲层以覆盖半导体层，从而基本上限定半导体层上方的牺牲栅。
在形成有半导体层并填充有第一牺牲层的第一沟槽在与第一方向相交(例如，垂直)的第二方向上的一侧，可以形成沿第一方向延伸的第二沟槽，第二沟槽可以在第二方向上延伸到第一沟槽的底面下方。可以在第二沟槽中填充第二牺牲层，从而可以在半导体层的这一侧以及底面下方限定牺牲栅。在形成第二沟槽时，第一沟槽中形成的半导体层和填充的第一牺牲层可以在第二方向上的另一侧保持连接到衬底，以防止半导体层坍塌。
类似地，在形成有半导体层并填充有第一牺牲层的第一沟槽在第二方向上的另一侧，可以形成沿第一方向延伸的第三沟槽，第三沟槽可以在第二方向上延伸到第一沟槽的底面下方直至第二牺牲层。可以在第三沟槽中填充第三牺牲层，从而可以在半导体层的该另一侧以及底面下方限定牺牲栅。由于第三沟槽延伸直至第二牺牲层，因此第三沟槽中填充的第三牺牲层可以与第二牺牲层相连接。此外，第二沟槽和第三沟槽可以沿着第一沟槽的侧壁形成，因此第二沟槽中的第二牺牲层、第三沟槽中的第三牺牲层可以与第一沟槽中的第一牺牲层 相连接。于是，第一牺牲层、第二牺牲层和第三牺牲层可以彼此连接而环绕半导体层，并因此可以成为牺牲栅。牺牲栅相对于半导体层可以具有刻蚀选择性，以便随后被替换为栅堆叠。
为使栅堆叠与衬底电隔离，可以在牺牲栅与衬底之间设置隔离层。例如，在第二沟槽和第三沟槽中分别填充第二牺牲层和第三牺牲层之前，可以先形成一定厚度的隔离层。第二沟槽和第二沟槽中形成的隔离层可以彼此连接，从而介于牺牲栅与衬底之间。
可以将牺牲栅构图为沿第二方向延伸的条形。可以牺牲栅为掩模对半导体层进行构图，使其留于牺牲栅下方从而用作沟道部。在衬底上该半导体层在第一方向上的相对两侧，可以通过例如外延生长来形成与半导体层相接的源/漏部。可以通过替代栅工艺，将牺牲栅替换为真正的栅堆叠。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1至29(b)示出了根据本公开实施例的制造半导体器件的流程中部分阶段的示意图。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
如上所述，可以在衬底1001中形成沟槽，以用作形成U形结构的模板。为形成沟槽，可以在衬底1001上形成硬掩模层，并在硬掩模层中限定开口，可以利用硬掩模层中的开口来在衬底1001中限定沟槽。另外，在基于U形结构(例如，用作沟道部)制作半导体器件期间，需要在U形结构的相对两侧中的每一侧分别形成加工通道(在一侧通过相应加工通道进行处理时，另一侧 保持连接至衬底，以避免U形结构坍塌)。为减少掩模步骤的数量以及实现自对准掩模，根据本公开的实施例，可以利用相对于彼此具有刻蚀选择性的不同材料来分别形成硬掩模层位于开口相对两侧的部分。
根据本公开的实施例，可以结合侧墙(spacer)形成工艺来设置符合上述条件的硬掩模层。例如，侧墙可以形成在芯模(mandrel)图案的侧壁上。于是，侧墙的一侧是芯模图案(作为硬掩模层的一部分)，而侧墙的另一侧可以形成相对于芯模图案具有刻蚀选择性的材料(作为硬掩模层的另一部分)。于是，芯模图案加上所述材料可以构成硬掩模层，而通过去除侧墙可以在如此的硬掩模层中限定开口，且开口两侧的硬掩模层部分相对于彼此可以具有刻蚀选择性。此外，通过利用侧墙限定开口，可以更好地控制开口的宽度及由此得到的沟槽的宽度。
例如，可以在衬底上通过例如淀积，依次形成刻蚀停止层1003和芯模层1005。刻蚀停止层1003相对于衬底1001和芯模层1005可以具有刻蚀选择性，例如包括氧化物(例如，氧化硅)，厚度为例如约2nm-10nm。芯模层1005可以包括多晶硅，以实现良好的刻蚀质量，厚度为例如约50nm-150nm。然后，如图2所示，可以利用光刻胶(未示出)，对芯模层1005进行选择性刻蚀如反应离子刻蚀(RIE)，以形成芯模图案(仍然标示为1005)。在此，RIE可以沿着竖直方向(例如，大致垂直于衬底1001表面的方向)，从而芯模图案1005可以具有竖直的侧壁。芯模图案1005可以具有沿第一方向(图中进入纸面的方向)延伸的条状。从而其侧壁可以沿第一方向延伸。RIE可以停止于刻蚀停止层1003。之后，可以去除光刻胶。
如图3所示，可以在芯模图案1005的侧壁上形成侧墙1007。侧墙的形成可以包括基本共形地形成例如淀积侧墙材料层，并对形成的侧墙材料层进行各向异性刻蚀如沿竖直方向的RIE(可以停止于刻蚀停止层1003)。可以根据要形成的沟槽的宽度(图中水平方向上的尺度)来确定侧墙1007的厚度(图中水平方向上的尺度)或者淀积的侧墙材料层的厚度。作为示例，淀积的侧墙材料层的厚度可以为约10nm-25nm。侧墙1007可以包括相对于芯模图案1005(和刻蚀停止层1003)具有刻蚀选择性的材料，例如SiC。
如图4所示，可以在衬底1001上形成第一子硬掩模层1009。第一子硬掩 模层1009可以与芯模图案1005(随后被替换为第二子硬掩模层1011，参见图5)一起限定硬掩模层。如上所述，第一子硬掩模层1009可以包括相对于侧墙1009以及芯模图案1005(或者，随后将之替换的第二子硬掩模层1011)具有刻蚀选择性的材料，例如氮化物(例如，氮化硅)。例如，可以通过淀积约50nm-150nm的氮化硅，并对淀积的氮化硅进行平坦化处理如化学机械抛光(CMP)直至露出侧墙1007、芯模图案1005，来形成氮化物层1009。
为避免以下在对衬底1001(在该示例中，Si)进行刻蚀来形成沟槽的过程中对芯模图案1005(在该示例中，多晶硅)刻蚀而导致硬掩模层损坏，可以将芯模图案1005替换为其他材料。如图5所示，可以通过刻蚀、淀积然后平坦化，将多晶硅的芯模图案1005替换为例如氧化物的第二子硬掩模层1011，其与第一子硬掩模层1009一起限定硬掩模层。
对于芯模图案1005的替换处理在某些情况下可以省略，例如在使用氧化物作为芯模图案1005的情况下(使用多晶硅作为芯模图案1005是为了实现更好的刻蚀质量)。
如图5所示，第一子硬掩模层1009和第二子硬掩模层1011一起构成硬掩模层，且其中嵌入有侧墙1007。这种形式的硬掩模层可以节省掩模步骤的数量，并且可以实现自对准掩模从而节省面积，这将在下面进一步详细描述。
如图6所示，可以通过选择性刻蚀，去除侧墙1007，于是在硬掩模层1009+1011中形成了开口，这些开口的宽度(图中水平方向上的尺度)由侧墙1007的宽度限定。以具有开口的硬掩模层1009+1011作为刻蚀掩模，依次对刻蚀停止层1003和衬底1001进行选择性刻蚀如沿竖直方向的RIE，以在衬底1001中形成沟槽T1。在此，在对刻蚀停止层1003进行刻蚀时，第二子硬掩模层1011(在该示例中，与刻蚀停止层1003同为氧化物)的高度可以降低。沟槽T1的宽度(图中水平方向上的尺度)可以由硬掩模层中的开口或者说侧墙1007的宽度限定。
沟槽T1的侧壁和底面提供了形成U形结构的模板。例如，如图7所示，可以在沟槽T1的侧壁和底面上例如通过外延生长来形成半导体层1015，得到U形纳米片。在此，以硅工艺为例进行描述，即半导体层1015包括Si。为了在以下提供刻蚀选择性(特别是在对衬底1001进行刻蚀时)，在形成半导体层 1015之前，可以在沟槽T1的侧壁和底面上例如通过外延生长来形成刻蚀停止层1013，半导体层1015可以在刻蚀停止层1013的表面上生长。刻蚀停止层1013可以包括相对于半导体层1015和衬底1001具有刻蚀选择性的材料，例如SiGe(例如，Ge原子百分比为约20％-50％)，厚度为例如约1nm-3nm。当然，在半导体层1015相对于衬底1001具有刻蚀选择性的情况下，也可以省略刻蚀停止层1013。
当前，半导体层1015的顶端可以具有小的弯折部分。为增强器件稳定性，可以去除半导体层1015顶端的这种弯折部分。例如，如图8所示，可以在形成有刻蚀停止层1013和半导体层1015的沟槽T中填充第一牺牲层1017，以遮蔽半导体层1015的下部而露出其顶端部分。这种填充可以通过淀积、平坦化如CMP然后回蚀来进行。考虑到在进行替代栅工艺时需要将刻蚀停止层1013一并去除，因此第一牺牲层1017可以包括与刻蚀停止层1013类似或相同的材料，以便随后对于相同刻蚀配方可以具有相似或相同的刻蚀选择性。例如，第一牺牲层1017可以包括SiGe，其中Ge的原子百分比与刻蚀停止层1013中基本相同或接近，为约20％-50％。然后，如图9所示，可以通过选择性刻蚀如RIE，去除半导体层1015被第一牺牲层1017露出的部分。于是，半导体层1015呈U形。在第一牺牲层1017的顶面基本平坦的情况下，U形半导体层1015的顶端可以处于实质上相同的高度。
这种U形半导体层1015可以用作半导体器件的沟道部。这种情况下，U形半导体层1015的两个竖直延伸部分(在沟槽T1的侧壁上延伸的部分)可以用作器件的有源鳍，于是得到的半导体器件可以称为双鳍场效应晶体管(DFFET)。另外，这两个有源鳍之间可以通过U形半导体层1015的横向延伸部分(在沟槽T1的底面上延伸的部分)而彼此连接，该横向延伸部分也可称作连接纳米片，并同样可用作半导体器件的沟道部。
为充分利用U形半导体层1015的各部分，可以形成围绕U形半导体层1015的栅堆叠。栅堆叠可以通过替代栅工艺形成。在替代栅工艺中，可以形成围绕U形半导体层1015的牺牲栅。也即，牺牲栅可以形成在U形半导体层1015的左侧和右侧以及上方和下方。
例如，如图9所示，在沟槽T1中，可以进一步填充牺牲层1019。同样， 这种填充可以通过淀积、平坦化如CMP然后回蚀来进行。该牺牲层1019可以包括与第一牺牲层1017类似或相同的材料，以便随后对于相同刻蚀配方可以具有相似或相同的刻蚀选择性。例如，该牺牲层1019可以包括SiGe，其中Ge的原子百分比与第一牺牲层1017中基本相同或接近，为约20％-50％。沟槽T1中的牺牲层1019与第一牺牲1017一起可以大致限定了U形半导体层1015上方的牺牲栅，它们在后继工艺中可以一起被处理(例如，被一起去除)，从而在以下附图中将它们示出为一体，并将它们统称为第一牺牲层。
为在U形半导体层1015的左侧、右侧和下方形成牺牲栅，需要进入U形半导体层1015左侧、右侧和下方的加工通道。如上所述，这样的加工通道可以通过第一子硬掩模层1009和第二子硬掩模层1011来分别限定。另外，为了替代栅工艺的方便，在U形半导体层1015的左侧和右侧以及上方和下方形成的牺牲栅(上方的牺牲栅包括上述的第一牺牲层)可以包括相同或相似的材料，并可以利用相同的刻蚀配方来去除。为避免在U形半导体层1015左侧、右侧和下方形成牺牲栅的过程中对第一牺牲层造成影响，可以在沟槽T1中第一牺牲层的顶部形成保护插塞。
例如，如图10所示，可以通过例如淀积，在衬底上形成保护材料层1021。保护材料层1021可以包括相对于硬掩模层1009+1011(以及第一牺牲层)具有刻蚀选择性的材料，例如SiC。在此，示出了保护材料层1021形成为填满沟槽T1，但其顶面上存在由于其下方各层的轮廓而导致的起伏。但是，本公开不限于此，例如保护材料层1021可以形成得足够厚，从而其顶面大致平坦。然后，如图11所示，可以对保护材料层1021回蚀，去除其位于第一子硬掩模层1009和第二子硬掩模层1011顶面上的部分，而位于沟槽T1中的一部分可以得以保留，形成保护插塞(仍然标示为1021)。同样地，保护插塞1021的顶面上可以存在起伏，但是本公开不限于此。
接下来，可以在U形半导体层1015(或者说，沟槽T1)在与第一方向相交(例如，垂直)的第二方向(图中纸面上的水平方向)上的相对两侧，分别形成加工通道。
例如，如图12所示，可以通过选择性刻蚀如RIE，去除第二子硬掩模层1011及其下方的刻蚀停止层1003，并可以对由此露出的衬底1001进行选择性 刻蚀如RIE从而形成沟槽T2。于是，对于各U形半导体层1015而言，其一侧在沟槽T2中露出，而另一侧仍然连接到衬底1001，从而保持机械稳定。
如果使用单一材料的硬掩模层，则可以在硬掩模层上形成光刻胶，并将光刻胶构图为遮蔽硬掩模层中在该实施例中第一子硬掩模层1009所在的位置，并露出硬掩模层中在该实施例中第二子硬掩模层1011所在的位置，并以如此构图的光刻胶作为掩模，对硬掩模层进行选择性刻蚀，以露出下方的衬底。可以看到，增加了掩模步骤。
另外，如图13所示，可以通过对衬底1001进一步选择性刻蚀，使用的刻蚀配方可以具有横向刻蚀特性，例如使用TMAH溶液的湿法腐蚀之类的各向同性刻蚀，使沟槽T2在第二方向上延伸到U形半导体层1015(或者说，沟槽T1)的下方，形成底切。在此，底切的程度(或者说，沟槽T2从沟槽T1的一侧侧壁向着沟槽T1的另一侧侧壁横向扩展的程度)可以小于沟槽T1的宽度w(使得其中形成有刻蚀停止层1013、半导体层1015和第一牺牲层的沟槽T1的底面不会完全悬空，从而保持机械稳定性)，并可以大于w/2(使得在另一侧形成沟槽时，半导体层1015可以得到充分的支撑)。通过这样的沟槽T2，可以在各沟槽T1的一侧(以及下方)形成牺牲栅。
考虑到栅堆叠与衬底之间的电隔离，如图14所示，在形成牺牲栅之前，可以在沟槽T2的底部先形成隔离层1023。隔离层1023可以包括合适的电介质材料，例如氧化物。隔离层1023可以通过淀积、平坦化如CMP然后回蚀来形成。在此，回蚀时使用的刻蚀配方可以具有横向刻蚀特性例如各向同性刻蚀，以使得在沟槽T1下方，隔离层1023的顶面可以距沟槽T1的底面一定距离，使得沟槽T1的底面不被隔离层1023覆盖(而是被随后形成的第二牺牲层覆盖)。然后，在底部形成有隔离层1023的沟槽T2中，可以进一步填充第二牺牲层1025。同样，这种填充可以通过淀积、平坦化如CMP然后回蚀来进行。第二牺牲层1025可以大致限定了U形半导体层1015的一侧以及部分底面下方的牺牲栅，于是可以包括与第一牺牲层类似或相同的材料，以便随后对于相同刻蚀配方可以具有相似或相同的刻蚀选择性。例如，第二牺牲层1025可以包括SiGe，其中Ge的原子百分比与第一牺牲层中基本相同或接近，为约20％-50％。
在之后的工艺中，材料相似或相同的刻蚀停止层1013、第一牺牲层和第二牺牲层1025可以被一起处理，在之后的附图中将它们示出为一体，并一起标注为1025′。
在各U形半导体层1015在第二方向上的另一侧，可以类似处理。例如，如图15所示，可以通过选择性刻蚀如RIE，去除第一子硬掩模层1009及其下方的刻蚀停止层1003，并可以对由此露出的衬底1001进行选择性刻蚀如RIE从而形成沟槽T3。在刻蚀过程中，可以使沟槽T1中的第一牺牲层以及沟槽T2中的第二牺牲层(在图15中一起标注为1025′)的侧壁以及隔离层1023的侧壁露出。由于如上所述，底切＞w/2，于是沟槽T1中结构的大部分底面可以被支撑，从而增强了机械稳定性。
如果使用单一材料的硬掩模层，则可以在硬掩模层上形成光刻胶，并将光刻胶构图为遮蔽硬掩模层中在该实施例中第二子硬掩模层1011所在的位置，并露出硬掩模层中在该实施例中第一子硬掩模层1009所在的位置，并以如此构图的光刻胶作为掩模，对硬掩模层进行选择性刻蚀，以露出下方的衬底。可以看到，增加了掩模步骤。
类似地，如图16所示，在沟槽T3底部，可以形成例如氧化物的隔离层。该隔离层的形成可以参照之前结合图14的描述。在此形成的隔离层与先前形成的隔离层1023可以彼此连接，在此将它们示出为一体，并一起标示为1023′。隔离层1023′的外露部分的顶面可以实质上处于相同高度，但本公开不限于此。另外，在形成隔离层的平坦化过程中，保护插塞1021可以变得与牺牲层1025′实质上共面。
然后，如图17所示，在底部形成有隔离层1023′的沟槽T3中，可以进一步填充第三牺牲层1027。同样，这种填充可以通过淀积、平坦化如CMP然后回蚀来进行。第三牺牲层1027可以大致限定了U形半导体层1015的另一侧以及其余部分底面下方的牺牲栅，于是可以包括与第一牺牲层、第二牺牲层类似或相同的材料，以便随后对于相同刻蚀配方可以具有相似或相同的刻蚀选择性。例如，第三牺牲层1027可以包括SiGe，其中Ge的原子百分比与第一牺牲层、第二牺牲层中基本相同或接近，为约20％-50％。另外，在形成第三牺牲层1027的回蚀过程中，牺牲层1025′也可以被回蚀一定程度，且其顶面可以 与第三牺牲层1027的顶面实质上共面。
可以看到，第三牺牲层1027与之前形成的牺牲层1025′围绕U形半导体层，构成牺牲栅，牺牲栅通过隔离层1023′与衬底1001电隔离。之后，将第三牺牲层1027与之前形成的牺牲层1025′示出为一体，且一起标示为1027′。
可以通过选择性刻蚀如RIE，去除保护插塞1021。对于露出的牺牲栅1027′，可以进行平坦化处理如CMP，以使其顶面平坦。在平坦化处理之前，可以淀积与牺牲栅1027′具有相似或相同刻蚀选择性的材料(例如，Ge原子百分比相似或相同的SiGe)，以增加牺牲栅1027′的高度。
接下来，可以进行替代栅工艺。
例如，如图18所示，在牺牲栅1027′上，可以通过例如淀积形成硬掩模层1029，以便于随后对牺牲栅1027′构图。例如，硬掩模层1029可以包括氮化物，厚度为例如约50nm-150nm。可以将牺牲栅1027′构图为沿第二方向延伸的条形，从而形成牺牲栅。例如，如图19所示，可以在硬掩模层1029上形成光刻胶1031，并将其构图为沿第二方向延伸的条形。然后，如图20(a)和20(b)所示，可以光刻胶1031作为掩模，通过选择性刻蚀如RIE依次对硬掩模层1029、牺牲栅1027′、半导体层1015进行选择性刻蚀。于是，牺牲栅1027′可以被构图为沿第二方向延伸的条状。刻蚀可以停止于氧化物的隔离层1023′。之后，可以去除光刻胶1031。
可以在牺牲栅1027′的侧壁上形成栅侧墙。例如，如图21所示，可以通过选择性刻蚀，使牺牲栅1027′(相对于半导体层1015)在横向上凹入一定深度。为了控制凹入深度，可以采用原子层刻蚀(ALE)。如图22(a)和22(b)所示，在如此形成的凹入内，可以填充电介质材料，以形成栅侧墙1033。这种填充例如可以通过淀积约2nm-5nm厚的氮化物，然后对淀积的氮化物进行RIE(直至暴露半导体层1015的表面)来形成。在此，同为氮化物的硬掩模层1029与牺牲栅1027′侧壁上的栅侧墙可以成为一体，并因此标注为1029′。
根据这种工艺，栅侧墙1033可以自对准地形成在牺牲栅1027′的侧壁上，而不会形成在半导体层1015的侧壁上。栅侧墙1033可以具有实质上均匀的厚度，该厚度例如取决于上述凹入的深度。另外，栅侧墙1033的外侧壁与半导体层1015的外侧壁可以基本上竖直对准，栅侧墙1033的内侧壁可以在竖直方 向上基本对准(通过在形成凹入时控制各处的刻蚀深度基本相同来实现)。
之后，可以在牺牲栅1027′两侧形成与半导体层1015的侧壁相接的源/漏部。
如图23所示，可以通过例如外延生长，形成源/漏部1035。源/漏部1035可以从暴露的半导体层1015的侧壁生长。生长的源/漏部1035与半导体层1015的侧壁相接。源/漏部1035在生长时可以被原位掺杂为与所要形成的器件相应的导电类型，例如对于n型器件为n型，对于p型器件为p型，掺杂浓度可以为约1E19-1E21cm-3。生长的源/漏部1035可以具有与半导体层1015不同的材料(例如，具有不同的晶格常数)，以便向半导体层1015施加应力。例如，对于n型器件，源/漏部1035可以包括Si：C(C原子百分比例如为约0.1％-5％)；对于p型器件，源/漏部1049可以包括SiGe(Ge原子百分比例如为约20％-75％)。在衬底上同时形成n型器件和p型器件的情况下，例如在CMOS工艺的情况下，可以针对n型器件和p型器件分别生长源/漏部。在生长一种类型器件的源/漏部时，可以通过遮蔽层例如光刻胶等来遮蔽另一种类型的器件区域。
在条形的牺牲栅1027′之间，除了生长的源/漏部1035之外，还存在着间隙，在这些间隙中可以填充电介质材料以形成层间电介质层。例如，如图24(a)和24(b)所示，在隔离层1023′上，可以通过例如淀积然后平坦化(直至露出牺牲栅1027′)，来形成层间电介质层。在此，层间电介质层可以包括氧化物，因此与之前形成的氧化物的隔离层1023′可以示出为一体，并一起标示为1037。
目前，同一源/漏部1035在相对两侧均连接到半导体层1015。也即，这两侧的器件当前电连接在一起。可以根据设计布局，在器件之间进行电隔离。
例如，如图25(a)和25(b)所示，可以在隔离层1037上形成光刻胶1039，并将其构图为遮蔽一个或多个牺牲栅1027′，并露出其他牺牲栅1027′。在该示例中，遮蔽了中间的牺牲栅1027′，而露出了两侧的牺牲栅1027′。可以通过例如RIE，依次对露出的牺牲栅1027′以及其下方的半导体层1015进行选择性刻蚀(可以停止于隔离层1037)，从而在栅侧墙1033之间留下了空间。之后，可以去除光刻胶1039。如图26(a)和26(b)所示，在留下的空间中，可以填充电介质材料如氧化物，以形成器件之间的隔离部。这种填充可以包括淀积且然后 平坦化。隔离部可以在侧墙1033之间延伸。隔离部两侧的侧墙1033不再用来限定栅堆叠，从而可以称为虚设栅侧墙。在该示例中，所形成的隔离部与之前形成的隔离层1037均包括氧化物，因此可以示出为一体，并一起标示为1037′。
需要指出的是，是否需要形成隔离部以及在哪些器件之间形成隔离部取决于电路设计。
在以下，仍以图24(a)和24(b)所示的情形为例进行描述，但这些描述也适用于图26(a)和26(b)所示的情形。
接下来，可以将牺牲栅1027′替换为栅堆叠，以完成器件制造。
例如，如图27(a)和27(b)所示，可以通过选择性刻蚀，去除牺牲栅1027′(如上所述，牺牲栅1027′中分别形成的不同部分如上述的第一牺牲层、第二牺牲层和第三牺牲层可以包括相似或相同的材料，并可以通过相同的刻蚀配方来刻蚀)，从而在栅侧墙1033内侧形成栅槽T4，可以在栅槽T4中形成栅堆叠。如图28(a)、28(b)、28(c)和28(d)所示，可以在栅槽T4中依次淀积栅介质层1041和栅导体层1043。栅介质层1041可以大致共形的方式形成，厚度例如为约2nm-5nm，且可以包括高k栅介质如HfO 2。在形成高k栅介质之前，还可以形成界面层，例如通过氧化工艺或淀积如原子层淀积(ALD)形成的氧化物，厚度为约0.2-2nm。栅导体层1043可以包括功函数调节金属如TiN、TaN等和栅导电金属如W等。可以对淀积的栅介质层1041和栅导体层1043进行平坦化处理如CMP，使其留于栅槽T4之内。
如果在衬底上同时形成p型器件和n型器件，则可以针对p型器件和n型器件分别形成不同的栅堆叠，例如它们各自具有不同的功函数。例如，在形成针对一种类型器件的第一栅堆叠之后，可以通过遮蔽层如光刻胶遮蔽该类型器件区域，去除另一类型器件区域中存在的第一栅堆叠(可以只去除栅导体层)，且然后形成针对该另一类型器件的第二栅堆叠。
可以看出，栅堆叠位于栅侧墙1033内侧，围绕各半导体层1015。半导体层1015在两侧分别连接源/漏部1035，在源/漏部1035之间形成沟道，类似于FinFET中的鳍片。
如上所述，在本公开的实施例中，机械稳定性可以提高，可以防止鳍片倒塌或粘连，这有利于提高良品率。鳍片之间通过连接纳米片彼此连接，该连接 纳米片也用作沟道部，于是可以充分利用器件面积。用作沟道部的半导体层1015通过外延生长形成，因此其厚度可以很好地控制。对于半导体层1015，可以使用不同半导体材料(例如，不同于衬底1001的半导体材料)，以进一步提升器件性能，这是因为外延生长的半导体层1015很薄，从而由于晶格失配而导致的缺陷较少。
另外，如图28(d)所示，当前各器件的栅堆叠彼此连续，从而这些器件各自的栅彼此电连接。可以根据设计布局，在器件之间进行电隔离。
例如，如图29(a)和29(b)所示，可以在隔离层1037′上形成光刻胶(未示出)以在需要隔离的器件区域之间露出栅堆叠，而遮蔽其余栅堆叠。之后，可以对露出的栅堆叠(特别是其中的栅导体层)进行选择性刻蚀如RIE，刻蚀可以停止于栅介质层(或者停止于下方的隔离层1037′)。在由于栅堆叠的露出部分的刻蚀而留下的空间中，可以填充电介质材料1045如氧化物。电介质材料1045的填充可以包括淀积且然后平坦化。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，可以基于这样的半导体器件形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、人工智能设备、可穿戴设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价 物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (28)

  1. 一种半导体器件，包括：
    沿相对于衬底的竖直方向延伸、且彼此对置的第一鳍片和第二鳍片；
    连接纳米片，将所述第一鳍片和所述第二鳍片的底端相连接，从而形成U形结构，
    其中，所述连接纳米片与所述衬底的顶面间隔开。
  2. 根据权利要求1所述的半导体器件，其中，所述连接纳米片实质上平行于所述衬底的顶面延伸。
  3. 根据权利要求1所述的半导体器件，其中，所述U形结构一体延伸，具有实质上均匀的厚度。
  4. 根据权利要求1所述的半导体器件，其中，所述U形结构包括与所述衬底不同的材料。
  5. 根据权利要求1所述的半导体器件，其中，所述第一鳍片和所述第二鳍片的顶面相对于所述衬底的顶面处于实质上相同的高度。
  6. 根据权利要求1所述的半导体器件，还包括：
    所述衬底上在第一方向上处于所述U形结构的相对两侧且与所述U形结构相接的源/漏部；以及
    所述衬底上沿与所述第一方向相交的第二方向延伸且与所述U形结构相交的栅堆叠。
  7. 根据权利要求6所述的半导体器件，其中，所述栅堆叠环绕所述U形结构。
  8. 根据权利要求6或7所述的半导体器件，还包括：设于所述栅堆叠与所述衬底之间的隔离层。
  9. 根据权利要求6或7所述的半导体器件，其中，在所述衬底上设置有多个所述半导体器件，所述多个半导体器件中至少一对在所述第一方向上相邻的半导体器件各自的所述第一鳍片实质上共面，各自的所述第二鳍片实质上共面，且各自的所述连接纳米片实质上共面。
  10. 根据权利要求6或7所述的半导体器件，还包括设置在所述栅堆叠的 侧壁上的栅侧墙，所述栅侧墙包括在所述U形结构之上的第一部分以及所述U形结构之下的第二部分。
  11. 根据权利要求10所述的半导体器件，其中，在所述衬底上设置有多个所述半导体器件，所述多个半导体器件中至少一对在所述第二方向上相邻的半导体器件各自的栅侧墙彼此一体连续延伸。
  12. 根据权利要求10所述的半导体器件，其中，所述栅侧墙的第一部分和第二部分具有相同的材料，并具有实质上相同的厚度。
  13. 根据权利要求10所述的半导体器件，其中，所述栅侧墙的第一部分和第二部分各自的内侧壁在竖直方向上实质上对准。
  14. 根据权利要求10所述的半导体器件，其中，
    在所述衬底上设置有多个所述半导体器件，所述多个半导体器件中在所述第一方向上相邻的半导体器件之间通过隔离部彼此电隔离，其中，所述隔离部在所述第一方向上的范围由沿所述第二方向延伸的虚设栅侧墙限定。
  15. 根据权利要求14所述的半导体器件，其中，所述半导体器件的源/漏部的顶部在所述第一方向上的范围由所述半导体器件的栅侧墙以及所述虚设栅侧墙限定。
  16. 根据权利要求6或7所述的半导体器件，其中，
    在所述衬底上设置有多个所述半导体器件，所述多个半导体器件中在所述第一方向上相邻的半导体器件之间通过隔离部彼此电隔离，其中，所述隔离部沿所述第二方向延伸。
  17. 根据权利要求16所述的半导体器件，其中，所述源/漏部沿所述第二方向延伸，
    所述半导体器件还包括：介于所述栅堆叠与所述源/漏部之间的栅侧墙以及介于所述源/漏部与所述隔离部之间的虚设栅侧墙，所述栅侧墙与所述虚设栅侧墙具有在所述第一方向上实质上相同的厚度。
  18. 根据权利要求17所述的半导体器件，还包括：与所述虚设栅侧墙在竖直方向上对准、且与所述U形结构相对应的U形结构。
  19. 一种制造半导体器件的方法，包括：
    在衬底中形成沿第一方向延伸的第一沟槽，所述第一沟槽包括彼此相对的、 沿所述第一方向延伸的侧壁和连接所述侧壁的底面；
    在所述第一沟槽中形成沿所述侧壁和所述底面延伸的半导体层；
    在形成有所述半导体层的所述第一沟槽中填充第一牺牲层；
    在填充有所述第一牺牲层的所述第一沟槽在与所述第一方向相交的第二方向上的第一侧，形成进入所述衬底中、沿所述第一方向延伸的第二沟槽，所述第二沟槽在所述第二方向上延伸到所述第一沟槽的底面下方，但所述第一沟槽中的所述半导体层和所述第一牺牲层保持在所述第一沟槽的在所述第二方向上与所述第一侧相对的第二侧仍然连接至所述衬底；
    在所述第二沟槽中形成第二牺牲层；
    在填充有所述第一牺牲层的所述第一沟槽的第二侧，形成进入所述衬底中、沿所述第一方向延伸的第三沟槽，所述第三沟槽在所述第二方向上延伸到所述第一沟槽的底面下方直至所述第二牺牲层；
    在所述第三沟槽中填充第三牺牲层，从而所述半导体层被所述第一牺牲层、所述第二牺牲层和所述第三牺牲层围绕，所述第一牺牲层、所述第二牺牲层和所述第三牺牲层能够相对于所述半导体层被选择性刻蚀。
  20. 根据权利要求19所述的方法，其中，
    在所述第二沟槽的底部形成隔离层的一部分，然后再填充所述第二牺牲层；
    在所述第三沟槽的底部形成隔离层的另一部分，然后再填充所述第三牺牲层，
    所述隔离层的一部分和另一部分彼此连接，从而介于所述衬底与所述第二牺牲层和所述第三牺牲层之间。
  21. 根据权利要求19所述的方法，其中，
    在所述第一沟槽中形成沿所述侧壁和所述底面延伸的刻蚀停止层，然后再形成所述半导体层。
  22. 根据权利要求19所述的方法，其中，填充第一牺牲层包括：
    在所述第一沟槽中填充所述第一牺牲层的一部分，使所述半导体层的顶端部露出；
    去除所述半导体层的露出的顶端部；
    在所述第一沟槽中填充所述第一牺牲层的其余部分。
  23. 根据权利要求19所述的方法，其中，所述第二沟槽暴露出的所述第一沟槽的底面在所述第二方向上的宽度小于所述第一沟槽的底面在所述第二方向上的整个宽度，但大于所述第一沟槽的底面在所述第二方向上的一半宽度。
  24. 根据权利要求20所述的方法，还包括：
    将所述第一牺牲层、所述第二牺牲层和所述第三牺牲层构图为沿所述第二方向延伸的条形牺牲栅；
    以所述牺牲栅为掩模，选择性刻蚀所述半导体层；
    在被刻蚀后的所述半导体层在所述第一方向上的相对两侧，形成用以形成源/漏部的另一半导体层；以及
    将所述牺牲栅替换为栅堆叠。
  25. 根据权利要求24所述的方法，还包括：
    选择性刻蚀所述牺牲栅，使所述牺牲栅的侧壁在所述第一方向上相对于所述半导体层的侧壁凹入；以及
    在所述牺牲栅的侧壁上形成侧墙。
  26. 根据权利要求24所述的方法，其中，形成在所述第一方向上设置的多个所述牺牲栅，该方法还包括：
    选择性刻蚀至少一个所述牺牲栅的相对两侧的两个牺牲栅中至少之一以及由此露出的所述半导体层，直至所述隔离层，以形成第四沟槽；以及
    在所述第四沟槽中填充电介质材料。
  27. 一种电子设备，包括如权利要求1至18中任一项所述的半导体器件。
  28. 根据权利要求27所述的电子设备，其中，所述电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
PCT/CN2021/082400 2020-04-23 2021-03-23 具有u形结构的半导体器件及其制造方法及电子设备 WO2021213115A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/919,652 US20230163204A1 (en) 2020-04-23 2021-03-23 Semiconductor device having u-shaped structure, method of manufacturing semiconductor device, and electronic device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010329915.2 2020-04-23
CN202010329915.2A CN111477684B (zh) 2020-04-23 2020-04-23 具有u形结构的半导体器件及其制造方法及电子设备

Publications (1)

Publication Number Publication Date
WO2021213115A1 true WO2021213115A1 (zh) 2021-10-28

Family

ID=71761703

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/082400 WO2021213115A1 (zh) 2020-04-23 2021-03-23 具有u形结构的半导体器件及其制造方法及电子设备

Country Status (3)

Country Link
US (1) US20230163204A1 (zh)
CN (1) CN111477684B (zh)
WO (1) WO2021213115A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111477684B (zh) * 2020-04-23 2024-03-15 中国科学院微电子研究所 具有u形结构的半导体器件及其制造方法及电子设备

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140239394A1 (en) * 2013-02-25 2014-08-28 International Business Machines Corporation U-shaped semiconductor structure
US20170069759A1 (en) * 2015-09-08 2017-03-09 Globalfoundries Inc. Three-dimensional finfet transistor with portion(s) of the fin channel removed in gate-last flow
CN109103254A (zh) * 2017-06-20 2018-12-28 台湾积体电路制造股份有限公司 半导体装置
CN111477684A (zh) * 2020-04-23 2020-07-31 中国科学院微电子研究所 具有u形结构的半导体器件及其制造方法及电子设备

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105932057B (zh) * 2016-06-24 2020-01-31 中国科学院微电子研究所 基于外延层的纳米线器件及其制造方法及包括其的电子设备
US10777658B2 (en) * 2018-04-17 2020-09-15 International Business Machines Corporation Method and structure of fabricating I-shaped silicon vertical field-effect transistors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140239394A1 (en) * 2013-02-25 2014-08-28 International Business Machines Corporation U-shaped semiconductor structure
US20170069759A1 (en) * 2015-09-08 2017-03-09 Globalfoundries Inc. Three-dimensional finfet transistor with portion(s) of the fin channel removed in gate-last flow
CN109103254A (zh) * 2017-06-20 2018-12-28 台湾积体电路制造股份有限公司 半导体装置
CN111477684A (zh) * 2020-04-23 2020-07-31 中国科学院微电子研究所 具有u形结构的半导体器件及其制造方法及电子设备

Also Published As

Publication number Publication date
US20230163204A1 (en) 2023-05-25
CN111477684A (zh) 2020-07-31
CN111477684B (zh) 2024-03-15

Similar Documents

Publication Publication Date Title
WO2021232916A1 (zh) 具有交错结构的半导体装置及其制造方法及电子设备
WO2021147610A1 (zh) C形沟道部半导体器件及其制造方法及包括其的电子设备
WO2021104364A1 (zh) 半导体装置及其制造方法及包括该半导体装置的电子设备
WO2021103854A1 (zh) 半导体器件及其制造方法及包括该半导体器件的电子设备
WO2021103910A1 (zh) 半导体器件及其制造方法及包括该半导体器件的电子设备
US20230317838A1 (en) Nanowire/nanosheet device having self-aligned isolation portion and method of manufacturing the same, and electronic apparatus
WO2021203901A1 (zh) 半导体器件及其制造方法及包括其的电子设备
WO2021203899A1 (zh) 半导体器件及其制造方法及包括其的电子设备
US11482627B2 (en) C-shaped active area semiconductor device, method of manufacturing the same and electronic device including the same
US11532756B2 (en) C-shaped active area semiconductor device, method of manufacturing the same and electronic device including the same
WO2021213115A1 (zh) 具有u形结构的半导体器件及其制造方法及电子设备
CN111106165B (zh) U形沟道半导体器件及其制造方法及包括其的电子设备
US11616150B2 (en) Semiconductor device with C-shaped channel portion and electronic apparatus including the same
CN115566071A (zh) 带侧墙的c形沟道部半导体器件及其制造方法及电子设备
CN111063684B (zh) 具有c形有源区的半导体装置及包括其的电子设备
CN116666439B (zh) 具有连续栅长的竖直半导体器件及其制造方法及电子设备
WO2023108885A1 (zh) 具有晶体侧墙的纳米线/片器件及制造方法及电子设备
CN117374076A (zh) 3ds fet及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21793814

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21793814

Country of ref document: EP

Kind code of ref document: A1