WO2021103854A1 - 半导体器件及其制造方法及包括该半导体器件的电子设备 - Google Patents

半导体器件及其制造方法及包括该半导体器件的电子设备 Download PDF

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WO2021103854A1
WO2021103854A1 PCT/CN2020/122114 CN2020122114W WO2021103854A1 WO 2021103854 A1 WO2021103854 A1 WO 2021103854A1 CN 2020122114 W CN2020122114 W CN 2020122114W WO 2021103854 A1 WO2021103854 A1 WO 2021103854A1
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layer
semiconductor device
channel
active layer
gate stack
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PCT/CN2020/122114
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English (en)
French (fr)
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朱慧珑
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中国科学院微电子研究所
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Priority to US17/777,811 priority Critical patent/US20220416047A1/en
Priority to DE112020005848.4T priority patent/DE112020005848T5/de
Priority to KR1020217028772A priority patent/KR20210125064A/ko
Publication of WO2021103854A1 publication Critical patent/WO2021103854A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Definitions

  • the present disclosure relates to the field of semiconductors, and more specifically, to a semiconductor device having a comb-tooth-shaped channel structure, a method of manufacturing the same, and electronic equipment including such a semiconductor device.
  • FinFET fin field effect transistors
  • MBCFET multi-bridge channel field effect transistors
  • the height of the fin can be higher and higher in order to obtain sufficient drive current while saving area.
  • the height of the fin is too large, it will cause many problems, such as fin collapse, gap filling, etching topography control, etc.
  • the MBCFET for the purpose of gate metal filling, the interval between the nanosheets included therein cannot be further reduced, and the self-heating problem becomes serious.
  • the height of MBCFETs cannot be used to enhance device performance.
  • the purpose of the present disclosure is at least partly to provide a semiconductor device, a manufacturing method thereof, and an electronic device including such a semiconductor device, so that reliable performance can be obtained when the device is further reduced.
  • a semiconductor device including a channel portion, a source/drain portion connected to the channel portion on opposite sides of the channel portion, and a gate stack that intersects the channel portion.
  • the channel portion includes a first portion extending in a vertical direction with respect to the substrate and a second portion extending from the first portion in a lateral direction with respect to the substrate.
  • a method of manufacturing a semiconductor device including: disposing a first sacrificial layer for a first isolation portion on a substrate; disposing at least one gate stack on the first sacrificial layer
  • the second sacrificial layer and the at least one first active layer are alternately stacked; the first sacrificial layer and the stacked layer are patterned into a ridge structure extending in the first direction on the substrate; the ridge structure and the first active layer are A second active layer connected to the first active layer is formed on the side wall on one side of the second direction intersecting in one direction; a second isolation part is formed on the periphery of the ridge structure on the substrate; the second sacrifice is removed Layer; forming a gate stack extending in the second direction so as to intersect the first active layer and the second active layer on the second isolation portion; removing the portion of the first active layer and the second active layer exposed by the gate stack , To expose the first sacrificial layer; remove the first sacrificial layer and the at least one first active layer are
  • an electronic device including the above-mentioned semiconductor device.
  • the channel part may be a comb-shaped structure.
  • the first part of the channel part may be similar to a fin in a fin field effect transistor (FinFET), and the second part of the channel part may be similar to a nanosheet field effect transistor (FET) or a multi-bridge channel field effect transistor (MBCFET) In the nanosheets. Therefore, the semiconductor device according to the embodiment of the present disclosure may have the advantages of both FinET and nanosheet FET or MBCFET.
  • the current driving capability can be provided by the first part and the second part of the channel part at the same time, so the performance of the device can be improved and the area can be saved.
  • the mechanical stability in the manufacturing stage is better, for example, better than that of a conventional MBCFET.
  • Figures 1 to 22(b) show schematic diagrams of some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure, in which Figures 1 to 9, 10(b), 14(a), 15(a), 16 (a), 19(a), 20(a), 21(a), 22(a) are cross-sectional views along the line AA', and Figures 10(a), 12(a), 17(a) are top views, Figure 10(c), 11(a), 12(b), 13(a), 15(b), 16(b), 19(b), 20(b), 21(b) are along the line BB′ Cross-sectional view of Figure 10(d), 11(b), 12(c), 13(b), 14(b), 15(c), 17(b), 17(c), 18, 19(c ), 20(c), 21(c) are cross-sectional views along the CC' line, and Figures 19(d), 20(d), 21(d), and 22(b) are the cross-sectional views along the DD' line.
  • the drawings show various structural schematic diagrams according to the embodiments of the present disclosure.
  • the figures are not drawn to scale, some details are enlarged and some details may be omitted for clarity of presentation.
  • the shapes of the various regions and layers shown in the figure, as well as the relative size and positional relationship between them, are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art may deviate according to actual conditions. Areas/layers with different shapes, sizes, and relative positions can be designed as needed.
  • a layer/element when a layer/element is referred to as being “on” another layer/element, the layer/element may be directly on the other layer/element, or there may be an intermediate layer/element between them. element.
  • the layer/element may be located "under” the other layer/element when the orientation is reversed.
  • the channel portion of the semiconductor device may include a first portion extending in a vertical direction relative to the substrate (e.g., a direction substantially perpendicular to the surface of the substrate) and from the first portion in a lateral direction relative to the substrate (e.g., , A direction substantially parallel to the surface of the substrate) extending the second part.
  • the second part may be spaced apart from the substrate. There may be a plurality of such second portions, which are spaced apart in the vertical direction.
  • the (each) second part may extend from the first part to the (same) side of the first part, for example, in a lateral direction with respect to the substrate.
  • the channel portion may have a comb-tooth shape as a whole.
  • the top surface of the first part may be higher than the top surface of the uppermost second part.
  • the first part of the channel part may be similar to a fin in a fin field effect transistor (FinFET), and the second part of the channel part may be similar to a nanosheet field effect transistor (FET) or a multi-bridge channel field effect transistor (MBCFET) In the nanosheets.
  • FinFET fin field effect transistor
  • MBCFET multi-bridge channel field effect transistor
  • the semiconductor device may have the advantages of both FinET and nanosheet FET or MBCFET.
  • the current driving capability can be provided by the first part and the second part of the channel part at the same time, so the performance of the device can be improved and the area can be saved.
  • the mechanical stability in the manufacturing stage is better, for example, better than that of a conventional MBCFET.
  • the semiconductor device may further include source/drain portions provided on opposite sides of the channel portion, and the source/drain portions are connected to the channel portion to form an active region of the semiconductor device.
  • the longitudinal direction of the active region may be along the first direction.
  • the source/drain portion may include the same material as the channel portion, or may include a different material so as to, for example, apply stress to the channel portion to enhance device performance.
  • the source/drain portion may be formed by growing from the underlying substrate and/or the sidewall of the channel portion.
  • the top surface of the source/drain portion may be higher than the top surface of the channel portion.
  • the first part and/or the second part of the channel part may include a single crystal semiconductor material to improve device performance.
  • the first part and/or the second part of the channel part can be formed by epitaxial growth, so their thickness can be better controlled.
  • the source/drain portion may also include a single crystal semiconductor material.
  • the semiconductor device may further include a gate stack intersecting the channel portion.
  • the gate stack may extend in a second direction that intersects (for example, perpendicular) to the first direction, and extends from one side of the channel portion to the other side across the channel portion.
  • the gate stack may enter the gap between each second part (when there are multiple second parts) of the channel part and the gap between the lowermost second part and the substrate.
  • the gate stack may contact the opposite sidewalls and top surfaces of the first part of the channel part, the upper and lower surfaces of the second part(s), and the sidewalls on the side away from the first part, and define the channel region therein.
  • the gate stack may have partition walls formed on sidewalls on opposite sides of the gate stack in the first direction.
  • the gate stack can be separated from the source/drain portion by a partition wall.
  • the side walls of the partition wall facing the source/drain parts may be substantially coplanar in the vertical direction.
  • the partition wall may include a first part extending on both sides of the channel part and on the uppermost second part of the channel part and between each second part of the channel part (if there are multiple second parts), and The second part extending between the lowermost second part of the channel part and the substrate.
  • the first part and the second part of the partition wall may comprise different materials.
  • the first part and the second part of the partition wall may have substantially the same thickness.
  • a first isolation portion may be provided between the channel portion and the substrate, and the gate stack, particularly a portion extending on the lower surface of the lowermost second portion in the channel portion, may be formed on the first isolation portion.
  • the first isolation portion may be formed under the channel portion in a manner of self-aligning to the gate stack. In the first direction, the first isolation part may be interposed between the source/drain parts.
  • a second isolation portion may also be provided on the substrate, and the gate stack, particularly the portion extending on both sides of the channel portion, may be formed on the second isolation portion.
  • a punch-through stop may be provided below the first part of the channel part, especially between the first isolation part and the second isolation part to suppress or even prevent the source/drain from passing under the first part. Current leakage in the area.
  • the PTS may be a semiconductor layer in contact with the substrate, and may be appropriately doped. The semiconductor layer in contact with the substrate can improve the heat dissipation performance of the device.
  • the first isolation part may extend below the first part of the channel part to suppress or even prevent current leakage between the source/drain parts.
  • the first isolation portion may extend in the second direction to be in contact with the second isolation portion.
  • Such a semiconductor device can be manufactured as follows, for example.
  • a comb-tooth-shaped channel portion can be provided on the substrate.
  • a first sacrificial layer may be formed on the substrate, and the first sacrificial layer may define the position of the first isolation portion.
  • An alternating stack of at least one second sacrificial layer and at least one first active layer may be formed on the first sacrificial layer. These layers can be formed by epitaxial growth.
  • the first active layer can be used to form the second part of the channel part, and the second sacrificial layer can be used to define the gap between the second part and the first isolation part and between the second parts (if there are more than one). Gap (where a gate stack can then be formed).
  • the uppermost layer of the stack may be a second sacrificial layer to ensure contact between the second active layer formed subsequently and each first active layer, especially the uppermost first active layer.
  • the first sacrificial layer and the stack may be patterned into a ridge structure extending in the first direction. In this way, the first active layer in the stack can be formed as a nanosheet.
  • a second active layer connected to the first active layer may be formed on a sidewall of the ridge structure, for example, a side in a second direction that intersects (for example, perpendicular) to the first direction.
  • the second active layer may extend vertically on the sidewall of the ridge structure and be formed as a fin.
  • the second active layer can be formed by epitaxially growing a semiconductor layer from the surface of the substrate and the ridge structure, and patterning the semiconductor layer.
  • a second isolation portion may be formed on the periphery of the ridge structure on the substrate (the second active layer is formed on the sidewall) so as to subsequently form a gate stack thereon.
  • the second sacrificial layer can be removed. In this way, the first active layer and the second active layer form a comb-shaped structure.
  • a comb-like structure is used for the channel portion.
  • the definition of the channel portion and the formation of the gate stack may be performed in combination.
  • a gate stack extending in the second direction so as to intersect the first active layer and the second active layer may be formed on the substrate, particularly on the second isolation portion.
  • the gate stack can be used as a mask to pattern the comb-shaped structure, leaving it under the gate stack to form a channel part, and the exposed parts on both sides of the gate stack can be removed.
  • the first sacrificial layer can be exposed on both sides of the gate stack.
  • the first sacrificial layer can be removed, thus leaving a void under the channel portion. In this gap, a first partition may be formed.
  • the gate stack can be used as a mask for patterning, so that the first isolation portion can be self-aligned to the gate stack.
  • the source/drain portions in contact with the first active layer and the second active layer may be formed by, for example, epitaxial growth.
  • the gate stack formed above may be a sacrificial gate stack.
  • the sacrificial gate stack can be replaced with a real gate stack through a replacement gate process.
  • the present disclosure can be presented in various forms, some examples of which will be described below.
  • the selection of various materials is involved.
  • the selection of materials also considers etching selectivity.
  • the required etching selectivity may or may not be indicated. It should be clear to those skilled in the art that when etching a certain material layer is mentioned below, if it is not mentioned that other layers are also etched or the figure does not show that other layers are also etched, then this kind of etching It may be selective, and the material layer may have etching selectivity relative to other layers exposed to the same etching recipe.
  • FIG. 1 to 22(b) show schematic diagrams of some stages in the process of manufacturing a vertical semiconductor device according to an embodiment of the present disclosure.
  • a substrate 1001 is provided.
  • the substrate 1001 may be in various forms, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk Si substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • SOI semiconductor-on-insulator
  • a well region (not shown) may be formed. If a p-type device is to be formed, the well region may be an n-type well; if an n-type device is to be formed, the well region may be a p-type well.
  • the well region may be formed, for example, by injecting corresponding conductivity type dopants (p-type dopants such as B or In, or n-type dopants such as As or P) into the substrate 1001 and then performing thermal annealing.
  • p-type dopants such as B or In, or n-type dopants such as As or P
  • the first sacrificial layer 1003 may be formed by, for example, epitaxial growth.
  • the first sacrificial layer 1003 can then be used to define the first isolation portion, and the thickness is, for example, about 10 nm-30 nm.
  • an etching stop layer 1005 can be formed on the first sacrificial layer 1003 by, for example, epitaxial growth.
  • the etch stop layer 1005 may be relatively thin, with a thickness of, for example, about 2 nm-5 nm.
  • alternately stacked layers of the second sacrificial layers 1007, 1011, 1015 and the first active layers 1009, 1013 can be formed by, for example, epitaxial growth.
  • the first active layers 1009 and 1013 can then form nanosheets of the channel portion, with a thickness of, for example, about 5 nm-15 nm.
  • in-situ doping can be performed to adjust the device threshold.
  • the second sacrificial layers 1007 and 1011 may define the gap between the nanosheets, and the thickness is, for example, about 10 nm-25 nm.
  • the uppermost second sacrificial layer 1015 may be slightly thinner, with a thickness of, for example, about 10 nm-20 nm.
  • the number of the second sacrificial layer and the first active layer in the alternating stack can be changed according to the device design, for example, it can be more or less.
  • the substrate 1001 and adjacent layers among the above-mentioned layers formed thereon may have etching selectivity with respect to each other.
  • the first sacrificial layer 1003 and the second sacrificial layers 1007, 1011, 1015 may include SiGe (for example, the atomic percentage of Ge is about 10%-30%), and the etch stop layer 1005 and the first active layers 1009, 1013 may Including Si.
  • a hard mask layer 1017 can be formed by, for example, deposition.
  • the hard mask layer 1017 may include nitride (for example, silicon nitride) with a thickness of about 30 nm-150 nm.
  • a thin etch stop layer or protective layer such as oxide (for example, silicon oxide) or other materials may be formed by, for example, deposition.
  • the hard mask layer 1017 may also include oxide, SiC, or the like.
  • the active area can be defined by patterning the first sacrificial layer 1003 and the above-mentioned stacked layer into a ridge structure.
  • a photoresist (not shown) may be formed on the hard mask layer 1017 and patterned into strips extending in the first direction (the direction into the paper surface in the figure) by photolithography. Then, the photoresist can be used as an etching mask, and each layer is selectively etched sequentially by, for example, reactive ion etching (RIE), and the pattern of the photoresist is transferred to the underlying layer.
  • RIE reactive ion etching
  • the etching may stop at the substrate 1001.
  • the stack of the first sacrificial layer 1003, the etch stop layer 1005, the second sacrificial layer 1007, 1011, 1015 and the first active layer 1009, 1013 can form a ridge structure extending in the first direction.
  • the size of the ridge structure to be formed can be determined according to the size of the nanosheet in the semiconductor device to be formed.
  • the second active layer 1019 may be formed on the sidewall of the ridge structure by, for example, selective epitaxial growth. Due to the selective epitaxial growth, the second active layer 1019 may be formed on the vertical sidewalls of the ridge structure and the surface of the substrate 1001. The second active layer 1019 may then form a fin of the channel part, with a thickness of, for example, about 5 nm-15 nm. Different from the thickness of the fin in the conventional FinFET which is usually determined by the etching process, the thickness of the second active layer 1019 (which is then used as the fin) according to the embodiment of the present disclosure can be determined by the epitaxial growth process, so it can be better controlled The thickness of the fins.
  • the first active layer and the second active layer may include the same material (Si).
  • the present disclosure is not limited to this.
  • the first active layer and the second active layer may include different semiconductor materials, so that the obtained threshold voltages of the first part and the second part of the channel part can be adjusted to match them.
  • the first active layer and the second active layer may include different doping concentrations and/or doping impurities (for example, impurities of different conductivity types) in order to adjust the resultant second layer of the channel part. The threshold voltage of one part and the second part.
  • the first active layer and the second active layer may have different thicknesses, which will cause the threshold voltage between the first part and the second part of the channel part. Different or mismatched.
  • the T-shaped structure formed by the first part and the second part may also affect the electric field distribution and thus the threshold voltage.
  • an isolation layer 1021 (the aforementioned second isolation portion) may be formed around the active region.
  • the isolation layer 1021 may be a shallow trench isolation (STI) defining an active region.
  • STI shallow trench isolation
  • an oxide layer that completely covers the ridge structure is formed on the substrate 1001, and the oxide layer is etched back to form the isolation layer 1021.
  • the deposited oxide layer may be planarized, such as chemical mechanical polishing (CMP), and the CMP may stop at the hard mask layer 1017.
  • CMP chemical mechanical polishing
  • the top surface of the isolation layer 1021 may be lower than the bottom surface of the lowermost first active layer 1009 and higher than the top surface of the first sacrificial layer 1003, for example, the top surface and the bottom surface of the second sacrificial layer 1007 located at the bottom between.
  • the second active layer 1019 in order to suppress the leakage current, it may be formed in the second active layer 1019, particularly the portion below the top surface of the isolation layer 1021 (ie, the portion below the portion used as the channel in the second active layer 1019).
  • Punch Through Stop (PTS) (see 1023 shown in FIG. 8).
  • the formation of PTS can be performed by means of the isolation layer 1021.
  • ion implantation may be performed toward the isolation layer 1021.
  • the ions implanted into the isolation layer 1021 may be scattered into the portion of the second active layer 1019 adjacent to the isolation layer 1021.
  • the implanted ions may have a conductivity type opposite to that of the device to be formed.
  • p-type dopants such as B or In can be implanted; and for p-type devices, n-type dopants such as As or P can be implanted.
  • the injected dose can be about 1E17-1E19cm -3 .
  • Annealing may be performed at a temperature of about 750-1050°C to activate the implanted dopants.
  • the second active layer 1019 may be removed between the ridge structure and the first active layer.
  • a photoresist (not shown) may be used to shield the sidewall of the second active layer 1019 on the other side (for example, the right side in the figure) of the ridge structure in the second direction.
  • Part, and the exposed part of the second active layer 1019 is removed by selective etching such as RIE. After that, the photoresist can be removed.
  • a protective layer for example, a thin oxide layer
  • PTS implantation is performed first, and then the second active layer 1019 is patterned.
  • the present disclosure is not limited to this.
  • the second active layer 1019 may be patterned first, and then PTS implantation may be performed.
  • the hard mask layer 1017 can be removed by selective etching such as wet etching using hot phosphoric acid.
  • the second sacrificial layer 1007, 1011, 1015 of SiGe may be selectively etched relative to the first active layer 1009, 1013, the second active layer 1019 and the etch stop layer 1005 of Si to remove them.
  • the comb-tooth structure includes a first portion 1019 extending in the vertical direction and second portions 1009 and 1013 extending from the first portion 1019 in the lateral direction.
  • the present disclosure is not limited to this, and the number of the second part may be more, for example, 3 or more, or less, for example, one.
  • the etch stop layer 1005 can help define the position of the lower surface of the gate stack or the position of the upper surface of the first isolation portion to be formed later.
  • the present disclosure is not limited to this. If the first sacrificial layer 1003 includes a material having an etch selectivity with respect to the second sacrificial layer 1007, 1011, 1015, the etch stop layer 1005 may be omitted.
  • a sacrificial gate stack may be formed on the isolation layer 1021.
  • the sacrificial gate stack may include a sacrificial gate dielectric layer 1025 and a sacrificial gate conductor layer 1027.
  • the sacrificial gate dielectric layer 1025 may include oxide, for example, formed by deposition or thermal oxidation.
  • the sacrificial gate conductor layer 1027 may include polycrystalline SiGe (the atomic percentage of Ge is about 10%-40%), for example, formed by deposition and then planarization such as CMP.
  • the formed sacrificial gate stack may surround the portions of each of the first active layers 1009, 1013 and the second active layer 1019 above the top surface of the isolation layer 1021.
  • both the sacrificial gate dielectric layer 1025 and the isolation layer 1021 include oxide, so they may appear to be integrated.
  • the sacrificial gate stack may be patterned into a stripe shape extending in the second direction.
  • a hard mask layer 1029 may be formed on the sacrificial gate stack.
  • the hard mask layer 1029 may include nitride, and the thickness is, for example, about 15 nm-150 nm.
  • a photoresist (not shown) may be formed on the hard mask layer 1029 and patterned into strips extending in the second direction by photolithography (see the top view of FIG. 10(a)).
  • photoresist can be used as an etching mask, and the hard mask layer 1029 and the sacrificial gate conductor layer 1027 are selectively etched sequentially by, for example, RIE.
  • the selective etching can stop at the sacrificial gate dielectric layer 1025 of oxide.
  • a first spacer 1031 may be formed on the sidewall of the sacrificial gate stack.
  • a layer of about 1nm-3nm of nitride can be deposited in a substantially conformal manner, and then the deposited nitride layer can be anisotropically etched in the vertical direction to remove its lateral extension and leave it behind. Vertically extend the part, thereby obtaining the first partition wall 1031.
  • an etch stop layer can also be formed, for example, by deposition, and the etching of the nitride layer can stop at the etch stop layer. Since the ridge structure (currently including the first active layer and the second active layer and the remaining sacrificial gate stack) also has vertical sidewalls, the first partition wall can also be formed on the sidewalls of the ridge structure, As shown in Figure 11(a).
  • the first active layer and the second active layer located on both sides of the first partition wall 1031 on the strip-shaped hard mask layer 1029 and its sidewalls can be removed section.
  • the sacrificial gate dielectric layer, the first active layer 1013, the sacrificial gate dielectric layer, the sacrificial gate conductor layer, and the sacrificial gate dielectric layer can be selectively etched sequentially by, for example, RIE.
  • the sacrificial gate stack may be formed in a strip shape corresponding to the hard mask layer 1029 and extending in the second direction. Due to the above processing, the ridge structure is substantially removed except for the part below the first partition wall formed on the sacrificial gate stack and its sidewalls (except for the two ends, part of the first sacrificial layer 1003 is left), Therefore, the first partition wall on its sidewall will not be left in the etching process due to the loss of support, although a separate etching process is not performed for the first partition wall of nitride here.
  • the comb-tooth-shaped structure is also left under the sacrificial gate stack and the first partition wall formed on the sidewall thereof to form a comb-tooth-shaped channel portion.
  • the second part of the channel part that is, the first active layers, may have substantially the same shape, and may be substantially aligned in the vertical direction.
  • the stop layer 1005 may be selectively etched by, for example, RIE, so as to expose the first sacrificial layer 1003 underneath.
  • the exposed first sacrificial layer 1003 may be partially etched, so that the protective layer (see 1033 shown in FIGS. 13(a) and 13(b)) formed later can completely cover the channel portion and the side of the sacrificial gate stack. Wall, as shown in Figure 12(c).
  • a protective layer 1033 may be formed on the sidewall of the channel portion exposed to the outside.
  • the protective layer 1033 may include SiC.
  • the protective layer 1033 may be formed by a partition wall process, and thus may exist on each vertical side wall. It should be pointed out here that if the channel portion can be basically not etched by the following etching recipe to which it is exposed (that is, it has etching selectivity), then this protective layer 1033 can also be omitted.
  • the first sacrificial layer 1003 can be selectively etched relative to the Si etching stop layer 1005 and the substrate 1001 (and the SiC protective layer 1033). Remove. In this way, a void is formed in the active region surrounded by the isolation layer 1021, and the surface of the substrate 1001 is exposed in the void.
  • an isolation portion 1035 (the above-mentioned first isolation portion) may be formed.
  • the etching stop layer 1005 in order to reduce the capacitance between the gate conductor and the substrate 1001 to be formed later, it may be removed by selective etching.
  • the etch stop layer 1005 and the second active layer 1009 and the substrate 1001 all include Si, when the etch stop layer 1005 is selectively etched, the second active layer 1009 and the substrate 1001 1001 can also be etched. In the examples shown in FIGS.
  • the isolation portion 1035 may be formed by depositing a dielectric material such as SiC, and then etching it back. When the deposited dielectric material is etched back, due to the hard mask layer 1029 and the first partition wall 1031 on the sidewall, the isolation portion 1035 can be self-aligned to the sacrificial gate stack (and the first partition wall on the sidewall). wall). In addition, due to the etch back, the protective layer 1033 of SiC previously formed can be removed, and the sidewall of the channel portion is exposed again. Referring to FIG. 15(a), there are both the isolation portion 1035 and the PTS under the first part of the channel portion.
  • a dielectric material such as SiC
  • the second active layer 1009 on both sides of the gap can be completely etched.
  • the formed isolation portion 1035 ′ can be connected to the isolation layer 1021 on opposite sides in the second direction (the horizontal direction in the figure).
  • the above-mentioned PTS formation process can be omitted, because the isolation portion 1035' can also play a role in suppressing leakage current.
  • source/drain portions connected to the exposed sidewalls of the channel portion may be formed in the gaps on both sides of the sacrificial gate stack (and the first partition walls on the sidewalls thereof).
  • a dielectric may be further inserted between the gate stack and the source/drain portion.
  • the sacrificial gate conductor layer 1027 can be selectively etched (here, isotropically etched) to make it relatively concave.
  • atomic layer etching ALE
  • the degree of recession of the sacrificial gate conductor layer 1027 may be approximately the same everywhere.
  • a second partition wall 1037 may be formed on the sidewall of the sacrificial gate conductor layer 1027 that is relatively concave.
  • the second partition wall 1037 may be formed by a process of deposition and then etch back. Therefore, the outer side wall of the second partition wall 1037 may be substantially aligned with the outer side wall of the first partition wall 1031.
  • the second partition wall 1037 may include a low-k dielectric material such as SiC.
  • the etching depth of the sacrificial gate conductor layer 1027 can be controlled so that the thickness of the second partition wall 1037 formed is substantially the same as the thickness of the first partition wall 1031, so that the upper and lower sides of the first active layer
  • the sacrificial gate stack (and the gate stack formed therefrom later) may have substantially the same gate length.
  • the source/drain portion 1039 can be formed by, for example, epitaxial growth.
  • the source/drain portion 1039 may grow from the exposed surface of the substrate 1001 and the surface of each of the first active layer and the second active layer.
  • the source/drain portion 1039 may be doped in situ to a conductivity type corresponding to the device to be formed during growth, for example, n-type for n-type devices and p-type for p-type devices.
  • the grown source/drain portion 1039 may have a different material from the channel portion (for example, have a different lattice constant) in order to apply stress to the channel portion.
  • the source/drain portion 1039 may include Si:C (atomic C is, for example, about 0.5%-3%); for a p-type device, the source/drain portion 1039 may include SiGe (atomic Ge is, for example, About 10%-75%).
  • the source/drain portions 1039 are formed as one body. As shown in FIG. 19(c), each first active layer in the form of a nanosheet is connected between the source/drain portions 1039 on opposite sides to form a second part of the channel portion, similar to an MBCFET. In addition, as shown in FIG. 19(d), the second active layer 1019 is connected between the source/drain portions 1039 on opposite sides to form a second part of the channel portion, similar to a FinFET.
  • a replacement gate process can be performed to complete the device manufacturing.
  • an interlayer dielectric layer 1041 can be formed on the substrate 1001, for example, by depositing a dielectric material such as oxide, to cover the sacrificial gate stack, source/drain 1039 and Isolation layer 1021.
  • the interlayer dielectric layer 1041 may be planarized, such as CMP, to expose the sacrificial gate conductor layer 1027.
  • the sacrificial gate conductor layer 1027 and the sacrificial gate dielectric layer 1025 can be removed by selective etching, thereby forming a space inside the first partition wall 1031 and the second partition wall 1037 ,
  • a gate stack can be formed in the space.
  • the gate dielectric layer 1043 and the gate conductor layer 1045 can be sequentially formed by a process such as CMP by deposition and then planarization.
  • the gate dielectric layer 1043 may be formed in a substantially conformal manner, with a thickness of, for example, about 2-5 nm, and may include a high-k gate dielectric such as HfO 2 .
  • an interface layer may also be formed on the surface of the channel portion, for example, an oxide formed by an oxidation process or deposition such as atomic layer deposition (ALD), with a thickness of about 0.2-2 nm.
  • the gate conductor layer 1045 may include a work function adjusting metal such as TiN, TaN, etc., and a gate conductive metal such as W, etc.
  • FIG. 22(a) and 22(b) show an embodiment in which the isolation portion 1035' is connected to the isolation layer 1021 on both sides.
  • the other aspects of this embodiment may be the same as those shown in Figs. 21(a) to 21(d).
  • the semiconductor device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, it is possible to form an integrated circuit (IC) based on such a semiconductor device, and thereby construct an electronic device. Therefore, the present disclosure also provides an electronic device including the above-mentioned semiconductor device.
  • the electronic device may also include components such as a display screen matched with an integrated circuit and a wireless transceiver matched with an integrated circuit.
  • Such electronic devices are, for example, smart phones, computers, tablet computers (PCs), wearable smart devices, mobile power supplies, and so on.
  • a manufacturing method of a system on chip is also provided.
  • the method may include the method described above.
  • a variety of devices can be integrated on the chip, at least some of which are manufactured according to the method of the present disclosure.

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Abstract

公开了一种半导体器件及其制造方法以及包括这种半导体器件的电子设备。根据实施例，半导体器件可以包括沟道部、在沟道部的相对两侧与沟道部相接的源/漏部以及与沟道部相交的栅堆叠。沟道部包括沿相对于衬底的竖直方向延伸的第一部分以及从第一部分沿相对于衬底的横向方向延伸的第二部分。

Description

半导体器件及其制造方法及包括该半导体器件的电子设备
相关申请的引用
本申请要求于2019年11月29日递交的题为“半导体器件及其制造方法及包括该半导体器件的电子设备”的中国专利申请201911210061.X的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，更具体地，涉及具有梳齿状沟道结构的半导体器件及其制造方法以及包括这种半导体器件的电子设备。
背景技术
提出了各种不同的结构来应对半导体器件进一步小型化的挑战，例如鳍式场效应晶体管(FinFET)以及多桥沟道场效应晶体管(MBCFET)。对于FinFET，随着其进一步缩小，鳍片的高度可以越来越高，以便在节省面积的同时获得足够的驱动电流。但是，如果鳍片高度过大，则会带来很多问题，例如鳍片坍塌、间隙填充、刻蚀形貌控制等。对于MBCFET，出于栅金属填充的目的，其中包括的纳米片之间的间隔不能继续缩小，且自加热问题变得严重。另外，与FinFET不同，MBCFET的高度并不能用来增强器件性能。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种半导体器件及其制造方法以及包括这种半导体器件的电子设备，以便在器件进一步缩小时能够获得可靠的性能。
根据本公开的一个方面，提供了一种半导体器件，包括沟道部、在沟道部的相对两侧与沟道部相接的源/漏部以及与沟道部相交的栅堆叠。沟道部包括沿相对于衬底的竖直方向延伸的第一部分以及从第一部分沿相对于衬底的横向方向延伸的第二部分。
根据本公开的另一方面，提供了一种制造半导体器件的方法，包括：在衬 底上设置用于第一隔离部的第一牺牲层；在第一牺牲层上设置至少一个用于栅堆叠的第二牺牲层和至少一个第一有源层的交替叠层；将第一牺牲层以及所述叠层构图为在衬底上沿第一方向延伸的脊状结构；在脊状结构与第一方向相交的第二方向上的一侧的侧壁上形成与第一有源层相接的第二有源层；在衬底上脊状结构的外围形成第二隔离部；去除第二牺牲层；在第二隔离部上形成沿第二方向延伸从而与第一有源层、第二有源层相交的栅堆叠；去除第一有源层和第二有源层被栅堆叠露出的部分，以露出第一牺牲层；去除所述第一牺牲层；在栅堆叠正下方由于所述第一牺牲层的去除而留下的空间中形成第一隔离部；以及在衬底上栅堆叠在第一方向上的两侧形成与第一有源层和第二有源层相接的源/漏部。
根据本公开的另一方面，提供了一种电子设备，包括上述半导体器件。
根据本公开的实施例，沟道部可以是梳齿状结构。沟道部的第一部分可以类似于鳍式场效应晶体管(FinFET)中的鳍片，而沟道部的第二部分可以类似于纳米片场效应晶体管(FET)或多桥沟道场效应晶体管(MBCFET)中的纳米片。因此，根据本公开实施例的半导体器件可以具有FinET以及纳米片FET或MBCFET两者的优点。在该半导体器件中可以由沟道部的第一部分和第二部分同时来提供电流驱动能力，因此可以改进器件性能，并可以节省面积。而且，由于第一部分和第二部分的相互耦接，在制造阶段机械稳定性较好，例如好于常规MBCFET。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至22(b)示出了根据本公开实施例的制造半导体器件的流程中部分阶段的示意图，其中，图1至9、10(b)、14(a)、15(a)、16(a)、19(a)、20(a)、21(a)、22(a)是沿AA′线的截面图，图10(a)、12(a)、17(a)是俯视图，图10(c)、11(a)、12(b)、13(a)、15(b)、16(b)、19(b)、20(b)、21(b)是沿BB′线的截面图，图10(d)、11(b)、12(c)、13(b)、14(b)、15(c)、17(b)、17(c)、18、19(c)、20(c)、21(c)是沿CC′线的截面图，图19(d)、20(d)、21(d)、22(b)是沿DD′线的截面图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，提出了一种具有梳齿状沟道结构的半导体器件。例如，该半导体器件的沟道部可以包括沿相对于衬底的竖直方向(例如，大致垂直于衬底表面的方向)延伸的第一部分以及从第一部分沿相对于衬底的横向方向(例如，大致平行于衬底表面的方向)延伸的第二部分。第二部分可以与衬底间隔开。可以存在多个这样的第二部分，该多个第二部分之间在竖直方向上间隔开。(各)第二部分可以从第一部分向着第一部分的(同)一侧例如沿相对于衬底的横向方向延伸。于是，沟道部可以总体上呈梳齿状。第一部分的顶面可以高于最上方的第二部分的顶面。沟道部的第一部分可以类似于鳍式场效应晶体管(FinFET)中的鳍片，而沟道部的第二部分可以类似于纳米片场效应晶体管(FET)或多桥沟道场效应晶体管(MBCFET)中的纳米片。
因此，根据本公开实施例的半导体器件可以具有FinET以及纳米片FET或MBCFET两者的优点。在该半导体器件中可以由沟道部的第一部分和第二部分同时来提供电流驱动能力，因此可以改进器件性能，并可以节省面积。而且，由于第一部分和第二部分的相互耦接，在制造阶段机械稳定性较好，例如 好于常规MBCFET。
该半导体器件还可以包括设于沟道部相对两侧的源/漏部，源/漏部与沟道部相接从而构成该半导体器件的有源区。有源区的纵向可以沿着第一方向。源/漏部可以包括与沟道部相同的材料，也可以包括不同的材料从而例如向沟道部施加应力以增强器件性能。源/漏部可以从下方的衬底和/或沟道部的侧壁生长来形成。源/漏部的顶面可以高出沟道部的顶面。
沟道部的第一部分和/或第二部分可以包括单晶半导体材料，以改善器件性能。例如，沟道部的第一部分和/或第二部分可以通过外延生长形成，因此它们的厚度可以得到更好的控制。当然，源/漏部也可以包括单晶半导体材料。分别生长的至少一些半导体层之间可以存在晶体界面。例如，在沟道部的第一部分与源/漏部分之间、在沟道部的第二部分与源/漏部之间、以及在沟道部的第一部分与第二部分之间中的至少之一处，可能存在可观察到的晶体界面。
该半导体器件还可以包括与沟道部相交的栅堆叠。栅堆叠可以沿与第一方向相交(例如垂直)的第二方向延伸，从沟道部的一侧跨过沟道部而延伸到另一侧。栅堆叠可以进入沟道部的各第二部分(存在多个第二部分的情况下)之间的间隙以及最下方的第二部分与衬底之间的间隙中。于是，栅堆叠可以与沟道部的第一部分的相对侧壁和顶面、(各)第二部分的上下表面和远离第一部分一侧的侧壁相接触，并在其中限定沟道区。
栅堆叠在第一方向上的相对两侧的侧壁上可以形成有隔墙。栅堆叠可以通过隔墙与源/漏部相隔。隔墙面向各源/漏部的侧壁在竖直方向上可以实质上共面。隔墙可以包括在沟道部的两侧以及在沟道部的最上的第二部分上延伸的第一部分以及在沟道部的各第二部分之间(如果存在多个第二部分的话)以及沟道部的最下的第二部分与衬底之间延伸的第二部分。隔墙的第一部分和第二部分可以包括不同的材料。隔墙的第一部分和第二部分可以具有基本相同的厚度。
在沟道部与衬底之间可以设置第一隔离部，栅堆叠特别是其在沟道部中最下方的第二部分的下表面上延伸的部分可以形成在第一隔离部上。如下所述，第一隔离部可以自对准于栅堆叠的方式形成于沟道部下方。在第一方向上，第一隔离部可以介于源/漏部之间。另外，衬底上还可以设置有第二隔离部，栅堆叠特别是其在沟道部两侧延伸的部分可以形成在第二隔离部上。
沟道部的第一部分之下，特别是在第一隔离部与第二隔离部之间，可以设置有穿通阻止部(PTS)，以抑制甚至防止源/漏部之间通过第一部分之下的区域的电流泄漏。PTS可以是与衬底相接的半导体层，并可以被适当掺杂。与衬底相接的这种半导体层可以改善器件的散热性能。或者，第一隔离部可以延伸至沟道部的第一部分之下，以抑制甚至防止源/漏部之间的电流泄漏。第一隔离部可以在第二方向上延伸至与第二隔离部相接。
这种半导体器件例如可以如下制造。
首先，可以在衬底上设置梳齿状的沟道部。
例如，可以在衬底上形成第一牺牲层，第一牺牲层可以限定第一隔离部的位置。在第一牺牲层上可以形成至少一个第二牺牲层和至少一个第一有源层的交替叠层。这些层可以通过外延生长来形成。第一有源层可以用来形成沟道部的第二部分，第二牺牲层可以用来限定第二部分与第一隔离部之间以及各第二部分(如果存在多个的话)之间的间隙(其中随后可以形成栅堆叠)。该叠层的最上层可以是第二牺牲层，以确保随后形成的第二有源层与各第一有源层特别是最上方的第一有源层之间的接触。可以将第一牺牲层以及该叠层构图为沿第一方向延伸的脊状结构。这样，该叠层中的第一有源层可以形成为纳米片。
可以在脊状结构一侧，例如与第一方向相交(例如垂直)的第二方向上的一侧，的侧壁上形成与第一有源层相接的第二有源层。第二有源层可以在脊状结构的侧壁上竖直延伸，形成为鳍片。例如，可以通过从衬底以及脊状结构的表面外延生长一半导体层，并对该半导体层进行构图来形成第二有源层。在衬底上脊状结构(侧壁上形成有第二有源层)的外围可以形成第二隔离部，以便随后在其上形成栅堆叠。可以去除第二牺牲层。这样，第一有源层与第二有源层形成了梳齿状结构。
可以得到的梳齿状结构为基础继续完成半导体器件的制造。
如上所述，梳齿状结构用于沟道部。沟道部的限定与栅堆叠的形成可以结合进行。例如，可以在衬底上，特别是在第二隔离部上，形成沿第二方向延伸从而与第一有源层和第二有源层相交的栅堆叠。可以栅堆叠为掩模对梳齿状结构进行构图，使其留于栅堆叠下方从而形成沟道部，而栅堆叠两侧露出的部分可以去除。
由于梳齿状结构的构图，第一牺牲层在栅堆叠两侧可以露出。可以去除第一牺牲层，这样在沟道部下方留下了空隙。在该空隙中，可以形成第一隔离部。在形成第一隔离部时，可以栅堆叠为掩模进行构图，从而第一隔离部可以自对准于栅堆叠。
在衬底上栅堆叠在第一方向上的两侧，可以通过例如外延生长来形成与第一有源层和第二有源层相接的源/漏部。
以上形成的栅堆叠可以是牺牲栅堆叠。可以通过替代栅工艺，将牺牲栅堆叠替换为真正的栅堆叠。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1至22(b)示出了根据本公开实施例的制造竖直半导体器件的流程中部分阶段的示意图。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。
在衬底1001中，可以形成阱区(未示出)。如果要形成p型器件，则阱区可以是n型阱；如果要形成n型器件，则阱区可以是p型阱。阱区例如可以通过向衬底1001中注入相应导电类型掺杂剂(p型掺杂剂如B或In，或n型掺杂剂如As或P)且随后进行热退火来形成。本领域存在多种方式来设置这种阱区，在此不再赘述。
在衬底1001上，可以通过例如外延生长，形成第一牺牲层1003。第一牺牲层1003随后可以用于限定第一隔离部，厚度为例如约10nm-30nm。另外，为了更好的刻蚀控制，可以在第一牺牲层1003上通过例如外延生长，形成刻 蚀停止层1005。刻蚀停止层1005可以较薄，厚度为例如约2nm-5nm。在刻蚀停止层1005上，可以通过例如外延生长，形成第二牺牲层1007、1011、1015和第一有源层1009、1013的交替叠层。第一有源层1009、1013随后可以形成沟道部的纳米片，厚度为例如约5nm-15nm。在生成第一有源层1009、1013时，可以进行原位掺杂，以调节器件阈值。第二牺牲层1007和1011可以限定纳米片之间的间隙，厚度为例如约10nm-25nm。最上的第二牺牲层1015可以稍薄，厚度为例如约10nm-20nm。该交替叠层中第二牺牲层和第一有源层的数目可以根据器件设计而改变，例如可以更多或更少。
衬底1001以及之上形成的上述各层中相邻的层相对于彼此可以具有刻蚀选择性。例如，第一牺牲层1003以及第二牺牲层1007、1011、1015可以包括SiGe(例如，Ge原子百分比为约10％-30％)，刻蚀停止层1005以及第一有源层1009、1013可以包括Si。
在上述叠层上，可以通过例如淀积，形成硬掩模层1017。例如，硬掩模层1017可以包括氮化物(例如，氮化硅)，厚度为约30nm-150nm。在淀积氮化物的硬掩模层1017之前，还可以通过例如淀积，形成一薄的例如氧化物(例如，氧化硅)或其他材料的刻蚀停止层或保护层(未示出)。或者，硬掩模层1017也可以包括氧化物或SiC等。
如图2所示，可以通过将第一牺牲层1003以及之上的上述叠层构图为脊状结构，来限定有源区。例如，可以在硬掩模层1017上形成光刻胶(未示出)，并通过光刻将其构图为沿第一方向(图中进入纸面的方向)延伸的条状。然后，可以光刻胶作为刻蚀掩模，通过例如反应离子刻蚀(RIE)依次对各层进行选择性刻蚀，将光刻胶的图案转移到下方的层中。刻蚀可以停止于衬底1001。于是，第一牺牲层1003、刻蚀停止层1005以及第二牺牲层1007、1011、1015和第一有源层1009、1013的叠层可以形成沿第一方向延伸的脊状结构。可以根据所要形成的半导体器件中纳米片的尺寸，来确定要形成的脊状结构的尺寸。
如图3所示，可以通过例如选择性外延生长，在脊状结构的侧壁上形成第二有源层1019。由于选择性外延生长，第二有源层1019可以形成在脊状结构的竖直侧壁以及衬底1001的表面上。第二有源层1019随后可以形成沟道部的鳍片，厚度为例如约5nm-15nm。与常规FinFET中鳍片的厚度通常由刻蚀工 艺决定不同，根据本公开实施例的第二有源层1019(随后用作鳍片)的厚度可以通过外延生长工艺决定，因此可以更好地控制鳍片的厚度。
在该示例中，第一有源层和第二有源层可以包括相同的材料(Si)。但是，本公开不限于此。例如，第一有源层和第二有源层可以包括不同的半导体材料，从而可以调节得到的沟道部的第一部分和第二部分各自的阈值电压，以使它们相匹配。附加地或者备选地，第一有源层和第二有源层可以包括不同的掺杂浓度和/或掺杂杂质(例如，不同导电类型的杂质)，以便调节得到的沟道部的第一部分和第二部分各自的阈值电压。这是因为，如果出于结构上的力学稳定性考虑，第一有源层和第二有源层可能具有不同的厚度，这会造成沟道部的第一部分和第二部分之间的阈值电压不同或失配。另外，第一部分与第二部分所形成的T型结构也可能影响电场分布从而影响阈值电压。
如图4所示，可以在有源区周围形成隔离层1021(上述的第二隔离部)。隔离层1021可以是限定有源区的浅沟槽隔离(STI)。例如，可以通过淀积，在衬底1001上形成完全覆盖脊状结构的氧化物层，并回蚀氧化物层，来形成隔离层1021。在回蚀之前，可以对淀积的氧化物层进行平坦化如化学机械抛光(CMP)，CMP可以停止于硬掩模层1017。回蚀后隔离层1021的顶面可以低于最下方的第一有源层1009的底面，高于第一牺牲层1003的顶面，例如位于最下方的第二牺牲层1007的顶面与底面之间。
另外，为了抑制漏电流，可以在第二有源层1019特别是其位于隔离层1021顶面下方的部分(即，第二有源层1019中用作沟道的部分之下的部分)中形成穿通阻止部(PTS)(参见图8中示出的1023)。PTS的形成可以借助于隔离层1021进行。如图5所示，可以向着隔离层1021进行离子注入。注入到隔离层1021中的离子可以被散射进入第二有源层1019与隔离层1021邻接的部分中。注入的离子可以具有与将要形成的器件的导电类型相反的导电类型。例如，对于n型器件，可以注入p型掺杂剂如B或In；而对于p型器件，可以注入n型掺杂剂如As或P。注入的剂量可以为约1E17-1E19cm -3。可以在约750-1050℃的温度下进行退火，以激活注入的掺杂剂。
为了使随后形成的栅堆叠能够进入第一有源层1009和1013之间的空间以及最下方的第一有源层1009下方的空间，可以去除第二有源层1019在脊状结 构与第一方向交叉的第二方向(例如，图5中纸面上的水平方向)上的一侧(例如，图中左侧)的侧壁上的部分。例如，如图6所示，可以通过光刻胶(未示出)遮蔽第二有源层1019在脊状结构的第二方向上另一侧(例如，图中右侧)的侧壁上的部分，并通过选择性刻蚀如RIE来去除第二有源层1019的暴露部分。之后，可以去除光刻胶。另外，为了保护留下的第二有源层1019，可以在其表面上形成一保护层(例如，薄氧化物层)。
在以上实施例中，先进行PTS注入，然后再构图第二有源层1019。但是，本公开不限于此。例如，如图7所示，可以先构图第二有源层1019，然后再进行PTS注入。
如图8所示，可以通过选择性刻蚀如使用热磷酸的湿法刻蚀，去除硬掩模层1017。另外，可以相对于Si的第一有源层1009、1013、第二有源层1019和刻蚀停止层1005，选择性刻蚀SiGe的第二牺牲层1007、1011、1015，以将其去除。这样，得到了梳齿状的结构。如图8所示，该梳齿状结构包括沿竖直方向延伸的第一部分1019以及从第一部分1019沿横向方向延伸的第二部分1009、1013。在该示例中，存在两个第二部分。但是，本公开不限于此，第二部分的数目可以更多例如3个以上，或者更少例如1个。
在该实施例中，刻蚀停止层1005可以帮助限定随后形成的栅堆叠的下表面的位置或者第一隔离部的上表面的位置。但是，本公开不限于此。如果第一牺牲层1003包括相对于第二牺牲层1007、1011、1015具有刻蚀选择性的材料，则可以省略这种刻蚀停止层1005。
如图9所示，可以在隔离层1021上形成牺牲栅堆叠。牺牲栅堆叠可以包括牺牲栅介质层1025和牺牲栅导体层1027。牺牲栅介质层1025可以包括氧化物，例如通过淀积或热氧化形成。牺牲栅导体层1027可以包括多晶SiGe(Ge的原子百分比为约10％-40％)，例如通过淀积然后平坦化如CMP形成。由于第二牺牲层的去除，所形成的牺牲栅堆叠可以围绕各第一有源层1009、1013和第二有源层1019在隔离层1021顶面上方的部分。在该示例中，牺牲栅介质层1025和隔离层1021均包括氧化物，因此它们看起来可能是一体的。
如图10(a)至10(d)所示，可以将牺牲栅堆叠构图为沿第二方向延伸的条形。具体地，可以在牺牲栅堆叠上形成硬掩模层1029。硬掩模层1029可以包括氮 化物，厚度例如为约15nm-150nm。可以在硬掩模层1029上形成光刻胶(未示出)，并通过光刻将其构图为沿第二方向延伸的条状(参见图10(a)的俯视图)。然后，可以光刻胶作为刻蚀掩模，通过例如RIE依次对硬掩模层1029和牺牲栅导体层1027进行选择性刻蚀。选择性刻蚀可以停止于氧化物的牺牲栅介质层1025。
参见图10(c)，在沿第二方向延伸的条形硬掩模层1029在第一方向上的相对两侧(即，图10(a)的俯视图中条形硬掩模层1029的上下两侧)，由于第一有源层的存在，牺牲栅导体层1027位于各第一有源层下方的部分可以留下。
如图11(a)和11(b)所示，可以在牺牲栅堆叠的侧壁上形成第一隔墙(spacer)1031。例如，可以以大致共形的方式淀积一层约1nm-3nm的氮化物，然后沿竖直方向对淀积的氮化物层进行各向异性刻蚀，以去除其横向延伸部分而留下其竖直延伸部分，从而得到第一隔墙1031。在淀积氮化物层之前，也可以例如通过淀积形成一刻蚀停止层，对氮化物层的刻蚀可以停止于该刻蚀停止层。由于脊状结构(当前包括第一有源层和第二有源层以及留下的牺牲栅堆叠)也存在竖直侧壁，因此第一隔墙也可以形成在脊状结构的侧壁上，如图11(a)所示。
如图12(a)至12(c)所示，可以去除第一有源层和第二有源层位于条形的硬掩模层1029及其侧壁上的第一隔墙1031两侧的部分。例如，参见图10(c)和图12(b)，可以通过例如RIE，依次选择性刻蚀牺牲栅介质层、第一有源层1013、牺牲栅介质层、牺牲栅导体层、牺牲栅介质层、第一有源层1009、牺牲栅介质层、牺牲栅导体层和牺牲栅介质层。这样，牺牲栅堆叠可以形成为与硬掩模层1029相对应的沿第二方向延伸的条形。由于以上处理，脊状结构除了留于牺牲栅堆叠及其侧壁上形成的第一隔墙下方的部分之外，大体上被去除(除了两端还有部分第一牺牲层1003留下)，因此其侧壁上的第一隔墙由于失去支撑而不会在刻蚀工艺中留下，尽管在此并未针对氮化物的第一隔墙执行单独的刻蚀工艺。另外，上述梳齿状结构也留于牺牲栅堆叠及其侧壁上形成的第一隔墙下方，形成梳齿状的沟道部。沟道部中的第二部分，即各第一有源层，可以具有基本相同的形状，且可以在竖直方向上基本对准。另外，还可以通过例如RIE，选择性刻蚀刻蚀停止层1005，以便露出之下的第一牺牲层1003。可以 对露出的第一牺牲层1003进行部分刻蚀，以便之后形成的保护层(参见图13(a)和13(b)中示出的1033)能够完全覆盖沟道部和牺牲栅堆叠的侧壁，如图12(c)所示。
如图12(c)所示，梳齿状沟道部在第一方向上的侧壁当前暴露于外。为保护沟道部(特别是在以下形成隔离部的过程中)，如图13(a)和13(b)所示，可以在沟道部暴露于外的侧壁上形成保护层1033。例如，保护层1033可以包括SiC。保护层1033可以通过隔墙工艺形成，因此可以存在于各竖直侧壁上。这里需要指出的是，如果沟道部可以基本上不被以下其所暴露于的刻蚀配方刻蚀(即，具有刻蚀选择性)，那么也可以省略这种保护层1033。
如图14(a)和14(b)所示，可以相对于Si的刻蚀停止层1005和衬底1001(以及SiC的保护层1033)，选择性刻蚀第一牺牲层1003，以将其去除。这样，就在隔离层1021所围绕的有源区中形成了空隙，在该空隙中，衬底1001的表面露出。
如图15(a)至15(c)所示，在上述空隙中，可以形成隔离部1035(上述的第一隔离部)。在形成了刻蚀停止层1005的情况下，为了降低随后形成的栅导体与衬底1001之间的电容，可以通过选择性刻蚀将其去除。在该示例中，由于刻蚀停止层1005与第二有源层1009和衬底1001均包括Si，因此在对刻蚀停止层1005进行选择性刻蚀时，第二有源层1009和衬底1001也可被刻蚀。在图15(a)至15(c)所示的示例中，上述空隙两侧的第二有源层1009并未被完全去除，而是留有一部分。隔离部1035可以通过淀积电介质材料如SiC，然后对其回蚀来形成。在回蚀所淀积的电介质材料时，由于硬掩模层1029及其侧壁上的第一隔墙1031，隔离部1035可以自对准于牺牲栅堆叠(及其侧壁上的第一隔墙)。另外，由于回蚀，之前形成的SiC的保护层1033可以被去除，于是沟道部的侧壁再次露出。参见图15(a)，沟道部的第一部分下方存在隔离部1035以及PTS两者。
根据本公开的另一实施例，如图16(a)和16(b)所示，在去除刻蚀停止层1005时，上述空隙两侧的第二有源层1009可以被完全刻蚀。这样，参考图16(a)，所形成的隔离部1035′可以在第二方向(图中水平方向)上的相对两侧与隔离层1021相接。这种情况下，可以省略上述PTS的形成工艺，因为隔离部1035′ 同样可以起到抑制漏电流的作用。
之后，可以在牺牲栅堆叠(及其侧壁上的第一隔墙)两侧、在上述空隙中形成与沟道部露出的侧壁相接源/漏部。
为了降低随后形成的栅堆叠与源/漏部之间的电容，可以在栅堆叠与源/漏部之间进一步插入电介质。为此，如图17(a)至17(c)所示，可以选择性刻蚀(在此，可以是各向同性刻蚀)牺牲栅导体层1027，以使其相对凹入。在此，可以采用原子层刻蚀(ALE)，以很好地控制刻蚀深度。牺牲栅导体层1027在各处的凹入程度可以大致相同。然后，如图18所示，可以在相对凹入的牺牲栅导体层1027的侧壁上形成第二隔墙1037。第二隔墙1037可以通过淀积然后回蚀的工艺来形成。因此，第二隔墙1037的外侧壁可以与第一隔墙1031的外侧壁基本上对齐。例如，第二隔墙1037可以包括低k电介质材料如SiC。根据本公开的实施例，可以控制对牺牲栅导体层1027的刻蚀深度，使得所形成的第二隔墙1037的厚度与第一隔墙1031的厚度基本相同，从而第一有源层上下侧的牺牲栅堆叠(以及后来由此形成的栅堆叠)可以具有基本相同的栅长。
如图19(a)至19(d)所示，可以通过例如外延生长，形成源/漏部1039。源/漏部1039可以从暴露的衬底1001的表面以及各第一有源层和第二有源层的表面生长。源/漏部1039在生长时可以被原位掺杂为与所要形成的器件相应的导电类型，例如对于n型器件为n型，对于p型器件为p型。生长的源/漏部1039可以具有与沟道部不同的材料(例如，具有不同的晶格常数)，以便向沟道部施加应力。例如，对于n型器件，源/漏部1039可以包括Si：C(C原子百分比例如为约0.5％-3％)；对于p型器件，源/漏部1039可以包括SiGe(Ge原子百分比例如为约10％-75％)。
在牺牲栅堆叠的相对两侧，源/漏部1039形成为一体。如图19(c)所示，纳米片形式的各第一有源层连接在相对两侧的源/漏部1039之间，形成沟道部的第二部分，类似于MBCFET。另外，如图19(d)所示，第二有源层1019连接在相对两侧的源/漏部1039之间，形成沟道部的第二部分，类似于FinFET。
接下来，可以进行替代栅工艺，以完成器件制造。
如图20(a)至20(d)所示，可以在衬底1001上，例如通过淀积电介质材料如氧化物，形成层间电介质层1041，以覆盖牺牲栅堆叠、源/漏部1039和隔离 层1021。可以对层间电介质层1041进行平坦化处理如CMP，以露出牺牲栅导体层1027。
如图21(a)至21(d)所示，可以通过选择性刻蚀，去除牺牲栅导体层1027和牺牲栅介质层1025，从而在第一隔墙1031和第二隔墙1037内侧形成空间，可以在该空间中形成栅堆叠。例如，可以通过淀积然后平坦化如CMP的工艺，依次形成栅介质层1043和栅导体层1045。栅介质层1043可以大致共形的方式形成，厚度例如为约2-5nm，且可以包括高k栅介质如HfO 2。在形成高k栅介质之前，还可以在沟道部的表面上形成界面层，例如通过氧化工艺或淀积如原子层淀积(ALD)形成的氧化物，厚度为约0.2-2nm。栅导体层1045可以包括功函数调节金属如TiN、TaN等和栅导电金属如W等。
图22(a)和22(b)示出了在隔离部1035′与两侧的隔离层1021相接的实施例。该实施例的其他方面可以与图21(a)至21(d)所示的相同。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，可以基于这样的半导体器件形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、计算机、平板电脑(PC)、可穿戴智能设备、移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (38)

  1. 一种半导体器件，包括：
    沟道部，包括：
    沿相对于衬底的竖直方向延伸的第一部分；以及
    从第一部分沿相对于衬底的横向方向延伸的第二部分；
    在沟道部的相对两侧与沟道部相接的源/漏部；以及
    与沟道部相交的栅堆叠。
  2. 根据权利要求1所述的半导体器件，其中，沟道部包括多个所述第二部分，各第二部分之间在竖直方向上彼此间隔开。
  3. 根据权利要求1或2所述的半导体器件，其中，沟道部包括单晶半导体材料。
  4. 根据权利要求1或2所述的半导体器件，其中，沟道部的第一部分与源/漏部之间，沟道部的第二部分与源/漏部之间，以及沟道部的第一部分与第二部分之间中至少之一处存在晶体界面。
  5. 根据权利要求1或2所述的半导体器件，其中，所述第一部分形成为鳍的形式，所述第二部分形成为纳米片的形式。
  6. 根据权利要求1或2所述的半导体器件，其中，所述第二部分或所述多个第二部分从第一部分向着第一部分的同一侧实质上沿相对于衬底的横向方向延伸。
  7. 根据权利要求6所述的半导体器件，其中，所述多个第二部分具有实质上相同的形状，且在竖直方向上实质上对准。
  8. 根据权利要求1或2所述的半导体器件，还包括：
    在栅堆叠的侧壁上形成的隔墙，所述隔墙面向各源/漏部的侧壁在竖直方向上实质上共面。
  9. 根据权利要求8所述的半导体器件，其中，所述隔墙包括：
    在沟道部的两侧以及在沟道部的最上的第二部分上延伸的第一部分；以及
    在沟道部的各第二部分之间以及沟道部的最下的第二部分与衬底之间延伸的第二部分，
    其中，隔墙的第一部分和第二部分包括不同的材料。
  10. 根据权利要求1或2所述的半导体器件，其中，栅堆叠在各第二部分的上、下表面上延伸，栅堆叠在各第二部分的上表面上延伸的部分的侧壁与栅堆叠在相应第二部分的下表面上延伸的部分的侧壁在竖直方向上实质上对齐。
  11. 根据权利要求1或2所述的半导体器件，其中，栅堆叠与沟道部的第二部分相交的部分的侧壁与栅堆叠与沟道部的第一部分相交的部分的侧壁实质上对齐。
  12. 根据权利要求1或2所述的半导体器件，其中，沟道部的第一部分的顶面高于最上的第二部分的顶面。
  13. 根据权利要求1或2所述的半导体器件，还包括：设于沟道部与衬底之间的第一隔离部。
  14. 根据权利要求13所述的半导体器件，还包括：
    在衬底上形成的第二隔离部，
    其中，栅堆叠形成在第一隔离部和第二隔离部上。
  15. 根据权利要求14所述的半导体器件，还包括：在沟道部的第一部分之下，在第一隔离部和第二隔离部之间的穿通阻止部。
  16. 根据权利要求15所述的半导体器件，其中，穿通阻止部为与衬底相接的半导体。
  17. 根据权利要求16所述的半导体器件，其中，
    所述半导体器件是n型器件，且穿通阻止部的半导体是p型掺杂；或者
    所述半导体器件是p型器件，且穿通阻止部的半导体是n型掺杂。
  18. 根据权利要求14所述的半导体器件，其中，第一隔离部与第二隔离部在栅堆叠的纵向延伸方向上相接。
  19. 根据权利要求13所述的半导体器件，其中，沟道部的第一部分通过第一隔离部与衬底相隔离。
  20. 根据权利要求13所述的半导体器件，其中，第一隔离部位于沟道部的第一部分之下，源/漏部之间。
  21. 根据权利要求13或20所述的半导体器件，其中，第一隔离部面向各源/漏部的侧壁与栅堆叠的相应侧壁实质上平行。
  22. 根据权利要求1或2所述的半导体器件，其中，沟道部的第一部分和第二部分包括不同的半导体材料。
  23. 根据权利要求1或2所述的半导体器件，其中，沟道部的第一部分和第二部分具有不同的掺杂浓度和/或掺杂杂质。
  24. 一种制造半导体器件的方法，包括：
    在衬底上设置用于第一隔离部的第一牺牲层；
    在第一牺牲层上设置至少一个用于栅堆叠的第二牺牲层和至少一个第一有源层的交替叠层；
    将第一牺牲层以及所述叠层构图为在衬底上沿第一方向延伸的脊状结构；
    在脊状结构与第一方向相交的第二方向上的一侧的侧壁上形成与第一有源层相接的第二有源层；
    在衬底上脊状结构的外围形成第二隔离部；
    去除第二牺牲层；
    在第二隔离部上形成沿第二方向延伸从而与第一有源层、第二有源层相交的栅堆叠；
    去除第一有源层和第二有源层被栅堆叠露出的部分，以露出第一牺牲层；
    去除所述第一牺牲层；
    在栅堆叠正下方由于所述第一牺牲层的去除而留下的空间中形成第一隔离部；以及
    在衬底上栅堆叠在第一方向上的两侧形成与第一有源层和第二有源层相接的源/漏部。
  25. 根据权利要求24所述的方法，还包括：
    在第一牺牲层上形成刻蚀停止层，
    其中，所述叠层形成在所述刻蚀停止层上。
  26. 根据权利要求25所述的方法，其中，第一牺牲层、第二牺牲层、第一有源层、第二有源层和刻蚀停止层均通过外延生长来设置。
  27. 根据权利要求25所述的方法，其中，
    去除第一牺牲层包括：相对于衬底和刻蚀停止层，选择性刻蚀第一牺牲层，
    该方法还包括：对刻蚀停止层进一步刻蚀，以将之去除。
  28. 根据权利要求24所述的方法，其中，第二隔离部的顶面高于最下方的第二牺牲层的底面且低于该第二牺牲层的顶面。
  29. 根据权利要求28所述的方法，其中，形成第二有源层包括：
    在形成第二隔离部之前，在衬底和所述脊状结构上外延生长半导体层；以及
    在形成第二隔离部之后，去除所述半导体层位于脊状结构顶部以及在第二方向上的另一侧的侧壁上的部分。
  30. 根据权利要求29所述的方法，其中，第一隔离部形成为在第二方向上与第一隔离部相接，或者两者之间夹有所述半导体层。
  31. 根据权利要求29所述的方法，还包括：
    向着第二隔离部进行离子注入处理，注入的离子通过散射而进入所述半导体层中形成穿通阻止部。
  32. 根据权利要求24所述的方法，其中，形成栅堆叠包括：
    在衬底上依次形成栅介质层和栅导体层；
    在栅导体层上形成沿第二方向延伸的硬掩模层；
    利用硬掩模层对栅导体层进行选择性刻蚀；以及
    在栅导体层的侧壁上形成第一隔墙。
  33. 根据权利要求32所述的方法，其中，去除第一有源层和第二有源层被栅堆叠露出的部分包括：
    以所述硬掩模层和第一隔墙为掩模，对第一有源层和第二有源层以及它们的表面上存在的栅介质层和栅导体层进行选择性刻蚀。
  34. 根据权利要求33所述的方法，其中，所述选择性刻蚀进行到第一牺牲层中，以露出第一牺牲层从而将之去除。
  35. 根据权利要求33所述的方法，还包括：
    在第一有源层和第二有源层在第一方向上的相对两侧的侧壁上形成保护层。
  36. 根据权利要求33所述的方法，还包括：
    使栅堆叠夹于相邻的第一有源层之间的部分以及夹于最下层的第一有源层与第一隔离部之间的部分在第一方向上的相对端部凹入；以及
    在所述端部处形成第二隔墙。
  37. 一种电子设备，包括如权利要求1至23中任一项所述的半导体器件。
  38. 根据权利要求37所述的电子设备，其中，所述电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
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