US20100207172A1 - Semiconductor structure and method of fabricating the semiconductor structure - Google Patents

Semiconductor structure and method of fabricating the semiconductor structure Download PDF

Info

Publication number
US20100207172A1
US20100207172A1 US12704975 US70497510A US2010207172A1 US 20100207172 A1 US20100207172 A1 US 20100207172A1 US 12704975 US12704975 US 12704975 US 70497510 A US70497510 A US 70497510A US 2010207172 A1 US2010207172 A1 US 2010207172A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
sgt
crystal plane
channel
sidewall
pillar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US12704975
Other versions
US8183628B2 (en )
Inventor
Fujio Masuoka
Keon Jae Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Masuoka Fujio
Unisantis Electronics Singapore Pte Ltd
Original Assignee
Unisantis electronics (Japan) Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827Vertical transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666Vertical transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642Vertical transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode

Abstract

In contrast to a conventional planar CMOS technique in design and fabrication for a field-effect transistor (FET), the present invention provides an SGT CMOS device formed on a conventional substrate using various crystal planes in association with a channel type and a pillar shape of an FET, without a need for a complicated device fabrication process. Further, differently from a design technique of changing a surface orientation in each planar FET, the present invention is designed to change a surface orientation in each SGT to achieve improvement in carrier mobility. Thus, a plurality of SGTs having various crystal planes can be formed on a common substrate to achieve a plurality of different carrier mobilities so as to obtain desired performance.

Description

    RELATED APPLICATIONS
  • Pursuant to 35 U.S.C. §119(e), this application claims the benefit of the filing date of Provisional U.S. patent application Ser. No. 61/207,543 filed on Feb. 13, 2009. This application is a continuation application of PCT/JP2007/071052 filed on Oct. 29, 2007. The entire contents of these applications are hereby incorporated by reference.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor structure and a fabrication method for the semiconductor structure, pertaining primarily to an SGT CMOS technique.
  • 2. Description of the Background Art
  • A CMOS (complementary metal-oxide semiconductor) technique, one of the elemental techniques for a very-large-scale integrated circuit (VLSI), is capable of forming literally tens of millions of transistors as a single integrated circuit. In the CMOS technique, there is a strong need for allowing ever-increasing device element density to be further increased.
  • With a view to increasing the number of high-performance transistors, one type of field-effect transistor (FET), called “surrounding gate transistor (SGT)”, has been proposed. As advantages of using the SGT, it is expected to suppress short channel effects (SCE) so as to reduce a leak current and obtain an ideal switching operation. In addition, a gate region can be enlarged, which allows the SGT to have an enhanced current control function without increasing a gate length.
  • As a way to facilitate a reduction in size of each CMOS device element while maintaining satisfactory performance, it is contemplated to increase carrier mobility of a semiconductor material. In a CMOS device, an electron is used as a carrier for an N-channel FET, and a hole is used as a carrier for a P-channel FET. The carrier in a semiconductor substrate is forced by an electric field applied to the substrate, wherein an electron and a hole are accelerated in respective opposite directions along the electric field. A velocity of the carrier, called “drift velocity, is proportional to an intensity of the applied electric field. A proportionality constant between the drift velocity and the electric field intensity is the carrier mobility. Along with an increase in carrier mobility, a current density becomes higher, and consequently a transistor switching speed becomes higher.
  • In a conventional planar CMOS device, carrier mobility in each device element varies depending on various factors, particularly, largely on a surface of a wafer. Specifically, a carrier is influenced by atomic periodicity (a pattern formed by atoms) dependent on a crystal plane. Thus, any planar device element has carrier mobility dependent on a crystal plane on which it is formed. Further, even if a channel direction of a planar FET formed on a certain crystal plane is changed, a carrier mobility stays constant.
  • In the conventional CMOS technique, a silicon substrate having a (100) crystal plane (i.e., a surface orientation of (100)) is used. The reason for selection of the silicon substrate having the (100) crystal plane is that (a) when a surface of a silicon substrate is formed along a (100) crystal plane, a surface state density between the silicon substrate and a silicon oxide film is minimized, and (b) electron mobility in the (100) crystal plane is greater than those in other crystal planes, and therefore a source-drain current in an N-channel FET formed on the semiconductor substrate having the (100) crystal plane is maximized. Differently, hole mobility is not maximized in the (100) crystal plane, and consequently a source-drain current in a P-channel FET formed on the semiconductor substrate having the (100) crystal plane becomes smaller. Thus, even if the N-channel FET exhibits excellent characteristics, the P-channel FET cannot have desired characteristics. If the P-channel FET is formed on a (110) crystal plane, the hole mobility is increased particularly when a high electric field is applied thereto. However, the (110) crystal plane has not been used in the conventional planar CMOS device, because the electron mobility deteriorates in the (110) crystal plane. It may also be said that the (100) crystal plane has been used in the conventional planar CMOS device, as a result of compromise between respective maximizations of the hole mobility and the electron mobility, in a situation where it is unable to use a different crystal plane for each device element.
  • As shown in FIGS. 85( a) to 85(c), an SGT CMOS device has been proposed in various prior art documents (see the following Non-Patent Documents 1 to 3 and Patent Document 1). FIG. 85( a) shows that an SGT CMOS device makes it possible to reduce a device area as compared with a planar CMOS device. FIG. 85( b) shows a circuit, a layout and structure of the SGT CMOS device.
  • A FinFET CMOS device using various crystal planes has also been proposed (see the following Patent Documents 2 and 3). As shown in FIG. 85( c), a FinFET CMOS inverter 300 is formed by a paired set of a PFET 302 and an NFET 308. Respective drains 306, 312 of the PFET 302 and the NFET 308 are connected to each other through a line 316 to have an output potential (Out), and respective gates 305, 311 of the PFET 302 and the NFET 308 are connected to each other through a gate conductor 314 to have an input potential (In). The FinFET CMOS inverter 300 comprising the above paired set is supplied with a power supply voltage (Vdd) through a line 317 connected to a source of the PFET 302, and connected to ground (Gnd) through a line 318 connected to a source 310 of the NFET 308. However, in each of the Patent Documents 2 and 3, crystal orientation and carrier mobility related to the crystal orientation have not been taken into account.
  • Thus, there remains a possibility that the SGT CMOS technique is improved by using various crystal planes in association with a current channel type and a pillar shape of an FET. In this case, it is considered that a desired performance of each CMOS device element can be maintained by optimizing carrier mobility or reducing carrier mobility in each device element, depending on a specific intended purpose.
  • As another approach to improving performance of each CMOS SGT, it is contemplated to select an optimal one of various shapes (cross-sectionally circular shape, square shape, etc) of a silicon pillar. A value of carrier mobility varies depending on a surface orientation of a sidewall of the silicon pillar. In other words, a shape and a surface orientation of the silicon pillar have an impact on carrier mobility. Further, physical properties (electric field, local carrier mobility, etc) of the device element are changed by changing the shape of the SGT pillar. An electric field is locally dependent on a structure of the SGT pillar, for example, where a curvature radius of a corner or an overall size in cross-section thereof is reduced, so that a change in perpendicular electric field causes a significant change in performance of the device element.
      • Patent Document 1: U.S. Pat. No. 5,258,635
      • Patent Document 2: U.S. Pat. No. 6,815,277
      • Patent Document 3: U.S. Pat. No. 6,658,259
      • Non-Patent Document 1: IEEE Trans. Electron Dev., Vol. 38(3), pp. 579-583 (1991)
      • Non-Patent Document 2: IEDM Tech. Dig., p. 736 (1987)
      • Non-Patent Document 3: The Japanese Journal of Applied Physics (JJAP), Vol. 43(10), p. 6904 (2004)
    SUMMARY OF THE INVENTION
  • In contrast to a conventional planar CMOS technique in design and fabrication for a field-effect transistor (FET), the present invention provides an SGT CMOS device formed on a conventional substrate using various crystal planes in association with a channel type and a pillar shape of an FET, without a need for a complicated device fabrication process. Further, differently from a design technique of changing a surface orientation in each planar FET, the present invention is designed to change a surface orientation in each SGT to achieve improvement in carrier mobility. Thus, a plurality of SGTs having various crystal planes can be formed on a common substrate to achieve a plurality of different carrier mobilities so as to obtain desired performance.
  • A method of fabricating a semiconductor structure, according to one embodiment of the present invention, comprises the steps of: providing a substrate having a given crystal plane; forming a first surrounding gate transistor (SGT) in such a manner that a first pillar body thereof defines a first current channel and a sidewall of the first pillar body is oriented on a second crystal plane which provides a first carrier mobility; and forming a second surrounding gate transistor (SGT) in such a manner that a second pillar body thereof defines a second current channel a sidewall of the second pillar body is oriented on a third crystal plane which provides a second carrier mobility different from the second carrier mobility.
  • This embodiment of the present invention includes many variations or modifications. As a first variation, the substrate may include a single-crystal silicon substrate, and/or may have a surface oriented on a (110) crystal plane and a (100) crystal plane. As a second variation, each of the first and second pillar bodies (SGT bodies) may be formed in a cross-sectionally circular shape. As a third variation, the first SGT may be one of a square pillar-type SGT (SGT having a cross-sectionally square-shaped pillar body) and a rectangular pillar-type SGT (SGT having a cross-sectionally rectangular-shaped pillar body), which is formed such that each of two parallel sidewalls of the pillar body has a (n m l) crystal plane, and each of the remaining two sidewalls has a (a b c) crystal plane, wherein each of n, m, l, a, b and c is any integer, and na+mb+lc=0, and the second SGT may be one of a square pillar-type SGT and a rectangular pillar-type SGT, which is formed such that each of two parallel sidewalls of the pillar body has a (p q r) crystal plane, and each of the remaining two sidewalls has a (e f g) crystal plane, wherein each of p, q, r, e, f and g is any integer, and pe+fg+qr=0. As a fourth variation, the first SGT may be formed to have a cross-sectionally circular-shaped pillar body having a surface oriented on a plurality of crystal planes, and the second SGT may be formed to have one of a cross-sectionally square-shaped pillar body and a cross-sectionally rectangular-shaped pillar body, which is formed such that each of two parallel sidewalls of the pillar body has a (n m l) crystal plane, and each of the remaining two sidewalls has a (a b c) crystal plane, wherein each of n, m, l, a, b and c is any integer, and na+mb+lc=0. As a fifth variation, the first SGT may be one of a first P-channel SGT (PFET) and a first N-channel SGT (NFET), and the second SGT may be one of a second P-channel SGT (PFET) and a second N-channel SGT (NFET). In the fifth variation, a pillar body of one of the first PFET and the first NFET is formed (and/or rotated) such that a sidewall thereof provides one of an optimized carrier mobility and an unoptimized carrier mobility.
  • In accordance with a first aspect of the present invention, there is provided a semiconductor structure which comprises: a first single-crystal semiconductor sidewall channel having a surface oriented on a first crystal plane; and a second single-crystal semiconductor sidewall channel having a surface oriented on a second crystal plane different from the first crystal plane, wherein the first crystal plane and the second crystal plane are not equivalent by a symmetry transformation.
  • In the semiconductor structure of the present invention, the first single-crystal semiconductor sidewall channel may have a first carrier mobility, and the second single-crystal semiconductor sidewall channel may have a second carrier mobility, wherein a value of the first carrier mobility is different from a value of the second carrier mobility.
  • The semiconductor structure of the present invention may be formed on a wafer having a (100) crystal plane and/or a (110) crystal plane.
  • In the semiconductor structure of the present invention, the first single-crystal semiconductor sidewall channel may constitute a first surrounding gate transistor (SGT), and the second single-crystal semiconductor sidewall channel may constitute a second surrounding gate transistor (SGT).
  • In the above semiconductor structure, the first SGT may be one of a first P-channel SGT (PFET) and a second N-channel SGT (NFET), and the second SGT may be one of a second P-channel SGT (PFET) and a second N-channel SGT (NFET).
  • In the above semiconductor structure, a pillar body of one of the first PFET and the first NFET may be formed such that a sidewall thereof is oriented on the first crystal plane to have one of an optimized carrier mobility and an unoptimized carrier mobility, and a pillar body of one of the second PFET and the second NFET may be formed such that a sidewall thereof is oriented on the second crystal plane to have one of an unoptimized carrier mobility and an optimized carrier mobility.
  • In the above semiconductor structure, a pillar body of one of the first PFET and the first NFET may be formed such that an entire sidewall thereof is oriented on a combination of two or more of a (100) crystal plane, a (110) crystal plane and a (111) crystal plane, and a pillar body of one of the second PFET and the second NFET may be formed such that an entire sidewall thereof is oriented on a combination of two or more of a (100) crystal plane, a (110) crystal plane and a (111) crystal plane.
  • In the above semiconductor structure, each of the first PFET and the first NFET may have a cross-sectionally circular-shaped pillar body, wherein the pillar body of one of the first PFET and the first NFET is formed such that a sidewall thereof has a plurality of crystal planes, and a pillar body of one of the second PFET and the second NFET may be formed such that an entire sidewall thereof is oriented on a combination of two or more of a (100) crystal plane, a (110) crystal plane and a (111) crystal plane.
  • The above semiconductor structure may comprise an SGT CMOS device formed on a silicon wafer having a (100) crystal plane to include the first NFET and the first and second PFETs, wherein the first NFET is formed to have a cross-sectionally quadrangular-shaped pillar body and each of the first and second PFETs is formed to have a cross-sectionally quadrangular-shaped pillar body, and wherein: the cross-sectionally quadrangular-shaped pillar body of the first NFET is formed such that a sidewall thereof has a (100) crystal plane; and the cross-sectionally quadrangular-shaped pillar body of the second PFET is formed such that a sidewall thereof has a (110) crystal plane.
  • The above semiconductor structure may comprise an SGT CMOS device formed on a silicon wafer having a (110) crystal plane to include the first NFET having the cross-sectionally circular-shaped pillar body, and the first PFET, wherein the first PFET is formed to have a cross-sectionally rectangular-shaped pillar body, and wherein: the cross-sectionally circular-shaped pillar body of the first NFET is formed such that a sidewall thereof has a plurality of crystal planes; and the cross-sectionally rectangular-shaped pillar body of the first PFET is formed such that each of two sidewalls thereof defining short sides has a (100) crystal plane, and each of two sidewalls thereof defining long sides has a (110) crystal plane.
  • The above semiconductor structure may comprise an SGT CMOS device formed on a silicon wafer having a (110) crystal plane to include the first NFET having the cross-sectionally circular-shaped pillar body, and the first PFET, wherein the first PFET is formed to have a cross-sectionally quadrangular-shaped pillar body, and wherein: the cross-sectionally circular-shaped pillar body of the first NFET is formed such that a sidewall thereof has a plurality of crystal planes; and the cross-sectionally quadrangular-shaped pillar body of the first PFET is formed such that each of two of four sidewalls thereof has a (100) crystal plane, and each of the remaining two sidewalls has a (110) crystal plane.
  • In the semiconductor structure of the present invention, each of bodies of the first single-crystal semiconductor sidewall channel and the second single-crystal semiconductor sidewall channel may be made of a material selected from a group consisting of silicon, germanium, a silicon compound, a germanium compound, a Group III-V material, and a Group II-IV material.
  • In the above semiconductor structure, each of bodies of the first single-crystal semiconductor sidewall channel and the second single-crystal semiconductor sidewall channel may be doped in a concentration ranging from 1010 to 1017.
  • In accordance with a second aspect of the present invention, there is provided a method of fabricating a semiconductor structure, which comprises the steps of: providing a substrate having a surface oriented on a first crystal plane to be subsequently used as a channel; forming a first surrounding gate transistor (SGT) in such a manner that a first pillar body thereof defines a first channel, and a sidewall of the first pillar body is oriented on a second crystal plane which provides a first carrier mobility; and forming a second surrounding gate transistor (SGT) in such a manner that a second pillar body thereof defines a second channel, and a sidewall of the second pillar body is oriented on a third crystal plane which provides a second carrier mobility different from the first carrier mobility.
  • In the method of the present invention, the surface of the substrate may be oriented on a (100) crystal plane and/or a (110) crystal plane.
  • In the method of the present invention, the step of forming a first SGT may include forming the first SGT to have a cross-sectionally quadrangular (or rectangular)-shaped first pillar body configured such that each of two parallel sidewalls of the first pillar body is oriented on a (n m l) crystal plane, and each of the remaining two sidewalls is oriented on a (a b c) crystal plane, wherein each of n, m, l, a, b and c is any integer, and na+mb+lc=0, and the step of forming a second SGT may include forming the second SGT to have a cross-sectionally quadrangular (or rectangular)-shaped second pillar body configured such that each of two parallel sidewalls of the second pillar body is oriented on a (p q r) crystal plane, and each of the remaining two sidewalls is oriented on a (e f g) crystal plane, wherein each of p, q, r, e, f and g is any integer, and pe+gf+rg=0.
  • In the method of the present invention, the step of forming a first SGT may include forming the first SGT to have a cross-sectionally circular-shaped first pillar body configured such that a sidewall of the first pillar body is oriented on a plurality of crystal planes, and the step of forming a second SGT may include forming the second SGT to have a cross-sectionally quadrangular (or rectangular)-shaped second pillar body configured such that each of two parallel sidewalls of the second pillar body is oriented on a (n m l) crystal plane, and each of the remaining two sidewalls is oriented on a (a b c) crystal plane, wherein each of n, m, l, a, b and c is any integer, and na+mb+lc=0.
  • In the method of the present invention, the step of forming a first SGT may include the sub-step of forming one of a first P-channel SGT (PFET) and a first N-channel SGT (NFET), and the step of forming a second SGT may include the sub-step of forming one of a second P-channel SGT (PFET) and a second N-channel SGT (NFET).
  • In the above method, the sub-step of forming one of a first PFET and a first NFET may include forming one of the first PFET and the first NFET in such a manner that the sidewall of the first pillar body is oriented on a specific crystal plane to have one of an optimized carrier mobility and an unoptimized carrier mobility, and the sub-step of forming one of a second PFET and a second NFET may include forming one of the second PFET and the second NFET in such a manner that the sidewall of the second pillar body is oriented on a specific crystal plane to have one of an optimized carrier mobility and an unoptimized carrier mobility.
  • In the above method, the sub-step of forming one of a first PFET and a first NFET may include forming one of the first PFET and the first NFET to have a cross-sectionally circular-shaped first pillar body configured such that a sidewall of the first pillar body is oriented on a plurality of crystal planes to have one of an optimized carrier mobility and an unoptimized carrier mobility, and the sub-step of forming one of a second PFET and a second NFET may include forming one of the second PFET and the second NFET in such a manner that the sidewall of the second SGT pillar body is oriented on a specific crystal plane to have one of an optimized carrier mobility and an unoptimized carrier mobility.
  • In the above method, the sub-step of forming one of a first PFET and a first NFET may include forming one of the first PFET and the first NFET in such a manner that the entire sidewall of the first pillar body is oriented on a combination of two or more of a (100) crystal plane, a (110) crystal plane and a (111) crystal plane, and the sub-step of forming one of a second PFET and a second NFET may include forming one of the second PFET and the second NFET in such a manner that the entire sidewall of the second pillar body is oriented on a combination of two or more of a (100) crystal plane, a (110) crystal plane and a (111) crystal plane.
  • In the above method, the sub-step of forming one of a first PFET and a first NFET may include forming one of the first PFET and the first NFET in such a manner that the entire sidewall of the first pillar body is oriented on a plurality of crystal planes, and the sub-step of forming one of a second PFET and a second NFET may include forming one of the second PFET and the second NFET in such a manner that the entire sidewall of the second pillar body is oriented on a combination of two or more of a (100) crystal plane, a (110) crystal plane and a (111) crystal plane.
  • The above method may further comprise the step of forming an SGT CMOS device on a silicon wafer having a (100) crystal plane to include a first NMOS SGT (NFET) having a cross-sectionally square-shaped pillar body, and first and second PMOS SGTs (PFETs) each having a cross-sectionally quadrangular-shaped pillar body, wherein: the pillar body of the first NFET is formed such that a sidewall thereof is oriented on a (100) crystal plane; and the pillar body of the second PFET is formed such that a sidewall thereof is oriented on a (110) crystal plane.
  • The above method may further comprise the step of forming an SGT CMOS device on a silicon wafer having a (100) crystal plane to include a first NMOS SGT (NFET) having a cross-sectionally circular-shaped pillar body, and a second PMOS SGT (PFET) having a cross-sectionally quadrangular-shaped pillar body, wherein: the pillar body of the first NFET is formed such that a sidewall thereof is oriented on a plurality of crystal planes; and the pillar body of the second PFET is formed such that each of two parallel sidewalls thereof is oriented on a (100) crystal plane, and each of the remaining two parallel sidewalls is oriented on a (110) crystal plane.
  • The above method may further comprise the step of forming an SGT CMOS device on a silicon wafer having a (110) crystal plane to include a first NMOS SGT (NFET) having a cross-sectionally circular-shaped pillar body, and a second PMOS SGT (PFET) having a cross-sectionally quadrangular-shaped pillar body, wherein: the pillar body of the first NFET is formed such that a sidewall thereof is oriented on a plurality of crystal planes; and the pillar body of the second PFET is formed such that each of two parallel sidewalls thereof is oriented on a (100) crystal plane, and each of the remaining two parallel sidewalls is oriented on a (110) crystal plane.
  • As used in the specification, the term “optimized” generally means that carrier mobility is set to the highest level. However, depending on an intended purpose, carrier mobility is set to a level less than the highest level, in some cases. The term “optimized” is also used to refer to such cases.
  • These and other objects, features and advantages of the present invention will become more apparent upon reading the following detailed description along with the accompanying drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1( a) is a schematic sectional view showing a surface orientation of a sidewall of a silicon SGT pillar formed on a silicon wafer having a (100) crystal plane (Si (100) wafer).
  • FIG. 1( b) is a schematic sectional view showing a surface orientation of a sidewall of a silicon SGT pillar formed on a silicon wafer having a (110) crystal plane (Si (110) wafer).
  • FIG. 2( a) is a graph showing a relationship between a crystal plane of an active region of a transistor and the mobility of electrons flowing through the active region (quotation from U.S. Pat. No. 3,603,848)
  • FIG. 2( b) is a graph showing a relationship between a crystal plane of an active region of a transistor and the mobility of holes flowing through the active region (quotation from U.S. Pat. No. 3,603,848).
  • FIG. 3( a) is a schematic diagram showing a circular pillar-type SGT.
  • FIG. 3( b) is a sectional view of the circular pillar-type SGT, taken along the line B-B′ in FIG. 3( a).
  • FIG. 3( c) is a sectional view of the circular pillar-type SGT, taken along the line A-A′ in FIG. 3( a).
  • FIG. 4( a) is a schematic diagram showing a perfect square pillar-type SGT.
  • FIG. 4( b) is a sectional view of the perfect square pillar-type SGT, taken along the line B-B′ in FIG. 4( a).
  • FIG. 4( c) is a sectional view of the perfect square pillar-type SGT, taken along the line A-A′ in FIG. 4( a).
  • FIG. 5( a) is a schematic diagram showing a corner-rounded square pillar-type SGT.
  • FIG. 5( b) is a sectional view of the corner-rounded square pillar-type SGT, taken along the line B-B′ in FIG. 5( a).
  • FIG. 5( c) is a sectional view of the corner-rounded square pillar-type SGT, taken along the line A-A′ in FIG. 5( a).
  • FIG. 6( a) is a schematic diagram showing an oblate oval pillar-type SGT.
  • FIG. 6( b) is a sectional view of the oblate oval pillar-type SGT, taken along the line B-B′ in FIG. 6( a).
  • FIG. 6( c) is a sectional view of the oblate oval pillar-type SGT, taken along the line A-A′ in FIG. 6( a).
  • FIG. 7( a) is a schematic diagram showing a perfect square pillar-type NMOS SGT (Qn200) fabricated on a Si (100) wafer.
  • FIG. 7( b) is a sectional view of the NMOS SGT (Qn200), taken along the line B-B′ in FIG. 7( a), wherein a current direction and a surface orientation of a sidewall of the NMOS SGT (Qn200) are illustrated.
  • FIG. 7( c) is a sectional view of the NMOS SGT (Qn200), taken along the line A-A′ in FIG. 7( a), wherein C-C′ indicates a distance from a surface of a silicon pillar.
  • FIG. 8( a) is a schematic diagram showing a corner-rounded square pillar-type NMOS SGT (Qn201) fabricated on a Si (100) wafer.
  • FIG. 8( b) is a sectional view of the NMOS SGT (Qn201), taken along the line B-B′ in FIG. 8( a), wherein a current direction and a surface orientation of a sidewall of the NMOS SGT (Qn201) are illustrated.
  • FIG. 8( c) is a sectional view of the NMOS SGT (Qn201), taken along the line A-A′ in FIG. 8( a).
  • FIG. 9( a) is a schematic diagram showing a perfect square pillar-type NMOS SGT (Qn202) fabricated on a Si (100) wafer.
  • FIG. 9( b) is a sectional view of the NMOS SGT (Qn202), taken along the line B-B′ in FIG. 9( a), wherein a current direction and a surface orientation of a sidewall of the NMOS SGT (Qn202) are illustrated.
  • FIG. 9( c) is a sectional view of the NMOS SGT (Qn202), taken along the line A-A′ in FIG. 9( a).
  • FIG. 10( a) is a schematic diagram showing a circular pillar-type NMOS SGT (Qn203) fabricated on a Si (100) wafer.
  • FIG. 10( b) is a sectional view of the NMOS SGT (Qn203), taken along the line B-B′ in FIG. 10( a), wherein a current direction and a surface orientation of a sidewall of the NMOS SGT (Qn203) are illustrated.
  • FIG. 10( c) is a sectional view of the NMOS SGT (Qn203), taken along the line A-A′ in FIG. 10( a), wherein C-C′ indicates a distance from a surface of a silicon pillar.
  • FIG. 11 is a graph showing an Id-Vg curve (per-unit length current to gate voltage) in each of the circular pillar-type and square pillar-type NMOS SGTs (Qn203 in FIGS. 10( a) to 10(c), Qn200 in FIGS. 7( a) to 7(c), Qn201 in FIGS. 8( a) to 8(c), Qn202 in FIGS. 9( a) to 9(c)) fabricated on the Si (100) wafer.
  • FIG. 12 is a graph showing an Id-Vg curve (per-pillar current to gate voltage) in each of the circular pillar-type and square pillar-type NMOS SGTs (Qn203 in FIGS. 10( a) to 10(c), Qn200 in FIGS. 7( a) to 7(c), Qn201 in FIGS. 8( a) to 8(c), Qn202 in FIGS. 9( a) to 9(c)) fabricated on the Si (100) wafer.
  • FIG. 13 is a graph showing an electron density with respect to a distance from the surface of the silicon pillar (C-C′ in FIGS. 7( c) and 10(c)), in each of the circular pillar-type and square pillar-type NMOS SGTs (Qn203 in FIGS. 10( a) to 10(c), Qn200 in FIGS. 7( a) to 7(c)), under conditions that a gate voltage=1 V, and Vd=0.05 V.
  • FIG. 14 is a graph showing a perpendicular electric field with respect to a distance from the surface of the silicon pillar (C-C′ in FIGS. 7( c) and 10(c)), in each of the circular pillar-type and square pillar-type NMOS SGTs (Qn203 in FIGS. 10( a) to 10(c), Qn200 in FIGS. 7( a) to 7(c)), under conditions that a gate voltage=1 V, and Vd=0.05 V.
  • FIG. 15 is a graph showing a local Darwish carrier mobility with respect to a distance from the surface of the silicon pillar (C-C′ in FIGS. 7( c) and 10(c)), in each of the circular pillar-type and square pillar-type NMOS SGTs (Qn203 in FIGS. 10( a) to 10(c), Qn200 in FIGS. 7( a) to 7(c)), under conditions that a gate voltage=1 V, and Vd=0.05 V.
  • FIG. 16 is a graph showing a Darwish carrier mobility with respect to a perpendicular electric field, in each of the circular pillar-type and square pillar-type NMOS SGTs (Qn203 in FIGS. 10( a) to 10(c), Qn200 in FIGS. 7( a) to 7(c)).
  • FIG. 17( a) is a schematic diagram showing an NMOS SGT (Qn204) fabricated on a Si (100) wafer.
  • FIG. 17( b) is a sectional view of the NMOS SGT (Qn204), taken along the line B-B′ in FIG. 17( a), wherein a current direction and a surface orientation of a sidewall of the NMOS SGT (Qn204) are illustrated.
  • FIG. 17( c) is a sectional view of the NMOS SGT (Qn204), taken along the line A-A′ in FIG. 17( a).
  • FIG. 18 is a graph showing an Id-Vg curve (per-unit length current to gate voltage) in the NMOS SGT (Qn204 in FIGS. 17( a) to 17(c)) fabricated on the Si (100) wafer, under a condition that Vd=0.05 V.
  • FIG. 19 is a graph showing an Id-Vg curve (per-pillar current to gate voltage) in the NMOS SGT (Qn204 in FIGS. 17( a) to 17(c)) fabricated on the Si (100) wafer, under a condition that Vd=0.05 V.
  • FIG. 20( a) is a schematic diagram showing a perfect square pillar-type PMOS SGT (Qp200) fabricated on a Si (100) wafer.
  • FIG. 20( b) is a sectional view of the PMOS SGT (Qp200), taken along the line B-B′ in FIG. 20( a), wherein a current direction and a surface orientation of a sidewall of the PMOS SGT (Qp200) are illustrated.
  • FIG. 20( c) is a sectional view of the PMOS SGT (Qp200), taken along the line A-A′ in FIG. 20( a).
  • FIG. 21( a) is a schematic diagram showing a corner-rounded square pillar-type PMOS SGT (Qp201) fabricated on a Si (100) wafer.
  • FIG. 21( b) is a sectional view of the PMOS SGT (Qp201), taken along the line B-B′ in FIG. 21( a), wherein a current direction and a surface orientation of a sidewall of the PMOS SGT (Qp201) are illustrated.
  • FIG. 21( c) is a sectional view of the PMOS SGT (Qp201), taken along the line A-A′ in FIG. 21( a).
  • FIG. 22( a) is a schematic diagram showing a perfect square pillar-type PMOS SGT (Qp202) fabricated on a Si (100) wafer.
  • FIG. 22( b) is a sectional view of the PMOS SGT (Qp202), taken along the line B-B′ in FIG. 22( a), wherein a current direction and a surface orientation of a sidewall of the PMOS SGT (Qp202) are illustrated.
  • FIG. 22( c) is a sectional view of the PMOS SGT (Qp202), taken along the line A-A′ in FIG. 22( a).
  • FIG. 23( a) is a schematic diagram showing a circular pillar-type PMOS SGT (Qp203) fabricated on a Si (100) wafer.
  • FIG. 23( b) is a sectional view of the PMOS SGT (Qp203), taken along the line B-B′ in FIG. 23( a), wherein a current direction and a surface orientation of a sidewall of the PMOS SGT (Qp203) are illustrated.
  • FIG. 23( c) is a sectional view of the PMOS SGT (Qp203), taken along the line A-A′ in FIG. 23( a).
  • FIG. 24 is a graph showing an Id-Vg curve (per-unit length current to gate voltage) in each of the circular pillar-type and square pillar-type PMOS SGTs (Qp203 in FIGS. 23( a) to 23(c), Qp200 in FIGS. 20( a) to 20(c), Qp201 in FIGS. 21( a) to 21(c), Qp202 in FIGS. 22( a) to 22(c)) fabricated on the Si (100) wafer, under a condition that Vd=−0.05 V.
  • FIG. 25 is a graph showing an Id-Vg curve (per-pillar current to gate voltage) in each of the circular pillar-type and square pillar-type PMOS SGTs (Qp203 in FIGS. 23( a) to 23(c), Qn200 in FIGS. 20( a) to 20(c), Qn201 in FIGS. 21( a) to 21(c), Qn202 in FIGS. 22( a) to 22(c)) fabricated on the Si (100) wafer, under the condition that Vd=−0.05 V.
  • FIG. 26( a) is a schematic diagram showing a PMOS SGT (Qp204) fabricated on a Si (100) wafer.
  • FIG. 26( b) is a sectional view of the PMOS SGT (Qp204), taken along the line B-B′ in FIG. 26( a), wherein a current direction and a surface orientation of a sidewall of the PMOS SGT (Qp204) are illustrated.
  • FIG. 26( c) is a sectional view of the PMOS SGT (Qp204), taken along the line A-A′ in FIG. 26( a).
  • FIG. 27 is a graph showing an Id-Vg curve (per-unit length current to gate voltage) in the PMOS SGT (Qp204 in FIGS. 26( a) to 26(c)) fabricated on the Si (100) wafer, under a condition that Vd=0.05 V.
  • FIG. 28 is a graph showing an Id-Vg curve (per-pillar current to gate voltage) in the PMOS SGT (Qp204 in FIGS. 26( a) to 26(c)) fabricated on the Si (100) wafer, under a condition that Vd=0.05 V.
  • FIG. 29( a) is a schematic diagram showing a perfect square pillar-type NMOS SGT (Qn210) fabricated on a Si (110) wafer.
  • FIG. 29( b) is a sectional view of the NMOS SGT (Qn210), taken along the line B-B′ in FIG. 29( a), wherein a current direction and a surface orientation of a sidewall of the NMOS SGT (Qn210) are illustrated.
  • FIG. 29( c) is a sectional view of the NMOS SGT (Qn210), taken along the line A-A′ in FIG. 29( a).
  • FIG. 30( a) is a schematic diagram showing a circular pillar-type NMOS SGT (Qn211) fabricated on a Si (110) wafer.
  • FIG. 30( b) is a sectional view of the NMOS SGT (Qn211), taken along the line B-B′ in FIG. 30( a), wherein a current direction and a surface orientation of a sidewall of the NMOS SGT (Qn211) are illustrated.
  • FIG. 30( c) is a sectional view of the NMOS SGT (Qn211), taken along the line A-A′ in FIG. 30( a).
  • FIG. 31( a) is a schematic diagram showing an NMOS SGT (Qn212) fabricated on a Si (110) wafer.
  • FIG. 31( b) is a sectional view of the NMOS SGT (Qn212), taken along the line B-B′ in FIG. 31( a), wherein a current direction and a surface orientation of a sidewall of the NMOS SGT (Qn212) are illustrated.
  • FIG. 31( c) is a sectional view of the NMOS SGT (Qn212), taken along the line A-A′ in FIG. 31( a).
  • FIG. 32( a) is a schematic diagram showing an NMOS SGT (Qn213) fabricated on a Si (110) wafer.
  • FIG. 32( b) is a sectional view of the NMOS SGT (Qn213), taken along the line B-B′ in FIG. 32( a), wherein a current direction and a surface orientation of a sidewall of the NMOS SGT (Qn213) are illustrated.
  • FIG. 32( c) is a sectional view of the NMOS SGT (Qn213), taken along the line A-A′ in FIG. 32( a).
  • FIG. 33 is a graph showing an Id-Vg curve (per-unit length current to gate voltage) in each of the NMOS SGTs (Qn210 in FIGS. 29( a) to 29(c), Qn211 in FIGS. 30( a) to 30(c), Qn212 in FIGS. 31( a) to 31(c), Qn213 in FIGS. 32( a) to 32(c)) fabricated on the Si (110) wafer, under a condition that Vd=0.05 V.
  • FIG. 34 is a graph showing an Id-Vg curve (per-pillar current to gate voltage) in each of the NMOS SGTs (Qn210 in FIGS. 29( a) to 29(c), Qn211 in FIGS. 30( a) to 30(c), Qn212 in FIGS. 31( a) to 31(c), Qn213 in FIGS. 32( a) to 32(c)) fabricated on the Si (110) wafer, under a condition that Vd=0.05 V.
  • FIG. 35( a) is a schematic diagram showing a perfect square pillar-type PMOS SGT (Qp210) fabricated on a Si (110) wafer.
  • FIG. 35( b) is a sectional view of the PMOS SGT (Qp210), taken along the line B-B′ in FIG. 35( a), wherein a current direction and a surface orientation of a sidewall of the PMOS SGT (Qp210) are illustrated.
  • FIG. 35( c) is a sectional view of the PMOS SGT (Qp210), taken along the line A-A′ in FIG. 35( a).
  • FIG. 36( a) is a schematic diagram showing a circular pillar-type PMOS SGT (Qp211) fabricated on a Si (110) wafer.
  • FIG. 36( b) is a sectional view of the PMOS SGT (Qp211), taken along the line B-B′ in FIG. 36( a), wherein a current direction and a surface orientation of a sidewall of the PMOS SGT (Qp211) are illustrated.
  • FIG. 36( c) is a sectional view of the PMOS SGT (Qp211), taken along the line A-A′ in FIG. 36( a).
  • FIG. 37( a) is a schematic diagram showing a PMOS SGT (Qp212) fabricated on a Si (110) wafer.
  • FIG. 37( b) is a sectional view of the PMOS SGT (Qp212), taken along the line B-B′ in FIG. 37( a), wherein a current direction and a surface orientation of a sidewall of the PMOS SGT (Qp212) are illustrated.
  • FIG. 37( c) is a sectional view of the PMOS SGT (Qp212), taken along the line A-A′ in FIG. 37( a).
  • FIG. 38( a) is a schematic diagram showing a PMOS SGT (Qp213) fabricated on a Si (110) wafer.
  • FIG. 38( b) is a sectional view of the PMOS SGT (Qp213), taken along the line B-B′ in FIG. 38( a), wherein a current direction and a surface orientation of a sidewall of the PMOS SGT (Qp213) are illustrated.
  • FIG. 38( c) is a sectional view of the PMOS SGT (Qp213), taken along the line A-A′ in FIG. 38( a).
  • FIG. 39 is a graph showing an Id-Vg curve (per-unit length current to gate voltage) in each of the PMOS SGTs (Qp210 in FIGS. 35( a) to 35(c), Qp211 in FIGS. 36( a) to 36(c), Qp212 in FIGS. 37( a) to 37(c), Qp213 in FIGS. 38( a) to 38(c)) fabricated on the Si (110) wafer.
  • FIG. 40 is a graph showing an Id-Vg curve (per-pillar current to gate voltage) in each of the PMOS SGTs (Qp210 in FIGS. 35( a) to 35(c), Qp21 in FIGS. 36( a) to 36(c), Qp212 in FIGS. 37( a) to 37(c), Qp213 in FIGS. 38( a) to 38(c)) fabricated on the Si (110) wafer.
  • FIG. 41( a) is a schematic diagram showing a rectangular pillar-type PMOS SGT (Qp220) fabricated on a Si (110) wafer.
  • FIG. 41( b) is a sectional view of the PMOS SGT (Qp220), taken along the line B-B′ in FIG. 41( a), wherein a current direction and a surface orientation of a sidewall of the PMOS SGT (Qp220) are illustrated.
  • FIG. 41( c) is a sectional view of the PMOS SGT (Qp220), taken along the line A-A′ in FIG. 41( a).
  • FIG. 42( a) is a schematic diagram showing a rectangular pillar-type PMOS SGT (Qp221) fabricated on a Si (110) wafer.
  • FIG. 42( b) is a sectional view of the PMOS SGT (Qp221), taken along the line B-B′ in FIG. 42( a), wherein a current direction and a surface orientation of a sidewall of the PMOS SGT (Qp221) are illustrated.
  • FIG. 42( c) is a sectional view of the PMOS SGT (Qp221), taken along the line A-A′ in FIG. 42( a).
  • FIG. 43 is a graph showing an Id-Vg curve (per-unit length current to gate voltage) in each of the rectangular PMOS SGTs (Qp220 in FIGS. 41( a) to 41(c), Qp221 in FIGS. 42( a) to 42(c)) fabricated on the Si (110) wafer.
  • FIG. 44 is a graph showing an Id-Vg curve (per-pillar current to gate voltage) in each of the rectangular PMOS SGTs (Qp220 in FIGS. 41( a) to 41(c), Qp221 in FIGS. 42( a) to 42(c)) fabricated on the Si (110) wafer
  • FIG. 45 is a table showing an absolute current value (per-unit length current, per-pillar current) in each of a total 18 types of combinational SGT CMOS devices each having a different pillar shape and a surface orientation associated therewith as shown in FIGS. 7( a) to 44 (The absolute current value of the Id-Vg curve in each SGT is obtained under a condition that Vg−Vth=0.6 V, and Vd=0.05 V. The threshold voltage (Vth) was defined as a gate voltage in a state when a drain current per unit gate width is 10−10 A/nm.)
  • FIG. 46 is a table showing normalized current values calculated from FIG. 45, in the 18 types of combinational SGT CMOS devices (An absolute current value in the circular pillar-type NMOS SGT (Qn203 in FIGS. 10( a) to 10(c)) under the conditions that Vg−Vth=0.6 V, and Vd=0.05 V, is selected as a reference value (=100) for each of a current density and a per-pillar current).
  • FIG. 47( a) is an equivalent circuit diagram of an SGT CMOS inverter (combinational device 52 in FIG. 46) fabricated on a Si (100) wafer.
  • FIG. 47( b) is a schematic diagram of the SGT CMOS inverter in FIG. 47( a).
  • FIG. 48( a) is an equivalent circuit diagram of an SGT CMOS inverter (combinational device 66 in FIG. 46) fabricated on a Si (110) wafer.
  • FIG. 48( b) is a schematic diagram of the SGT CMOS inverter in FIG. 48( a).
  • FIG. 49( a) is an equivalent circuit diagram of an SGT CMOS inverter (combinational device 61 in FIG. 46) fabricated on a Si (110) wafer.
  • FIG. 49( b) is a schematic diagram of the SGT CMOS inverter in FIG. 49( a) (the SGT CMOS inverter comprises one circular pillar-type NMOS SGT (Qn211 in FIGS. 30( a) to 30(c)) and one perfect square pillar-type PMOS SGT (Qp210 in FIGS. 35( a) to 35(c)), wherein it is formed on a Si (110) wafer)
  • FIG. 50( a) is an equivalent circuit diagram of an SGT CMOS inverter fabricated on a Si (110) wafer
  • FIG. 50( b) is a schematic diagram of the SGT CMOS inverter in FIG. 50( a) (Except for a doping concentration for a silicon pillar body, a structure of the SGT CMOS inverter in FIG. 50( b) and a simulation condition therefor are identical to those of the SGT CMOS inverter (combinational device 61 in FIG. 46) in FIG. 49( b). A high doping concentration (3×1018) for a silicon pillar body is applied to both an NMOS SGT (Na for Qn100) and a PMOS SGT (Nd for Qp100)).
  • FIG. 51 is a schematic diagram showing an electron density contour in a perfect square pillar-type PMOS SGT (Qp100 in FIGS. 50( a) and 50(b)) having a high doping concentration of 3×1018.
  • FIG. 52 is a schematic diagram showing an electron density contour in a perfect square pillar-type PMOS SGT (Qp101 in FIGS. 49( a) and 49(b)) having a low doping concentration of 3.9×1015.
  • FIG. 53 is a schematic diagram showing an electron density contour in a circular pillar-type NMOS SGT (Qn100 in FIGS. 50( a) and 50(b)) having a high doping concentration of 3×1018.
  • FIG. 54 is a schematic diagram showing an electron density contour in a circular pillar-type NMOS SGT (Qn101 in FIGS. 49( a) and 49(b)) having a low doping concentration of 3.9×1015.
  • FIGS. 55( a) and 55(b) are a circuit diagram and a top plan view of a completed SGT CMOS device (combinational CMOS device 66 in FIG. 46).
  • FIGS. 55( c), 55(d), 55(e) and 55(f) are sectional view of the completed SGT CMOS device, taken, respectively, along the line B-B′, the line C-C′ and the line D-D′ in FIG. 55( b).
  • FIG. 56 is a flowchart showing a fabrication method of the present invention.
  • FIGS. 57( a) to 57(f) are perspective views and a top plan view showing a lithographic process for patterning a nanosized square (rectangular)-shaped hard mask on a silicon wafer using two orthogonal exposure lights each including a plurality of straight lines.
  • FIG. 58( a) is a top plan view showing a semiconductor structure according to one embodiment of the present invention in one step of the fabrication method in FIG. 56.
  • FIG. 58( b) is a sectional view of the semiconductor structure in FIG. 58( a).
  • FIG. 59( a) is a top plan view showing a semiconductor structure according to the embodiment, and a lithographic mask, in one step of the fabrication method in FIG. 56.
  • FIG. 59( b) is a sectional view of the semiconductor structure in FIG. 59( a).
  • FIG. 60( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 60( b) is a sectional view of the semiconductor structure in FIG. 60( a).
  • FIG. 61( a) is a top plan view showing a semiconductor structure according to the embodiment, and a lithographic mask, in one step of the fabrication method in FIG. 56.
  • FIG. 61( b) is a sectional view of the semiconductor structure in FIG. 61( a).
  • FIG. 62( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 62( b) is a sectional view of the semiconductor structure in FIG. 62( a).
  • FIG. 63( a) is a top plan view showing a semiconductor structure according to the embodiment, and a lithographic mask, in one step of the fabrication method in FIG. 56.
  • FIG. 63( b) is a sectional view of the semiconductor structure in FIG. 63( a).
  • FIG. 64( a) is a top plan view showing a semiconductor structure according to the embodiment, and a lithographic mask, in one step of the fabrication method in FIG. 56.
  • FIG. 64( b) is a sectional view of the semiconductor structure in FIG. 64( a).
  • FIG. 65( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 65( b) is a sectional view of the semiconductor structure in FIG. 65( a).
  • FIG. 66( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 66( b) is a sectional view of the semiconductor structure in FIG. 66( a).
  • FIG. 67( a) is a top plan view showing a semiconductor structure according to the embodiment, and a lithographic mask, in one step of the fabrication method in FIG. 56.
  • FIG. 67( b) is a sectional view of the semiconductor structure in FIG. 67( a).
  • FIG. 68( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 68( b) is a sectional view of the semiconductor structure in FIG. 68( a).
  • FIG. 69( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 69( b) is a sectional view of the semiconductor structure in FIG. 69( a).
  • FIG. 70( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 70( b) is a sectional view of the semiconductor structure in FIG. 70( a).
  • FIG. 71( a) is a top plan view showing a semiconductor structure according to the embodiment, and a lithographic mask, in one step of the fabrication method in FIG. 56.
  • FIG. 71( b) is a sectional view of the semiconductor structure in FIG. 71( a).
  • FIG. 72( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 72( b) is a sectional view of the semiconductor structure in FIG. 72( a).
  • FIG. 73( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 73( b) is a sectional view of the semiconductor structure in FIG. 73( a).
  • FIG. 74( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 74( b) is a sectional view of the semiconductor structure in FIG. 74( a).
  • FIG. 75( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 75( b) is a sectional view of the semiconductor structure in FIG. 75( a).
  • FIG. 76( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 76( b) is a sectional view of the semiconductor structure in FIG. 76( a).
  • FIG. 77( a) is a top plan view showing a semiconductor structure according to the embodiment, and a lithographic mask, in one step of the fabrication method in FIG. 56.
  • FIG. 77( b) is a sectional view of the semiconductor structure in FIG. 77( a).
  • FIG. 78( a) is a top plan view showing a semiconductor structure according to the embodiment, and a lithographic mask, in one step of the fabrication method in FIG. 56.
  • FIG. 78( b) is a sectional view of the semiconductor structure in FIG. 78( a).
  • FIG. 79( a) is a top plan view showing a semiconductor structure according to the embodiment, and a lithographic mask, in one step of the fabrication method in FIG. 56.
  • FIG. 79( b) is a sectional view of the semiconductor structure in FIG. 79( a).
  • FIG. 80( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 80( b) is a sectional view of the semiconductor structure in FIG. 80( a).
  • FIG. 81( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 81( b) is a sectional view of the semiconductor structure in FIG. 81( a).
  • FIG. 82( a) is a top plan view showing a semiconductor structure according to the embodiment, in one step of the fabrication method in FIG. 56.
  • FIG. 82( b) is a sectional view of the semiconductor structure in FIG. 82( a).
  • FIG. 83( a) is a top plan view showing a semiconductor structure according to the embodiment, and a lithographic mask, in one step of the fabrication method in FIG. 56.
  • FIG. 83( b) is a sectional view of the semiconductor structure in FIG. 83( a).
  • FIG. 84( a) is a top plan view showing a semiconductor structure according to the embodiment, and a lithographic mask, in one step of the fabrication method in FIG. 56.
  • FIG. 84( b) is a sectional view of the semiconductor structure in FIG. 84( a).
  • FIG. 85( a) is an explanatory diagram showing that an SGT CMOS device makes it possible to reduce a device area as compared with a conventional planar CMOS device.
  • FIG. 85( b) is a circuit diagram and a structural diagram showing a conventional SGT CMOS inverter.
  • FIG. 85( c) is a schematic diagram showing a conventional FinFET CMOS inverter using various crystal planes in a current channel of an FET.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • With reference to the accompanying drawings, the present invention will now be described based on various embodiments thereof. The same reference number is used for identifying the same constituent feature.
  • As mentioned above, in the present invention, various crystal planes are used for FET channels to optimize carrier mobility or reduce carrier mobility in each specific device element, based on physical properties of a semiconductor. For facilitating understanding of the present invention, an outline of crystal lattice and crystal orientation will be firstly described.
  • The present invention can be used in various methods for fabricating a plurality of CMOS SGTs on a common substrate using various crystal planes in association with a channel type and a pillar shape of an FET so as to optimize or reduce carrier mobility in each required specific device element to obtain desired performance. It will be understood by those skilled in the art that the present invention is not limited to specific structures illustrated in the accompanying drawings and specific steps which will be described in detail in the specification. It will also be understood that a dopant to be selected and used in the present invention to form various regions of the device element is not limited to a specific type, as long as the dopant is not inconsistent with an intended electric operation of the device element.
  • FIGS. 1( a) and 1(b) show various surface orientations of each sidewall of silicon SGT pillars formed on a respective one of a silicon wafer having a (100) crystal plane (hereinafter referred to as “Si (100) wafer”) (FIG. 1( a)) and a silicon wafer having a (110) crystal plane (hereinafter referred to as “Si (110) wafer”) (FIG. 1( b)) (see Cullity, et al., “Elements of X-ray diffraction”, 2nd edition, Addison-Wesley Publishing Company, Inc., p. 76, 1978). FIGS. 2( a) and 2(b) are graphs showing how electron mobility (FIG. 2( a)) and hole mobility (FIG. 2( b)) are changed depending on the surface orientation of the sidewall of the SGT pillar illustrated in FIGS. 1( a) and 1(b) (see U.S. Pat. No. 3,603,848 granted to Sato, et al.) A device element on the Si (100) wafer uses a left plot (0°/(011) to 45°/(001) sidewall; [100] zone), and a device element on the Si (110) wafer uses a right plot (0°/(011) to 90°/(001) sidewall; [110] zone). In either wafer, a direction of current flow is perpendicular to the wafer.
  • FIGS. 3( a) to 3(c) are schematic diagrams showing a circular pillar-type SGT (SGT having a silicon pillar formed in a cross-sectionally circular shape), wherein R, L and WSGT indicate a radius of the pillar, a gate length and a gate width, respectively. FIGS. 4( a) to 5(c) are schematic diagrams showing a perfectly square pillar-type SGT (SGT having a silicon pillar formed in a cross-sectionally perfectly square shape) (FIGS. 4( a) to 4(c)) and a corner-rounded square pillar-type SGT (SGT having a silicon pillar formed in a cross-sectionally generally square shape with rounded corners) (FIGS. 5( a) to 5(c)), wherein t, r, L and WSGT indicate a thickness of the pillar, a radius of the rounded corner, a gate length and gate width, respectively. FIGS. 6( a) to 6(c) are schematic diagrams showing an oblate oval pillar-type SGT (SGT having a silicon pillar formed in a cross-sectionally oblate oval shape. The oblate oval shape comprises right and left semicircular segments and an intermediate rectangular segment. In FIGS. 6( a) to 6(c), R, t, L and WSGT indicate a radius of each of the right and left semicircular segments, a length of the intermediate rectangular segment, a gate length and a gate width, respectively. In each of the SGTs, a source, a gate and a drain are arranged in a direction perpendicular to a silicon substrate. Further, a gate electrode is disposed to fully surround the silicon pillar, so that a channel region is formed along a sidewall of the pillar. As one example, a semiconductor wafer has a size to allow the pillar to have a height dimension of about 20 to 300 nm and other size (t or R) of about 5 to 250 nm.
  • In order to perform a simulation for a semiconductor structure of the present invention (FIGS. 7( a) to 44), the following structure was employed by way of example. A pillar body region of a silicon pillar is uniformly doped with boron (3.9×1015) for an NMOS SGT or arsine (3.9×1015) for a PMOS SGT. Each of t and 2R (related to a size of the silicon pillar) is set at 35 nm. In order to adjust a threshold voltage while suppressing an OFF-current, metal silicide having a work function of 4.65 eV is used as a gate material. A thickness of a gate oxide is set at 1 nm. A diffusion layer (having a length (l) of 20 nm) in a source/drain region is doped with boron (1×1020) for a PFET or arsine (1×1020) for an NFET. In this simulation, quantum charge confinement effects are left out of consideration. A vertical sidewall of each of a circular pillar-type NMOS SGT and a circular pillar-type PMOS SGT is divided equally into thirty-six segments. Thus, a surface orientation of each of the sidewall segments is changed by 10 degrees. In this manner, the sidewall of the cross-sectionally circular pillar is divided into thirty-six segments, so that each of the device elements is made up of thirty-six individual MOSFET sub-elements. A terminal current of the entire device element is calculated by summing respective currents of the sub-elements.
  • I d = n = 1 36 i D n
  • A vertical sidewall of each of a perfectly square pillar-type SGT and a corner-rounded square pillar-type SGT is divided to form four pentahedrons 501 to 504 (for the perfectly square pillar-type SGT) or to form eight polyhedrons 505 to 512 (for the corner-rounded square pillar-type SGT), as shown in FIGS. 4( b) and 5(b) which are sectional views taken along the respective lines B-B′ in FIGS. 4( a) and 5(a). A vertical sidewall of an oblate oval pillar-type SGT is divided to form thirty-six polyhedrons and one hexahedron (total thirty-seven individual MOSFET sub-elements). The simulation of the device elements is performed using an ATLAS three-dimensional simulator (SILVACO). The three-dimensional simulator is set while taking into account a Boltzmann carrier statistics model, a Darwish CVT mobility model and a Shockley-Reed-Hall recombination model.
  • FIGS. 7( a), 8(a) and 9(a) are schematic diagrams showing three square pillar-type NMOS SGTs (Qn200, Qn201, Qn202) each fabricated on a Si (100) wafer. FIGS. 7( b), 8(b) and 9(b) are sectional views of the square pillar-type NMOS SGTs (Qn200, Qn201, Qn202), taken along the respective lines B-B′ in FIGS. 7( a), 8(a) and 9(a). Each of FIGS. 7( b), 8(b) and 9(b) shows a current direction and a surface orientation of a sidewall in a respective one of the NMOS SGTs (Qn200, Qn201, Qn202). It is noted that the surface orientation of the sidewall of the NMOS SGT Qn202 corresponds to a surface orientation obtained by rotating the NMOS SGT Qn200 by 45 degrees. FIGS. 7( c), 8(c) and 9(c) are vertical sectional views of the square pillar-type NMOS SGTs (Qn200, Qn201, Qn202), taken along the respective lines A-A′ in FIGS. 7( a), 8(a) and 9(a). FIG. 10( a) is a schematic diagram showing a circular pillar-type NMOS SGT Qn203 fabricated on a Si (100) wafer. FIG. 10( b) is a sectional view of the circular pillar-type NMOS SGT (Qn203), taken along the line B-B′ in FIG. 10( a). FIG. 10( c) is a vertical sectional view of the circular pillar-type NMOS SGT (Qn203), taken along the line A-A′ in FIG. 10( a).
  • FIG. 11 shows an Id-Vg curve (current per unit length (per-unit length current) to gate voltage) in each of the circular pillar-type and square pillar-type NMOS SGTs (Qn203 in FIGS. 10( a) to 10(c), Qn200 in FIGS. 7( a) to 7(c), Qn201 in FIGS. 8( a) to 8(c), and Qn202 in FIGS. 9( a) to 9(c)) fabricated on the Si (100) wafer, under a condition that Vd=0.05 V. As seen in FIG. 11, the square pillar-type NMOS SGT having a sidewall with a surface orientation of (100) has a per-unit length current greater than that in each of the circular pillar-type NMOS SGT and the square pillar-type NMOS SGT having a sidewall with a surface orientation of (110), at the same Vg (ON). Further, the respective Id-Vg curves (per-unit length current to gate voltage) of the perfect square pillar-type SGT and the corner-rounded square pillar-type SGT have approximately the same characteristic. FIG. 12 shows an Id-Vg curve (current per pillar (per-pillar current) to gate voltage) in each of the circular pillar-type and square pillar-type NMOS SGTs (Qn203 in FIGS. 10( a) to 10(c), Qn200 in FIGS. 7( a) to 7(c), Qn201 in FIGS. 8( a) to 8(c), and Qn202 in FIGS. 9( a) to 9(c)) fabricated on the Si (100) wafer, under a condition that Vd=0.05 V. The circular pillar-type SGT has a gate width less than that in the square pillar-type SGT. Thus, in the circular pillar-type SGT, a relative current value (per-pillar current) in FIG. 12 is significantly lowered from a current value (per-unit length current) in FIG. 11, as compared with the square pillar-type SGTs.
  • FIGS. 13 to 16 show a result of detailed three-dimensional simulation performed for the circular pillar-type SGT (Qn203 in FIGS. 10( a) to 10(c)) and the square pillar-type NMOS SGT (Qn200 in FIGS. 7( a) to 7(c)) each formed on the Si (100) wafer. FIG. 13 shows how an electron density distribution is changed in a depth direction (along each of the lines C-C′ in FIGS. 10( b) and 7(b)) from a surface of the Si sidewall of the circular pillar-type SGT (Qn203 in FIGS. 10( a) to 10(c)) and the square pillar-type NMOS SGT (Qn200 in FIGS. 7( a) to 7(c)), under conditions that Vg=1 V and Vd=0.05 V. FIG. 14 shows how a perpendicular electric field (electric field perpendicular to the surface of the pillar) is changed in the depth direction (along each of the lines C-C′ in FIGS. 10( b) and 7(b)) from the surface of the Si sidewall of the circular pillar-type SGT (Qn203 in FIGS. 10( a) to 10(c)) and the square pillar-type NMOS SGT (Qn200 in FIGS. 7( a) to 7(c)), under conditions that Vg=1 V and Vd=0.05 V. FIG. 15 shows how a local carrier mobility is changed in the depth direction (along each of the lines C-C′ in FIGS. 10( b) and 7(b)) from the surface of the Si sidewall of the circular pillar-type SGT (Qn203 in FIGS. 10( a) to 10(c)) and the square pillar-type NMOS SGT (Qn200 in FIGS. 7( a) to 7(c)), under conditions that Vg=1 V and Vd=0.05 V. FIG. 15 shows how a local carrier mobility is changed in the depth direction (along each of the lines C-C′ in FIGS. 10( b) and 7(b)) from the surface of the Si sidewall of the circular pillar-type SGT (Qn203 in FIGS. 10( a) to 10(c)) and the square pillar-type NMOS SGT (Qn200 in FIGS. 7( a) to 7(c)), under conditions that Vg=1 V and Vd=0.05 V. FIG. 16 shows how a Darwish carrier mobility (Darwish model-based carrier mobility) is changed with respect to the perpendicular electric field, in each of the circular pillar-type SGT (Qn203 in FIGS. 10( a) to 10(c)) and the square pillar-type NMOS SGT (Qn200 in FIGS. 7( a) to 7(c)). A potential and an electron density distribution were derived by solve a Poisson equation and a drift-diffusion-type transport equation.
  • As seen in FIGS. 13 and 14, as to each of the electron density and the perpendicular electric field, the circular pillar-type SGT and the square pillar-type SGT exhibit similar distributions along an x-axis (distance from the surface). However, the circular pillar-type SGT and the square pillar-type SGT exhibit a large difference in each of the local carrier mobility and the Darwish carrier mobility dependent on the surface orientation of the sidewall and the perpendicular electric field, which causes a difference in performance between the device elements in terms of the Id-Vg curve (FIG. 11). Specifically, a value of the current is proportional to each of the electron density and the carrier mobility, and thereby a current in the Id-Vg curve of the square pillar-type SGT (Qn200 in FIG. 11) is greater than that in the Id-Vg curve of the circular pillar-type SGT (Qn203 in FIG. 11), under the same gate electrode (Vg=1 V). For understanding of a more detail relationship between the above parameters, the formulas of the Darwish CVT model and the drift-diffusion-type transport model will be referred to as follows.
  • Darwish CVT:
  • μ T = 1 μ A C + 1 μ b + 1 μ Sr μ A C = a E b + cN d T L E e μ sr = f E g ,
  • wherein:
      • μT is a carrier mobility;
      • μAC is a surface carrier mobility based on scattering due to acoustical phonon;
      • μb is a carrier mobility based on intervalley scattering due to acoustical phonon;
      • μsr is a surface roughness coefficient; and
      • E is a perpendicular electric field.
  • Further, a, b, c, d, e, f and g are constants or parameters as dependent factors, such as doping, temperature and surface orientation.
  • Drift-Diffusion-Type Transport Model

  • J n(current densities)=− T·n n∇Φ n
  • , wherein: q is an electron charge; μ7·n is an electron mobility; n is an electron density; and Φn is a quasi-Fermi level (see: Darwish, et al., “An Improved Electron and Hole Mobility Model for General Purpose Device Simulation”, IEEE Electron Devices, Vol. 44, No. 9, September 1997, p. 1529; and “ATLAS User's Manual: Device Simulation Software”, Silvaco International, August 2006, pp. 3-26)
  • FIG. 17( a) is a schematic diagram showing an NMOS SGT (Qn204) fabricated on a Si (100) wafer. FIG. 17( b) is a sectional view of the NMOS SGT (Qn204), taken along the line B-B′ in FIG. 17( a), and FIG. 17( c) is a sectional view of the NMOS SGT (Qn204), taken along the line A-A′ in FIG. 17( a). FIG. 18 shows an Id-Vg curve (per-unit length current to gate voltage) of the NMOS SGT (Qn204) fabricated on the Si (100) wafer, under a condition that Vd=0.05 V. FIG. 19 shows an Id-Vg curve (per-pillar current to gate voltage) of the NMOS SGT (Qn204) fabricated on the Si (100) wafer, under a condition that Vd=0.05 V.
  • FIGS. 20( a), 21(a) and 22(a) are schematic diagrams showing three square pillar-type PMOS SGTs (Qp200, Qp201, Qp202) each fabricated on a Si (100) wafer. FIGS. 20( b), 21(b) and 22(b) are sectional views of the square pillar-type PMOS SGTs (Qp200, Qp201, Qp202), taken along the respective lines B-B′ in FIGS. 20( a), 21(a) and 22(a). Each of FIGS. 20( b), 21(b) and 22(b) shows a current direction and a surface orientation of a sidewall in a respective one of the PMOS SGTs (Qp200, Qp201, Qp202). The surface orientation of the sidewall of the PMOS SGT Qp202 corresponds to a surface orientation obtained by rotating the PMOS SGT Qp200 by 45 degrees. FIGS. 20( c), 21(c) and 22(c) are vertical sectional views of the square pillar-type PMOS SGTs (Qp200, Qp201, Qp202), taken along the respective lines A-A′ in FIGS. 20( a), 21(a) and 22(a). FIG. 23( a) is a schematic diagram showing a circular pillar-type PMOS SGT (Qp203) fabricated on a Si (100) wafer. FIG. 23( b) is a sectional view of the circular pillar-type PMOS SGT (Qp203), taken along the line B-B′ in FIG. 23( a). FIG. 23( c) is a vertical sectional view of the circular pillar-type PMOS SGT (Qp203), taken along the line A-A′ in FIG. 23( a).
  • FIG. 24 shows an Id-Vg curve (per-unit length current to gate voltage) in each of the circular pillar-type and square pillar-type PMOS SGTs (Qp203 in FIGS. 23( a) to 23(c), Qp200 in FIGS. 20( a) to 20(c), Qp201 in FIGS. 21( a) to 21(c), and Qp202 in FIGS. 22( a) to 22(c)) fabricated on the Si (100) wafer. As seen in FIG. 24, the square pillar-type PMOS SGT having a sidewall with a surface orientation of (110) has a per-unit length current greater than that in each of the circular pillar-type PMOS SGT and the square pillar-type PMOS SGT having a sidewall with a surface orientation of (100), at the same Vg (ON). Further, the respective Id-Vg curves (per-unit length current to gate voltage) of the perfect square pillar-type SGT and the corner-rounded square pillar-type SGT have approximately the same characteristic. FIG. 25 shows an Id-Vg curve (per-pillar current to gate voltage) in each of the circular pillar-type and square pillar-type PMOS SGTs (Qp203 in FIGS. 23( a) to 23(c), Qp200 in FIGS. 20( a) to 20(c), Qp201 in FIGS. 21( a) to 21(c), and Qn202 in FIGS. 22( a) to 22(c)) fabricated on the Si (100) wafer.
  • FIG. 26( a) is a schematic diagram showing a PMOS SGT (Qp204) fabricated on a Si (100) wafer. FIG. 26( b) is a sectional view of the PMOS SGT (Qp204), taken along the line B-B′ in FIG. 26( a), and FIG. 26( c) is a sectional view of the PMOS SGT (Qp204), taken along the line A-A′ in FIG. 26( a). FIG. 27 shows an Id-Vg curve (per-unit length current to gate voltage) of the PMOS SGT (Qp204) fabricated on the Si (100) wafer, under a condition that Vd=0.05 V. FIG. 28 shows an Id-Vg curve (per-pillar current to gate voltage) of the PMOS SGT (Qp204) fabricated on the Si (100) wafer, under a condition that Vd=0.05 V.
  • FIG. 29( a) is a schematic diagram showing a perfect square pillar-type NMOS SGT (Qn210) fabricated on a Si (110) wafer, and FIG. 29( b) is a sectional view of the NMOS SGT (Qn210), taken along the line B-B′ in FIG. 29( a). FIG. 29( b) shows a current direction and a surface orientation of a sidewall in the SGT. A current direction in the SGT fabricated on the Si (100) wafer is <100>, whereas a current direction in the SGT fabricated on the Si (110) wafer is <110>. FIG. 29( c) is a sectional view of the NMOS SGT (Qn210), taken along the line A-A′ in FIG. 29( a). FIG. 30( a) is a schematic diagram showing a circular pillar-type NMOS SGT (Qn211) fabricated on a Si (110) wafer. FIG. 30( b) is a sectional view of the NMOS SGT (Qn211), taken along the line B-B′ in FIG. 30( a), and FIG. 30( c) is a sectional view of the NMOS SGT (Qn211), taken along the line A-A′ in FIG. 30( a). FIGS. 31( a) and 32(a) are schematic diagrams showing two NMOS SGTs (Qn212 and Qn213) each fabricated on a Si (110) wafer. FIGS. 31( b) and 32(b) are sectional views of the NMOS SGTs (Qn212 and Qn213), taken along the respective lines B-B′ in FIGS. 31( a) and 32(a), and FIGS. 31( c) and 32(c) are sectional views of the NMOS SGTs (Qn212 and Qn213), taken along the respective lines A-A′ in FIGS. 31( a) and 32(a). FIG. 33 shows an Id-Vg curve (per-unit length current to gate voltage) in each of the NMOS SGTs (Qn210 in FIGS. 29( a) to 29(c), Qn211 in FIGS. 30( a) to 30(c), Qn212 in FIGS. 31( a) to 31(c), and Qn213 in FIGS. 32( a) to 32(c)) fabricated on the Si (110) wafer, under a condition that Vd=0.05 V. FIG. 34 shows an Id-Vg curve (per-pillar current to gate voltage) in each of the NMOS SGTs (Qn210 in FIGS. 29( a) to 29(c), Qn211 in FIGS. 30( a) to 30(c), Qn212 in FIGS. 31( a) to 31(c), and Qn213 in FIGS. 32( a) to 32(c)) fabricated on the Si(110) wafer, under a condition that Vd=0.05 V.
  • FIG. 35( a) is a schematic diagram showing a perfect square pillar-type PMOS SGT (Qp210) fabricated on a Si (110) wafer. FIG. 35( b) is a sectional view of the PMOS SGT (Qp210), taken along the line B-B′ in FIG. 35( a), and FIG. 35( c) is a sectional view of the PMOS SGT (Qp210), taken along the line A-A′ in FIG. 35( a). FIG. 36( a) is a schematic diagram showing a circular pillar-type PMOS SGT (Qp211) fabricated on a Si (110) wafer. FIG. 36( b) is a sectional view of the PMOS SGT (Qp211), taken along the line B-B′ in FIG. 36( a), and FIG. 36( c) is a sectional view of the PMOS SGT (Qp211), taken along the line A-A′ in FIG. 36( a). FIGS. 37( a) and 38(a) are schematic diagrams showing two PMOS SGTs (Qp212 and Qp213) each fabricated on a Si (110) wafer. FIGS. 37( b) and 38(b) are sectional views of the PMOS SGTs (Qp212 and Qp213), taken along the respective lines B-B′ in FIGS. 37( a) and 38(a), and FIGS. 37( c) and 37(c) are sectional views of the PMOS SGTs (Qp212 and Qp213), taken along the respective lines A-A′ in FIGS. 37( a) and 38(a). FIG. 39 shows an Id-Vg curve (per-unit length current to gate voltage) in each of the PMOS SGTs (Qp210 in FIGS. 35( a) to 35(c), Qp211 in FIGS. 36( a) to 36(c), Qp212 in FIGS. 37( a) to 37(c), and Qp213 in FIGS. 38( a) to 38(c)) fabricated on the Si (110) wafer. FIG. 40 shows an Id-Vg curve (per-pillar current to gate voltage) in each of the PMOS SGTs (Qp210 in FIGS. 35( a) to 35(c), Qp211 in FIGS. 36( a) to 36(c), Qp212 in FIGS. 37( a) to 37(c), and Qp213 in FIGS. 38( a) to 38(c)) fabricated on the Si (110) wafer.
  • FIGS. 41( a) and 42(a) are schematic diagrams showing two rectangular pillar-type PMOS SGTs (SGTs each having a silicon pillar formed in a cross-sectionally rectangular shape) (Qp220 and Qp221), fabricated on a Si (110) wafer. FIGS. 41( b) and 41(b) are horizontal sectional views of the PMOS SGTs (Qp220 and Qp221), taken along the respective lines B-B′ in FIGS. 41( a) and 42(a), and FIGS. 41( c) and 42(c) are vertical sectional views of the PMOS SGTs (Qp220 and Qp221), taken along the respective lines A-A′ in FIGS. 41( a) and 42(a). FIG. 43 shows an Id-Vg curve (per-unit length current to gate voltage) in each of the rectangular pillar-type and square pillar-type PMOS SGTs (Qp220 in FIGS. 41( a) to 41(c), Qp221 in FIGS. 42( a) to 42(c), and Qp210 in FIGS. 35( a) to 35(c)) fabricated on the Si (110) wafer. FIG. 44 shows an Id-Vg curve (per-pillar current to gate voltage) in each of the rectangular pillar-type and square pillar-type e PMOS SGTs (Qp220 in FIGS. 41( a) to 41(c), Qp221 in FIGS. 42( a) to 42(c), and Qp210 in FIGS. 35( a) to 35(c)) fabricated on the Si (110) wafer.
  • FIG. 45 is a table showing an absolute value of current (per-unit length current and per-pillar current) in each of a plurality of SGT CMOS devices made up of various combinations of a plurality of types of PMOS SGTs and a plurality of types of NMOS SGTs. Specifically, a cross-sectional shape of a pillar is changed, and further the shape is rotated, to allow the combinational CMOS devices to be obtained with various per-unit width currents and per-pillar currents. As one example, FIG. 45 shows a total of 18 types of combinational CMOS devices which are different from each other in pillar shape and corresponding surface orientation as shown in FIGS. 7( a) to 44. The absolute value of current in the Id-Vg curves for each SGT was obtained under conditions that Vg−Vth=0.6 V, and Vd=0.05 V.
  • FIG. 46 is a table showing normalized current values in the plurality of types of combinational SGT CMOS devices. In this table, an absolute value of current in the circular pillar-type NMOS SGT (Qn203 in FIGS. 10( a) to 10(c)) (under the conditions that Vg−Vth=0.6 V, and Vd=0.05 V) was selected as a reference value (=100), wherein the threshold voltage Vth was defined as a gate voltage in a state when a drain current per unit gate width is 10−10 A/nm. Depending on a specific intended purpose, a CMOS structure suitable for optimizing or reducing carrier mobility of a device element can be selected from the combinational CMOS devices illustrated in FIG. 46. It is not meant that each of the number of NMOS elements and the number of PMOS elements in each of the combinational CMOS devices illustrated in FIG. 46 must be one. Although each of the combinational CMOS devices may be obviously made up of one NMOS element and one PMOS element, it may be made up, for example, of one NMOS element and two PMOS elements, depending on an intended purpose. In the conventional SGT CMOS device (FIGS. 85( a) and 85(b)), an NMOS SGT and a PMOS SGT each having the same surface orientation are used, in the same manner as that in the combinational device 53 in FIG. 46 or the combinational device 54 in FIG. 46.
  • FIGS. 47( a) to 48(b) show two of the combinational CMOS devices illustrated in FIG. 46, by way of example. FIG. 47( a) is a circuit diagram of a SGT CMOS inverter (corresponding to the combinational device 52 in FIG. 46) fabricated on a Si (100) wafer, and FIG. 47( b) is a layout diagram of the SGT CMOS inverter in FIG. 47( a). The CMOS inverter in FIGS. 47( a) and 47(b) comprises one perfect square pillar-type NMOS SGT (Qn1; each of four sidewalls of a cross-sectionally perfect square-shaped pillar therein has a surface orientation set to a (100) crystal plane), and two 45-degree rotated perfect square pillar-type PMOS SGTs (Qp1 and Qp2; each of four sidewalls of a cross-sectionally perfect square-shaped pillar in each of the SGTs has a surface orientation set to a (110) crystal plane). Respective drains of the NMOS SGT and each of the PMOS SGTs are connected to each other through a local line to have an output potential (Vout1), and respective gates of the NMOS SGT and each of the PMOS SGTs are connected to each other through a gate conductor to have an input (Vin1). Further, in the CMOS inverter having the above connection, a power supply voltage (Vdd1) is supplied to a source of each of the PMOS SGTs through a local line, and a source of the NMOS SGT is connected to ground (Gnd1) through a local line. In this manner, the combinational device having the above series connection is connected between the Vdd1 and the Gnd1. The reason for selection of the layout illustrated in FIG. 47( b) is that this layout allows each of the NMOS element and the PMOS element to exhibit excellent element performance (i.e., a desired current level in an Id-Vg curve). In a typical inverter as shown in FIG. 47( b), a current level in an Id-Vg curve of the NMOS element is fairly greater than that in an Id-Vg curve of the PMOS element, and therefore it is necessary to combine one perfect square pillar-type NMOS SGT (Qn1) with two perfect square pillar-type PMOS SGTs (Qp1 and Qp2).
  • FIG. 48( a) is a circuit diagram of a SGT CMOS inverter (corresponding to the combinational device 66 in FIG. 46) fabricated on a Si (110) wafer, and FIG. 48( b) is a layout diagram of the SGT CMOS inverter in FIG. 48( a). The CMOS inverter in FIGS. 48( a) and 48(b) comprises one circular pillar-type NMOS SGT (Qn3), and one rectangular pillar-type PMOS SGT (Qp3). In the rectangular pillar-type PMOS SGT, each of two parallel (relatively long) sidewalls has a surface orientation set to a (110) crystal plane, and each of the remaining two parallel (relatively short) sidewalls has a surface orientation set to a (100) crystal plane. Respective drains of the PMOS SGT and the NMOS SGT are connected to each other through a local line to have an output potential (Vout3), and respective gates of the PMOS SGT and the NMOS SGT are connected to each other through a gate conductor to have an input (Vin3). Further, in the CMOS inverter having the above connection, a power supply voltage (Vdd3) is supplied to a source of the PMOS SGT through a local line, and a source of the NMOS SGT is connected to ground (Gnd3) through a local line. In this manner, the combinational device having the above series connection is connected between the Vdd3 and the Gnd3. The reason for selection of the layout illustrated in FIG. 48( b) is that this layout allows the CMOS inverter to exhibit high performance while allowing the circular pillar-type NMOS element to exhibit element performance (a current level in an Id-Vg curve) similar to that of the rectangular pillar-type PMOS element. Instead of the combination of one NMOS SGT and two PMOS SGTs, the combinational CMOS device illustrated in FIGS. 48( a) and 48(b) comprises one NMOS SGT and one PMOS SGT, so that a cell size is significantly reduced as compared with the combinational device illustrated in FIGS. 47( a) and 47(b). The resection in cell size provides a higher package density of sophisticated electronic devices, such as MPU and DRAM, and a lower interconnection resistance. This makes it possible to achieve a high-performance CMOS device having a high switching speed. In the present invention, the reduction in size of the cell size (or equalization between respective current levels in an NMOS element and a PMOS element) is achieved by using a plurality of crystal planes. In the conventional planer CMOS device, the equalization between respective current levels in an NMOS element and a PMOS element has to be achieved by fabricating the PMOS element to allow a channel width thereof to become greater than that of the NMOS element.
  • FIGS. 49( a) to 54 show how performance (particularly, behavior of an OFF current) of an SGT CMOS device is dependent on doping of a silicon pillar body. FIG. 49( b) is a top plan view showing an SGT CMOS device (corresponding to the combinational CMOS device 61 in FIG. 46) fabricated on a Si (110) wafer, and FIG. 49( a) is a circuit diagram of the SGT CMOS device in FIG. 49( b). FIG. 50( b) is a top plan view showing an SGT CMOS device fabricated on a Si (110) wafer (wherein a doping concentration for a silicon pillar body is 3×1018), and FIG. 50( a) is a circuit diagram of the SGT CMOS device in FIG. 50( b). Except for the doping concentration for the silicon pillar body, a structure of the SGT CMOS device in FIG. 50( b) and a simulation condition therefor are identical to those of the SGT CMOS device in FIG. 49( b). Specifically, a doping concentration for a silicon pillar body in each of an NMOS SGT (Qn101) and a PMOS SGT (Qp101) in FIG. 49( b) (doping concentration in Qn101: Na; doping concentration in Qp101: Nd) is set at 3.9×1015, whereas a doping concentration for a silicon pillar body in each of an NMOS SGT (Qn100) and a PMOS SGT (Qp100) in FIG. 50( b) (doping concentration in Qn100: Na; doping concentration in Qp100: Nd) is set at 3×1018. FIG. 51 shows an electron density in an OFF-current state (Ioff=1012 A/nm) of a perfect square pillar-type PMOS SGT (Qp100) having a silicon pillar body doped in a concentration Nd of 3×1018. FIG. 52 shows an electron density in an OFF-current state (Ioff=1012 A/nm) of a perfect square pillar-type PMOS SGT (Qp101) having a silicon pillar body doped in a concentration Nd of 3.9×1015. FIG. 53 shows a hole density in an OFF-current state (Ioff=1012 A/nm) of a circular pillar-type NMOS SGT (Qn100) having a silicon pillar body doped in a concentration Na of 3×1018. FIG. 54 shows a hole density in an OFF-current state (Ioff=1012 A/nm) of a circular pillar-type NMOS SGT (Qn101) having a silicon pillar body doped in a concentration Na of 3.9×1015. As shown in FIG. 51, as compared with the low channel-doped SGT (FIG. 52), a strong corner effect (i.e., large accumulation of carriers in corners) occurs in the high channel-doped SGT (FIG. 51). Further, the perfect square pillar-type SGT (FIG. 51) exhibits a corner effect greater than that the circular pillar-type SGT (FIG. 53), because the perfect square pillar-type SGT has four right-angled corners. It is known that this corner effect causes an undesirable device cutoff characteristic (see Song, et al., “Design optimization of Gate-All-Around (GAA) MOSFETs”, IEEE Trans, Nanotechnology, Vol. 5, No. 3, March 2006, pp. 186-1221). Thus, an adverse influence of the corner effect can be significantly reduced by using the low channel-doping concentration (3.9×1015). In particular, as a preferred embodiment of the present invention, if the doping concentration for the silicon pillar body is set at a low value ranging from 1010 to 1017, the corner effect can be reduced to provide enhanced element performance. If the doping concentration for the silicon pillar body is further reduced, a variation in Vth is suppressed to provide enhanced carrier mobility.
  • FIG. 55( a) is a circuit diagram showing an SGT CMOS device (combinational CMOS device 66 in FIG. 46) fabricated on a Si (110) wafer. FIG. 55( b) is a top plan view of the SGT CMOS device in FIG. 55( a), and FIGS. 55( c) to 55(f) are sectional views of the SGT CMOS device, taken, respectively, along the line A-A′, the line B-B′, the line C-C′ and the line D-D′ in FIG. 55( b). A silicon pillar 128 of an NMOS SGT (Qn5) and a silicon pillar 129 of a PMOS SGT (Qp5) are fabricated on a semiconductor 114, and surrounded by a gate oxide 131 and a gate conductor 132. The NMOS SGT (Qn5) and the PMOS SGT (Qp5) are isolated from each other by a trench region 115, and each of the NMOS SGT (Qn5) and the PMOS SGT (Qp5) is formed with a bottom drain (118, 116) and an upper source (138, 137). The SGT CMOS device is connected to each of a drain voltage (Vdd5) and ground (Gnd5) via silicide (salicide) layers 120, 139 formed through a self-alignment process, and a metal line 152. Isolation between respective conductors is performed using dielectric materials 150, 130. Respective drains of the PMOS SGT (Qp5) and the NMOS SGT (Qn5) are connected to each other through a local line to have an output potential (Vout5), and respective gates of the PMOS SGT (Qp5) and the NMOS SGT (Qn5) are connected to each other through a gate conductor 132 to have an input potential (Vin5). In the SGT CMOS device, the power supply voltage (Vdd5) is supplied to a source of the PFET (Qp5) through a local line, and a source of the NFET (Qn5) is connected to the ground (Gnd5) through a local line. In this manner, the combinational device having the above series connection is connected between the Vdd5 and the Gnd5.
  • FIG. 56 shows a preferred method 100 of the present invention to achieve an actual polyhedral SGT CMOS device (FIG. 55). FIGS. 57( a) to 57(f) show a process of performing lithographic exposure twice in such a manner that two pairs of parallel straight lines mutually intersect at right angles, so as to pattern a nanosized square hard mask on a silicon wafer. FIGS. 58( a), 59(a), - - - , 83(a) and 84(a) are top plan views of a semiconductor structure according to one embodiment of the present invention, and a lithographic mask, in each step of the fabrication method illustrated in FIG. 56. FIGS. 58( b), 59(b), - - - , 83(b) and 84(b) are sectional views taken, respectively, along the lines A-A′ in FIGS. 58( a), 59(a), - - - , 83(a) and 84(a).
  • In the fabrication method of the present invention, a SGT CMOS device is formed through the following steps. Firstly, a substrate having a surface with a first crystal orientation is prepared. This surface will be subsequently used as a channel. Then, a first transistor is formed in such a manner that a sidewall of a first SGT body defines a first current channel, wherein the sidewall of the first SGT body has a second crystal orientation with a first carrier mobility. Then, a second transistor is formed in such a manner that a sidewall of a second SGT body defines a second current channel, wherein the sidewall of the second SGT body has a third crystal orientation with a second carrier mobility different from the first carrier mobility.
  • More specifically, in a first step 102 of the method 100 in FIG. 56, a first crystal plane subsequently usable as a current channel of an FET, such as (110) crystal plane or (100) crystal plane, is prepared. A crystal lattice arrangement has a great impact on material properties, such as electric properties (e.g., carrier mobility), of a substrate. For example, a substrate having a (110) crystal plane or a (100) crystal plane is provided, and then an SGT is formed thereon through the method 100, to allow a crystal plane thereof to be used as a current channel of the FET, as described later.
  • Thus, based on the method 100 of the present invention, a combinational CMOS device comprising an N-channel SGT (NFET) and a P-channel SGT (PFET) can be freely fabricated in any combination of different sidewall surfaces, such as (100) crystal plane, (110) crystal plane and (111) crystal plane. In the NFET, electron mobility is optimized in association with a sidewall having a (100) crystal plane in a square pillar-type SGT on a Si (100) wafer. In the PFET, hole mobility is optimized in association with a sidewall having a (110) crystal plane in a square pillar-type SGT on the Si (100) wafer. Further, in the NFET, electron mobility is reduced in association with a sidewall having various crystal planes in a rectangular pillar-type SGT on a Si (110) wafer. In the PFET, hole mobility is optimized in association with a sidewall having a (110) or (110) crystal plane in a rectangular pillar-type SGT on a Si (110) wafer.
  • As shown in FIG. 2, even in a sidewall having a certain surface orientation, carrier mobility largely varies depending on a current direction (for example, when a channel direction in a (110) crystal plane is <110>, hole mobility is 230 cm2/Vs, whereas, when the channel direction in the (110) crystal plane is <100>, the hole mobility is 148 cm2/Vs). In SGTs, the current direction is determined by a crystal orientation of a silicon wafer (i.e., the current direction of an SGT formed on a Si (110) wafer becomes <110>, whereas the current direction of an SGT formed on a Si (100) wafer becomes <100>). A sidewall having a (100) crystal plane, a (110) crystal plane or a (111) crystal plane is significantly useful surface. The method 100 of the present invention can be used to achieve a large number of combinations of surfaces rotated by 220 degrees with respect to a surface of a substrate. A plurality of equivalent crystal planes obtained by the method 100 can be expressed as a (n m 0) crystal plane on the Si (100) wafer or (a a b) crystal plane on the Si (110) wafer, wherein each of n, m, a and b is any integer (see FIG. 1 related to various usable sidewall surfaces of SGTs fabricated on the Si (100) wafer and the Si (110) wafer). Thus, the method 100 of the present invention can be used to optimize carrier mobility or reduce carrier mobility in each specific device element according to need.
  • With reference to FIGS. 57( a) to 57(f), a process of fabricating a quadrangular-shaped hard mask 87 for use in etching for a silicon pillar will be described. Although it is not impossible to pattern a photoresist to define a line or space having a nano size (size less than 30 μm), it is not easy to actually pattern a photoresist to form a quadrangular-shaped photoresist pattern 86 having a nano size (size less than 30 μm), due to restraint in lithographic resolution. A quadrangular-shaped photoresist pattern formed by subjecting a photoresist to lithographic exposure once using a photomask patterned to define a quadrangular shape is apt to have rounded corners or a columnar shape.
  • In the present invention, a photoresist is subjected to lithographic exposure twice using two photomasks 81-1, 81-2 (each having a size less than 30 μm) to form a photoresist pattern 86 having a shape closer to a perfect quadrangular shape. Specifically, in a first step, a hard mask thin film 83 is deposited, as shown in FIG. 57( a). The hard mask thin film 83 serves as an etching stopper layer, which is used over the entire SGT fabrication process according to need. In this preferred embodiment, silicon nitride (Si3N4) or silicon dioxide (SiO2) is used as a material of the hard mask thin film 83. In a next step, the hard mask thin film 83 is patterned, and etching is performed. This step may be performed using any suitable technique which is commonly known in the art. For example, a surface of the hard mask thin film 83 is covered with an appropriate photoresist 82, and then ultraviolet light is emitted through a photomask 81-1 having patterns for defining a line and a space, so that an unmasked region of the photoresist (FIG. 57( a)) is exposed to the ultraviolet light. Then, the ultraviolet light is emitted through a photomask 81-2, and the photoresist is subject to further exposure. Thus, only a square (or rectangular)-shaped region 85 of the photoresist is kept from the lithographic exposures (FIG. 57( b)). Then, when the exposed photoresist is removed using a developing solution, only the photoresist region 85 is left on the hard mask 83. A surface orientation (related to electron or hole mobility) of a sidewall of an SGT is dependent on in what direction the mask is provided, as will become clear later.
  • Initially, a predetermined mask is selected according to the method 100 of the present invention, to allow a specific surface orientation of a sidewall of a silicon pillar to be assigned to each of a plurality of different device elements. After forming a shape of a small SGT on the hard mask thin film 83 covered with the photoresist, the hard mask thin film 83 is subjected to etching having an appropriate directionality, to form a small quadrangular-shaped pattern 87. Subsequently, the photoresist 86 is removed by an appropriate chemical process to form a hard mask film 87 on a semiconductor, as shown in FIGS. 57( e) and 57(f).
  • FIGS. 58( a) to 84(b) show sectional views of the semiconductor structure according to one embodiment of the present invention, and top plan views of a lithographic mask, in each step of the method 100 in FIG. 56. Referring to a substrate illustrated in FIGS. 58( a) and 58(b), the substrate 114 in this embodiment may be a silicon wafer composed of a single-crystal bulk, or an SOI (Silicon On Insulator) wafer. Except an isolation process, a required process for the SOI wafer is fundamentally the same as that for the bulk silicon wafer.
  • Further, although FIGS. 58( a) and 58(b) show the wafer 114 as a type having a simple configuration, a wafer having a more complicated configuration may also be used. The wafer 114 may be made of (but not limited to) one selected from the group consisting of Si, Ge, GaP, InAs, InP, SiGe, GeAs, and any other Group III-V compound, or any other material suitable as a wafer. A surface of the wafer 114 is formed to have a first crystal plane to be subsequently used as a crystal plane for a current channel of an FET. Specifically, in this preferred embodiment, a surface of a single-crystal silicon wafer is formed to have a (110) crystal plane or a (100) crystal plane.
  • In a next step illustrated in FIGS. 59( a) to 60(b), the semiconductor 114 is subjected to anisotropic etching using a hard mask 121 to form an isolation region 115. As described in connection with FIGS. 57( a) to 57(f), an isolation mask (mask 1 in FIG. 59( a)) is used to pattern the hard mask 121 on the silicon wafer 114. Etching for the silicon wafer (in FIGS. 60( a) and 60(b)) may be performed by reactive ion etching (RIE) suited to etch the semiconductor 114.
  • Subsequently, as shown in FIGS. 61( a) to 62(b), in a step 104 of the method 100, after forming the trench isolation region 115 in the substrate, one or more SGT pillars 128, 129 are formed from the semiconductor wafer 114. The pillar (128, 129) (i.e., pillar body) serves as a body of a transistor (i.e., SGT body). Any number of pillars (or SGTs) may be formed on the substrate, and these pillars may be formed using any one of the aforementioned techniques. In the step 104, a pillar is preferably formed from the semiconductor wafer by the following process.
  • In a first sub-step, a thin layer of a hard mask 113 is patterned using a mask 2 illustrated in FIG. 61( a). The hard mask 113 (Si3N4 or SiO2) acts as an etching stopper layer. Then, the semiconductor 114 is subjected to anisotropic etching using the hard mask 113 to form two silicon pillars 128, 129. This etching may be performed by means of a reactive ion etching (RIE) process. Consequently, the pillars are left as shown in FIG. 62( b), in such a manner that a part of the semiconductor 114 is included in the pillars, and the hard mask film is superimposed on each of the pillars. The pillars have vertical sidewalls 122, 123 disposed in opposed relation to each other.
  • A direction of the mask is determined in a preceding sub-step, so that each of the sidewalls 122, 123 is formed to have a specific crystal plane. This makes it possible to optimize carrier mobilities in both the sidewalls according to need, or reduce carrier mobility in at least one of the sidewalls according to need, so as to achieve intended performance. Thus, the sidewalls 122, 123 of the pillar bodies can be formed to have crystal orientations providing different carrier mobilities, just in an intended manner. Further, the sidewall 122 and the sidewall 123 can be formed to have respective ones of a first crystal plane, and a second crystal plane which is not equivalent to the first crystal plane by a symmetry transformation. Furthermore, each of the sidewalls 122, 123 can be formed to have either one of optimized carrier mobility, and unoptimized carrier mobility (i.e., carrier mobility less than the optimized carrier mobility).
  • Each of the pillars is subjected to doping according to need. Generally, the doping is performed by ion implantation, to form a P-well structure (P-well) and an N-well structure (N-well). Typically, a doping level of each of the P-well and the N-well is in the range of 1017 to 5×1018 cm−3. Alternatively, an NFET and a PFET may be formed using an intrinsic silicon wafer without forming a well structure. In a CMOS technique of the present invention, an intrinsic silicon wafer is used, for example, to integrate an NFET and a PFET on a common substrate.
  • The above process is one preferred example for implementing the step 104 (FIG. 56) to form one or more pillars from the semiconductor 114. A sidewall of a pillar body to be provided with a gate forms a current channel, and two non-gate regions on both sides of the channel serve as a source region and a drain region, as described later. In the case where two pillars (SGTs) are formed, a sidewall of one of two SGT bodies forming a current channel is formed to have a first crystal plane with a specific crystal orientation, and the sidewall of the other pillar body is formed to have a second crystal plane which is not equivalent to the first crystal plane by a symmetry transformation. Specifically, each of the sidewalls 122, 123 of the pillar bodies may be formed to have either one of a crystal plane (surface orientation) providing optimized carrier mobility, and a crystal plane (surface orientation) providing unoptimized carrier mobility (i.e., carrier mobility less than the optimized carrier mobility). Further, the sidewalls of the SGT bodies may be formed to have any combination of surface orientations, such as (100), (110) and (111). In this case, the (110) crystal plane allows carrier mobility in a PFET to be optimized, and the (100) crystal plane allows carrier mobility in an NFET to be optimized. In case where a first SGT body is formed in a circular pillar type having a surface with various crystal planes, and a second SGT body is formed in a square or rectangular pillar type, two parallel sidewalls of the silicon pillars may be formed to have any combination of surface orientations, such as (100), (110) and (111).
  • FIGS. 63( a) and 63(b) show a process of implanting an acceptor 116 into the semiconductor 114 to form a drain region underneath a PMOS SGT. During this process, an NMOS region is masked with a mask 117 (e.g., silicon nitride or silicon dioxide) formed by photolithography using a photomask (mask 3). In other words, a selective implantation of the acceptor 116 is performed. Subsequently, the acceptor mask 117 (FIGS. 63( a) and 63(b)) is removed, and then a dopant mask 125 is formed on the substrate 114 by photolithography using a photomask (mask 4), as shown in FIGS. 64( a) and 64(b). Then, a dopant 118 is implanted into the semiconductor 114 to form a drain region underneath an NMOS SGT. An amount of and a ratio between the acceptor and the dopant to be implanted are selected in a design stage. Various conventional techniques may be used to form each of the source region and the drain region (S/D region). The S/D region can be formed at various levels of complexity using the various existing techniques for forming the S/D region. In some embodiments of the present invention, an ion-implantation process is used to form the S/D region. Through the ion-implantation process, as for the NFET, an impurity ion, such as P, As or Sb, is implanted into the S/D region at an energy of 1 to 5 keV and in a dose amount of 5×1014 to 2×1015 cm−3. As for the PFET, an impurity ion, such as B, In or Ga, is implanted into the S/D region at an energy of 0.5 to 3 keV and in a dose amount of 5×1014 to 2×1015 cm−3.
  • FIGS. 65( a) to 67(b) show a process of forming a salicide (self-aligned silicide) contact for the drain. In a first sub-step, the dopant mask 125 in FIG. 64( b) is removed, and then a dielectric material 127 is deposited. A top of each of the silicon pillars is covered with the hard mask 113, and a top of the hard mask 113 is further covered with the dielectric material 127 in a uniform manner, as shown in FIG. 65( b). In a next sub-step, each of the silicon pillars is covered with a dielectric material 119 using a conventional spacer forming technique (i.e., uniform RIE etching). In a final sub-step illustrated in FIGS. 67( a) and 67(b), a self-aligned silicide (salicide) contact 120 is formed on the drain regions underneath the NMOS SGT (NMOS device element) and the PMOS SGT (PMOS device element). For example, a currently used silicide having a low resistivity and a low contact resistance includes C52 phases of TiSi2, CoSi2 and NiSi.
  • Referring to FIGS. 68( a) to 69(b), a flat nitride layer (or oxide layer) 130 is deposited to have a height less than that of the silicon pillars using chemical mechanical polishing (CMP) and subsequently using an etch-back process. For this purpose, a thick nitride layer is deposited to a height above the silicon pillars, and then flattened by chemical mechanical polishing (CMP) (FIGS. 68( a) and 68(b)). Then, the polished nitride layer 126 is etched back by plasma etching, as shown in FIGS. 69( a) and 69(b). This process is intended to reduce a parasitic resistance in an overlap region between a gate and the underneath grain region (see Kunz, et al., “Reduction of Parasitic Capacitance in Vertical MOSFETc by Spacer local Oxidation” IEEE Electron devices, Vol. 50, No. 6, June 200, p. 148, for further detailed information).
  • With reference to FIGS. 70( a) to 71(b), a process of forming a gate stack in steps 106 to 109 of the method 100 will be described. In the step 106, a gate dielectric layer 131 is formed on the opposed vertical sidewalls 122, 123. The gate dielectric layer 131 can be formed by thermal oxidation at a temperature of 750 to 800° C., or by depositing a dielectric material to form a thin layer. As is well known, SiO2, a nitrided oxide material, a high-K dielectric material or a combination thereof, may be used as a material of the gate dielectric layer 131. After the formation of the gate dielectric layer 131, a gate conductive layer 132 is deposited. The gate conductive layer 132 may be deposited using conventional photolithography and etching. The gate conductive layer 132 is generally made of a polysilicon material. Alternatively, the gate conductive layer 132 may be made of any other suitable conductive material, such as amorphous silicon, a combination of amorphous silicon and polysilicon, or polysilicon-germanium. In case where the gate conductive layer 132 is made of a metal, a high melting-point metal, such as W, Mo or Ta, may be used. Further, a silicide gate conductor comprising polysilicon and Ni or Co added thereto may be used.
  • In the step 108 of surrounding the silicon material by the gate conductive layer 132, such a layer may be deposited in the form of a doped layer (in-situ doping). In the case where the gate conductive layer 132 is a metal layer, the metal layer may be deposited by a vapor-deposition process, such as a physical vapor deposition process or a chemical vapor deposition process. In the above manner, the oxide layer 131 is formed on the sidewalls 122, 123 of the pillars formed by the semiconductor 141, and a gate structure is formed on the oxide layer 131. Then, as shown in FIGS. 72( a) to 73(b), a CMP/etching stopper layer 133 (e.g., nitride layer) and a thick oxide layer 134 are deposited. Through a subsequent CMP process, the oxide layer 134 is polished until it reaches the CMP stopper layer 133 (FIGS. 74( a) and 74(b)). In the next step 109, the exposed CMP stopper layer and gate conductive layer are etched back by plasma etching, to form a gate conductive layer pattern (FIGS. 75( a) and 75(b)).
  • Subsequently, in a step 110 of the method 100, SGTs illustrated in FIGS. 76( a) to 84(b) are completed. Specifically, a silicon epitaxial layer 135 is firstly deposited (FIGS. 76( a) and 76(b)), and then patterned using photolithography (mask 6 in FIG. 77( a)) and etching. Then, as shown in FIGS. 78( a) and 78(b), an acceptor 137 is implanted into the epitaxial silicon layer 135 to form a source region in an upper portion of the PMOS SGT. This implantation is a selective implantation of the acceptor 137. Thus, during the implantation, an NMOS region is masked with a mask 136 formed by photolithography using a photomask (mask 7 in FIG. 78( a)). Subsequently, the acceptor mask 136 (FIG. 78( b)) is removed, and then a dopant mask 140 is formed (FIG. 79( b)) by photolithography using a photomask (mask 8 in FIG. 79( a)). Then, a dopant 138 is implanted into the epitaxial silicon layer 135 to form a source region in an upper portion of the NMOS SGT. Then, after removing the implantation mask 140 (FIGS. 80( a) and 80(b)), a metal silicide 139 is formed on the source region in each of the upper portions of the NMOS SGT and PMOS SGT, in a self-alignment manner.
  • The step 110 is further continued to form a contact for each of the source, the drain and the gate, as shown in FIGS. 82( a) to 84(b). Specifically, an inter-metal dielectric material 150 is deposited, and then flattened by a CMP process or the like (FIGS. 82( a) and 82(b)). Then, as shown in FIGS. 83( a) and 83(b), contact hole 151 is formed by an anisotropic process (e.g., RIE) or the like using a photomask (mask 9). Subsequently, a metal layer is deposited, and then a metal layer 152 is formed using a photomask (mask 10) and an RIE process or the like (FIGS. 84( a) and 84(b)). Alternatively, the metal layer 152 may be formed using a damascene process.
  • A plurality of CMOS SGTs according to the present invention which are formed on a common substrate by using various crystal planes in association with a FET current channel type and a pillar shape, can be used in various circuits, such as a high-performance logic device, a low-power logic device, and a high-density memory device (including a high-density multi-giga bit DRAM). Further, the CMOS SGTs according to the present invention can be easily combined with other element, such as a capacitor, a resistor or a memory cell.
  • The present invention is suitably applied to a semiconductor structure and a fabrication method for the semiconductor structure.

Claims (27)

  1. 1. A semiconductor structure comprising:
    a first pillar having a first single-crystal semiconductor sidewall channel having a surface oriented on a first crystal plane; and
    a second pillar having a second single-crystal semiconductor sidewall channel having a surface oriented on a second crystal plane different from the first crystal plane,
    wherein the first crystal plane and the second crystal plane are not equivalent by a symmetry transformation and the shapes of said first pillar and said second pillar are not equivalent by a symmetry transformation.
  2. 2. The semiconductor structure as defined in claim 1, wherein the first single-crystal semiconductor sidewall channel has a first carrier mobility, and the second single-crystal semiconductor sidewall channel has a second carrier mobility, wherein a value of the first carrier mobility is different from a value of the second carrier mobility.
  3. 3. A semiconductor structure comprising:
    a first pillar having a first single-crystal semiconductor sidewall channel having a surface oriented on a first crystal plane; and
    a second pillar having a second single-crystal semiconductor sidewall channel having a surface oriented on a second crystal plane different from the first crystal plane,
    wherein the first crystal plane and the second crystal plane are not equivalent by a symmetry transformation and the surface orientation of the substrate on which said first and second pillars are formed is (110).
  4. 4. The semiconductor structure as defined in claim 1, wherein the first single-crystal semiconductor sidewall channel constitutes a first surrounding gate transistor (SGT), and the second single-crystal semiconductor sidewall channel constitutes a second surrounding gate transistor (SGT).
  5. 5. The semiconductor structure as defined in claim 4, wherein the first SGT is one of a first P-channel SGT (PFET) and a first N-channel SGT (NFET), and the second SGT is one of a second P-channel SGT (PFET) and a second N-channel SGT (NFET).
  6. 6. The semiconductor structure as defined in claim 5, wherein:
    a pillar body of one of the first PFET and the first NFET is formed such that a sidewall thereof is oriented on the first crystal plane to have one of an optimized carrier mobility and an unoptimized carrier mobility; and
    a pillar body of one of the second PFET and the second NFET is formed such that a sidewall thereof is oriented on the second crystal plane to have one of an unoptimized carrier mobility and an optimized carrier mobility.
  7. 7. A semiconductor structure comprising:
    a first single-crystal semiconductor sidewall channel having a surface oriented on a first crystal plane; and
    a second single-crystal semiconductor sidewall channel having a surface oriented on a second crystal plane different from the first crystal plane,
    wherein the first crystal plane and the second crystal plane are not equivalent by a symmetry transformation,
    wherein said a first single-crystal semiconductor sidewall channel constitute a part of a first SGT and said a second single-crystal semiconductor sidewall channel constitute a part of a second SGT
    wherein the first SGT is one of a first P-channel SGT (PFET) and a first N-channel SGT (NFET), and the second SGT is one of a second P-channel SGT (PFET) and a second N-channel SGT (NFET),
    wherein all the sidewalls of one of said first PFET and said first NFET have surfaces comprising an arbitrary combination of crystal planes of (100), (110) and (111), and
    wherein all the sidewalls of one of said second PFET and said second NFET have surfaces comprising an arbitrary combination of crystal planes of (100), (110) and (111).
  8. 8. A semiconductor structure comprising:
    a first single-crystal semiconductor sidewall channel having a surface oriented on a first crystal plane; and
    a second single-crystal semiconductor sidewall channel having a surface oriented on a second crystal plane different from the first crystal plane,
    wherein the first crystal plane and the second crystal plane are not equivalent by a symmetry transformation,
    wherein said a first single-crystal semiconductor sidewall channel constitute a part of a first SGT and said a second single-crystal semiconductor sidewall channel constitute a part of a second SGT
    wherein the first SGT is one of a first P-channel SGT (PFET) and a first N-channel SGT (NFET), and the second SGT is one of a second P-channel SGT (PFET) and a second N-channel SGT (NFET), and
    wherein the sidewall of one of said first PFET having a cross-sectionally circular-shaped pillar body and said first NFET having a cross-sectionally circular-shaped pillar body has a plurality of crystal planes and all the surfaces of either one of said second PFET and said second NFET have crystal orientation comprising an arbitrary combination of crystal planes of (100), (110) and (111).
  9. 9. The semiconductor structure as defined in claim 7, which comprises an SGT CMOS device formed on a silicon wafer having a (100) crystal plane to include the first NFET and the first and second PFETs, wherein the first NFET is formed to have a cross-sectionally quadrangular-shaped pillar body and each of the first and second PFETs is formed to have a cross-sectionally quadrangular-shaped pillar body, and wherein:
    the cross-sectionally quadrangular-shaped pillar body of the first NFET is formed such that a sidewall thereof has a (100) crystal plane; and
    the cross-sectionally quadrangular-shaped pillar body of the second PFET is formed such that a sidewall thereof has a (110) crystal plane.
  10. 10. The semiconductor structure as defined in claim 8, which comprises an SGT CMOS device formed on a silicon wafer having a (110) crystal plane to include the first NFET having the cross-sectionally circular-shaped pillar body, and the first PFET, wherein the first PFET is formed to have a cross-sectionally rectangular-shaped pillar body, and wherein:
    the cross-sectionally circular-shaped pillar body of the first NFET is formed such that a sidewall thereof has a plurality of crystal planes; and
    the cross-sectionally rectangular-shaped pillar body of the first PFET is formed such that each of two sidewalls thereof defining short sides has a (100) crystal plane, and each of two sidewalls thereof defining long sides has a (110) crystal plane.
  11. 11. The semiconductor structure as defined in claim 8, which comprises an SGT CMOS device formed on a silicon wafer having a (110) crystal plane to include the first NFET having the cross-sectionally circular-shaped pillar body, and the first PFET, wherein the first PFET is formed to have a cross-sectionally quadrangular-shaped pillar body, and wherein:
    the cross-sectionally circular-shaped pillar body of the first NFET is formed such that a sidewall thereof has a plurality of crystal planes; and
    the cross-sectionally quadrangular-shaped pillar body of the first PFET is formed such that each of two of four sidewalls thereof has a (100) crystal plane, and each of the remaining two sidewalls has a (110) crystal plane.
  12. 12. The semiconductor structure as defined in claim 1, wherein each of bodies of the first single-crystal semiconductor sidewall channel and the second single-crystal semiconductor sidewall channel is made of a material selected from a group consisting of silicon, germanium, a silicon compound, a germanium compound, a Group III-V material, and a Group II-IV material.
  13. 13. The semiconductor structure as defined in claim 5, each of bodies of the first single-crystal semiconductor sidewall channel and the second single-crystal semiconductor sidewall channel is doped in a concentration ranging from 1010 to 107.
  14. 14. A method of fabricating a semiconductor structure, comprising the steps of:
    providing a substrate having a surface oriented on a first crystal plane to be subsequently used as a channel;
    forming a first surrounding gate transistor (SGT) in such a manner that a first pillar body thereof defines a first channel, and a sidewall of the first pillar body is oriented on a second crystal plane which provides a first carrier mobility; and
    forming a second surrounding gate transistor (SGT) in such a manner that a second pillar body thereof defines a second channel, and a sidewall of the second pillar body is oriented on a third crystal plane which provides a second carrier mobility different from the first carrier mobility,
    wherein the pillar shape of said first crystal plane and the pillar shape of said second crystal plane are not equivalent by a symmetry transformation.
  15. 15. A method of fabricating a semiconductor structure, comprising the steps of:
    providing a substrate having a surface oriented on a first crystal plane to be subsequently used as a channel;
    forming a first surrounding gate transistor (SGT) in such a manner that a first pillar body thereof defines a first channel, and a sidewall of the first pillar body is oriented on a second crystal plane which provides a first carrier mobility; and
    forming a second surrounding gate transistor (SGT) in such a manner that a second pillar body thereof defines a second channel, and a sidewall of the second pillar body is oriented on a third crystal plane which provides a second carrier mobility different from the first carrier mobility,
    wherein the surface of the substrate is oriented on a (110) crystal plane.
  16. 16. The method as defined in claim 14, wherein:
    the step of forming a first SGT includes forming the first SGT to have a cross-sectionally quadrangular (or rectangular)-shaped first pillar body configured such that each of two parallel sidewalls of the first pillar body is oriented on a (n m l) crystal plane, and each of the remaining two sidewalls is oriented on a (a b c) crystal plane, wherein each of n, m, l, a, b and c is any integer, and na+mb+lc=0; and
    the step of forming a second SGT includes forming the second SGT to have a cross-sectionally quadrangular (or rectangular)-shaped second pillar body configured such that each of two parallel sidewalls of the second pillar body is oriented on a (p q r) crystal plane, and each of the remaining two sidewalls is oriented on a (e f g) crystal plane, wherein each of p, q, r, e, f and g is any integer, and pe+qf+rg=0.
  17. 17. A method of fabricating a semiconductor structure, comprising the steps of:
    providing a substrate having a surface oriented on a first crystal plane to be subsequently used as a channel;
    forming a first surrounding gate transistor (SGT) in such a manner that a first pillar body thereof defines a first channel, and a sidewall of the first pillar body is oriented on a second crystal plane which provides a first carrier mobility; and
    forming a second surrounding gate transistor (SGT) in such a manner that a second pillar body thereof defines a second channel, and a sidewall of the second pillar body is oriented on a third crystal plane which provides a second carrier mobility different from the first carrier mobility,
    wherein the step of forming the first SGT includes forming the first SGT such that the sidewalls of said first pillar-shaped SGT body are oriented by a plurality of crystal planes, and
    wherein the step of forming the second SGT includes forming the second SGT to have a cross-sectionally quadrangular (or rectangular)-shaped second pillar body configured such that each of two parallel sidewalls of the second pillar body is oriented on a (n m l) crystal plane, and each of the remaining two sidewalls is oriented on a (a b c) crystal plane, wherein each of n, m, l, a, b and c is any integer, and na+mb+lc=0.
  18. 18. The method as defined in claim 14, wherein:
    the step of forming a first SGT includes the sub-step of forming one of a first P-channel SGT (PFET) and a first N-channel SGT (NFET); and
    the step of forming a second SGT includes the sub-step of forming one of a second P-channel SGT (PFET) and a second N-channel SGT (NFET).
  19. 19. The method as defined in claim 18, wherein:
    the sub-step of forming one of a first PFET and a first NFET includes forming one of the first PFET and the first NFET in such a manner that the sidewall of the first pillar body is oriented on a specific crystal plane to have one of an optimized carrier mobility and an unoptimized carrier mobility; and
    the sub-step of forming one of a second PFET and a second NFET includes forming one of the second PFET and the second NFET in such a manner that the sidewall of the second pillar body is oriented on a specific crystal plane to have one of an optimized carrier mobility and an unoptimized carrier mobility.
  20. 20. A method of fabricating a semiconductor structure, comprising the steps of:
    providing a substrate having a surface oriented on a first crystal plane to be subsequently used as a channel;
    forming a first surrounding gate transistor (SGT) in such a manner that a first pillar body thereof defines a first channel, and a sidewall of the first pillar body is oriented on a second crystal plane which provides a first carrier mobility, and
    forming a second surrounding gate transistor (SGT) in such a manner that a second pillar body thereof defines a second channel, and a sidewall of the second pillar body is oriented on a third crystal plane which provides a second carrier mobility different from the first carrier mobility,
    wherein said forming a first surrounding gate transistor includes forming one of a first p-channel SGT (PFET) and a first n-channel SGT (NFET),
    wherein said forming a second surrounding gate transistor includes forming one of a second p-channel SGT (PFET) and a second n-channel SGT (NFET),
    wherein the sub-step of forming one of a first PFET and a first NFET includes forming one of the first PFET and the first NFET to have a cross-sectionally circular-shaped first pillar body configured such that a sidewall of the first pillar body is oriented on a plurality of crystal planes to have one of an optimized carrier mobility and an unoptimized carrier mobility; and
    the sub-step of forming one of a second PFET and a second NFET includes forming one of the second PFET and the second NFET in such a manner that the sidewall of the second SGT pillar body is oriented on a specific crystal plane to have one of an optimized carrier mobility and an unoptimized carrier mobility.
  21. 21. A method of fabricating a semiconductor structure, comprising the steps of:
    providing a substrate having a surface oriented on a first crystal plane to be subsequently used as a channel;
    forming a first surrounding gate transistor (SGT) in such a manner that a first pillar body thereof defines a first channel, and a sidewall of the first pillar body is oriented on a second crystal plane which provides a first carrier mobility, and
    forming a second surrounding gate transistor (SGT) in such a manner that a second pillar body thereof defines a second channel, and a sidewall of the second pillar body is oriented on a third crystal plane which provides a second carrier mobility different from the first carrier mobility,
    wherein said forming a first surrounding gate transistor includes forming one of a first p-channel SGT (PFET) and a first n-channel SGT (NFET),
    wherein said forming a second surrounding gate transistor includes forming one of a second p-channel SGT (PFET) and a second n-channel SGT (NFET),
    wherein the sub-step of forming one of a first PFET and a first NFET includes forming one of the first PFET and the first NFET in such a manner that the entire sidewall of the first pillar body is oriented on a combination of two or more of a (100) crystal plane, a (110) crystal plane and a (111) crystal plane; and
    the sub-step of forming one of a second PFET and a second NFET includes forming one of the second PFET and the second NFET in such a manner that the entire sidewall of the second pillar body is oriented on a combination of two or more of a (100) crystal plane, a (110) crystal plane and a (111) crystal plane.
  22. 22. A method of fabricating a semiconductor structure, comprising the steps of:
    providing a substrate having a surface oriented on a first crystal plane to be subsequently used as a channel;
    forming a first surrounding gate transistor (SGT) in such a manner that a first pillar body thereof defines a first channel, and a sidewall of the first pillar body is oriented on a second crystal plane which provides a first carrier mobility, and
    forming a second surrounding gate transistor (SGT) in such a manner that a second pillar body thereof defines a second channel, and a sidewall of the second pillar body is oriented on a third crystal plane which provides a second carrier mobility different from the first carrier mobility,
    wherein said forming a first surrounding gate transistor includes forming one of a first p-channel SGT (PFET) and a first n-channel SGT (NFET),
    wherein said forming a second surrounding gate transistor includes forming one of a second p-channel SGT (PFET) and a second n-channel SGT (NFET),
    wherein the sub-step of forming one of a first PFET and a first NFET includes forming one of the first PFET and the first NFET in such a manner that the entire sidewall of the first pillar body is oriented on a plurality of crystal planes; and
    the sub-step of forming one of a second PFET and a second NFET includes forming one of the second PFET and the second NFET in such a manner that the entire sidewall of the second pillar body is oriented on a combination of two or more of a (100) crystal plane, a (110) crystal plane and a (111) crystal plane.
  23. 23. The method as defined in claim 21, which further comprises the step of forming an SGT CMOS device on a silicon wafer having a (100) crystal plane to include a first NMOS SGT (NFET) having a cross-sectionally square-shaped pillar body, and first and second PMOS SGTs (PFETs) each having a cross-sectionally quadrangular-shaped pillar body, wherein: the pillar body of the first NFET is formed such that a sidewall thereof is oriented on a (100) crystal plane; and the pillar body of the second PFET is formed such that a sidewall thereof is oriented on a (110) crystal plane.
  24. 24. The method as defined in claim 22, which further comprises the step of forming an SGT CMOS device on a silicon wafer having a (100) crystal plane to include a first NMOS SGT (NFET) having a cross-sectionally circular-shaped pillar body, and a second PMOS SGT (PFET) having a cross-sectionally quadrangular-shaped pillar body, wherein: the pillar body of the first NFET is formed such that a sidewall thereof is oriented on a plurality of crystal planes; and the pillar body of the second PFET is formed such that each of two parallel sidewalls thereof is oriented on a (100) crystal plane, and each of the remaining two parallel sidewalls is oriented on a (110) crystal plane.
  25. 25. The method as defined in claim 22, which further comprises the step of forming an SGT CMOS device on a silicon wafer having a (110) crystal plane to include a first NMOS SGT (NFET) having a cross-sectionally circular-shaped pillar body, and a second PMOS SGT (PFET) having a cross-sectionally quadrangular-shaped pillar body, wherein: the pillar body of the first NFET is formed such that a sidewall thereof is oriented on a plurality of crystal planes; and the pillar body of the second PFET is formed such that each of two parallel sidewalls thereof is oriented on a (100) crystal plane, and each of the remaining two parallel sidewalls is oriented on a (110) crystal plane.
  26. 26. A method of forming a square-shaped or rectangular-shaped SGT pillar, comprising the steps of:
    providing two sets of photomask which coincide with a line for patterning a nanosized square-shaped or rectangular-shaped semiconductor pillar;
    forming a square-shaped or rectangular-shaped SGT pillar through two set of separate light exposures by using said two sets of photomask.
  27. 27. The method as defined in claim 26, further comprising the steps of:
    providing a substrate having a surface oriented on a first crystal plane to be subsequently used as a channel;
    forming a first surrounding gate transistor (SGT) in such a manner that a first pillar body thereof defines a first channel, and a sidewall of the first pillar body is oriented on a second crystal plane which provides a first carrier mobility, and
    forming a second surrounding gate transistor (SGT) in such a manner that a second pillar body thereof defines a second channel, and a sidewall of the second pillar body is oriented on a third crystal plane which provides a second carrier mobility different from the first carrier mobility.
US12704975 2007-10-29 2010-02-12 Semiconductor structure and method of fabricating the semiconductor structure Active 2028-04-30 US8183628B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/071052 WO2009057194A1 (en) 2007-10-29 2007-10-29 Semiconductor structure, and manufacturing method for that semiconductor structure
US20754309 true 2009-02-13 2009-02-13
US12704975 US8183628B2 (en) 2007-10-29 2010-02-12 Semiconductor structure and method of fabricating the semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12704975 US8183628B2 (en) 2007-10-29 2010-02-12 Semiconductor structure and method of fabricating the semiconductor structure
US13412959 US8482041B2 (en) 2007-10-29 2012-03-06 Semiconductor structure and method of fabricating the semiconductor structure

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/071052 Continuation WO2009057194A1 (en) 2007-10-29 2007-10-29 Semiconductor structure, and manufacturing method for that semiconductor structure

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13412959 Division US8482041B2 (en) 2007-10-29 2012-03-06 Semiconductor structure and method of fabricating the semiconductor structure

Publications (2)

Publication Number Publication Date
US20100207172A1 true true US20100207172A1 (en) 2010-08-19
US8183628B2 US8183628B2 (en) 2012-05-22

Family

ID=42559122

Family Applications (2)

Application Number Title Priority Date Filing Date
US12704975 Active 2028-04-30 US8183628B2 (en) 2007-10-29 2010-02-12 Semiconductor structure and method of fabricating the semiconductor structure
US13412959 Active US8482041B2 (en) 2007-10-29 2012-03-06 Semiconductor structure and method of fabricating the semiconductor structure

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13412959 Active US8482041B2 (en) 2007-10-29 2012-03-06 Semiconductor structure and method of fabricating the semiconductor structure

Country Status (1)

Country Link
US (2) US8183628B2 (en)

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100207201A1 (en) * 2008-01-29 2010-08-19 Fujio Masuoka Semiconductor device and production method therefor
US20100213539A1 (en) * 2008-01-29 2010-08-26 Unisantis Electronics (Japan) Ltd. Semiconductor device and production method therefor
US20100270611A1 (en) * 2009-04-28 2010-10-28 Fujio Masuoka Semiconductor device including a mos transistor and production method therefor
US20100314671A1 (en) * 2009-06-11 2010-12-16 Elpida Memory, Inc. Semiconductor device and method of forming the same
US20110079841A1 (en) * 2009-10-01 2011-04-07 Fujio Masuoka Semiconductor device
US20110215381A1 (en) * 2010-03-08 2011-09-08 Fujio Masuoka Solid state imaging device
US20110248354A1 (en) * 2009-12-01 2011-10-13 Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Hybrid material inversion mode gaa cmosfet
US20110254058A1 (en) * 2010-02-11 2011-10-20 Shanghai Institute of Microsystem and Information Technology Chinese Academy Gate-All-Around CMOSFET devices
US20110254100A1 (en) * 2009-12-01 2011-10-20 Shanghai Institute of Microsystem and Information Technology Chinese Academy Hybrid material accumulation mode gaa cmosfet
US20110254101A1 (en) * 2009-12-01 2011-10-20 Shanghai Institute of Microsystem and Information Technology Chinese Academy Hybrid material inversion mode gaa cmosfet
US20110254099A1 (en) * 2009-12-01 2011-10-20 Shanghai Institute of Microsystem and Information Technology Chinese Academy Hybrid material accumulation mode GAA CMOSFET
US20110254013A1 (en) * 2009-12-01 2011-10-20 Shanghai Institute of Microsystem and Infomation Technology Chinese Academy Hybrid orientation accumulation mode gaa cmosfet
US20110254102A1 (en) * 2009-12-01 2011-10-20 Shanghai Institute of Microsystem and Information Technology Chinese Academy Hybrid orientation inversion mode gaa cmosfet
US8482041B2 (en) 2007-10-29 2013-07-09 Unisantis Electronics Singapore Pte Ltd. Semiconductor structure and method of fabricating the semiconductor structure
US8487357B2 (en) 2010-03-12 2013-07-16 Unisantis Electronics Singapore Pte Ltd. Solid state imaging device having high sensitivity and high pixel density
US8486785B2 (en) 2010-06-09 2013-07-16 Unisantis Electronics Singapore Pte Ltd. Surround gate CMOS semiconductor device
US8564034B2 (en) 2011-09-08 2013-10-22 Unisantis Electronics Singapore Pte. Ltd. Solid-state imaging device
US8669601B2 (en) 2011-09-15 2014-03-11 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device having pillar-shaped semiconductor
US20140117366A1 (en) * 2012-10-31 2014-05-01 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US8748938B2 (en) 2012-02-20 2014-06-10 Unisantis Electronics Singapore Pte. Ltd. Solid-state imaging device
US8772175B2 (en) 2011-12-19 2014-07-08 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing semiconductor device and semiconductor device
US8916478B2 (en) 2011-12-19 2014-12-23 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing semiconductor device and semiconductor device
US20150008448A1 (en) * 2013-07-02 2015-01-08 General Electric Company Metal-oxide-semiconductor (mos) devices with increased channel periphery and methods of manufacture
US20150048296A1 (en) * 2013-08-19 2015-02-19 SK Hynix Inc. Semiconductor device having fin gate, resistive memory device including the same, and method of manufacturing the same
US20150048294A1 (en) * 2013-08-19 2015-02-19 SK Hynix Inc. Variable resistive memory device including vertical channel pmos transistor and method of manufacturing the same
US20150048292A1 (en) * 2013-08-19 2015-02-19 SK Hynix Inc. Semiconductor device having vertical channel, resistive memory device including the same, and method of manufacturing the same
US20150048295A1 (en) * 2013-08-19 2015-02-19 SK Hynix Inc. Semiconductor device having fin gate, resistive memory device including the same, and method of manufacturing the same
US9153697B2 (en) 2010-06-15 2015-10-06 Unisantis Electronics Singapore Pte Ltd. Surrounding gate transistor (SGT) structure
US20150333152A1 (en) * 2014-05-16 2015-11-19 Taiwan Semiconductor Manufacturing Company Limited Vertical structure and method of forming the same
US9373620B2 (en) * 2014-09-12 2016-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Series connected transistor structure and method of manufacturing the same
US20170271508A1 (en) * 2016-03-21 2017-09-21 Samsung Electronics Co., Ltd. Semiconductor devices

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9525053B2 (en) 2013-11-01 2016-12-20 Samsung Electronics Co., Ltd. Integrated circuit devices including strained channel regions and methods of forming the same
US9099385B2 (en) * 2013-11-08 2015-08-04 Sandisk 3D Llc Vertical 1T-1R memory cells, memory arrays and methods of forming the same
US9450026B2 (en) 2014-03-24 2016-09-20 Kabushiki Kaisha Toshiba Semiconductor device

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258635A (en) * 1988-09-06 1993-11-02 Kabushiki Kaisha Toshiba MOS-type semiconductor integrated circuit device
US5811336A (en) * 1994-08-31 1998-09-22 Nec Corporation Method of forming MOS transistors having gate insulators of different thicknesses
US6483171B1 (en) * 1999-08-13 2002-11-19 Micron Technology, Inc. Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same
US6658259B2 (en) * 2002-03-07 2003-12-02 Interwave Communications International, Ltd. Wireless network having a virtual HLR and method of operating the same
US6740937B1 (en) * 2000-06-05 2004-05-25 Oki Electric Industry Co., Ltd. Basic cells configurable into different types of semiconductor integrated circuits
US6815277B2 (en) * 2001-12-04 2004-11-09 International Business Machines Corporation Method for fabricating multiple-plane FinFET CMOS
US20040256639A1 (en) * 2003-06-17 2004-12-23 International Business Machines Corporation Low leakage heterojunction vertical transistors and high performance devices thereof
US20040262681A1 (en) * 2003-05-28 2004-12-30 Fujio Masuoka Semiconductor device
US20050263821A1 (en) * 2004-05-25 2005-12-01 Cho Young K Multiple-gate MOS transistor and a method of manufacturing the same
US7368334B2 (en) * 2003-04-04 2008-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-on-insulator chip with multiple crystal orientations
US20080227241A1 (en) * 2007-03-12 2008-09-18 Yukio Nakabayashi Method of fabricating semiconductor device
US20100200913A1 (en) * 2008-01-29 2010-08-12 Unisantis Electronics (Japan) Ltd. Semiconductor storage device

Family Cites Families (106)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5017977A (en) 1985-03-26 1991-05-21 Texas Instruments Incorporated Dual EPROM cells on trench walls with virtual ground buried bit lines
JPS6337633A (en) 1986-07-31 1988-02-18 Nec Corp Semiconductor integrated circuit device
JPH03187272A (en) 1989-12-15 1991-08-15 Mitsubishi Electric Corp Mos type field effect transistor and manufacture thereof
US5308782A (en) 1992-03-02 1994-05-03 Motorola Semiconductor memory device and method of formation
JP2748072B2 (en) 1992-07-03 1998-05-06 三菱電機株式会社 Semiconductor device and manufacturing method thereof
WO1994014198A1 (en) 1992-12-11 1994-06-23 Intel Corporation A mos transistor having a composite gate electrode and method of fabrication
JPH06268173A (en) 1993-03-15 1994-09-22 Toshiba Corp Semiconductor memory device
JP3403231B2 (en) 1993-05-12 2003-05-06 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JP3745392B2 (en) 1994-05-26 2006-02-15 株式会社ルネサステクノロジ Semiconductor device
JP2797984B2 (en) 1994-10-27 1998-09-17 日本電気株式会社 A solid-state imaging device and manufacturing method thereof
JP3318814B2 (en) 1995-03-15 2002-08-26 ソニー株式会社 A solid-state imaging device and a driving method thereof
KR0165398B1 (en) 1995-05-26 1998-12-15 윤종용 Vertical transistor manufacturing method
JPH098290A (en) 1995-06-20 1997-01-10 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US5767549A (en) 1996-07-03 1998-06-16 International Business Machines Corporation SOI CMOS structure
JP4014708B2 (en) 1997-08-21 2007-11-28 株式会社ルネサステクノロジ A method of designing a semiconductor integrated circuit device
US6242775B1 (en) 1998-02-24 2001-06-05 Micron Technology, Inc. Circuits and methods using vertical complementary transistors
JP3467416B2 (en) 1998-04-20 2003-11-17 Necエレクトロニクス株式会社 The semiconductor memory device and manufacturing method thereof
JP2000039628A (en) 1998-05-16 2000-02-08 Semiconductor Energy Lab Co Ltd Semiconductor display device
JP3718058B2 (en) 1998-06-17 2005-11-16 株式会社ルネサステクノロジ The method of manufacturing a semiconductor integrated circuit device
JP2000243085A (en) 1999-02-22 2000-09-08 Hitachi Ltd Semiconductor device
JP3621844B2 (en) 1999-02-24 2005-02-16 シャープ株式会社 Amplifying solid-state imaging device
US6392271B1 (en) 1999-06-28 2002-05-21 Intel Corporation Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
US6777254B1 (en) 1999-07-06 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method thereof
DE19945136A1 (en) 1999-09-21 2001-04-12 Infineon Technologies Ag Vertical pixel cells
JP2001237421A (en) 2000-02-24 2001-08-31 Toshiba Corp Semiconductor device, sram and method of manufacturing the same
US6882012B2 (en) 2000-02-28 2005-04-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method of manufacturing the same
US6624459B1 (en) 2000-04-12 2003-09-23 International Business Machines Corp. Silicon on insulator field effect transistors having shared body contact
JP3713418B2 (en) 2000-05-30 2005-11-09 富士ゼロックス株式会社 Method for producing a three-dimensional image processing apparatus
JP4021602B2 (en) 2000-06-16 2007-12-12 株式会社東芝 A semiconductor memory device
JP2002033399A (en) 2000-07-13 2002-01-31 Toshiba Corp Semiconductor integrated circuit and its manufacturing method
US6406962B1 (en) 2001-01-17 2002-06-18 International Business Machines Corporation Vertical trench-formed dual-gate FET device structure and method for creation
JP2002231951A (en) 2001-01-29 2002-08-16 Sony Corp Semiconductor device and its manufacturing method
US6531727B2 (en) 2001-02-09 2003-03-11 Micron Technology, Inc. Open bit line DRAM with ultra thin body transistors
US6448601B1 (en) 2001-02-09 2002-09-10 Micron Technology, Inc. Memory address and decode circuits with ultra thin body transistors
JP3908911B2 (en) 2001-02-16 2007-04-25 シャープ株式会社 Method of manufacturing an image sensor
JP3899236B2 (en) 2001-02-16 2007-03-28 シャープ株式会社 Method of manufacturing an image sensor
FR2823009B1 (en) 2001-04-02 2004-07-09 St Microelectronics Sa Method of manufacturing a vertical insulated gate transistor has low recovery of the grid on the source and the drain, and integrated circuit comprising such a transistor
US6927433B2 (en) 2001-06-28 2005-08-09 Isetec, Inc Active pixel image sensor with two transistor pixel, in-pixel non-uniformity correction, and bootstrapped reset lines
JP2003068883A (en) 2001-08-24 2003-03-07 Hitachi Ltd Semiconductor storage device
US6461900B1 (en) 2001-10-18 2002-10-08 Chartered Semiconductor Manufacturing Ltd. Method to form a self-aligned CMOS inverter using vertical device integration
JP2004165462A (en) 2002-11-14 2004-06-10 Sony Corp Solid-state imaging device and its manufacturing method
US7138685B2 (en) 2002-12-11 2006-11-21 International Business Machines Corporation Vertical MOSFET SRAM cell
KR100467027B1 (en) 2003-01-07 2005-01-24 삼성전자주식회사 Static random access memory having vertical transistors and method for fabricating the same
JP2004259733A (en) 2003-02-24 2004-09-16 Seiko Epson Corp Solid-state image pickup device
JP2004319808A (en) 2003-04-17 2004-11-11 Takehide Shirato Mis field effect transistor and its manufacturing method
US7052941B2 (en) 2003-06-24 2006-05-30 Sang-Yun Lee Method for making a three-dimensional integrated circuit structure
JP4651920B2 (en) 2003-07-15 2011-03-16 ルネサスエレクトロニクス株式会社 Semiconductor device
JP4758061B2 (en) 2003-10-16 2011-08-24 パナソニック株式会社 A solid-state imaging device and manufacturing method thereof
JP4416474B2 (en) 2003-10-28 2010-02-17 株式会社ルネサステクノロジ A semiconductor memory device
US7372091B2 (en) 2004-01-27 2008-05-13 Micron Technology, Inc. Selective epitaxy vertical integrated circuit components
US6878991B1 (en) 2004-01-30 2005-04-12 Micron Technology, Inc. Vertical device 4F2 EEPROM memory
JP4218894B2 (en) 2004-07-08 2009-02-04 シャープ株式会社 A solid-state imaging device and manufacturing method thereof
US7518182B2 (en) * 2004-07-20 2009-04-14 Micron Technology, Inc. DRAM layout with vertical FETs and method of formation
US7247570B2 (en) 2004-08-19 2007-07-24 Micron Technology, Inc. Silicon pillars for vertical transistors
US7442970B2 (en) 2004-08-30 2008-10-28 Micron Technology, Inc. Active photosensitive structure with buried depletion layer
US7241655B2 (en) 2004-08-30 2007-07-10 Micron Technology, Inc. Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
US7271052B1 (en) 2004-09-02 2007-09-18 Micron Technology, Inc. Long retention time single transistor vertical memory gain cell
US8110869B2 (en) * 2005-02-11 2012-02-07 Alpha & Omega Semiconductor, Ltd Planar SRFET using no additional masks and layout method
JP5017795B2 (en) 2005-04-13 2012-09-05 日本電気株式会社 A method of manufacturing a field effect transistor
US7371627B1 (en) * 2005-05-13 2008-05-13 Micron Technology, Inc. Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US20060261406A1 (en) 2005-05-18 2006-11-23 Yijian Chen Vertical integrated-gate CMOS device and its fabrication process
KR100673012B1 (en) 2005-09-02 2007-01-24 삼성전자주식회사 Double-gate type dynamic random access memory device having vertical channel transistors and method of fabricating the same
FR2891664B1 (en) 2005-09-30 2007-12-21 Commissariat Energie Atomique Vertical MOS transistor and method of manufacture
KR100800469B1 (en) 2005-10-05 2008-02-01 삼성전자주식회사 Circuitry device comprising vertical transistors with buried bit lines and manufacturing method for the same
US7977736B2 (en) 2006-02-23 2011-07-12 Samsung Electronics Co., Ltd. Vertical channel transistors and memory devices including vertical channel transistors
JP2007250652A (en) 2006-03-14 2007-09-27 Fujio Masuoka Semiconductor device
JP2008028240A (en) 2006-07-24 2008-02-07 Toshiba Corp Solid-state imaging apparatus
JP2008053388A (en) 2006-08-23 2008-03-06 Toshiba Corp Semiconductor device, and its manufacturing method
US8058683B2 (en) 2007-01-18 2011-11-15 Samsung Electronics Co., Ltd. Access device having vertical channel and related semiconductor device and a method of fabricating the access device
JP5114968B2 (en) 2007-02-20 2013-01-09 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
JP5130596B2 (en) 2007-05-30 2013-01-30 国立大学法人東北大学 Semiconductor device
JP2009037115A (en) 2007-08-03 2009-02-19 Sony Corp Semiconductor device, its manufacturing method, and display device
US8330089B2 (en) 2007-09-12 2012-12-11 Unisantis Electronics Singapore Pte Ltd. Solid-state imaging device
KR101109088B1 (en) 2007-09-12 2012-01-31 유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드 Solid-state image sensor
US8101500B2 (en) * 2007-09-27 2012-01-24 Fairchild Semiconductor Corporation Semiconductor device with (110)-oriented silicon
JP4900195B2 (en) 2007-10-26 2012-03-21 大日本印刷株式会社 Authoring system, method and computer program
JP5204121B2 (en) 2007-10-29 2013-06-05 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. The method of manufacturing a semiconductor structure and the semiconductor structure
US8183628B2 (en) 2007-10-29 2012-05-22 Unisantis Electronics Singapore Pte Ltd. Semiconductor structure and method of fabricating the semiconductor structure
JP2009117518A (en) 2007-11-05 2009-05-28 Toshiba Corp Semiconductor memory device and method of manufacturing the same
US7935598B2 (en) 2007-12-24 2011-05-03 Hynix Semiconductor Inc. Vertical channel transistor and method of fabricating the same
US7956434B2 (en) 2007-12-27 2011-06-07 Dongbu Hitek Co., Ltd. Image sensor and method for manufacturing the same
JP4316658B2 (en) 2008-01-29 2009-08-19 日本ユニサンティスエレクトロニクス株式会社 A method of manufacturing a semiconductor device
US8212298B2 (en) 2008-01-29 2012-07-03 Unisantis Electronics Singapore Pte Ltd. Semiconductor storage device and methods of producing it
WO2009095999A1 (en) 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. Semiconductor storage device
US8378425B2 (en) 2008-01-29 2013-02-19 Unisantis Electronics Singapore Pte Ltd. Semiconductor storage device
WO2009095998A1 (en) 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. Semiconductor storage device
US8598650B2 (en) 2008-01-29 2013-12-03 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
WO2009096001A1 (en) 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. Semiconductor storage device and memory embedded semiconductor device, and manufacturing method thereof
WO2009095997A1 (en) 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. Semiconductor device and its manufacturing method
WO2009096002A1 (en) 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. Manufacturing method of semiconductor storage device
US8188537B2 (en) 2008-01-29 2012-05-29 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
JP4316657B2 (en) 2008-01-29 2009-08-19 日本ユニサンティスエレクトロニクス株式会社 Semiconductor device
WO2009101704A1 (en) 2008-02-15 2009-08-20 Unisantis Electronics (Japan) Ltd. Method for manufacturing semiconductor device
WO2009133623A1 (en) 2008-05-02 2009-11-05 日本ユニサンティスエレクトロニクス株式会社 Solid-state imaging element
US8097907B2 (en) 2008-05-02 2012-01-17 Unisantis Electronics Singapore Pte Ltd. Solid-state imaging device
KR100971412B1 (en) 2008-05-21 2010-07-21 주식회사 하이닉스반도체 Method for forming vertical channel transistor of semiconductor device
JP2010034191A (en) 2008-07-28 2010-02-12 Toshiba Corp Semiconductor memory device and manufacturing method thereof
US8338292B2 (en) 2009-02-18 2012-12-25 International Business Machines Corporation Body contacts for FET in SOI SRAM array
JP5317343B2 (en) 2009-04-28 2013-10-16 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. Semiconductor device and manufacturing method thereof
US7968876B2 (en) 2009-05-22 2011-06-28 Macronix International Co., Ltd. Phase change memory cell having vertical channel access transistor
KR101116354B1 (en) 2009-09-30 2012-03-09 주식회사 하이닉스반도체 Semiconductor device with buried bitline interconnected one side contact and method for manufacturing the same
US8067800B2 (en) 2009-12-28 2011-11-29 Force Mos Technology Co., Ltd. Super-junction trench MOSFET with resurf step oxide and the method to make the same
KR101211442B1 (en) 2010-03-08 2012-12-12 유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드 A solid-state imaging device
JP5054182B2 (en) 2010-03-12 2012-10-24 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. The solid-state imaging device
JP5066590B2 (en) 2010-06-09 2012-11-07 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. Semiconductor device and manufacturing method thereof
JP5087655B2 (en) 2010-06-15 2012-12-05 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. Semiconductor device and manufacturing method thereof

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258635A (en) * 1988-09-06 1993-11-02 Kabushiki Kaisha Toshiba MOS-type semiconductor integrated circuit device
US5811336A (en) * 1994-08-31 1998-09-22 Nec Corporation Method of forming MOS transistors having gate insulators of different thicknesses
US5905283A (en) * 1994-08-31 1999-05-18 Nec Corporation Method of forming a MOS transistor having gate insulators of different thicknesses
US6483171B1 (en) * 1999-08-13 2002-11-19 Micron Technology, Inc. Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same
US20040169293A1 (en) * 2000-06-05 2004-09-02 Akihiro Sushihara Basic cells configurable into different types of semiconductor integrated circuits
US20050127404A1 (en) * 2000-06-05 2005-06-16 Akihiro Sushihara Basic cells configurable into different types of semiconductor integrated circuits
US6740937B1 (en) * 2000-06-05 2004-05-25 Oki Electric Industry Co., Ltd. Basic cells configurable into different types of semiconductor integrated circuits
US20060033524A1 (en) * 2000-06-05 2006-02-16 Akihiro Sushihara Basic cells configurable into different types of semiconductor integrated circuits
US6815277B2 (en) * 2001-12-04 2004-11-09 International Business Machines Corporation Method for fabricating multiple-plane FinFET CMOS
US6658259B2 (en) * 2002-03-07 2003-12-02 Interwave Communications International, Ltd. Wireless network having a virtual HLR and method of operating the same
US7368334B2 (en) * 2003-04-04 2008-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-on-insulator chip with multiple crystal orientations
US20040262681A1 (en) * 2003-05-28 2004-12-30 Fujio Masuoka Semiconductor device
US20040256639A1 (en) * 2003-06-17 2004-12-23 International Business Machines Corporation Low leakage heterojunction vertical transistors and high performance devices thereof
US6943407B2 (en) * 2003-06-17 2005-09-13 International Business Machines Corporation Low leakage heterojunction vertical transistors and high performance devices thereof
US20050263821A1 (en) * 2004-05-25 2005-12-01 Cho Young K Multiple-gate MOS transistor and a method of manufacturing the same
US20080227241A1 (en) * 2007-03-12 2008-09-18 Yukio Nakabayashi Method of fabricating semiconductor device
US20100200913A1 (en) * 2008-01-29 2010-08-12 Unisantis Electronics (Japan) Ltd. Semiconductor storage device

Cited By (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8482041B2 (en) 2007-10-29 2013-07-09 Unisantis Electronics Singapore Pte Ltd. Semiconductor structure and method of fabricating the semiconductor structure
US8188537B2 (en) * 2008-01-29 2012-05-29 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
US20100213539A1 (en) * 2008-01-29 2010-08-26 Unisantis Electronics (Japan) Ltd. Semiconductor device and production method therefor
US8343835B2 (en) 2008-01-29 2013-01-01 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
US8372713B2 (en) 2008-01-29 2013-02-12 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
US20100207201A1 (en) * 2008-01-29 2010-08-19 Fujio Masuoka Semiconductor device and production method therefor
US8598650B2 (en) 2008-01-29 2013-12-03 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
US8497548B2 (en) * 2009-04-28 2013-07-30 Unisantis Electronics Singapore Pte Ltd. Semiconductor device including a MOS transistor and production method therefor
US20100270611A1 (en) * 2009-04-28 2010-10-28 Fujio Masuoka Semiconductor device including a mos transistor and production method therefor
US8647947B2 (en) 2009-04-28 2014-02-11 Unisantis Electronics Singapore Pte Ltd. Semiconductor device including a MOS transistor and production method therefor
US20100314671A1 (en) * 2009-06-11 2010-12-16 Elpida Memory, Inc. Semiconductor device and method of forming the same
US8610202B2 (en) 2009-10-01 2013-12-17 Unisantis Electronics Singapore Pte Ltd. Semiconductor device having a surrounding gate
US20110079841A1 (en) * 2009-10-01 2011-04-07 Fujio Masuoka Semiconductor device
US8264042B2 (en) * 2009-12-01 2012-09-11 Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences Hybrid orientation accumulation mode GAA CMOSFET
US20110254102A1 (en) * 2009-12-01 2011-10-20 Shanghai Institute of Microsystem and Information Technology Chinese Academy Hybrid orientation inversion mode gaa cmosfet
US8274119B2 (en) * 2009-12-01 2012-09-25 Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences Hybrid material accumulation mode GAA CMOSFET
US8274118B2 (en) * 2009-12-01 2012-09-25 Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences Hybrid material accumulation mode GAA CMOSFET
US8330229B2 (en) * 2009-12-01 2012-12-11 Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences Hybrid orientation inversion mode GAA CMOSFET
US8330228B2 (en) * 2009-12-01 2012-12-11 Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences Hybrid material inversion mode GAA CMOSFET
US20110254013A1 (en) * 2009-12-01 2011-10-20 Shanghai Institute of Microsystem and Infomation Technology Chinese Academy Hybrid orientation accumulation mode gaa cmosfet
US8350298B2 (en) * 2009-12-01 2013-01-08 Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences Hybrid material inversion mode GAA CMOSFET
US20110254100A1 (en) * 2009-12-01 2011-10-20 Shanghai Institute of Microsystem and Information Technology Chinese Academy Hybrid material accumulation mode gaa cmosfet
US20110254099A1 (en) * 2009-12-01 2011-10-20 Shanghai Institute of Microsystem and Information Technology Chinese Academy Hybrid material accumulation mode GAA CMOSFET
US20110254101A1 (en) * 2009-12-01 2011-10-20 Shanghai Institute of Microsystem and Information Technology Chinese Academy Hybrid material inversion mode gaa cmosfet
US20110248354A1 (en) * 2009-12-01 2011-10-13 Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Hybrid material inversion mode gaa cmosfet
US8354721B2 (en) * 2010-02-11 2013-01-15 Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences Gate-all-around CMOSFET devices
US20110254058A1 (en) * 2010-02-11 2011-10-20 Shanghai Institute of Microsystem and Information Technology Chinese Academy Gate-All-Around CMOSFET devices
US20110215381A1 (en) * 2010-03-08 2011-09-08 Fujio Masuoka Solid state imaging device
US8575662B2 (en) 2010-03-08 2013-11-05 Unisantis Electronics Singapore Pte Ltd. Solid state imaging device having high pixel density
US8487357B2 (en) 2010-03-12 2013-07-16 Unisantis Electronics Singapore Pte Ltd. Solid state imaging device having high sensitivity and high pixel density
US8486785B2 (en) 2010-06-09 2013-07-16 Unisantis Electronics Singapore Pte Ltd. Surround gate CMOS semiconductor device
US8609494B2 (en) 2010-06-09 2013-12-17 Unisantis Electronics Singapore Pte Ltd. Surround gate CMOS semiconductor device
US9153697B2 (en) 2010-06-15 2015-10-06 Unisantis Electronics Singapore Pte Ltd. Surrounding gate transistor (SGT) structure
US8564034B2 (en) 2011-09-08 2013-10-22 Unisantis Electronics Singapore Pte. Ltd. Solid-state imaging device
US8669601B2 (en) 2011-09-15 2014-03-11 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device having pillar-shaped semiconductor
US9035384B2 (en) 2011-12-19 2015-05-19 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device
US9245889B2 (en) 2011-12-19 2016-01-26 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing semiconductor device and semiconductor device
US8772175B2 (en) 2011-12-19 2014-07-08 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing semiconductor device and semiconductor device
US8916478B2 (en) 2011-12-19 2014-12-23 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing semiconductor device and semiconductor device
US9806163B2 (en) 2011-12-19 2017-10-31 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device having an nMOS SGT and a pMOS SGT
US9362353B2 (en) 2011-12-19 2016-06-07 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device
US9748244B2 (en) 2011-12-19 2017-08-29 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing semiconductor device and semiconductor device
US9478545B2 (en) 2011-12-19 2016-10-25 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing semiconductor device and semiconductor device
US8748938B2 (en) 2012-02-20 2014-06-10 Unisantis Electronics Singapore Pte. Ltd. Solid-state imaging device
US20140117366A1 (en) * 2012-10-31 2014-05-01 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US9355908B2 (en) * 2012-10-31 2016-05-31 Kabushiki Kaisha Toshiba Semiconductor pillar transistors having channels with different crystal orientations
US20150008448A1 (en) * 2013-07-02 2015-01-08 General Electric Company Metal-oxide-semiconductor (mos) devices with increased channel periphery and methods of manufacture
US9748341B2 (en) * 2013-07-02 2017-08-29 General Electric Company Metal-oxide-semiconductor (MOS) devices with increased channel periphery
US20150048295A1 (en) * 2013-08-19 2015-02-19 SK Hynix Inc. Semiconductor device having fin gate, resistive memory device including the same, and method of manufacturing the same
US9224836B2 (en) * 2013-08-19 2015-12-29 SK Hynix Inc. Semiconductor device having vertical channel, resistive memory device including the same, and method of manufacturing the same
US9231055B2 (en) * 2013-08-19 2016-01-05 SK Hynix Inc. Semiconductor device having fin gate, resistive memory device including the same, and method of manufacturing the same
US20150048296A1 (en) * 2013-08-19 2015-02-19 SK Hynix Inc. Semiconductor device having fin gate, resistive memory device including the same, and method of manufacturing the same
US9299805B2 (en) * 2013-08-19 2016-03-29 SK Hynix Inc. Variable resistive memory device including vertical channel PMOS transistor
US20150048294A1 (en) * 2013-08-19 2015-02-19 SK Hynix Inc. Variable resistive memory device including vertical channel pmos transistor and method of manufacturing the same
US9082697B2 (en) * 2013-08-19 2015-07-14 SK Hynix Inc. Variable resistive memory device including vertical channel PMOS transistor and method of manufacturing the same
US20150048292A1 (en) * 2013-08-19 2015-02-19 SK Hynix Inc. Semiconductor device having vertical channel, resistive memory device including the same, and method of manufacturing the same
US9397198B2 (en) * 2013-08-19 2016-07-19 SK Hynix Inc. Method of manufacturing semiconductor device having fin gate
US9466671B2 (en) * 2013-08-19 2016-10-11 SK Hynix Inc. Semiconductor device having fin gate, resistive memory device including the same, and method of manufacturing the same
US9054033B2 (en) * 2013-08-19 2015-06-09 SK Hynix Inc. Semiconductor device having vertical channel, resistive memory device including the same, and method of manufacturing the same
US9190491B1 (en) * 2013-08-19 2015-11-17 SK Hynix Inc. Variable resistive memory device including vertical channel PMOS transistor and method of manufacturing the same
US20150333152A1 (en) * 2014-05-16 2015-11-19 Taiwan Semiconductor Manufacturing Company Limited Vertical structure and method of forming the same
US9966448B2 (en) * 2014-05-16 2018-05-08 Taiwan Semiconductor Manufacturing Company Limited Method of making a silicide beneath a vertical structure
US9620500B2 (en) 2014-09-12 2017-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Series-connected transistor structure
US9373620B2 (en) * 2014-09-12 2016-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Series connected transistor structure and method of manufacturing the same
US20170271508A1 (en) * 2016-03-21 2017-09-21 Samsung Electronics Co., Ltd. Semiconductor devices

Also Published As

Publication number Publication date Type
US8482041B2 (en) 2013-07-09 grant
US8183628B2 (en) 2012-05-22 grant
US20120171825A1 (en) 2012-07-05 application

Similar Documents

Publication Publication Date Title
US7042009B2 (en) High mobility tri-gate devices and methods of fabrication
Taur et al. CMOS scaling into the nanometer regime
US7115945B2 (en) Strained silicon fin structure
US6762448B1 (en) FinFET device with multiple fin structures
US6645797B1 (en) Method for forming fins in a FinFET device using sacrificial carbon layer
US7564105B2 (en) Quasi-plannar and FinFET-like transistors on bulk silicon
US6252284B1 (en) Planarized silicon fin device
US5675164A (en) High performance multi-mesa field effect transistor
US6709982B1 (en) Double spacer FinFET formation
US6580137B2 (en) Damascene double gated transistors and related manufacturing methods
US6432754B1 (en) Double SOI device with recess etch and epitaxy
US6815277B2 (en) Method for fabricating multiple-plane FinFET CMOS
US6800885B1 (en) Asymmetrical double gate or all-around gate MOSFET devices and methods for making same
US7138302B2 (en) Method of fabricating an integrated circuit channel region
US6972461B1 (en) Channel MOSFET with strained silicon channel on strained SiGe
US20100213539A1 (en) Semiconductor device and production method therefor
US7288445B2 (en) Double gated transistor and method of fabrication
US7265008B2 (en) Method of IC production using corrugated substrate
US20070108528A1 (en) Sram cell
US8169025B2 (en) Strained CMOS device, circuit and method of fabrication
US6977194B2 (en) Structure and method to improve channel mobility by gate electrode stress modification
US7190050B2 (en) Integrated circuit on corrugated substrate
US6495882B2 (en) Short-channel schottky-barrier MOSFET device
US20070235817A1 (en) Write margin improvement for SRAM cells with SiGe stressors
US7411252B2 (en) Substrate backgate for trigate FET

Legal Events

Date Code Title Description
AS Assignment

Owner name: UNISANTIS ELECTRONICS (JAPAN) LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MASUOKA, FUJIO;LEE, KEON JAE;REEL/FRAME:024326/0275

Effective date: 20100310

AS Assignment

Owner name: UNISANTIS ELECTRONICS SINGAPORE PTE LTD., SINGAPOR

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UNISANTIS ELECTRONICS JAPAN LTD.;REEL/FRAME:026970/0670

Effective date: 20110913

FPAY Fee payment

Year of fee payment: 4