CN113257815B - 竖直相邻器件之间带隔离部的半导体装置及电子设备 - Google Patents

竖直相邻器件之间带隔离部的半导体装置及电子设备 Download PDF

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CN113257815B
CN113257815B CN202110477558.9A CN202110477558A CN113257815B CN 113257815 B CN113257815 B CN 113257815B CN 202110477558 A CN202110477558 A CN 202110477558A CN 113257815 B CN113257815 B CN 113257815B
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semiconductor device
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semiconductor layer
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CN113257815A (zh
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朱慧珑
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Institute of Microelectronics of CAS
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Abstract

公开了一种竖直相邻器件之间带隔离部的半导体装置及包括这种半导体装置的电子设备。根据实施例，该半导体装置可以包括：衬底；依次叠置在衬底上的第一竖直型半导体器件和第二竖直型半导体器件，第一竖直型半导体器件和第二竖直型半导体器件各自包括在竖直方向上依次叠置的第一源/漏区、沟道区和第二源/漏区；以及用于电隔离第一竖直型半导体器件与第二竖直型半导体器件的隔离结构，其中，隔离结构包括pn结。

Description

竖直相邻器件之间带隔离部的半导体装置及电子设备
技术领域
本公开涉及半导体领域，具体地，涉及竖直相邻器件之间带隔离部的半导体装置及包括这种半导体装置的电子设备。
背景技术
在水平型器件如金属氧化物半导体场效应晶体管(MOSFET)中，源极、栅极和漏极沿大致平行于衬底表面的方向布置。由于这种布置，水平型器件不易进一步缩小。与此不同，在竖直型器件中，源极、栅极和漏极沿大致垂直于衬底表面的方向布置。因此，相对于水平型器件，竖直型器件更容易缩小。对于竖直型器件，可以通过彼此叠置来增加集成密度。在叠置的竖直型器件之间，特别是在有源区为单晶的情况下，除键合工艺之外，目前尚无有效的方法来实现电隔离。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种竖直相邻器件之间带隔离部的半导体装置及包括这种半导体装置的电子设备。
根据本公开的一个方面，提供了一种半导体装置，包括：衬底；依次叠置在衬底上的第一竖直型半导体器件和第二竖直型半导体器件，第一竖直型半导体器件和第二竖直型半导体器件各自包括在竖直方向上依次叠置的第一源/漏区、沟道区和第二源/漏区；以及用于电隔离第一竖直型半导体器件与第二竖直型半导体器件的隔离结构，其中，隔离结构包括pn结。
根据本公开的另一方面，提供了一种电子设备，包括上述半导体装置。
根据本公开的实施例，彼此叠置的竖直型半导体器件可以通过它们之间基于pn结的隔离结构而相互电隔离。pn结可以在半导体层中形成。因此，隔离结构的形成可以与竖直型半导体器件的制作兼容。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1和2示出了根据本公开实施例的制造半导体装置的流程中部分阶段的示意图；
图3和4示出了根据本公开另一实施例的制造半导体装置的流程中部分阶段的示意图；
图5和6示出了根据本公开另一实施例的制造半导体装置的流程中部分阶段的示意图；
图7和8示出了根据本公开另一实施例的制造半导体装置的流程中部分阶段的示意图；
图9和10示出了根据本公开另一实施例的制造半导体装置的流程中部分阶段的示意图；
图11和12示出了根据本公开另一实施例的制造半导体装置的流程中部分阶段的示意图；
图13和14示出了根据本公开另一实施例的制造半导体装置的流程中部分阶段的示意图；
图15示出了根据本公开另一实施例的半导体装置的示意图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，提供了一种包括彼此叠置的竖直型半导体器件的半导体装置。竖直型半导体器件包括相对于衬底竖直(例如，大致垂直于衬底表面)延伸的有源区，包括上下两端的源/漏区以及源/漏区之间的沟道区。例如，有源区可以包括在衬底上依次叠置的第一源/漏层、沟道层和第二源/漏层。各层之间可以彼此邻接，当然中间也可能存在其他半导体层，例如泄漏抑制层和/或开态电流增强层(带隙比相邻层大或小的半导体层)。在第一源/漏层和第二源/漏层中可以形成器件的源/漏区，且在沟道层中可以形成器件的沟道区。这些层可以通过外延生长形成，并可以是单晶。
在竖直方向上相邻的器件之间，可以设置基于pn结的隔离结构。由于pn结可以通过半导体层来形成，故而隔离结构的形成可以结合在器件的制作中。例如，所述半导体层可以通过外延生长，设置在相邻器件的有源区之间。这样，可以不影响器件有源区的晶体质量。
这种pn结可以作为npn结或pnp结的一部分而存在。基于pn结的隔离结构可以通过相邻器件之间另外设置的半导体层来形成，或者也可以包括至少一个源/漏层。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离，导电材料用于形成电极、互连结构等)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1和2示出了根据本公开实施例的制造半导体装置的流程中部分阶段的示意图。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底如Si晶片为例进行描述。
在衬底1001上，可以通过例如外延生长，形成用于限定第一竖直型半导体器件(参见图2中的D1)的有源区的半导体层、用于限定第二竖直型半导体器件(参见图2中的D2)的有源区的半导体层以及用于限定它们之间的隔离部(参见图2中的I1、I2)的半导体层。例如，用于限定第一器件D1的有源区的半导体层可以包括第一源/漏层1003、沟道层1005和第二源/漏层1007。类似地，用于限定第二器件D2的有源区的半导体层可以包括第一源/漏层1013、沟道层1015和第二源/漏层1017。用于限定隔离部的半导体层可以包括第一半导体层1009和第二半导体层1011。这些半导体层可以具有良好的晶体质量，并可以是单晶结构。相邻的半导体层之间可以具有清晰的晶体界面。
这些半导体层可以包括各种合适的半导体材料，例如，元素半导体材料如Si或Ge之类的IV族元素半导体材料，化合物半导体材料如SiGe之类的IV族化合物半导体材料或者InP、GaAs之类的III-V族化合物半导体材料。可以基于衬底的性质、要实现的器件性能等因素，来选择半导体层的材料。
在本实施例中，在Si晶片上形成的各半导体层可以是Si系材料。例如，除了沟道层1005和1015包括SiGe(用于提供刻蚀选择性，以便形成自对准的栅堆叠)，其余各半导体层均可以包括Si。但是，本公开不限于此。例如，沟道层1005和1015也可以包括与其余半导体层相同的材料。
用于形成有源区的各半导体层可以根据所要形成的器件的导电类型而被适当地掺杂。例如，源/漏层可以被掺杂为与所要实现的器件的导电类型相同的导电类型，而沟道层可以未有意掺杂，或者被轻掺杂为例如与所要实现的器件的导电类型相反的导电类型以调节器件阈值电压。在本实施例中，第一器件D1可以具有第一导电类型如p型，因此第一源/漏层1003和第二源/漏层1007可以被p型重掺杂，而沟道层1005可以未有意掺杂或被n型轻掺杂。类似地，第二器件D2可以具有第二导电类型如n型，因此第一源/漏层1013和第二源/漏层1017可以被n型重掺杂，而沟道层1015可以未有意掺杂或被p型轻掺杂。半导体层的掺杂可以通过在外延生长时原位掺杂实现，或者可以通过其他掺杂方法如离子注入来实现。
另外，用于限定隔离部的半导体层可以根据其相对两侧的器件的导电类型而被适当地掺杂，以提供pn结。例如，第一半导体层1009可以被n型轻掺杂，而第二半导体层1011可以被p型轻掺杂。第一半导体层1009和第二半导体层1011中至少之一的掺杂浓度可以低于约2×1019cm-3。
在相邻的半导体层之间可以具有掺杂浓度界面。
各半导体层可以具有合适的厚度。例如，源/漏层1003、1007、1013、1017可以具有约10至50nm的厚度，沟道层1005、1015可以具有约10至100nm的厚度，第一半导体层1009和第二半导体层1011可以具有约15至50nm的厚度。注意，第一器件D1和第二器件D2可以具有不同的尺寸，例如可以具有不同的沟道层厚度(以实现不同的栅长)，以实现不同的电气特性。
可以从上述半导体层中构图器件的有源区。例如，如图2所示，可以通过光刻，将上述半导体层的叠层构图为竖直延伸的柱状(例如，圆柱状)。这种构图可以借助于顶部的硬掩模层(图2中未示出)。各半导体层的相应侧壁可以在竖直方向上实质上共面。
可以通过例如选择性刻蚀，使沟道层(在此，SiGe)相对于上下的源/漏层(在此，Si)在横向上凹入。为更好地控制刻蚀深度，例如可以采用原子层刻蚀(ALE)。然后，可以通过例如淀积栅介质材料和栅导体材料，并回蚀，来形成栅介质层1019和栅导体层1021。如此形成的栅堆叠(1019/1021)可以嵌入到沟道层相对于源/漏层的凹入中，并自对准于沟道层。例如，栅介质层1019可以包括厚度为约1至5nm的高k栅介质如HfO2，栅导体层1021可以包括金属。
在该示例中，第一器件D1和第二器件D2包括相同的栅堆叠配置。但是，本公开不限于此。第一器件D1和第二器件D2可以包括不同的栅堆叠配置，特别是在它们的导电类型不同时。
例如，可以在沟道层1005、1015相对于源/漏层的凹入中，形成牺牲栅。可以在衬底1001上形成一定厚度的电介质层，该电介质层的顶面可以处于要形成第一器件D1的栅堆叠的高度，例如处于第一器件D1的沟道层1005的顶面高度与底面高度之间以减少栅堆叠与源/漏层之间的交迭。然后，可以去除牺牲栅，以释放所述凹入的空间，并在该电介质层上进行适于第一器件D1的第一栅堆叠的形成，形成的第一栅堆叠嵌入到所述凹入中。可以通过进一步淀积来提升电介质层的高度，使其顶面处于要形成第二器件D2的栅堆叠的高度，例如处于第二器件D2的沟道层1015的顶面高度与底面高度之间以减少栅堆叠与源/漏层之间的交迭。然后，可以去除第二器件D2的沟道层1015相对于源/漏层的凹入中形成的第一栅堆叠，并在电介质层上进行适于第二器件D2的第二栅堆叠的形成，形成的第二栅堆叠可以嵌入到第二器件D2的沟道层1015相对于源/漏层的凹入中。
在此，示出了两个器件D1和D2彼此叠置的示例。但是，本公开不限于此。例如，可以在竖直方向上叠置更多的器件，且可以根据需要，在相邻的器件之间设置隔离部。
如图2所示，根据本实施例的半导体装置可以包括彼此叠置的第一器件D1和第二器件D2。第一器件D1和第二器件D2各自可以包括形成于第一源/漏层1003、1013中的第一源/漏区，形成于第二源/漏层1007、1017中的第二源/漏区，以及位于它们之间、形成于沟道层1005、1015中的沟道区。栅堆叠(1019/1021)可以围绕沟道层1005、1015的外周。
在第一器件D1与第二器件D2之间，可以具有隔离结构I1、I2。在此，隔离结构I1包括第一器件D1的第二源/漏层1007、第一半导体层1009和第二半导体层1011，它们由于各自的掺杂而形成pnp结。类似地，隔离结构I2包括第一半导体层1009、第二半导体层1011和第二器件D2的第一源/漏层1013，它们由于各自的掺杂而形成npn结。隔离结构I1和隔离结构I2可以实现第一器件D1与第二器件D2之间的电隔离。在此，用于形成隔离结构的各半导体层可以与用于限定有源区的半导体层一起通过外延生长形成，因此可以减少对有源区的晶体结构的破坏，并因此抑制器件性能的劣化。
图3和4示出了根据本公开另一实施例的制造半导体装置的流程中部分阶段的示意图。图3和图4所示的实施例与图1和图2所示的实施例基本上相同，除了第一半导体层1009和第二半导体层1011被替换为第三半导体层2009和第四半导体层2011之外。以下，将主要描述该实施例与上述实施例之间的不同之处，重复的说明将不再赘述。
具体地，在该实施例中，第三半导体层2009和第四半导体层2011可以包括与沟道层1005、1015相同的材料如SiGe，并因此也在横向上凹入，从而栅堆叠也会嵌入到该凹入中。在此，在第三半导体层2009和第四半导体层2011所形成的相对凹入中形成的栅堆叠可以是用于第一器件D1的第一栅堆叠，或者用于第二器件D2的第二栅堆叠，甚至也可以是不同配置的另一栅堆叠。
在以上实施例中，第一器件D1和第二器件D2具有不同导电类型，因此可以在它们之间设置导电类型彼此不同的两个半导体层，并因此形成npn结以及pnp结，以实现电隔离。但是，本公开不限于此。例如，第一器件D1和第二器件D2可以具有相同导电类型。
图5和6示出了根据本公开另一实施例的制造半导体装置的流程中部分阶段的示意图。以下，将主要描述该实施例与上述实施例之间的不同之处，重复的说明将不再赘述。
如图5所示，可以通过例如外延生长，在衬底1001上设置用于限定第一器件D1的有源区的半导体层以及用于限定第二器件D2的有源区的半导体层。与图1中所示的实施例不同，在该实施例中，第一器件D1的第一源/漏层1003和第二源/漏层1007均被n型重掺杂，从而与第二器件D2具有相同的导电类型。
另外，在第一器件D1与第二器件D2之间，可以设置p型轻掺杂的第五半导体层3011。类似地，第五半导体层3011可以包括厚度为约15至50nm的Si，且掺杂浓度可以低于约2×1019cm-3。
然后，如图6所示，可以按照上述工艺来限定有源区，并形成栅堆叠。在该实施例中，隔离结构I包括第一器件D1的第二源/漏层1007、第五半导体层3011和第二器件D2的第一源/漏层1013，它们由于各自的掺杂而形成npn结。隔离结构I可以实现第一器件D1与第二器件D2之间的电隔离。
在该实施例中，第一器件D1和第二器件D2均为n型导电性，隔离结构I包括npn结。根据其他实施例，第一器件D1和第二器件D2可以具有p型导电性，相应地隔离结构I可以包括pnp结。
图7和8示出了根据本公开另一实施例的制造半导体装置的流程中部分阶段的示意图。图7和图8所示的实施例与图5和图6所示的实施例基本上相同，除了第五半导体层3011被替换为第六半导体层4011之外。以下，将主要描述该实施例与上述实施例之间的不同之处，重复的说明将不再赘述。
具体地，在该实施例中，第六半导体层4011可以包括与沟道层1005、1015相同的材料如SiGe，并因此也在横向上凹入，从而栅堆叠也会嵌入到该凹入中。另外，可以改变第六半导体层4011中的掺杂浓度，以实现更高的阈值电压(隔离结构I本身可以等价于一个竖直型器件)，从而实现更好的电隔离。
在以上实施例中，第一器件D1和第二器件D2具有相同导电类型，因此可以在它们之间设置相反导电类型的半导体层，并因此与第一器件D1和第二器件D2各自的源/漏层一起形成npn结或pnp结，以实现电隔离。但是，本公开不限于此。例如，可以在第一器件D1与第二器件D2之间直接设置npn结或pnp结。
图9和10示出了根据本公开另一实施例的制造半导体装置的流程中部分阶段的示意图。图9和图10所示的实施例与图5和图6所示的实施例基本上相同，除了第五半导体层3011被替换为第七半导体层5009、第八半导体层5010和第九半导体层5011之外。以下，将主要描述该实施例与上述实施例之间的不同之处，重复的说明将不再赘述。
具体地，在该实施例中，可以在第一器件D1与第二器件D2之间设置分别被p型轻掺杂、n型轻掺杂和p型轻掺杂的第七半导体层5009、第八半导体层5010和第九半导体层5011，从而它们可以形成pnp结。类似地，第七半导体层5009、第八半导体层5010和第九半导体层5011各自可以包括厚度为约15至50nm的Si，且其中至少一个的掺杂浓度可以低于约2×1019cm-3。因此，在该实施例中，隔离结构I包括第七半导体层5009、第八半导体层5010和第九半导体层5011构成的pnp结。
根据其他实施例，第一器件D1和第二器件D2可以具有p型导电性，隔离结构I也可以包括pnp结。
图11和12示出了根据本公开另一实施例的制造半导体装置的流程中部分阶段的示意图。图11和图12所示的实施例与图9和图10所示的实施例基本上相同，除了第七半导体层5009、第八半导体层5010和第九半导体层5011被分别替换为第十半导体层6009、第十一半导体层6010和第十二半导体层6011之外。以下，将主要描述该实施例与上述实施例之间的不同之处，重复的说明将不再赘述。
具体地，在该实施例中，第十半导体层6009、第十一半导体层6010和第十二半导体层6011可以包括与沟道层1005、1015相同的材料如SiGe，并因此也在横向上凹入，从而栅堆叠也会嵌入到该凹入中。
在以上实施例中，第一器件D1和第二器件D2具有相同导电性，隔离结构I包括pnp结。但是，本公开不限于此。例如，也可以设置npn结。
图13和14示出了根据本公开另一实施例的制造半导体装置的流程中部分阶段的示意图。图13和图14所示的实施例与图9和图10所示的实施例基本上相同，除了第七半导体层5009、第八半导体层5010和第九半导体层5011被分别替换为第十三半导体层7009、第十四半导体层7010和第十五半导体层7011之外。以下，将主要描述该实施例与上述实施例之间的不同之处，重复的说明将不再赘述。
具体地，在该实施例中，第十三半导体层7009、第十四半导体层7010和第十五半导体层7011分别被n型轻掺杂、p型轻掺杂和n型轻掺杂(其中至少之一的掺杂浓度可以低于约2×1019cm-3)，相应地隔离结构I可以包括npn结。
根据其他实施例，第一器件D1和第二器件D2可以具有p型导电性，隔离结构I也可以包括npn结。
根据另一实施例，如图15所示，在隔离结构I外周也可以形成栅堆叠。
根据本公开实施例的半导体装置可以应用于各种电子设备。例如，可以基于这样的半导体装置形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体装置的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、个人计算机(PC)、平板电脑、人工智能设备、可穿戴设备或移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (22)

1.一种半导体装置，包括：
衬底；
依次叠置在所述衬底上的第一竖直型半导体器件和第二竖直型半导体器件，所述第一竖直型半导体器件和所述第二竖直型半导体器件各自包括在竖直方向上依次叠置的第一源/漏区、沟道区和第二源/漏区；以及
用于电隔离所述第一竖直型半导体器件与所述第二竖直型半导体器件的隔离结构，
其中，所述隔离结构包括pn结。
2.根据权利要求1所述的半导体装置，其中，所述隔离结构包括pnp结和npn结中至少之一。
3.根据权利要求1所述的半导体装置，其中，所述pn结中p型掺杂区的掺杂浓度和n型掺杂区的掺杂浓度至少之一低于2×1019cm-3。
4.根据权利要求2所述的半导体装置，其中，所述pnp结或所述npn结中p型掺杂区的掺杂浓度和n型掺杂区的掺杂浓度至少之一低于2×1019cm-3。
5.根据权利要求1所述的半导体装置，其中，所述pn结包括所述第一竖直型半导体器件的第二源/漏区或所述第二竖直型半导体器件的第一源/漏区。
6.根据权利要求2所述的半导体装置，其中，所述pnp结或所述npn结包括所述第一竖直型半导体器件的第二源/漏区和所述第二竖直型半导体器件的第一源/漏区中至少之一。
7.根据权利要求1至6中任一项所述的半导体装置，其中，所述第一竖直型半导体器件与所述第二竖直型半导体器件各自的第一源/漏区、沟道区和第二源/漏区包括单晶半导体材料。
8.根据权利要求7所述的半导体装置，其中，所述隔离结构包括单晶半导体材料。
9.根据权利要求1至4中任一项所述的半导体装置，其中，
所述第一竖直型半导体器件的第二源/漏区为第一导电类型，所述第二竖直型半导体器件的第一源/漏区为第二导电类型，
所述半导体装置还包括设置在所述第一竖直型半导体器件的第二源/漏区与所述第二竖直型半导体器件的第一源/漏区之间的第二导电类型半导体层和第一导电类型半导体层，
其中，所述隔离结构包括：所述第一竖直型半导体器件的第二源/漏区、所述第二导电类型半导体层与所述第一导电类型半导体层构成的pnp结和npn结之一，以及所述第二导电类型半导体层、所述第一导电类型半导体层与所述第二竖直型半导体器件的第一源/漏区构成的pnp结和npn结中另一个。
10.根据权利要求9所述的半导体装置，还包括：
所述第一竖直型半导体器件的沟道区外周的第一栅堆叠；
所述第二竖直型半导体器件的沟道区外周的第二栅堆叠；以及
所述第二导电类型半导体层和所述第一导电类型半导体层外周的第三栅堆叠。
11.根据权利要求9所述的半导体装置，其中，
所述第一竖直型半导体器件的第二源/漏区以及所述第二竖直型半导体器件的第一源/漏区为重掺杂，
所述第二导电类型半导体层以及所述第一导电类型半导体层为轻掺杂。
12.根据权利要求1至4中任一项所述的半导体装置，其中，
所述第一竖直型半导体器件的第二源/漏区为第一导电类型，所述第二竖直型半导体器件的第一源/漏区为第一导电类型，
所述半导体装置还包括设置在所述第一竖直型半导体器件的第二源/漏区与所述第二竖直型半导体器件的第一源/漏区之间的第二导电类型半导体层，
其中，所述隔离结构包括所述第一竖直型半导体器件的第二源/漏区、所述第二导电类型半导体层与所述第二竖直型半导体器件的第一源/漏区构成的pnp结和npn结之一。
13.根据权利要求12所述的半导体装置，还包括：
所述第一竖直型半导体器件的沟道区外周的第一栅堆叠；
所述第二竖直型半导体器件的沟道区外周的第二栅堆叠；以及
所述第二导电类型半导体层外周的第三栅堆叠。
14.根据权利要求12所述的半导体装置，其中，
所述第一竖直型半导体器件的第二源/漏区以及所述第二竖直型半导体器件的第一源/漏区为重掺杂，
所述第二导电类型半导体层为轻掺杂。
15.根据权利要求1至4中任一项所述的半导体装置，其中，
所述第一竖直型半导体器件的第二源/漏区为第一导电类型，所述第二竖直型半导体器件的第一源/漏区为第一导电类型，
所述半导体装置还包括设置在所述第一竖直型半导体器件的第二源/漏区与所述第二竖直型半导体器件的第一源/漏区之间的第二导电类型半导体层、第一导电类型半导体层和另一第二导电类型半导体层，
其中，所述隔离结构包括：所述第二导电类型半导体层、所述第一导电类型半导体层和所述另一第二导电类型半导体层构成的pnp结和npn结之一。
16.根据权利要求15所述的半导体装置，还包括：
所述第一竖直型半导体器件的沟道区外周的第一栅堆叠；
所述第二竖直型半导体器件的沟道区外周的第二栅堆叠；以及
所述第二导电类型半导体层、所述第一导电类型半导体层和所述另一第二导电类型半导体层外周的第三栅堆叠。
17.根据权利要求15所述的半导体装置，其中，
所述第一竖直型半导体器件的第二源/漏区以及所述第二竖直型半导体器件的第一源/漏区为重掺杂，
所述第二导电类型半导体层、所述第一导电类型半导体层和所述另一第二导电类型半导体层为轻掺杂。
18.根据权利要求1至4中任一项所述的半导体装置，其中，
所述第一竖直型半导体器件的第二源/漏区为第一导电类型，所述第二竖直型半导体器件的第一源/漏区为第一导电类型，
所述半导体装置还包括设置在所述第一竖直型半导体器件的第二源/漏区与所述第二竖直型半导体器件的第一源/漏区之间的第一导电类型半导体层、第二导电类型半导体层和另一第一导电类型半导体层，
其中，所述隔离结构包括：所述第一导电类型半导体层、所述第二导电类型半导体层和所述另一第一导电类型半导体层构成的pnp结和npn结之一。
19.根据权利要求18所述的半导体装置，还包括：
所述第一竖直型半导体器件的沟道区外周的第一栅堆叠；
所述第二竖直型半导体器件的沟道区外周的第二栅堆叠；以及
所述第一导电类型半导体层、所述第二导电类型半导体层和所述另一第一导电类型半导体层外周的第三栅堆叠。
20.根据权利要求18所述的半导体装置，其中，
所述第一竖直型半导体器件的第二源/漏区以及所述第二竖直型半导体器件的第一源/漏区为重掺杂，
所述第一导电类型半导体层、所述第二导电类型半导体层和所述另一第一导电类型半导体层为轻掺杂。
21.一种电子设备，包括如权利要求1至20中任一项所述的半导体装置。
22.根据权利要求21所述的电子设备，其中，所述电子设备包括智能电话、个人计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
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