WO2022252855A1 - 半导体装置及其制造方法及包括其的电子设备 - Google Patents

半导体装置及其制造方法及包括其的电子设备 Download PDF

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WO2022252855A1
WO2022252855A1 PCT/CN2022/087854 CN2022087854W WO2022252855A1 WO 2022252855 A1 WO2022252855 A1 WO 2022252855A1 CN 2022087854 W CN2022087854 W CN 2022087854W WO 2022252855 A1 WO2022252855 A1 WO 2022252855A1
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layer
semiconductor device
source
drain layer
drain
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PCT/CN2022/087854
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English (en)
French (fr)
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朱慧珑
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中国科学院微电子研究所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

Definitions

  • the present disclosure relates to the field of semiconductors, and in particular, to a semiconductor device vertically stacked with devices of different widths, a method of manufacturing the same, and electronic equipment including such a semiconductor device.
  • a horizontal type device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the source, gate and drain are arranged in a direction substantially parallel to the surface of the substrate. Due to this arrangement, the horizontal type device cannot be easily further scaled down.
  • the source, gate, and drain are arranged in a direction substantially perpendicular to the substrate surface. Therefore, vertical devices are easier to scale down than horizontal devices. For vertical devices, integration density can be increased by stacking them on top of each other.
  • a semiconductor device including: a substrate; a first semiconductor device and a second semiconductor device stacked on the substrate in a vertical direction, the first semiconductor device and the second semiconductor device Each includes a first source/drain layer, a channel layer, and a second source/drain layer stacked in sequence in a vertical direction, and a gate stack surrounding the periphery of the channel layer.
  • One end of the first source/drain layer, the second source/drain layer and the gate stack of the first semiconductor device in the first direction is relative to the first source/drain layer, the second source/drain layer and the gate of the second semiconductor device.
  • Respective one ends of the stack in the first direction protrude in the first direction to form a first step
  • the second semiconductor device defines a second step.
  • One end of the first source/drain layer of each of the first semiconductor device and the second semiconductor device in a second direction intersecting the first direction is relative to a corresponding end of the second source/drain layer and gate stack in the second direction protruding in the second direction, thereby respectively forming a first sub-step and a second sub-step, wherein the first sub-step is on the first step, and the second sub-step is on the second step.
  • the gate stack is opposite to the one end in the second direction with respect to the other end of the second source/drain layer opposite to the one end in the second direction The other end protrudes in the second direction.
  • a method of manufacturing a semiconductor device including: providing a stack including n device layers on a substrate, each device layer including a first source/drain layer, a trench layer stacked in sequence, The channel defining layer and the second source/drain layer, wherein, n is an integer greater than or equal to 2; a stepped structure is formed on one side of the stack in the first direction: the device layer of the lower layer forms a step relative to the device layer of the upper layer; On the opposite sides in one direction, the channel defining layer in each device layer is recessed in the first direction relative to the first source/drain layer and the second source/drain layer, and in the first gap thus obtained forming a first sacrificial gate; on one side of stacking in a second direction intersecting with the first direction, making the channel defining layer in each device layer relative to the first source/drain layer and the second source/drain layer in Recessing in the second direction to obtain a second void; forming a stack including n device layers on a substrate, each
  • an electronic device including the above-mentioned semiconductor device.
  • devices with different widths can be vertically stacked, and the components of the lower device that need to be electrically connected, such as source/drain regions and gate stacks, can protrude relative to the upper device to facilitate electrical connection.
  • a large integration density can be realized.
  • FIG. 1 to 32(d) show schematic diagrams of some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure
  • Fig. 12(a), 16(a), 24(a), 26(a), 27(a), 28, 32(a) are top views, and Fig. 12(a) shows AA' line, BB' line, CC' line and DD' line position,
  • Figures 1 to 11, 12(b), 14(a), 15(a), 16(b), 23, 24(b), 25(a), 26(b), 27(b), 29(a ), 30(a), 31(a), 32(b) are cross-sectional views along line AA',
  • Fig. 12 (c), 13, 14 (b), 15 (b) are sectional views along BB' line
  • Figures 15(c), 16(c), 17 to 21, 22(a), 24(c), 25(b), 26(c), 27(c), 29(b), 30(b), 31(b), 32(c) are cross-sectional views along line CC',
  • 22(b), 24(d), 25(c), 26(d), 27(d), 29(c), 31(c), and 32(d) are cross-sectional views along line DD'.
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on” another layer/element in one orientation, the layer/element can be located “below” the other layer/element when the orientation is reversed.
  • a semiconductor device including vertical type semiconductor devices stacked on each other.
  • the vertical semiconductor device includes an active region extending vertically relative to the substrate (for example, approximately perpendicular to the surface of the substrate), for example, it may include a first source/drain layer, a channel layer and a second source/drain layer stacked in sequence. leaky layer.
  • Source/drain regions may be (at least partially) formed in the first source/drain layer and the second source/drain layer, and a channel region may be formed in the channel layer.
  • a conductive channel can be formed through the channel region between the source/drain regions located at both ends of the channel region.
  • a gate stack may be formed around the periphery of the channel layer.
  • the layers may be adjacent to each other, and of course there may be other semiconductor layers in between, such as leakage suppression layers and/or on-state current enhancement layers (semiconductor layers with larger or smaller band gaps than adjacent layers). These layers can be formed by epitaxial growth and can be single crystal.
  • the components of the lower device that need to be electrically connected can protrude laterally relative to the upper device, so that the corresponding contact part.
  • one end of the first source/drain layer, the second source/drain layer and the gate stack of the device below in the first direction may be opposite to the first source/drain layer, the second source/drain layer of the device above
  • the corresponding one end of the gate stack in the first direction protrudes in the first direction, and the protruding part forms a step to each contact part of the first source/drain layer, the second source/drain layer and the gate stack of the device below It can be set on this step.
  • the topmost device itself can also be considered a "step".
  • the lower first source/drain layer can protrude laterally relative to the upper second source/drain layer and gate stack, and the lower gate stack can protrude relative to the upper second source/drain layer.
  • the drain layer protrudes laterally in order to produce the corresponding contacts.
  • one end of the first source/drain layer of the same device in the second direction intersecting (eg, perpendicular) to the first direction may be stacked with respect to the corresponding one end of the second source/drain layer and gate in the second direction.
  • the protruding portion forms a sub-step on which a contact to the first source/drain layer can be provided.
  • the other end of the gate stack of the same device in the second direction may protrude in the second direction relative to the other end of the second source/drain layer in the second direction, and the protruding part forms a sub-step to the gate stack
  • the contact portion can be set on the sub-step.
  • various devices may form a stepped structure in the first direction (including various steps), and different layers of each device may form a stepped structure in the second direction (including various sub-steps).
  • Each step may extend in the second direction, and each sub-step may be provided on the step of the corresponding device (more specifically, at opposite ends of each step in the second direction).
  • the steps in the stepped structure in the first direction ensure that at least a part of the parts that need to be electrically connected in each device will not be blocked by the parts that need to be electrically connected in other devices, and the steps in the stepped structure in the second direction
  • the sub-steps ensure that the parts of each device that need to be electrically connected are not blocked by other parts of the device itself that need to be electrically connected.
  • the widths of the devices, especially the channel layers thereof, in the first direction may be different. More specifically, the width of the lower device in the first direction may be greater than the width of the upper device in the first direction, and thus may have a larger driving current and higher performance. As the number of stacked devices increases, the width of the underlying device can also increase, and thus performance can be increased without reducing integration density.
  • the channel layer may have the form of nanosheets extending in the first direction.
  • the width of the channel layer in the first direction can define the gate width
  • the height in the vertical direction can define the gate length
  • the thickness in the second direction can define the thickness of the nanosheet.
  • Such a semiconductor device can be manufactured as follows, for example.
  • a stack comprising two or more device layers may be provided on a substrate.
  • Each device layer can be used to define a corresponding device, for example comprising a first source/drain layer, a channel defining layer and a second source/drain layer stacked in sequence.
  • at least some of the device layers may further include an isolation-defining layer for isolation between devices. The isolation-defining layer can be replaced with an isolation material in a subsequent process.
  • a stepped structure may be formed on one side of the stack in the first direction, so that the lower device layer protrudes relative to the upper device layer in the first direction to form a step.
  • the stepped structure can be formed by photoresist trimming combined with sequential etching.
  • the channel defining layer may be relatively recessed, and a first sacrificial gate may be formed in the gap thus obtained. This facilitates the subsequent formation of a Gate-All-Around (GAA) configuration.
  • GAA Gate-All-Around
  • the isolation-defining layer may also be relatively recessed. In order to avoid the formation of the first sacrificial gate in such a recess of the isolation-defining layer, a plug may be formed in such a recess first.
  • a second direction intersecting (e.g., perpendicular) to the first direction, on one side (which may be referred to as a "first side") sacrificial gates (positions defining gate stacks) for each device layer may relatively protrude so that To form a sub-step, the first source/drain layer in each device layer on the opposite side (which may be referred to as a "second side”) may protrude relatively to form a sub-step.
  • processing can be performed on the first side and the second side respectively. While one side is being treated, the masking layer can be used to shade the other side.
  • the channel defining layer when processing the first side, can be relatively recessed by selective etching to obtain voids.
  • a channel layer can be formed by, for example, epitaxial growth.
  • the channel layer may be nanosheets extending along the first direction.
  • a second sacrificial gate In the space left after growing the nanosheets in the void, a second sacrificial gate may be formed.
  • the second source/drain layer can be relatively recessed by selective etching, so that each second sacrificial gate can form a sub-step relative to the corresponding second source/drain layer.
  • the first source/drain layer has no etch selectivity relative to the second source/drain layer (the first source/drain layer and the second source/drain layer are usually the same material)
  • the first source/drain layer It can also be relatively recessed.
  • a dielectric may be filled. The dielectric filled in this way can on the one hand define the gate space in the subsequent replacement gate process, and on the other hand prevent the first side from being affected when the second side is processed.
  • the channel-defining layer can be removed by selective etching, and a third sacrificial gate can be formed in the gap thus obtained.
  • the channel layer can be formed by the first sacrificial gate (on opposite sides in the first direction), the second sacrificial gate (on the first side in the second direction), and the third sacrificial gate (on the second side in the second direction). surrounded by the second side).
  • the layer above the first source/drain layer may be removed in a certain region (for example, an end region) of the exposed part (that is, each step) of each device layer by selective etching, so that the first source/drain layer in each device layer
  • the source/drain layers protrude relatively to form sub-steps.
  • etch selectivity is also considered in the selection of materials.
  • the desired etch selectivity may or may not be indicated.
  • 1 to 32( d ) show schematic diagrams of some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure.
  • the substrate 1001 may be various types of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • SOI semiconductor-on-insulator
  • SiGe substrates SiGe substrates
  • a bulk Si substrate such as a Si wafer is taken as an example for description.
  • a first device layer L 1 , a second device layer L 2 and a third device layer L 3 may be formed by, for example, epitaxial growth.
  • the active area of the device can be defined from each device layer L 1 , L 2 , L 3 .
  • the first device layer L 1 may include a first source/drain layer 1005 1 , a channel defining layer 1007 1 and a second source/drain layer 1009 1 .
  • the second device layer L 2 may include the first source/drain layer 1005 2 , the channel defining layer 1007 2 and the second source/drain layer 1009 2
  • the third device layer L 3 may include the first source/drain layer 1005 3 , a channel defining layer 1007 3 and a second source/drain layer 1009 3
  • the device layers L 1 , L 2 , L 3 may respectively include isolation-defining layers 1003 1 , 1003 2 , 1003 3 .
  • These semiconductor layers can be of good crystalline quality and can be of single crystal structure. There may be a clear crystal interface between adjacent semiconductor layers.
  • an isolation-defining layer is provided between every two adjacent device layers.
  • the present disclosure is not limited thereto.
  • some adjacent device layers may be electrically connected to each other, so no isolation defining layer may be provided between them.
  • These semiconductor layers can include various suitable semiconductor materials, for example, elemental semiconductor materials such as IV group element semiconductor materials such as Si or Ge, compound semiconductor materials such as SiGe and other group IV compound semiconductor materials, or InP, GaAs and the like. III-V compound semiconductor materials.
  • elemental semiconductor materials such as IV group element semiconductor materials such as Si or Ge
  • compound semiconductor materials such as SiGe and other group IV compound semiconductor materials
  • InP GaAs and the like.
  • III-V compound semiconductor materials III-V compound semiconductor materials.
  • the material of the semiconductor layer can be selected based on the properties of the substrate, the device performance to be achieved, and the like.
  • each semiconductor layer formed on the Si wafer may be a Si-based material.
  • each source/drain layer may include Si
  • each channel-defining layer and isolation-defining layer may include SiGe (eg, Ge may have an atomic percentage of about 10 to 30%, preferably about 15%).
  • the semiconductor layer in each device layer can be suitably doped according to the conductivity type of the device to be formed.
  • the first source/drain layer and the second source/drain layer may be heavily doped (for example, with a doping concentration of about 1E18 to 1E21 cm ⁇ 3 ) to the same conductivity type as that of the device to be realized, and the trench
  • the track-defining layer may be unintentionally doped, or lightly doped, eg, to a conductivity type opposite to that of the device to be realized to adjust the device threshold voltage.
  • the first source/drain layer and the second source/drain layer in the same device layer may be doped to opposite conductivity types.
  • Doping of the semiconductor layer can be achieved by in-situ doping during epitaxial growth, or by other doping methods such as ion implantation. There may be a dopant concentration interface between adjacent semiconductor layers.
  • Each semiconductor layer may have an appropriate (in the vertical direction) thickness.
  • the first and second source/drain layers may each have a thickness of about 20 to 50 nm
  • the isolation defining layer may have a thickness of about 10 to 20 nm
  • the channel defining layer may have a thickness of about 15 to 100 nm.
  • the thickness of each channel defining layer may be greater than the thickness of each isolation defining layer.
  • at least some of the device layers may have different dimensions to achieve different electrical characteristics.
  • the thickness of the channel-defining layers in at least some of the device layers can be different (to achieve different gate lengths).
  • the thickness of the source/drain layers in at least some of the device layers may also vary.
  • the thickness of the source/drain layer in the upper device layer can be smaller than the thickness of the source/drain layer in the lower device layer, so that the subsequently formed device in the lower device layer can have a smaller resistance or a larger conduction current.
  • a hard mask layer 1011 may be formed to assist patterning.
  • the hard mask layer 1011 may include nitride (eg, silicon nitride) with a thickness of about 50 to 200 nm.
  • FIG. 1 three device layers L 1 , L 2 and L 3 are shown, and a three-layer device may then be formed.
  • the present disclosure is not limited thereto. More or fewer device layers may be provided, and devices of corresponding levels may be formed.
  • the active region of the device can be patterned from the semiconductor layer described above.
  • first direction for example, a horizontal direction within the paper in FIG. 1
  • second direction for example, a direction perpendicular to the paper in FIG. 1
  • isolations such as shallow trench isolations (STIs)
  • a stepped structure may be formed in the active region.
  • the active region of the lower device layer may protrude laterally relative to the active region of the upper device layer, thereby forming a step.
  • photoresist trimming combined with sequential etching can be used to pattern the stepped structure.
  • each of the device layers L 1 , L 2 , and L 3 can be regarded as a "one layer", so that between the first device layer L 1 and the second device layer L 2 , and the second device layer L Steps are respectively formed between 2 and the third device layer L3 .
  • a stepped structure may be formed only on one or more sides of the active region, but not on other one or more sides of the active region (that is, on the other one or more sides, different devices
  • the active regions in the layers can be substantially aligned in the vertical direction) in order to save area.
  • a pad layer 1013 may be formed on the hard mask layer 1011. During subsequent trimming of the photoresist, pad layer 1013 may remain substantially unaffected, and thus keep the edges of the active region defined thereby substantially aligned in the vertical direction (ie, without forming a stepped structure).
  • the pad layer 1013 may include a material having etch selectivity with respect to the hard mask layer 1011 , such as oxide (eg, silicon oxide).
  • the pad layer 1013 can be patterned to be separated from each other in the first direction, and respectively have linear patterns extending along the second direction (only two of them are shown in the figure, as an example), so as to respectively (in combination with the following photoresist ) define the active regions of individual devices in each device layer.
  • the sum of the height H in the vertical direction and the width W in the first direction of each pattern of the pad layer 1013 may be greater than the width W 1 and the width W 1 of individual devices to be defined in the first device layer L 1 as the lowermost device layer.
  • W n-1 of the individual devices to be defined in the second device layer from top to bottom that is, (H+W)>(W 1 -W n-1 ), where n represents the substrate
  • W n-1 represents the (n-1)th device layer L n-1 (note: in this paper, for the device layer and its related features such as width, etc., will be from bottom to top number, as shown) will define the width of the individual devices.
  • n 3, thus (H+W)>(W 1 ⁇ W 2 ). This relationship can ensure that when the photoresist is subsequently trimmed, the photoresist can remain in contact with the pad layer 1013 without being separated from each other before being completely removed.
  • a photoresist 1015 may be further formed on the hard mask layer 1011 .
  • the photoresist 1015 may be patterned to be separated from each other in the first direction, respectively to be in the shape of a line extending along the second direction and to overlap the corresponding pattern of the pad layer 1013 on one side, so as to (in combination with the corresponding pattern in the pad layer 1013 ) define the active regions of individual devices in each device layer.
  • the width of the pattern of the photoresist 1015 and the corresponding pattern of the pad layer 1013 in the lateral direction here, the first direction
  • the thickness of the photoresist 1015 in the vertical direction may be greater than (H+W), so as to ensure that when the photoresist is subsequently trimmed, the photoresist can remain in contact with the pad layer 1013 before being completely removed, without being separated from each other.
  • the pad layer 1013 and the photoresist 1015 can be used as an etching mask to etch the device layer, such as reactive ion etching (RIE).
  • RIE reactive ion etching
  • the etch recipe can be substantially non-selective to each of the device layers (eg, Si and SiGe).
  • the etching depth can be controlled to be the sum of the thickness D 1 of the first device layer L 1 and the depth D STI of the STI to be formed, ie, D 1 +D STI .
  • D STI may be about 50 to 200 nm.
  • the photoresist 1015 may be trimmed such that the trimmed photoresist 1015 ′ in combination with the pad layer 1013 can define active regions of individual devices in the second device layer L 2 .
  • the pattern of the photoresist 1015' and the width of the corresponding pattern of the stack 1013 in the lateral direction (here, the first direction) may correspond to the width of the second device layer Width W 2 of individual devices in L 2 . That is, the photoresist 1015 needs to be trimmed by (W 1 ⁇ W 2 ).
  • the pad layer 1013 and the photoresist 1015 ′ can be used as an etching mask to etch the device layer, such as RIE.
  • the etch recipe can be substantially non-selective to individual ones of the device layers.
  • the etching depth can be controlled to be the thickness D 2 of the second device layer L 2 .
  • the photoresist trimming process described in connection with FIG. 5 and the etching process described in connection with FIG. 6 may be repeated.
  • the photoresist may be further trimmed (in this example, a final trim may remove photoresist 1015').
  • the width W of the pattern of the pad layer 1013 may correspond to the width W 3 of an individual device in the uppermost third device layer L 3 .
  • the pad layer 1013 can be used as an etching mask to etch the device layer, such as RIE.
  • the etch recipe can be substantially non-selective to individual ones of the device layers.
  • the etching depth can be controlled to be the thickness D 3 of the third device layer L 3 .
  • the photoresist that has been trimmed one or more times as described above can be removed, leaving the pad layer 1013, and using the pad layer 1013 as an etching mask, the device layer is etched, and the etching depth can be up to the second Thickness D n of n device layer L n .
  • the stepped structure shown in FIG. 7 is formed.
  • the lower device layer protrudes relative to the upper device layer, thereby forming steps S 1 , S 2 .
  • the top thereof may also be referred to as a step S 3 .
  • the steps S 1 , S 2 , S 3 may be plate-like extending along the second direction.
  • the second/drain layer of the corresponding device layer L 1 , L 2 , L 3 may be exposed.
  • semiconductor layers in the same device layer may be substantially aligned in the vertical direction. In the example of FIG.
  • the steps S 1 , S 2 in the stepped structure are defined by the original top surfaces of the second/drain layers 1009 1 , 1009 2 in the respective device layers L 1 , L 2 , which is ideal Happening.
  • the exposed parts of the second/drain layers 1009 1 , 1009 2 in the device layers L 1 , L 2 may be etched away by a certain thickness.
  • trenches extending in the second direction are formed in the substrate 1001, which can then be used to form STIs.
  • the orientation of the stepped structure is not limited to that shown in FIG. 7 .
  • the ladder structure can have different orientations.
  • the ladder structures of devices adjacent to each other in the first direction may face opposite directions.
  • the situation shown in FIG. 7 is taken as an example for description.
  • the orientation shown in Figure 7 has the advantage of a larger processing space, especially at the top.
  • sacrificial gates may be formed on opposite sides of the channel defining layers 1007 1 , 1007 2 , 1007 3 in the first direction.
  • the channel defining layers 1007 1 , 1007 2 , and 1007 3 (in this example, SiGe) in each device layer may be relatively recessed in the first direction by selective etching. , to provide space for the formation of the sacrificial grid.
  • the isolation-defining layers 1003 1 , 1003 2 , 1003 3 are also relatively recessed in the first direction to approximately the same extent.
  • the etch depth of the channel-defining layers 1007 1 , 1007 2 , 1007 3 and the isolation-defining layers 1003 1 , 1003 2 , 1003 3 may be about 2 to 10 nm.
  • the etch depth in each device layer may be substantially the same.
  • atomic layer etching ALE can be used.
  • a plug 1017 is formed in the opposite recess.
  • the plug 1017 may include a material having etch selectivity with respect to the hard mask layer 1011 and the pad layer 1013 , such as SiC. Since the thickness of each channel-defining layer is greater than that of each isolation-defining layer as described above, the plug 1017 may not be formed in the relative recesses of the channel-defining layers 1007 1 , 1007 2 , 1007 3 .
  • SiC may be deposited with a thickness greater than the maximum thickness in each isolation-defining layer but less than half of the minimum thickness in each channel-defining layer. Then, the deposited SiC can completely fill up the relative recesses of the isolation-defining layers 1003 1 , 1003 2 , 1003 3 .
  • the deposited SiC can be etched back to a certain thickness (e.g., slightly greater than the deposited thickness), so that the SiC can be left in the opposite recesses of the isolation-defining layers 1003 1 , 1003 2 , 1003 3 to form plugs 1017 , and from the channel
  • the relative recesses defining the layers 1007 1 , 1007 2 , 1007 3 are removed.
  • the formation of the plug 1017 can be omitted.
  • sacrificial gates 1019 may be formed in the opposite recesses of the channel defining layers 1007 1 , 1007 2 , 1007 3 .
  • the first sacrificial gate 1019 may include a material having etch selectivity with respect to the plug 1017 , such as nitride.
  • nitride may be deposited, and vertical RIE may be performed on the deposited nitride to form the first sacrificial gate 1019 .
  • a dielectric such as an oxide may be deposited and planarized such as chemical mechanical polishing (CMP) (which may stop at the hard mask layer 1011 ) to form the isolation material 1021 .
  • CMP chemical mechanical polishing
  • the isolation material can fill the gaps in the device layer caused by the above-mentioned processing, so as to facilitate the subsequent processing.
  • each device layer is separated in the first direction, but still extends continuously in the second direction.
  • the device layers can be separated in a second direction.
  • a photoresist 1023 may be formed on the isolation material 1021 and patterned into patterns separated in the second direction, such as stripes extending in the first direction. These strips extending along the first direction define active regions of individual devices where they intersect with previously formed device layers extending along the second direction.
  • Isolation may be formed in exposed regions of the photoresist 1023 between these stripe patterns. Specifically, the active layer in these regions can be removed and filled with a dielectric.
  • the line AA' extends along the first direction, and the cross-section (perpendicular to the substrate surface) indicated by it passes through the active region (especially through the subsequently formed channel layer 1033 used as a trench part of the track);
  • the BB' line extends along the first direction, and the section indicated (perpendicular to the substrate surface) passes through the subsequently formed STI;
  • the CC' line extends along the second direction, and the section indicated (perpendicular to the substrate surface)
  • the section of the substrate surface) passes through the step S3 ;
  • the line DD' extends in the second direction and the section (perpendicular to the substrate surface) indicated by it passes through the step S2 .
  • the hard mask layer 1011 in these regions may be removed by, for example, RIE, to expose the underlying device layer (here, the third device layer L 3 ). Then, the exposed third device layer L 3 may be removed by, for example, RIE.
  • the etching depth can be controlled so that the etching stops near the top surface of the second source/drain layer 1009 2 of the second device layer L 2 .
  • the part of the second source/drain layer 1009 2 of the second device layer L2 originally covered by the third device layer L3 can be exposed due to the removal of the third device layer L3 , and the other part (ie, the step S2 ) is then Covered by isolation material 1021.
  • the isolation material 1021 can be reduced to a certain thickness by, for example, RIE.
  • the top surface of the reduced-thickness isolation material 1021 may be near the top surface of the second source/drain layer 10092 of the second device layer, thereby being able to expose substantially the entire first part of the second device layer L2 including the step S2 .
  • Two source/drain layers 1009 2 are two source/drain layers 1009 2 .
  • this process can be repeated by removing approximately one device layer and reducing the isolation material 1021 to substantially the same thickness as the device layer (so that the next device layer can be substantially fully exposed), until the depth of the STI to be formed is reached. Afterwards, the photoresist 1023 may be removed. Thus, each device layer is separated into active regions of individual devices. In the gaps between these active areas, a dielectric can be filled by eg deposition followed by planarization like CMP (possibly stopping at the hard mask layer 1011). The dielectric filled here may comprise the same dielectric as oxide as the previous isolation material 1021, and thus they are shown integrally as isolation material 1021'.
  • the isolation material 1021 ′ can be etched back by dry etching such as RIE or wet etching.
  • the etch back isolation material may form an STI 1025 having a thickness of about D STI .
  • the top surface of the STI 1025 is shown flush with the top surface of the substrate 1001 for the convenience of illustration only.
  • the top surface of the STI 1025 may be (slightly) lower or (slightly) higher than the top surface of the substrate 1001 .
  • each device layer is separated in the second direction into active regions of individual devices.
  • the active regions of individual devices are defined, and a ladder structure is formed in the first direction between the overlapping active regions.
  • a stepped structure may be formed in each device layer.
  • the stepped structure may be formed in the second direction so as not to interfere with the above stepped structure formed in the first direction.
  • a stepped structure can be formed on opposite sides in the second direction.
  • the opposite sides in the second direction may be processed separately.
  • the masking layer can be used to shield the other sides while exposing the side to be processed.
  • the masking layer 1027 may be formed in a substantially conformal manner by, for example, deposition.
  • the masking layer 1027 may include a material having etch selectivity with respect to the hard mask layer 1011, the first sacrificial gate 1019, and the STI 1025, such as SiC.
  • a photoresist 1029 may be formed on the masking layer 1027 (in FIG. The source region is on one side in the second direction. In the illustrated embodiment, the photoresist 1029 exposes a region between every two adjacent active regions in the second direction.
  • the masking layer 1027 can be etched such as RIE by using the photoresist 1029 as an etching mask, so that one side of each active region in the second direction is exposed. Afterwards, photoresist 1029 may be removed. Note that in FIG. 16( a ), the shielding layer 1027 is not shown for the convenience of readers to understand the relationship between the photoresist and the active region.
  • opposite sides upper side and lower side in FIG. 16( a )
  • the shielding layer may expose the same side of each active region in the second direction.
  • the isolation-defining layers 1003 1 , 1003 1 , 1003 2 , 1003 3 are relatively recessed in the second direction, and plugs 1031 are formed in the recesses thus obtained.
  • the plug 1031 may include a material having etch selectivity with respect to the hard mask layer 1011 and the masking layer 1027 , such as oxide.
  • each channel defining layer 1007 1 , 1007 can be made 2 , 1007 and 3 are further recessed to define the grid space. Due to the presence of the plug 1031 , the isolation-defining layers 1003 1 , 1003 2 , 1003 3 may not be affected.
  • each trench The degree of recessing of the lane-defining layers 1007 1 , 1007 2 , 1007 3 may be approximately the same, and the sidewalls after the recessing may remain substantially aligned in the vertical direction and may remain substantially coplanar.
  • an etching recipe capable of acting on both the channel-defining layer and the source/drain layer can also be used, such as through ALE, to further refine the channel-defining layer and the source/drain layer. Etch a certain depth T. This helps achieve consistent gate lengths.
  • the channel layer 1033 can be formed by, for example, epitaxial growth.
  • the channel layer 1033 may include a semiconductor material such as Si that has etch selectivity with respect to the channel defining layer.
  • the growth of the channel layer 1033 is controlled to have a thickness approximately equal to T. In this way, on the opposite sides of the channel layer 1033 in the second direction (the left and right sides of the paper in FIG. thickness of).
  • the channel layer 1033 may be formed in the form of nanosheets.
  • Epitaxial growth can also occur on other semiconductor surfaces.
  • the epitaxially grown channel layer can be etched, for example by RIE in the vertical direction, so that it can remain under the hard mask layer 1011, while the gaps between the active regions can still remain for further use. Processing channel for processing.
  • a sacrificial gate 1035 (which may be referred to as a “second sacrificial gate”) may be formed in the gate space by, for example, deposition followed by vertical RIE.
  • the second sacrificial gate 1035 may include the same material as the first sacrificial gate 1019 such as nitride, so as to be removed simultaneously in a subsequent replacement gate process.
  • FIG. 21 schematically shows a part used as a source/drain (for example, a part extending substantially horizontally) and a part used as a channel (for example, a part extending substantially vertically) in the channel layer 1033 with dotted lines. interface between. Such interfaces may be defined by doping concentrations. Diffusion of dopants to the upper and lower sides of the channel layer 1033 used as sources/drains may have substantially the same characteristics, so the parts used as channels in the channel layer 1033 may be self-aligned to the corresponding channel definition Floor.
  • each second source/drain layer 1009 1 , 1009 2 , 1009 3 and The part of the channel layer 1033 (here, both are Si) located on the top surface of the second sacrificial gate 1035 is recessed in the second direction (the first source/drain layers 1005 1 , 1005 2 , 1005 3 and the channel layer 1033
  • the portion located on the bottom surface of the second sacrificial gate 1035 can also be recessed in the second direction), and the depth of the recess can be such that the portion used as a channel in the channel layer 1033 (here, the vertically extending portion) can be guaranteed integrity.
  • the second sacrificial gate 1035 protrudes relative to the second source/drain layers 1009 1 , 1009 2 , 1009 3 (and the channel layer 1033 ), thereby forming a "sub" step.
  • the second sacrificial gate of each device layer forms sub-steps SS 1 (see FIG. 34 ), SS 2 , SS 3 on the side of the second source/drain layer in the corresponding device layer in the second direction.
  • sub-steps the reason why such protruding parts are called "sub-steps" here is that these sub-steps can be formed on the corresponding steps (as mentioned above, Fig. 22(a) shows the situation at the step S3 , Figure 22(b) shows the situation at the step S2 ).
  • the ends of the isolation defining layers 1003 1 , 1003 2 , 1003 3 and the plug 1031 can be suspended and thus can be removed due to erosion during the etching process .
  • the plug 1031 can be removed first, and then this selective etching is performed.
  • the etch recipe can be chosen to work both on the second source/drain layer 1009 1 , 1009 2 , 1009 3 and the channel layer 1033 as well as the isolation-defining layer 1003 1 , 1003 2 , 1003 3 . Then, the isolation defining layers 1003 1 , 1003 2 , 1003 3 may be recessed together with the second source/drain layers 1009 1 , 1009 2 , 1009 3 and the channel layer 1033 .
  • a dielectric 1037 eg, oxide
  • a dielectric 1037 can be filled by, for example, deposition, planarization (which may stop at masking layer 1027 ) and then etch back. Due to the presence of masking layer 1027, dielectric 1037 is formed thereunder.
  • Figure 22(b) shows the situation at the step S2 between the second device layer L2 and the third device layer L3 , and the step S1 between the first device layer L1 and the second device layer L2 The same is true here. That is, the dielectric 1037 also forms a ladder structure together with each device layer. That is, the gate space defined by the dielectric 1037 can maintain the previously formed stepped structure.
  • the processing on one side of each active region in the second direction is realized. Thereafter, the other side of each active region in the second direction may be processed.
  • a photoresist 1039 can be formed on the shielding layer 1027, and it can be patterned to expose the other side of each active region in the second direction (see FIG. 24(a), so
  • the "other side” is the side where each active region is shielded by the shielding layer 1027 in the second direction as shown in FIG. 16(a)).
  • the dielectric 1037 and the second sacrificial gate 1035 there is no need to form a separate shielding layer.
  • the photoresist 1039 can be patterned to expose (at least partly) each step and shield the vertical sidewalls of each device layer.
  • 24(a) to 24(d) show the structure after etching, such as RIE, of the masking layer 1027 using the photoresist 1039 as an etching mask. Afterwards, the photoresist 1039 may be removed.
  • a cross section taken on the line AA' passes through the channel layer 1033, so in the cross-sectional view shown in FIG. 23 , the channel layer 1033 exists.
  • the dotted line schematically shows the interface between the portion of the channel layer 1033 used as a source/drain and the portion used as a channel.
  • the width of the portion of the channel layer 1033 used as a channel may define a gate width. Therefore, the width of the first sacrificial gate 1019 in the first direction may be relatively small so as not to reduce the gate width.
  • the height of the portion of the channel layer 1033 serving as a channel may define a gate length, and may be substantially equal to the thickness of the channel defining layer in the vertical direction.
  • the channel layer 1033 may be in the form of nanosheets such that the dimension in the second direction may be (much) smaller than the width in the first direction and the height in the vertical direction.
  • the plug 1041 may be formed as described above in connection with FIGS. 16( a ) to 16( c ).
  • the plug 1041 may include a material having etch selectivity with respect to the second sacrificial gate 1035 and the dielectric 1037 , such as SiC.
  • a thin etch stop layer such as oxide may first be formed, for example by deposition. This helps to avoid affecting the masking layer 1027', which is also SiC here, when the plug 1041 is formed.
  • the channel-defining layers 1007 1 , 1007 2 , 1007 3 can be removed by selective etching (due to the existence of the plug 1041, the removal of the isolation-defining layers 1003 1 , 1003 2 , 1003 3 can be avoided here), and in In the gate space left by the removal of the channel defining layers 1007 1 , 1007 2 , 1007 3 , a sacrificial gate 1043 (may be referred to as a “third sacrificial gate”) is formed by, for example, deposition followed by vertical RIE.
  • the third sacrificial gate 1043 may include the same material (here, nitride) as the first sacrificial gate 1019 and the second sacrificial gate 1035 so as to be removed together later.
  • nitride the same material
  • the portion of the hard mask layer 1011 which is also a nitride here which is not shielded by the masking layer 1027 ′ can also be removed.
  • the first sacrificial gate 1019 is located on opposite sides of the channel layer 1033 (specifically, the part used as a channel) in the first direction, and the third sacrificial gate 1043 and the sacrificial gate 1035 are respectively located on the channel layer 1033 (specifically, the part used as the channel). ground, which serves as part of the channel) on opposite sides in the second direction. That is, each sacrificial gate surrounds the outer circumference of the channel layer 1033 (particularly, a portion serving as a channel). In addition, as mentioned above, each sacrificial gate may have approximately the same gate length, approximately equal to the thickness of the channel defining layer in the vertical direction.
  • the isolation defining layer may be replaced by an isolation material to achieve electrical isolation between vertically adjacent devices.
  • the plug 1041 can be removed by selective etching to expose the isolation-defining layers 1003 1 , 1003 2 , 1003 3 .
  • the isolation-defining layers 1003 1 , 1003 2 , 1003 3 can be removed by selective etching.
  • an isolation layer 1045 can be formed, for example by deposition and then etch back, so as to achieve electrical isolation.
  • the isolation layer 1045 may comprise a dielectric material, such as SiC, having etch selectivity with respect to the sacrificial gates 1019, 1035, 1043 (here, nitride) and the dielectric 1037 (here, oxide).
  • the second source/drain layers 1009 1 , 1009 2 , 1009 3 of each device layer can have exposed surfaces, so as to make contacts to them later. .
  • the first source/drain layer 1005 1 , 1005 2 , 1005 3 of each device layer may also be exposed, so as to subsequently make contacts thereto.
  • a photoresist 1047 may be formed (in Figure 26(a), to aid understanding, the photoresist 1047 is shown partially transparent to reveal the underlying structure ), and patterned to mask a portion of each step S 1 , S 2 , S 3 and expose the rest of each step S 1 , S 2 , S 3 . That is, each step S 1 , S 2 , S 3 may be divided into two parts based on the photoresist 1047 (the two parts may have substantially the same area).
  • the photoresist 1047 can be patterned into strips extending along the first direction, so each step S 1 , S 2 , S 3 can be divided into two parts that are side by side in the second direction, and the third A portion of the side where the sacrificial gate 1043 is located is exposed.
  • the photoresist 1047 can be used as an etching mask to sequentially selectively etch the corresponding second source/drain layer and the sacrificial gate at the steps S 1 , S 2 , and S 3 by selective etching such as RIE. Therefore, in each device layer, at each step S 1 , S 2 , S 3 , the first source/drain layer protrudes relative to the second source/drain layer and the sacrificial gate, thereby forming sub-steps SS 4 , SS 5 , SS 6 . Afterwards, photoresist 1047 may be removed.
  • active regions including the first source/drain layer, the second source/drain layer and the channel layer therebetween
  • sacrificial gates surrounding the channel layer
  • the exposed first source/drain layer and second source/drain layer at each step S 1 , S 2 , S 3 can be silicided processed to form silicide 1049 .
  • a metal such as Ni or NiPt may be deposited and annealed at a temperature of about 300 to 700° C. so that the deposited metal reacts with the semiconductor elements in the first source/drain layer and the second source/drain layer, thereby Generate metal-semiconductor compounds such as NiSi or NiPtSi. Afterwards, unreacted residual metals can be removed.
  • the level of the portion of the masking layer 1027' exposed by the photoresist 1047 may be removed first by, for example, RIE in the vertical direction.
  • Extended portion to increase the area of each sub-step SS 4 , SS 5 , SS 6 (thus facilitating subsequent contacts thereto), while maintaining the vertical extension of the exposed portion of the shielding layer 1027′ (as a sidewall) to protect the side walls.
  • a structure as shown in Fig. 28 can be obtained.
  • a replacement gate process may be performed.
  • the masking layer 1027 ′ and the sacrificial gates 1019 , 1035 , and 1043 can be removed by selective etching.
  • a gate stack may be formed, eg by deposition followed by vertical RIE.
  • the gate stack may include a gate dielectric layer 1051 and a gate conductor layer 1053 .
  • the gate dielectric layer 1051 may include a high-k dielectric such as HfO 2
  • the gate conductor layer 1053 may include metal.
  • the gate stack may surround the periphery of the channel layer 1033 (in particular, the portion serving as the channel), thereby forming an all-around gate structure.
  • a shielding layer 1055 such as SiC may be formed to shield the area with less overlap (one side in the second direction) and expose the area with greater overlap ( the other side in the second direction).
  • the gate stack can be recessed to a certain depth (thus reducing the overlap with the source/drain) by selective etching.
  • a dielectric material such as nitride (see 1057 in Fig. 30(b)) may be filled by, for example, deposition followed by RIE in the vertical direction. Afterwards, the shielding layer 1055 may be removed.
  • gate stacks ( 1051 / 1053 ) of the same configuration are formed for each device layer.
  • the present disclosure is not limited thereto.
  • gate stacks of different configurations eg, with different work functions
  • the first gate stack (1051/1053) for the first device layer L1 after the first gate stack (1051/1053) for the first device layer L1 is formed as described above, it can be deposited and then etched back, for example, in An interlayer dielectric layer 1059 (eg, oxide) is formed to a certain height on the substrate 1001 .
  • the height of the interlayer dielectric layer 1059 is such that the first gate stack (1051/1053) formed in the first device layer L1 can be shielded, while the first gate stack (1051/1053) formed in the second device layer L2 and the third device layer L3 is exposed.
  • the exposed gate conductor layer 1053 in the first gate stack can be removed by selective etching.
  • the second gate stack has the same gate dielectric layer as the first gate stack.
  • the present disclosure is not limited thereto.
  • the gate dielectric layer 1051 can be removed, and another gate dielectric layer can be formed.
  • a third gate stack different from the second gate stack is to be formed for the third device layer L 3 (it may be the same as the first gate stack, of course it may also be different from the first stack), similar processing may be performed.
  • the top surface of the interlayer dielectric 1059 can be raised by deposition followed by etch back to shield the first gate stack (1051/1053) formed in the first device layer L1 and the first gate stack (1051/1053) formed in the second device layer L2
  • the second gate stack (1051/1061) is exposed, and the second gate stack formed in the third device layer L3 is exposed.
  • the exposed gate conductor layer 1061 in the second gate stack can be removed by selective etching.
  • part of the gate space in the third device layer L 3 is released. In the released gate space, a gate conductor layer may be formed.
  • Figures 31(a) and 31(b) show the structure after forming the respective gate stacks for all device layers.
  • An interlayer dielectric layer 1059' may be formed covering all device layers by deposition followed by planarization.
  • the contact portions 1063 1 , 1063 to the corresponding device layers L 1 , L 2 , L 3 are fabricated. 2 , 1063 3 .
  • the contact portion may be formed by etching a contact hole in the interlayer dielectric layer 1059' and filling the hole with a conductive material such as metal.
  • a diffusion barrier layer may be formed first.
  • the contact 10633 may include a contact 10633-1 to the first source/drain layer in the third device layer L3 (at the sub-step SS 6 ), a contact 1063 3 -2 to the second source/drain layer, and a contact 1063 3 -3 (on the sub-step SS 3 ) to the gate stack (in particular, the gate conductor layer therein).
  • the contact 10633-1 to the first source/drain layer in the third device layer L3 (at the sub-step SS 6 )
  • a contact 1063 3 -2 to the second source/drain layer
  • a contact 1063 3 -3 on the sub-step SS 3
  • the contact portions 1063 3 -1 , 1063 3 -2 , and 1063 3 -3 on the step S 3 may be arranged substantially in a straight line along the second direction.
  • the contact 10632 may include a contact 10632-1 to the first source/drain layer in the second device layer L1 (at the sub-step SS 5 ), a contact 1063 2 -2 to the second source/drain layer and a contact 1063 2 -3 (on the sub-step SS 2 ) to the gate stack (in particular, the gate conductor layer therein).
  • the gate stack in particular, the gate conductor layer therein.
  • the contact portions 1063 2 -1 , 1063 2 -2 , and 1063 2 -3 on the step S 2 may be arranged substantially in a straight line along the second direction. The same is true on step S1 , although it is not shown here.
  • the contact portions on each step are arranged in a straight line.
  • the present disclosure is not limited thereto.
  • the contact portions on each step may be arranged in a zigzag shape in the second direction. In this way, area can be saved while the pitch between the contacts remains the same (the size of the device in the second direction can be reduced while keeping the width of the device in the first direction constant).
  • a semiconductor device may include two or more device layers L 1 , L 2 , L 3 stacked in the vertical direction (z direction), and each device layer may be The corresponding devices are defined in the layers.
  • Each device layer may include a first source/drain layer, a channel layer, and a second source/drain layer stacked in a vertical direction (z direction).
  • the channel layer may be a nanosheet extending in a first direction (x direction) with a thickness direction in a second direction (y direction) intersecting (eg, perpendicular to) the first direction.
  • the width of the channel layer in the first direction (x direction) may define the gate width, and the height in the vertical direction (z direction) may define the gate length.
  • the width of the channel layer in the lower device layer may be greater than the width of the channel layer in the upper device layer.
  • the gate stack can be on the periphery of the channel layer, forming a GAA configuration. In FIG. 34 , gate stacks G 1 , G 2 , G 3 are shown for respective device layers L 1 , L 2 , L 3 .
  • the gate stack G1 may include the gate dielectric layer 1051 and the gate conductor layer 1053
  • the gate stack G2 may include the gate dielectric layer 1051 and the gate conductor layer 1061
  • the gate stack G3 may include the gate dielectric layer 1051 and the gate conductor layer 1053.
  • conductor layer 1053 may include an isolation layer 1045 disposed between adjacent device layers. Note that an isolation layer is not necessarily required between every two adjacent device layers.
  • the lower device layer may protrude in a first direction (x direction) relative to the upper device layer, thereby forming a stepped structure.
  • the first device layer L 1 can protrude in the first direction relative to the second device layer L 2 to form a step S 1 ;
  • the second device layer L 2 can extend in the first direction relative to the third device layer L 3 protruding to form a step S 2 ;
  • the third device layer L 3 may form a step S 3 . Note that it is not necessary to form a step between every two adjacent device layers.
  • sub-steps may be formed on the respective steps S 1 , S 2 , and S 3 .
  • the sub-steps may be formed at opposite ends of the corresponding steps in the second direction (y direction).
  • the gate stack G 1 can be opposite to the second source/drain layer 1009 1 (and the first source/drain layer 1005 1 ) of the first device layer L 1 , which can be in the second direction This side of the can be substantially aligned in the vertical direction) protruding in the second direction to form a sub-step SS 1 ; the first source/drain layer 1005 1 of the first device layer L 1 can be relative to the second source/drain layer 1005 1
  • the drain layer 1009 1 and the gate stack G 1 (here, the gate stack G 1 is recessed in the second direction relative to the second source/drain layer 1009 1 to reduce parasitic capacitance, as described above) extend in the second direction.
  • the gate stack G 2 can be opposite to the second source/drain layer 1009 2 (and the first source/drain layer 1005 2 ) of the second device layer L 2 , which can be in the second direction This side on the upper side can be substantially aligned in the vertical direction) protruding in the second direction to form a sub-step SS 2 ; the first source/drain layer 1005 2 of the second device layer L 2 can be relative to the second source The /drain layer 1009 2 and the gate stack G 2 (here, the gate stack G 2 is recessed in the second direction relative to the second source/drain layer 1009 2 to reduce parasitic capacitance, as described above) in the second direction protrudes to form a sub-step SS 5 .
  • the gate stack G 3 can be opposite to the second source/drain layer 1009 3 (and the first source/drain layer 1005 3 ) of the third device layer L 3 , which can be in the second direction This side on the top can be substantially aligned in the vertical direction) protruding in the second direction to form a sub-step SS 3 ; the first source/drain layer 1005 3 of the third device layer L 3 can be opposite to the second source The /drain layer 1009 3 and the gate stack G 3 (here, the gate stack G 3 is recessed in the second direction relative to the second source/drain layer 1009 3 to reduce parasitic capacitance, as described above) in the second direction protrudes to form a sub-step SS 6 .
  • the contacts to the respective device layers L 1 , L 2 , L 3 may be on the respective steps S 1 , S 2 , S 3 .
  • the contacts to the respective gate stacks G 1 , G 2 , G 3 may be on the respective sub-steps SS 1 , SS 2 , SS 3 and the contacts to the first source/drain layers 1005 1 , 1005 2 , 1005 3 may be on the corresponding sub-steps SS 4 , SS 5 , SS 6 .
  • a semiconductor device can be applied to various electronic devices.
  • an integrated circuit IC
  • electronic equipment can be constructed thereby. Therefore, the present disclosure also provides an electronic device including the above semiconductor device.
  • the electronic equipment may also include components such as a display screen coordinated with the integrated circuit and a wireless transceiver coordinated with the integrated circuit.
  • Such electronic devices are, for example, smart phones, personal computers (PCs), tablet computers, artificial intelligence devices, wearable devices, or power banks.
  • SoC system on a chip
  • the method may include the methods described above.
  • a variety of devices can be integrated on a chip, at least some of which are fabricated according to the methods of the present disclosure.

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Abstract

一种半导体装置及其制造方法，以及包括这种半导体装置的电子设备。该半导体装置包括彼此竖直叠置的第一器件和第二器件，第一器件和第二器件各自包括竖直叠置的第一源/漏层（1005 1、1005 2）、沟道层（1007 1、1007 2）和第二源/漏层（1009 1、1009 2）以及围绕沟道层（1007 1、1007 2）外周的栅堆叠（1051/1053）。第一器件相对于第二器件在第一方向上伸出而形成第一台阶（S 1），第二器件限定第二台阶（S 2）。在与第一方向相交的第二方向上的一侧，各器件的第一源/漏层（1005 1、1005 2）相对于第二源/漏层（1009 1、1009 2）和栅堆叠（1051/1053）在第二方向上伸出，从而形成子台阶，各子台阶在相应的台阶上；在第二方向上的另一侧，各器件的栅堆叠（1051/1053）相对于第二源/漏层（1009 1、1009 2）在第二方向上伸出。

Description

半导体装置及其制造方法及包括其的电子设备
相关申请的引用
本申请要求于2021年6月2日递交的题为“半导体装置及其制造方法及包括其的电子设备”的中国专利申请202110616618.0的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，具体地，涉及竖直地叠置有不同宽度的器件的半导体装置及其制造方法以及包括这种半导体装置的电子设备。
背景技术
在水平型器件如金属氧化物半导体场效应晶体管(MOSFET)中，源极、栅极和漏极沿大致平行于衬底表面的方向布置。由于这种布置，水平型器件不易进一步缩小。与此不同，在竖直型器件中，源极、栅极和漏极沿大致垂直于衬底表面的方向布置。因此，相对于水平型器件，竖直型器件更容易缩小。对于竖直型器件，可以通过彼此叠置来增加集成密度。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种竖直地叠置有不同宽度的器件的半导体装置及其制造方法以及包括这种半导体装置的电子设备。
根据本公开的一个方面，提供了一种半导体装置，包括：衬底；在竖直方向上叠置在衬底上的第一半导体器件和第二半导体器件，第一半导体器件和第二半导体器件各自包括在竖直方向上依次叠置的第一源/漏层、沟道层和第二源/漏层以及围绕沟道层的外周的栅堆叠。第一半导体器件的第一源/漏层、第二源/漏层和栅堆叠在第一方向上的一端相对于第二半导体器件的第一源/漏层、第二源/漏层和栅堆叠在第一方向上的相应的一端在第一方向上伸出，从而形成第一台阶，第二半导体器件限定第二台阶。第一半导体器件和第二半导体器件各自的第一源/漏层在与第一方向相交的第二方向上的一端相对于第二源/漏 层和栅堆叠在第二方向上的相应的一端在第二方向上伸出，从而分别形成第一子台阶和第二子台阶，其中，第一子台阶在第一台阶上，第二子台阶在第二台阶上。在第一半导体器件和第二半导体器件中的每一个中，相对于第二源/漏层在第二方向上与所述一端相对的另一端，栅堆叠在第二方向上与所述一端相对的另一端在第二方向上伸出。
根据本公开的另一方面，提供了一种制造半导体装置的方法，包括：在衬底上设置包括n个器件层的堆叠，每个器件层包括依次叠置的第一源/漏层、沟道限定层和第二源/漏层，其中，n是大于或等于2的整数；在堆叠在第一方向的一侧形成阶梯结构：下层的器件层相对于上层的器件层形成台阶；在第一方向上的相对两侧，使各器件层中的沟道限定层相对于第一源/漏层和第二源/漏层在第一方向上凹进，并在由此得到的第一空隙中形成第一牺牲栅；在堆叠在与第一方向相交的第二方向上的一侧，使各器件层中的沟道限定层相对于第一源/漏层和第二源/漏层在第二方向上凹进，并得到第二空隙；在各沟道限定层的凹进的侧壁上形成沟道层；在第二空隙中形成沟道层之后的空间中形成第二牺牲栅；在堆叠在第二方向上的所述一侧，在各器件层中形成阶梯结构：各第二牺牲栅相对于相应器件层中的第二源/漏层形成子台阶；在堆叠在第二方向上与所述一侧相对的另一侧，通过选择性刻蚀，去除沟道限定层，并在由此得到的第三空隙中形成第三牺牲栅；在堆叠在第二方向上的所述另一侧，在各器件层中形成阶梯结构：同一器件层中的第一源/漏层相对于第二源/漏层和沟道限定层形成子台阶，子台阶在相应器件层所形成的台阶上；以及将第一牺牲栅、第二牺牲栅和第三牺牲栅替换为栅堆叠。
根据本公开的另一方面，提供了一种电子设备，包括上述半导体装置。
根据本公开的实施例，可以竖直地叠置具有不同宽度的器件，下方的器件需要电连接的部件，如源/漏区和栅堆叠，可以相对上方的器件伸出，以便于电连接。于是，可以实现大的集成密度。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至32(d)示出了根据本公开实施例的制造半导体装置的流程中部分阶段的示意图；
图33示出了根据本公开另一实施例的半导体装置中接触部的布局的局部俯视图；
图34示出了根据本公开另一实施例的半导体装置的示意透视图，
其中，
图12(a)、16(a)、24(a)、26(a)、27(a)、28、32(a)是俯视图，图12(a)中示出了AA′线、BB′线、CC′线和DD′线的位置，
图1至11、12(b)、14(a)、15(a)、16(b)、23、24(b)、25(a)、26(b)、27(b)、29(a)、30(a)、31(a)、32(b)是沿AA′线的截面图，
图12(c)、13、14(b)、15(b)是沿BB′线的截面图，
图15(c)、16(c)、17至21、22(a)、24(c)、25(b)、26(c)、27(c)、29(b)、30(b)、31(b)、32(c)是沿CC′线的截面图，
图22(b)、24(d)、25(c)、26(d)、27(d)、29(c)、31(c)、32(d)是沿DD′线的截面图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时， 该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，提供了一种包括彼此叠置的竖直型半导体器件的半导体装置。竖直型半导体器件包括相对于衬底竖直(例如，大致垂直于衬底表面)延伸的有源区，例如可以包括依次叠置的第一源/漏层、沟道层和第二源/漏层。源/漏区可以(至少部分地)形成在第一源/漏层和第二源/漏层中，沟道区可以形成在沟道层中。分处于沟道区两端的源/漏区之间可以通过沟道区形成导电通道。栅堆叠可以绕沟道层的外周形成。各层之间可以彼此邻接，当然中间也可能存在其他半导体层，例如泄漏抑制层和/或开态电流增强层(带隙比相邻层大或小的半导体层)。这些层可以通过外延生长形成，并可以是单晶。
对于叠置的器件，处于下方的器件需要电连接的部件(例如，第一源/漏层、第二源/漏层和栅堆叠)可以相对于上方的器件在横向上伸出，以便制作相应的接触部。例如，处于下方的器件的第一源/漏层、第二源/漏层和栅堆叠在第一方向上的一端可以相对于上方的器件的第一源/漏层、第二源/漏层和栅堆叠在第一方向上的相应的一端在第一方向上伸出，伸出部分形成台阶，到下方器件的第一源/漏层、第二源/漏层和栅堆叠的各接触部可以设于该台阶上。最上方的器件自身也可以视为一级“台阶”。
另外，对于同一器件而言，处于下方的第一源/漏层可以相对于上方的第二源/漏层和栅堆叠在横向上伸出，处于下方的栅堆叠可以相对于上方的第二源/漏层在横向上伸出，以便制作相应的接触部。例如，同一器件的第一源/漏层在与第一方向相交(例如，垂直)的第二方向上的一端可以相对于第二源/漏层和栅堆叠在第二方向上的相应的一端在第二方向上伸出，伸出部分形成子台阶，到第一源/漏层的接触部可以设于该子台阶上。另外，同一器件的栅堆叠在第二方向上的另一端可以相对于第二源/漏层在第二方向上的另一端在第二方向上伸出，伸出部分形成子台阶，到栅堆叠的接触部可以设于该子台阶上。
也即，各个器件彼此之间可以形成第一方向上的阶梯结构(包括各个台阶)，各器件自身的不同层之间可以形成第二方向上的阶梯结构(包括各个子台阶)。各个台阶可以在第二方向上延伸，而各个子台阶可以设置于相应器件的台阶上(更具体地，各台阶在第二方向上的相对两端处)。第一方向上的阶梯结构中的各台阶确保了每个器件需要电连接的部件至少有一部分在其上方不会被其 他器件中需要电连接的部件所遮挡，第二方向上的阶梯结构中的各子台阶确保了每个器件需要电连接的部件在其上方不会被该器件自身需要电连接的其他部件所遮挡。
由于这种阶梯结构，各器件特别是其沟道层在第一方向上的宽度(可以限定栅宽)可以不同。更具体地，下方的器件在第一方向上的宽度可以大于上方的器件在第一方向上的宽度，并因此可以具有较大的驱动电流以及较高的性能。随着叠置器件数目的增加，下方器件的宽度也可以增加，并因此性能可以提升，而不会降低集成密度。
沟道层可以具有沿第一方向延伸的纳米片的形式。沟道层在第一方向上的宽度如上所述可以限定栅宽，在竖直方向上的高度可以限定栅长，在第二方向上的厚度可以限定纳米片的厚度。
这种半导体装置例如可以如下制造。
可以在衬底上设置包括两个或更多个器件层的堆叠。每个器件层可以用来限定相应的器件，例如包括依次叠置的第一源/漏层、沟道限定层和第二源/漏层。另外，为了器件之间的隔离，至少一些器件层还可以包括隔离限定层。隔离限定层可以在后继的工艺中被替换为隔离材料。
可以在该堆叠在第一方向上的一侧形成阶梯结构，使得下层的器件层相对于上层的器件层在第一方向上伸出而形成台阶。例如，可以通过光刻胶修整结合逐次刻蚀来形成阶梯结构。
另外，在第一方向上的相对两侧，可以使沟道限定层相对凹进，并在如此得到的空隙形成第一牺牲栅。这有助于随后形成全环绕栅(Gate-All-Around，GAA)配置。在隔离限定层相对于沟道限定层不具备刻蚀选择性或者刻蚀选择性较小的情况下，隔离限定层也可以相对凹进。为避免第一牺牲栅形成在隔离限定层的这种凹进中，可以先在这种凹进中形成插塞。
在与第一方向相交(例如，垂直)的第二方向上，在一侧(可以称作“第一侧”)，针对各器件层的牺牲栅(限定栅堆叠的位置)可以相对伸出从而形成子台阶，在相对的另一侧(可以称作“第二侧”)各器件层中的第一源/漏层可以相对伸出从而形成子台阶。于是，在第二方向上，可以针对第一侧和第二侧分别进行处理。在对其中一侧进行处理时，可以利用遮蔽层来遮蔽另一侧。
例如，在对第一侧进行处理时，可以通过选择性刻蚀，使沟道限定层相对凹进，得到空隙。在该空隙中，可以通过例如外延生长，来形成沟道层。于是，沟道层可以是沿着第一方向延伸的纳米片。在该空隙中生长纳米片之后留下的空间中，可以形成第二牺牲栅。可以通过选择性刻蚀，使第二源/漏层相对凹进，从而各第二牺牲栅可以相对于相应的第二源/漏层形成子台阶。在第一源/漏层相对于第二源/漏层不具备刻蚀选择性的情况下(第一源/漏层和第二源/漏层通常为相同材料)，第一源/漏层也可以相对凹进。在第一源/漏层和第二源/漏层的这种相对凹进中，可以填充电介质。如此填充的电介质一方面可以在后继替代栅工艺中限定栅空间，另一方面可以防止在对第二侧进行处理时影响到第一侧。
在对第二侧进行处理时，可以通过选择性刻蚀，去除沟道限定层，并在由此得到的空隙中形成第三牺牲栅。于是，沟道层可以被第一牺牲栅(在第一方向上的相对两侧)、第二牺牲栅(在第二方向上的第一侧)和第三牺牲栅(在第二方向上的第二侧)所围绕。可以通过选择性刻蚀，在各器件层的暴露部分(即，各个台阶)的一定区域(例如，端部区域)，去除第一源/漏层上方的层，从而在各器件层中第一源/漏层相对伸出而形成子台阶。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离，导电材料用于形成电极、互连结构等)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1至32(d)示出了根据本公开实施例的制造半导体装置的流程中部分阶段的示意图。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底如 Si晶片为例进行描述。
在衬底1001上，可以通过例如外延生长，形成第一器件层L 1、第二器件层L 2和第三器件层L 3。可以从各器件层L 1、L 2、L 3来限定器件的有源区。例如，第一器件层L 1可以包括第一源/漏层1005 1、沟道限定层1007 1和第二源/漏层1009 1。类似地，第二器件层L 2可以包括第一源/漏层1005 2、沟道限定层1007 2和第二源/漏层1009 2，第三器件层L 3可以包括第一源/漏层1005 3、沟道限定层1007 3和第二源/漏层1009 3。另外，为了后继制作电隔离的目的，器件层L 1、L 2、L 3可以分别包括隔离限定层1003 1、1003 2、1003 3。这些半导体层可以具有良好的晶体质量，并可以是单晶结构。相邻的半导体层之间可以具有清晰的晶体界面。
注意，在此每两个相邻的器件层之间均设置了隔离限定层。但是，本公开不限于此。例如，根据电路设计，某些相邻的器件层可以彼此电连接，因此它们之间可以不设置隔离限定层。
这些半导体层可以包括各种合适的半导体材料，例如，元素半导体材料如Si或Ge之类的1V族元素半导体材料，化合物半导体材料如SiGe之类的IV族化合物半导体材料或者InP、GaAs之类的III-V族化合物半导体材料。可以基于衬底的性质、要实现的器件性能等因素，来选择半导体层的材料。
在本实施例中，在Si晶片上形成的各半导体层可以是Si系材料。另外，考虑到后继工艺，相邻的半导体层之间可以具有刻蚀选择性。例如，各源/漏层可以包括Si，各沟道限定层以及隔离限定层可以包括SiGe(例如，Ge的原子百分比可以为约10至30％，优选地为约15％)。
各器件层中的半导体层可以根据所要形成的器件的导电类型而被适当地掺杂。例如，第一源/漏层和第二源/漏层可以被重掺杂(例如，掺杂浓度为约1E18至1E21cm -3)为与所要实现的器件的导电类型相同的导电类型，而沟道限定层可以未有意掺杂，或者被轻掺杂为例如与所要实现的器件的导电类型相反的导电类型以调节器件阈值电压。或者，对于隧穿型器件，同一器件层中的第一源/漏层和第二源/漏层可以被掺杂为相反的导电类型。半导体层的掺杂可以通过在外延生长时原位掺杂实现，或者可以通过其他掺杂方法如离子注入来实现。在相邻的半导体层之间可以具有掺杂浓度界面。
各半导体层可以具有合适的(竖直方向上的)厚度。例如，第一和第二源/漏层均可以具有约20至50nm的厚度，隔离限定层可以具有约10至20nm的厚度，沟道限定层可以具有约15至100nm的厚度。考虑到后继工艺，各沟道限定层的厚度可以大于各隔离限定层的厚度。另外，至少一些器件层可以具有不同的尺度，以实现不同的电气特性。例如，至少一些器件层中的沟道限定层的厚度可以不同(以实现不同的栅长)。另外，至少一些器件层中的源/漏层的厚度也可以不同。例如，上方的器件层中源/漏层的厚度可以小于下方的器件层中源/漏层的厚度，于是，下方的器件层中随后形成的器件可以具有较小的电阻或者较大的导通电流。
另外，在半导体层上方，可以形成硬掩模层1011，以辅助构图。例如，硬掩模层1011可以包括氮化物(例如，氮化硅)，厚度为约50至200nm。
在图1中，示出了三个器件层L 1、L 2和L 3，且随后可以形成三层器件。但是，本公开不限于此。可以设置更多或更少的器件层，并可以形成相应层级的器件。
可以从上述半导体层构图器件的有源区。
例如，可以形成沿第一方向(例如，图1中纸面内的水平方向)以及与第一方向相交(例如，垂直)的第二方向(例如，图1中垂直于纸面的方向)延伸的槽，并在槽中填充电介质，来形成隔离如浅沟槽隔离(STI)，从而限定被这些隔离所围绕的有源区。
在此，由于叠置了多个器件层，为便于连接到各个器件层，可以在有源区中形成阶梯结构。具体地，下方器件层的有源区可以相对于上方器件层的有源区在横向上伸出，从而形成台阶。本领域存在多种方式来形成这种阶梯结构。例如，可以利用光刻胶修整(trim)结合逐次刻蚀，来构图阶梯结构。在构图时，可以将器件层L 1、L 2、L 3各自分别视为“一层”，于是可以在第一器件层L 1与第二器件层L 2之间、以及第二器件层L 2与第三器件层L 3之间，分别形成台阶。
另外，这种阶梯结构可以仅形成在有源区的一侧或多侧，但并不形成在有源区的其他一侧或多侧(也即，在该其他一侧或多侧，不同器件层中的有源区可以在竖直方向上实质上对齐)，以便节省面积。为限定有源区的并不需要形 成阶梯结构的该其他一侧或多侧，如图2所示，可以在硬掩模层1011上形成垫层1013。在后继修整光刻胶时，垫层1013可以保持基本不受影响，并因此保持由其限定的有源区的边缘在竖直方向上保持基本对齐(即，不会形成阶梯结构)。垫层1013可以包括相对于硬掩模层1011具有刻蚀选择性的材料，例如氧化物(例如，氧化硅)。
垫层1013可以构图为在第一方向上彼此分离，且分别呈沿第二方向延伸的线形的图案(图中仅示出了其中两个，作为示例)，以分别(结合下述光刻胶)限定各器件层中单独器件的有源区。垫层1013的各个图案在竖直方向上的高度H与在第一方向上的宽度W之和可以大于作为最下方器件层的第一器件层L 1中将要限定的单独器件的宽度W 1与作为从上往下的第二个器件层中将要限定的单独器件的宽度W n-1之差，也即，(H+W)＞(W 1-W n-1)，其中，n表示衬底1001上形成的器件层的总数，W n-1表示第(n-1)器件层L n-1(注：在本文中，对于器件层及其相关特征如宽度等，将从下往上编号，如图所示)中将要限定的单独器件的宽度。在本实施例中，n＝3，因此(H+W)＞(W 1-W 2)。该关系可以保证在后继对光刻胶进行修整时，光刻胶在被完全去除之前可以保持与垫层1013相接，而不会彼此分离。
另外，如图3所示，可以在硬掩模层1011上进一步形成光刻胶1015。光刻胶1015可以构图为在第一方向上彼此分离，分别呈沿第二方向延伸的线形且在一侧与垫层1013的相应图案相交迭的图案，以(结合垫层1013中相应的图案)限定各器件层中单独器件的有源区。光刻胶1015的图案与垫层1013的相应图案在横向(在此，第一方向)上的宽度(如图3中的带箭头线段所示)，可以对应于最下方的第一器件层L 1中单独器件的宽度W1。另外，光刻胶1015在竖直方向上的厚度可以大于(H+W)，以保证在后继对光刻胶进行修整时，光刻胶在被完全去除之前可以保持与垫层1013相接，而不会彼此分离。
然后，如图4所示，可以垫层1013和光刻胶1015作为刻蚀掩模，对器件层进行刻蚀，如反应离子刻蚀(RIE)。在此，刻蚀配方可以对器件层中的各层(例如，Si和SiGe)基本上无选择性。可以控制刻蚀深度为第一器件层L 1的厚度D 1与将要形成的STI的深度D STI之和，即，D 1+D STI。例如，D STI可以为约50至200nm。
如图5所示，可以对光刻胶1015进行修整，使得修整后的光刻胶1015′与垫层1013相结合可以限定第二器件层L 2中单独器件的有源区。具体地，光刻胶1015′的图案与叠层1013的相应图案在横向(在此，第一方向)上的宽度(如图5中的带箭头线段所示)，可以对应于第二器件层L 2中单独器件的宽度W 2。也即，光刻胶1015需要被修整(W 1-W 2)的量。
然后，如图6所示，可以垫层1013和光刻胶1015′作为刻蚀掩模，对器件层进行刻蚀，如RIE。同样，刻蚀配方可以对器件层中的各层基本上无选择性。可以控制刻蚀深度为第二器件层L 2的厚度D 2。
更一般地，可以重复结合图5描述的光刻胶修整处理以及结合图6描述的刻蚀处理。例如，可以对光刻胶依次修整(W 1-W 2)、(W 2-W 3)、(W 3-W 4)、…、(W n-2-W n-1)的量(对光刻胶进行修整的总量为(W 1-W 2)+(W 2-W 3)+(W 3-W 4)+…+(W n-2-W n-1)＝(W 1-W n-1)，这也是该项出现在以上关系式中的原因)，并在每次修整光刻胶之后，以修整后的光刻胶结合垫层1013作为刻蚀掩模，对器件层进行刻蚀，刻蚀深度可以依次为第二器件层L 2的厚度D 2、第三器件层L 3的厚度D 3、…、第(n-1)器件层L n-1的厚度D n-1。
之后，如图7所示，可以进一步修整光刻胶(在该示例中，最后一次修整可以去除光刻胶1015′)。垫层1013的图案的宽度W可以对应于最上方的第三器件层L 3中单独器件的宽度W 3。可以垫层1013作为刻蚀掩模，对器件层进行刻蚀，如RIE。同样，刻蚀配方可以对器件层中的各层基本上无选择性。可以控制刻蚀深度为第三器件层L 3的厚度D 3。
更一般地，可以去除如上所述经过一次或多次修整的光刻胶，留下垫层1013，并以垫层1013作为刻蚀掩模，对器件层进行刻蚀，刻蚀深度可以上第 n器件层L n的厚度D n。
于是，形成了图7所示的阶梯结构。如图7所示，下方的器件层相对于上方的器件层伸出，从而形成各个台阶S 1、S 2。另外，对于最上方的器件层(在该示例中，第三器件层L 3)，其顶部也可以称作台阶S 3。台阶S 1、S 2、S 3可以呈沿第二方向延伸的板状。在各台阶S 1、S 2、S 3处，相应器件层L 1、L 2、L 3的第二/漏层可以露出。另外，同一器件层中的各半导体层可以在竖直方向上基本对齐。在图7的示例中，示出了阶梯结构中的台阶S 1、S 2由相应器件层 L 1、L 2中的第二/漏层1009 1、1009 2的原本顶表面限定，这是理想情况。在实际工艺中，器件层L 1、L 2中的第二/漏层1009 1、1009 2的露出部分可能被刻蚀掉一定厚度。
另外，在衬底1001中形成了沿第二方向延伸的槽，随后可以用来形成STI。
阶梯结构的取向不限于图7所示。根据电路设计，阶梯结构可以具有不同的取向。例如，如图8所示，第一方向上彼此相邻的器件各自的阶梯结构可以向着相反方向。以下，仅为描述方便起见，以图7所示的情形为例进行描述。图7所示的取向具有处理空间较大(特别是在顶部)的优点。
为形成GAA配置，可以在沟道限定层1007 1、1007 2、1007 3在第一方向上的相对两侧形成牺牲栅。例如，如图9所示，可以通过选择性刻蚀，使各器件层中的沟道限定层1007 1、1007 2、1007 3(在该示例中，为SiGe)在第一方向上相对凹进，以提供形成牺牲栅的空间。在该示例中，隔离限定层1003 1、1003 2、1003 3(在该示例中，也为SiGe)也会在第一方向上相对凹进大致相同的程度。例如，对沟道限定层1007 1、1007 2、1007 3和隔离限定层1003 1、1003 2、1003 3的刻蚀深度可以为约2至10nm。各器件层中的刻蚀深度可以实质上相同。为较好地控制刻蚀深度，可以采用原子层刻蚀(ALE)。
为避免牺牲栅形成在隔离限定层1003 1、1003 2、1003 3的相对凹入中(这是不希望的)，如图10所示，可以在隔离限定层1003 1、1003 2、1003 3的相对凹入中形成插塞1017。插塞1017可以包括相对于硬掩模层1011和垫层1013具备刻蚀选择性的材料，如SiC。由于如上所述各沟道限定层的厚度大于各隔离限定层的厚度，因此插塞1017可以不形成在沟道限定层1007 1、1007 2、1007 3的相对凹入中。具体地，可以淀积厚度大于各隔离限定层中最大的厚度但小于各沟道限定层中的最小厚度的二分之一厚的SiC。于是，淀积的SiC可以完全填满隔离限定层1003 1、1003 2、1003 3的相对凹入。可以将淀积的SiC回蚀一定厚度(例如，稍大于淀积厚度)，从而SiC可以留于隔离限定层1003 1、1003 2、1003 3的相对凹入中形成插塞1017，而从沟道限定层1007 1、1007 2、1007 3的相对凹入中去除。
在隔离限定层1003 1、1003 2、1003 3相对于沟道限定层1007 1、1007 2、1007 3具备刻蚀选择性的情况下，可以省略插塞1017的形成。
之后，如图11所示，可以在沟道限定层1007 1、1007 2、1007 3的相对凹入中形成牺牲栅1019(可以称作“第一牺牲栅”)。第一牺牲栅1019可以包括相对于插塞1017具备刻蚀选择性的材料，例如氮化物。例如，可以淀积氮化物，并对淀积的氮化物进行竖直方向的RIE，来形成第一牺牲栅1019。
另外，可以淀积电介质如氧化物，并对其进行平坦化如化学机械抛光(CMP)(可以停止于硬掩模层1011)，来形成隔离材料1021。隔离材料可以填充器件层中由于上述处理而导致的空隙，以便于接下来的处理。
通过上述形成阶梯结构的处理，各器件层在第一方向上被分离，但在第二方向上仍连续延伸。接下来，可以在第二方向上将各器件层分离。
如图12(a)至12(c)所示，可以在隔离材料1021上形成光刻胶1023，并将其构图为在第二方向上分离的图案，例如沿第一方向延伸的条形。这些沿第一方向延伸的条形与之前形成的沿第二方向延伸的各器件层在相交之处限定了单独器件的有源区。
在光刻胶1023的这些条形图案之间露出的区域中可以形成隔离。具体地，可以去除这些区域中的有源层，并填充电介质。
在图12(a)中，AA′线沿第一方向延伸，且其表示的(垂直于衬底表面的)截面穿过有源区(特别是穿过随后形成的沟道层1033用作沟道的部分)；BB′线沿第一方向延伸，且其表示的(垂直于衬底表面的)截面穿过随后形成的STI；CC′线沿第二方向延伸，且其表示的(垂直于衬底表面的)截面穿过台阶S 3；DD′线沿第二方向延伸，且其表示的(垂直于衬底表面的)截面穿过台阶S 2。
例如，如图13所示，可以通过例如RIE，去除这些区域中的硬掩模层1011，以露出下方的器件层(在此，第三器件层L 3)。然后，可以通过例如RIE，去除露出的第三器件层L 3。在此，可以控制刻蚀深度，使得刻蚀停止在第二器件层L 2的第二源/漏层1009 2的顶面附近。第二器件层L 2的第二源/漏层1009 2原本被第三器件层L 3覆盖的部分可以由于第三器件层L 3的去除而被露出，另一部分(即，台阶S 2)则被隔离材料1021覆盖。可以通过例如RIE，使隔离材料1021减少一定厚度。减少厚度的隔离材料1021的顶面可以在第二器件层的第二源/漏层1009 2的顶面附近，从而能够露出第二器件层L 2的包括台阶S 2 在内的基本上整个第二源/漏层1009 2。
如图14(a)和14(b)所示，可以重复这种处理，即，去除大致一个器件层，并将隔离材料1021减少与该器件层基本上相同的厚度(以使下一器件层的顶面能够基本上完全露出)，直至到达将要形成的STI的深度。之后，可以去除光刻胶1023。于是，各器件层被分离为单独器件的有源区。在这些有源区之间的间隙中，可以通过例如淀积然后平坦化如CMP(可以停止于硬掩模层1011)的方法，来填充电介质。在此填充的电介质可以与之前的隔离材料1021包括相同的电介质如氧化物，并因此它们被一体示出为隔离材料1021′。
然后，如图15(a)至15(c)所示，可以通过干法刻蚀如RIE或者湿法刻蚀，回蚀隔离材料1021′。回蚀后的隔离材料可以形成厚度为约D STI的STI 1025。注意，在附图中，仅为图示方便起见，将STI 1025的顶面示出为与衬底1001的顶面齐平。STI 1025的顶面可以(略)低于或(略)高于衬底1001的顶面。如图15(c)所示，各器件层在第二方向上分离为单独器件的有源区。
通过以上工艺，限定了单独器件的有源区，且彼此叠置的有源区之间在第一方向上形成阶梯结构。
在此，在各个器件层中，由于第一源/漏层、沟道限定层(限定随后形成的栅堆叠)和第二源/漏层彼此叠置，为便于连接到其中每一层，也可以在各个器件层中形成阶梯结构。该阶梯结构可以形成在第二方向上，以免与以上在第一方向上形成的阶梯结构相干扰。另外，考虑到处于下方的沟道限定层和第二源/漏层各自需要分别相对伸出，可以在第二方向上的相对两侧均形成阶梯结构。
可以对第二方向上的相对两侧分别进行处理。在处理过程中，可以利用遮蔽层来遮蔽其他侧，而露出需要处理的一侧。
例如，如图16(a)至16(c)所示，可以通过例如淀积，以大致共形的方式，形成遮蔽层1027。例如，遮蔽层1027可以包括相对于硬掩模层1011、第一牺牲栅1019和STI 1025具有刻蚀选择性的材料，如SiC。在遮蔽层1027上可以形成光刻胶1029(在图16(a)中，为帮助理解，光刻胶1029被显示为部分透明，以显示下方的结构)，并将其构图为能够露出各有源区在第二方向上的一侧。在所示的实施例中，光刻胶1029露出第二方向上每两个相邻有源区之间的区 域。可以光刻胶1029作为刻蚀掩模，对遮蔽层1027进行刻蚀如RIE，使得各有源区在第二方向上的一侧露出。之后，可以去除光刻胶1029。注意，在图16(a)中，为了方便读者明了光刻胶与有源区之间的关系，没有示出遮蔽层1027。
在该示例中，为便于构图，第二方向上相邻的两个有源区彼此的相反侧(在图16(a)中，上侧、下侧)露出。当然，本公开不限于此。例如，遮蔽层可以露出各个有源区在第二方向上的相同侧。
如以上结合图10所述，为避免牺牲栅形成在隔离限定层1003 1、1003 2、1003 3的外周，如图17所示，可以通过选择性刻蚀如ALE，使隔离限定层1003 1、1003 2、1003 3(同时沟道限定层1007 1、1007 2、1007 3)在第二方向上相对凹进，并在如此得到的凹入中形成插塞1031。关于插塞1031的形成，例如可以参见以上结合图10的描述。插塞1031可以包括相对于硬掩模层1011和遮蔽层1027具备刻蚀选择性的材料，如氧化物。
图18所示，通过各沟道限定层1007 1、1007 2、1007 3在第二方向上的一侧露出的表面，可以通过选择性刻蚀如ALE，使各沟道限定层1007 1、1007 2、1007 3进一步凹进，以限定栅空间。由于插塞1031的存在，隔离限定层1003 1、1003 2、1003 3可以不受影响。
由于沟道限定层1007 1、1007 2、1007 3可以具有相同的材料(在该示例中，SiGe)，且被相同的刻蚀配方刻蚀，因此在第二方向上的这一侧，各沟道限定层1007 1、1007 2、1007 3的凹进程度可以大致相同，且凹进之后的侧壁可以保持在竖直方向上实质上对齐，且可以保持实质上共面。
在另一实施例中，如图19所示，还可以使用能够作用于沟道限定层和源/漏层两者的刻蚀配方，通过例如ALE，对沟道限定层和源/漏层进一步刻蚀一定深度T。这有助于实现一致的栅长。
如图20所示，可以通过例如外延生长，形成沟道层1033。例如，沟道层1033可以包括相对于沟道限定层具有刻蚀选择性的半导体材料如Si。控制沟道层1033的生长，使其厚度大致等于T。这样，在沟道层1033在第二方向上的相对两侧(图20中纸面内的左右两侧)可以保持基本上一致的栅长(即，大致为沟道限定层在竖直方向上的厚度)。沟道层1033可以形成为纳米片的形式。
外延生长也可以发生在其他半导体表面上。可以通过例如竖直方向上的RIE，对外延生长的沟道层进行刻蚀，从而其可以留于硬掩模层1011的下方，而各有源区之间的空隙仍然可以保留以便用作进一步处理的加工通道。
如图21所示，可以通过例如淀积然后竖直方向的RIE，在栅空间中形成牺牲栅1035(可以称作“第二牺牲栅”)。第二牺牲栅1035可以包括与第一牺牲栅1019相同的材料如氮化物，以便在后继的替代栅工艺中可以被同时去除。
另外，可以进行退火处理，以将掺杂剂从源/漏层驱入沟道层1033中将用作源/漏的部分中，以降低外电阻并提升器件性能。图21中以虚线示意性示出了沟道层1033中用作源/漏的部分(例如，实质上水平延伸的部分)与用作沟道的部分(例如，实质上竖直延伸的部分)之间的界面。这种界面可以由掺杂浓度限定。掺杂剂向沟道层1033中上下两侧用作源/漏的部分的扩散可以具有基本相同的特性，因此沟道层1033中用作沟道的部分可以自对准于相应的沟道限定层。
在以下，仅为图示方便起见，不再示出沟道层1033中用作源/漏的部分与用作沟道的部分之间的区别。
在第二方向上的这一侧，如图22(a)和22(b)所示，可以通过选择性刻蚀如ALE，使各第二源/漏层1009 1、1009 2、1009 3以及沟道层1033(在此，均为Si)位于第二牺牲栅1035顶面上的部分在第二方向上凹进(第一源/漏层1005 1、1005 2、1005 3以及沟道层1033位于第二牺牲栅1035底面上的部分也可以同样在第二方向上凹进)，凹进深度可以使得能够保证沟道层1033中用作沟道的部分(在此，竖直延伸部分)的完整性。于是，在各器件层中，第二牺牲栅1035相对于第二源/漏层1009 1、1009 2、1009 3(以及沟道层1033)伸出，从而形成“子”台阶。
也即，各器件层的第二牺牲栅相对于相应器件层中的第二源/漏层在第二方向上的这一侧形成了子台阶SS 1(参见图34)、SS 2、SS 3。注意，在此将这种伸出部分称为“子台阶”的原因在于，这些子台阶可以形成于相应的台阶上(如上所述，图22(a)示出了台阶S 3处的情形，图22(b)示出了台阶S 2处的情形)。
另外，由于源/漏层和沟道层1033的凹进，隔离限定层1003 1、1003 2、1003 3 的端部以及插塞1031可以悬空，并因此可以在刻蚀处理中由于侵蚀而被去除。
或者，可以先去除插塞1031，再进行这种选择性刻蚀。刻蚀配方可以选择为对第二源/漏层1009 1、1009 2、1009 3和沟道层1033以及隔离限定层1003 1、1003 2、1003 3均能起作用。于是，隔离限定层1003 1、1003 2、1003 3可以与第二源/漏层1009 1、1009 2、1009 3和沟道层1033一起凹进。
在遮蔽层1027下方由于这种凹进而形成的空隙中，可以通过例如淀积、平坦化(可以停止于遮蔽层1027)然后回蚀，来填充电介质1037(例如，氧化物)。由于遮蔽层1027的存在，电介质1037形成在其下方。图22(b)示出了第二器件层L 2与第三器件层L 3之间的台阶S 2处的情形，第一器件层L 1与第二器件层L 2之间的台阶S 1处同样如此。也即，电介质1037也随各器件层一起，形成阶梯结构。也即，电介质1037限定的栅空间可以保持之前形成的阶梯结构。
以上，通过遮蔽层1027，实现了对各有源区在第二方向上一侧的处理。之后，可以对各有源区在第二方向上的另一侧进行处理。
为此，如图23所示，可以在遮蔽层1027上形成光刻胶1039，并将其构图为能够露出各有源区在第二方向上的另一侧(参见图24(a)，所述“另一侧”是各有源区在第二方向上如图16(a)中所示被遮蔽层1027遮蔽的这一侧)。在此，在第二方向上已经处理过的一侧，由于电介质1037和第二牺牲栅1035的存在(如图24(a)中的虚线圈所示)，无需特别形成单独的遮蔽层。
另外，考虑到以下为降低接触电阻而进行的硅化工艺，可以将光刻胶1039构图为还能够(至少部分地)露出各个台阶，而遮蔽各器件层的竖直侧壁。图24(a)至24(d)示出了利用光刻胶1039作为刻蚀掩模对遮蔽层1027进行刻蚀如RIE之后的结构。之后，可以去除光刻胶1039。
在此，基于AA’线截取的截面穿过沟道层1033，故而在图23所示的截面图中，存在沟道层1033。另外，图中以虚线示意性示出了沟道层1033用作源/漏的部分与用作沟道的部分之间的界面。如图23所示，在第一方向上，沟道层1033用作沟道的部分的宽度可以限定栅宽。因此，第一牺牲栅1019在第一方向上的宽度可以相对较小，以免使栅宽减小。另外，在竖直方向上，沟道层1033用作沟道的部分的高度可以限定栅长，并可以基本上等于沟道限定层在 竖直方向上的厚度。沟道层1033可以呈纳米片的形式，从而在第二方向上的尺寸可以(远)小于第一方向上的宽度和竖直方向上的高度。
可以如以上结合图16(a)至16(c)所述，形成插塞1041。插塞1041可以包括相对于第二牺牲栅1035和电介质1037具有刻蚀选择性的材料，如SiC。在SiC的情况下，可以先通过例如淀积形成一薄刻蚀停止层如氧化物。这有助于避免在形成插塞1041时影响到在此同为SiC的遮蔽层1027′。
然后，可以通过选择性刻蚀去除沟道限定层1007 1、1007 2、1007 3(由于插塞1041的存在，可以避免隔离限定层1003 1、1003 2、1003 3在此被去除)，并在由于沟道限定层1007 1、1007 2、1007 3的去除而留下的栅空间中，通过例如淀积然后竖直方向的RIE形成牺牲栅1043(可以称作“第三牺牲栅”)。第三牺牲栅1043可以包括与第一牺牲栅1019、第二牺牲栅1035相同的材料(在此，氮化物)，以便随后可以被一起去除。在形成第三牺牲栅1043时的RIE过程中，在此同为氮化物的硬掩模层1011未被遮蔽层1027′遮挡的部分也可以被去除。
第一牺牲栅1019处于沟道层1033(具体地，其用作沟道的部分)在第一方向上的相对两侧，且第三牺牲栅1043与牺牲栅1035分处于沟道层1033(具体地，其用作沟道的部分)在第二方向上的相对两侧。也即，各牺牲栅围绕沟道层1033(具体地，用作沟道的部分)的外周。另外，如上所述，各牺牲栅可以具有大致相同的栅长，约等于沟道限定层在竖直方向上的厚度。
可以将隔离限定层替换为隔离材料，以实现竖直方向上相邻的器件之间的电隔离。例如，如图25(a)至25(c)所示，可以通过选择性刻蚀，去除插塞1041，以露出隔离限定层1003 1、1003 2、1003 3。然后，可以通过选择性刻蚀，去除隔离限定层1003 1、1003 2、1003 3。在由于隔离限定层1003 1、1003 2、1003 3的去除而留下的空间中，可以通过例如淀积然后回蚀，形成隔离层1045，从而实现电隔离。隔离层1045可以包括相对于牺牲栅1019、1035、1043(在此，氮化物)以及电介质1037(在此，氧化物)具有刻蚀选择性的电介质材料，如SiC。
参见图25(a)，通过各台阶S 1、S 2、S 3，各器件层的第二源/漏层1009 1、1009 2、1009 3可以具有露出表面，以便随后制作到其的接触部。在各个台阶S 1、S 2、 S 3处，还可以露出各器件层的第一源/漏层1005 1、1005 2、1005 3，以便随后制作到其的接触部。
例如，如图26(a)至26(c)所示，可以形成光刻胶1047(在图26(a)中，为帮助理解，光刻胶1047被显示为部分透明，以显示下方的结构)，并将其构图为遮蔽各台阶S 1、S 2、S 3的一部分，而露出各台阶S 1、S 2、S 3的其余部分。也即，各台阶S 1、S 2、S 3可以基于光刻胶1047而被分为两部分(这两部分可以具有基本上相同的面积)。在该示例中，光刻胶1047可以被构图为沿着第一方向延伸的条形，因此各台阶S 1、S 2、S 3可以分为在第二方向上并排的两部分，且第三牺牲栅1043所在一侧的部分被露出。
可以光刻胶1047作为刻蚀掩模，通过选择性刻蚀如RIE，在各台阶S 1、S 2、S 3处依次选择性刻蚀相应的第二源/漏层和牺牲栅。于是，在各器件层中，在各台阶S 1、S 2、S 3处，第一源/漏层相对于第二源/漏层和牺牲栅伸出，从而形成子台阶SS 4、SS 5、SS 6。之后，可以去除光刻胶1047。
至此，已在各器件层中限定了有源区(包括第一源/漏层、第二源/漏层及它们之间的沟道层)以及(围绕沟道层的)牺牲栅。
为降低接触电阻，如图27(a)至27(d)所示，可以对各台阶S 1、S 2、S 3处暴露在外的第一源/漏层和第二源/漏层进行硅化处理，以形成硅化物1049。例如，可以淀积金属如Ni或NiPt，并在约300至700℃的温度下退火，使得淀积的金属与第一源/漏层和第二源/漏层中的半导体元素发生反应，从而生成金属半导体化合物如NiSi或NiPtSi。之后，可以去除未反应的剩余金属。
根据另一实施例，在以上结合图26(a)至26(d)描述的处理中，可以先通过例如竖直方向的RIE，来去除遮蔽层1027′被光刻胶1047暴露的部分的水平延伸部分，以增大各子台阶SS 4、SS 5、SS 6的面积(从而有利于随后制作到其的接触部)，同时保持遮蔽层1027′暴露部分的竖直延伸部分(作为侧墙)以保护侧壁。这样，可以得到如图28所示的结构。
接下来，可以进行替代栅工艺。
如图29(a)至29(c)所示，可以通过选择性刻蚀，去除遮蔽层1027′，去除牺牲栅1019、1035、1043。在由于牺牲栅1019、1035、1043的去除而留下的空间中，可以通过例如淀积然后竖直方向的RIE，来形成栅堆叠。栅堆叠可以 包括栅介质层1051和栅导体层1053。例如，栅介质层1051可以包括高k介质如HfO 2，栅导体层1053可以包括金属。栅堆叠可以围绕沟道层1033(具体地，用作沟道的部分)的外周，从而形成全围绕栅结构。
如图29(b)和29(c)所示，在各有源区在第二方向上的一侧，存在电介质1037，故而栅堆叠与源/漏之间的交迭较小。而在各有源区在第二方向上的另一侧，栅堆叠与源/漏之间的交迭较大。为减少这种交迭并因此降低由此导致的寄生电容，可以形成例如SiC的遮蔽层1055以遮蔽交迭较小的区域(第二方向上的一侧)而露出交迭较大的区域(第二方向上的另一侧)。在交迭较大的区域中，可以通过选择性刻蚀，使栅堆叠凹进一定深度(从而减小与源/漏之间的交迭)。在由于栅堆叠的凹进而形成的凹入中，可以通过例如淀积然后竖直方向的RIE，填充电介质材料如氮化物(参见图30(b)中的1057)。之后，可以去除遮蔽层1055。
在上述实施例中，针对各器件层形成相同配置的栅堆叠(1051/1053)。但是，本公开不限于此。例如，可以针对至少一些器件层形成不同配置的栅堆叠(例如，具有不同功函数)，特别是在这些器件层中的器件具有不同导电类型的情况下。
例如，如图30(a)和30(b)所示，在如上所述形成针对第一器件层L 1的第一栅堆叠(1051/1053)之后，可以通过例如淀积然后回蚀，在衬底1001上形成一定高度的层间电介质层1059(例如，氧化物)。层间电介质层1059的高度使得可以遮蔽在第一器件层L 1中形成的第一栅堆叠(1051/1053)，而露出在第二器件层L 2及第三器件层L 3中形成的第一栅堆叠(1051/1053)。可以通过选择性刻蚀，去除露出的第一栅堆叠中的栅导体层1053。于是，释放了第二器件层L 2及第三器件层L 3中的部分栅空间。在释放的栅空间中，可以形成另一栅导体层1061(参见图31(a)和31(b))。于是，形成了针对第二器件层L 2的第二栅堆叠(1051/1061)。
在此，第二栅堆叠与第一栅堆叠具有相同的栅介质层。但是，本公开不限于此。例如，可以去除栅介质层1051，并形成另一栅介质层。
另外，如果要针对第三器件层L 3形成不同于第二栅堆叠的第三栅堆叠(可以同于第一栅堆叠，当然也可以不同于第一堆叠)，可以进行类似的处理。例 如，可以通过淀积然后回蚀，使层间电介质1059的顶面升高，以遮蔽第一器件层L 1中形成的第一栅堆叠(1051/1053)以及第二器件层L 2中形成的第二栅堆叠(1051/1061)，而露出第三器件层L 3中形成的第二栅堆叠。可以通过选择性刻蚀，去除露出的第二栅堆叠中的栅导体层1061。于是，释放了第三器件层L 3中的部分栅空间。在释放的栅空间中，可以形成栅导体层。
图31(a)和31(b)示出了针对所有器件层形成相应栅堆叠之后的结构。可以通过淀积然后平坦化，形成覆盖所有器件层的层间电介质层1059′。
至此，已基本完成了器件的制作。可以在层间电介质层1059′中制作各种接触部，以实现电连接。
例如，如图32(a)至32(d)所示，分别在各台阶S 1、S 2、S 3上，制作到相应器件层L 1、L 2、L 3的接触部1063 1、1063 2、1063 3。接触部可以通过在层间电介质层1059′中刻蚀接触孔，并在孔中填充导电材料如金属来形成。在接触孔的侧壁和底面上，可以先形成扩散阻挡层。
另外，在每一个台阶上，可以设有分别到相应器件层中的第一源/漏层、第二源/漏层和栅堆叠的接触部。例如，如图32(c)所示，在台阶S 3上，接触部1063 3可以包括到第三器件层L 3中的第一源/漏层的接触部1063 3-1(在子台阶SS 6上)、到第二源/漏层的接触部1063 3-2以及到栅堆叠(具体地，其中的栅导体层)的接触部1063 3-3(在子台阶SS 3上)。如图32(a)所示，台阶S 3上的接触部1063 3-1、1063 3-2、1063 3-3可以沿第二方向大致成直线排列。类似地，如图32(d)所示，在台阶S 2上，接触部1063 2可以包括到第二器件层L 1中的第一源/漏层的接触部1063 2-1(在子台阶SS 5上)、到第二源/漏层的接触部1063 2-2以及到栅堆叠(具体地，其中的栅导体层)的接触部1063 2-3(在子台阶SS 2上)。如图32(a)所示，台阶S 2上的接触部1063 2-1、1063 2-2、1063 2-3可以沿第二方向大致成直线排列。在台阶S 1上同样如此，尽管在此并未示出。
在上述实施例中，每一台阶上的接触部成直线排列。但是，本公开不限于此。例如，如图33所示，每一台阶上的接触部可以在第二方向上呈之字形排列。这样，在接触部之间的间距保持相同的情况下，可以节省面积(在保持器件在第一方向上的宽度不变时，器件在第二方向上的尺寸可以减小)。
如图34所示，根据本公开实施例的半导体装置可以包括在竖直方向(z 方向)上叠置的两个或更多个器件层L 1、L 2、L 3，可以在每个器件层中限定相应的器件。每个器件层可以包括在竖直方向(z方向)上叠置的第一源/漏层、沟道层和第二源/漏层。如上所述，沟道层可以是沿第一方向(x方向)延伸的纳米片，其厚度方向在与第一方向相交(例如，垂直)的第二方向(y方向)上。沟道层在第一方向(x方向)上的宽度可以限定栅宽，在竖直方向(z方向)上的高度可以限定栅长。下层的器件层中沟道层的宽度可以大于上层的器件层中沟道层的宽度。栅堆叠可以沟道层的外周，形成GAA配置。在图34中，示出了分别针对各器件层L 1、L 2、L 3的栅堆叠G 1、G 2、G 3。例如，如上所述，栅堆叠G 1可以包括栅介质层1051和栅导体层1053，栅堆叠G 2可以包括栅介质层1051和栅导体层1061，栅堆叠G 3可以包括栅介质层1051和栅导体层1053。相邻器件层之间可以设置有隔离层1045。注意，并不一定每两个相邻的器件层之间都需要隔离层。
下方的器件层可以相对于上方的器件层在第一方向(x方向)上伸出，从而形成阶梯结构。例如，第一器件层L 1可以相对于第二器件层L 2在第一方向上伸出，形成台阶S 1；第二器件层L 2可以相对于第三器件层L 3在第一方向上伸出，形成台阶S 2；第三器件层L 3可以形成台阶S 3。注意，并不一定每两个相邻的器件层之间都需要形成台阶。
另外，在各台阶S 1、S 2、S 3上，可以形成子台阶。子台阶可以形成在相应台阶在第二方向(y方向)上的相对两端。例如，在第一台阶S 1上，栅堆叠G 1可以相对于第一器件层L 1的第二源/漏层1009 1(以及第一源/漏层1005 1，它们可以在第二方向上的这一侧可以在竖直方向上实质上对齐)在第二方向上伸出，形成子台阶SS 1；第一器件层L 1的第一源/漏层1005 1可以相对于第二源/漏层1009 1以及栅堆叠G 1(在此，栅堆叠G 1相对于第二源/漏层1009 1在第二方向上凹进，以降低寄生电容，如上所述)在第二方向上伸出，形成子台阶SS 4。类似地，在第二台阶S 2上，栅堆叠G 2可以相对于第二器件层L 2的第二源/漏层1009 2(以及第一源/漏层1005 2，它们可以在第二方向上的这一侧可以在竖直方向上实质上对齐)在第二方向上伸出，形成子台阶SS 2；第二器件层L 2的第一源/漏层1005 2可以相对于第二源/漏层1009 2以及栅堆叠G 2(在此，栅堆叠G 2相对于第二源/漏层1009 2在第二方向上凹进，以降低寄生电容，如 上所述)在第二方向上伸出，形成子台阶SS 5。类似地，在第三台阶S 3上，栅堆叠G 3可以相对于第三器件层L 3的第二源/漏层1009 3(以及第一源/漏层1005 3，它们可以在第二方向上的这一侧可以在竖直方向上实质上对齐)在第二方向上伸出，形成子台阶SS 3；第三器件层L 3的第一源/漏层1005 3可以相对于第二源/漏层1009 3以及栅堆叠G 3(在此，栅堆叠G 3相对于第二源/漏层1009 3在第二方向上凹进，以降低寄生电容，如上所述)在第二方向上伸出，形成子台阶SS 6。
到各器件层L 1、L 2、L 3的接触部可以处于相应的台阶S 1、S 2、S 3上。到各栅堆叠G 1、G 2、G 3的接触部可以处于相应的子台阶SS 1、SS 2、SS 3上，到第一源/漏层1005 1、1005 2、1005 3的接触部可以处于相应的子台阶SS 4、SS 5、SS 6上。
根据本公开实施例的半导体装置可以应用于各种电子设备。例如，可以基于这样的半导体装置形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体装置的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、个人计算机(PC)、平板电脑、人工智能设备、可穿戴设备或移动电源等。
根据本公开的实施例，还提供了一种芯片系统(SoC)的制造方法。该方法可以包括上述方法。具体地，可以在芯片上集成多种器件，其中至少一些是根据本公开的方法制造的。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (37)

  1. 一种半导体装置，包括：
    衬底；
    在竖直方向上叠置在所述衬底上的第一半导体器件和第二半导体器件，所述第一半导体器件和所述第二半导体器件各自包括在竖直方向上依次叠置的第一源/漏层、沟道层和第二源/漏层以及围绕所述沟道层的外周的栅堆叠，
    其中，所述第一半导体器件的第一源/漏层、第二源/漏层和栅堆叠在第一方向上的一端相对于所述第二半导体器件的第一源/漏层、第二源/漏层和栅堆叠在所述第一方向上的相应的一端在所述第一方向上伸出，从而形成第一台阶，所述第二半导体器件限定第二台阶，
    其中，所述第一半导体器件和所述第二半导体器件各自的第一源/漏层在与所述第一方向相交的第二方向上的一端相对于第二源/漏层和栅堆叠在所述第二方向上的相应的一端在所述第二方向上伸出，从而分别形成第一子台阶和第二子台阶，其中，所述第一子台阶在所述第一台阶上，所述第二子台阶在所述第二台阶上，
    其中，在所述第一半导体器件和所述第二半导体器件中的每一个中，相对于第二源/漏层在所述第二方向上与所述一端相对的另一端，栅堆叠在所述第二方向上与所述一端相对的另一端在所述第二方向上伸出。
  2. 根据权利要求1所述的半导体装置，还包括：
    电介质，与所述第一半导体器件和所述第二半导体器件各自的第一源/漏层和第二源/漏层在所述第二方向上的所述另一端相接，且在所述竖直方向上分别夹着所述第一半导体器件和所述第二半导体器件各自的栅堆叠。
  3. 根据权利要求1所述的半导体装置，还包括：
    在所述第二方向上排列的第一接触部、第二接触部、第三接触部；
    在所述第二方向上排列的第四接触部、第五接触部、第六接触部，
    其中，所述第一接触部、所述第二接触部和所述第三接触部处于所述第一台阶上方，所述第四接触部、所述第五接触部和所述第六接触部处于所述第二台阶上方，
    其中，所述第一接触部处于所述第一子台阶上方且着落于所述第一半导体器件的第一源/漏层，所述第二接触部着落于所述第一半导体器件的第二源/漏层，所述第三接触部靠近所述第一半导体器件的栅堆叠在所述第二方向上的所述另一端且着落于所述第一半导体器件的栅堆叠，
    其中，所述第四接触部处于所述第二子台阶上方且着落于所述第二半导体器件的第一源/漏层，所述第五接触部着落于所述第二半导体器件的第二源/漏层，所述第六接触部靠近所述第二半导体器件的栅堆叠在所述第二方向上的所述另一端且着落于所述第二半导体器件的栅堆叠。
  4. 根据权利要求3所述的半导体装置，其中，
    所述第一接触部、所述第二接触部、所述第三接触部在所述第二方向上排列成直线，且所述第四接触部、所述第五接触部、所述第六接触部在所述第二方向上排列成直线；或者
    所述第一接触部、所述第二接触部、所述第三接触部在所述第二方向上呈之字形排列成，且所述第四接触部、所述第五接触部、所述第六接触部在所述第二方向上呈之字形排列。
  5. 根据权利要求1所述的半导体装置，还包括：
    在竖直方向上介于所述第一半导体器件与所述第二半导体器件之间的隔离层。
  6. 根据权利要求5所述的半导体装置，其中，所述隔离层处在所述第一半导体器件的第二源/漏层和所述第二半导体器件的第一源/漏层之间并实现电隔离。
  7. 根据权利要求5或6所述的半导体装置，其中，所述隔离层与所述第二半导体器件的第一源/漏层在俯视图中实质上完全重合。
  8. 根据权利要求5或6所述的半导体装置，其中，所述隔离层在竖直方向上的厚度小于所述沟道层在竖直方向上的高度。
  9. 根据权利要求1所述的半导体装置，其中，所述第一半导体器件的第一源/漏层和第二源/漏层在所述第二方向上的所述另一端以及所述第二半导体器件的第一源/漏层和第二源/漏层在所述第二方向上的所述另一端在竖直方向上实质上对齐。
  10. 根据权利要求1所述的半导体装置，其中，所述第一半导体器件的第一源/漏层和第二源/漏层在所述第一方向上与所述一端相对的另一端以及所述第二半导体器件的第一源/漏层和第二源/漏层在所述第一方向上与所述一端相对的另一端在竖直方向上实质上对齐。
  11. 根据权利要求1所述的半导体装置，其中，
    所述第一半导体器件的栅堆叠在所述第一方向上的一端和相对的另一端与所述第一半导体器件的第二源/漏层的相应端在竖直方向上实质上对齐，
    所述第二半导体器件的栅堆叠在所述第一方向上的一端和相对的另一端与所述第二半导体器件的第二源/漏层的相应端在竖直方向上实质上对齐。
  12. 根据权利要求1所述的半导体装置，其中，
    所述第一半导体器件的栅堆叠在所述第二方向上的所述一端相对于所述第一半导体器件的第二源/漏层在所述第二方向上的所述一端在所述第二方向上凹进，
    所述第二半导体器件的栅堆叠在所述第二方向上的所述一端相对于所述第二半导体器件的第二源/漏层在所述第二方向上的所述一端在所述第二方向上凹进。
  13. 根据权利要求1所述的半导体装置，其中，
    在所述第一半导体器件中，在沟道层在所述第一方向上的相对两侧，栅堆叠具有实质上相同的第一宽度，所述第一宽度在所述第一方向上测量，
    在所述第二半导体器件中，在沟道层在所述第一方向上的相对两侧，栅堆叠具有实质上相同的第二宽度，所述第二宽度在所述第一方向上测量。
  14. 根据权利要求13所述的半导体装置，其中，所述第一宽度实质上等于所述第二宽度。
  15. 根据权利要求1所述的半导体装置，其中，所述沟道层具有所述第一方向上的第一维度、所述第二方向上的第二维度以及所述竖直方向上的第三维度，其中所述第二维度小于所述第一维度和所述第三维度，使得所述沟道层呈沿所述第一方向延伸的纳米片的形式，所述第二维度构成所述纳米片的厚度。
  16. 根据权利要求15所述的半导体装置，其中，所述第一半导体器件的沟道层的第一维度大于所述第二半导体器件的沟道层的第一维度。
  17. 根据权利要求16所述的半导体装置，其中，所述第一半导体器件的沟道层的第一维度比所述第二半导体器件的沟道层的第一维度多出大约如下数量：所述第一台阶在所述第一方向上的尺寸。
  18. 根据权利要求15所述的半导体装置，其中，所述沟道层在垂直于所述第一方向的截面中呈C形。
  19. 根据权利要求18所述的半导体装置，其中，所述第一半导体器件的所述C形的开口背对所述第一子台阶，所述第二半导体器件的所述C形的开口背对所述第二子台阶。
  20. 根据权利要求1所述的半导体装置，还包括：
    在竖直方向上叠置在所述第二半导体器件上的第三半导体器件，所述第三半导体器件包括在竖直方向上依次叠置的第一源/漏层、沟道层和第二源/漏层以及围绕所述沟道层的外周的栅堆叠，
    其中，所述第二半导体器件的第一源/漏层、第二源/漏层和栅堆叠在第一方向上的一端相对于所述第三半导体器件的第一源/漏层、第二源/漏层和栅堆叠在所述第一方向上的所述一端在所述第一方向上伸出，从而形成所述第二台阶，
    其中，所述第二子台阶在所述第二台阶上。
  21. 根据权利要求20所述的半导体装置，其中，所述第三半导体器件限定第三台阶，
    其中，所述第三半导体器件的第一源/漏层在所述第二方向上的一端相对于第二源/漏层和栅堆叠在所述第二方向上的相应的一端在所述第二方向上伸出，从而形成第三子台阶，其中，所述第三子台阶在在所述第三台阶上，
    其中，在所述第三半导体器件中，相对于第二源/漏层在所述第二方向上与所述一端相对的另一端，栅堆叠在所述第二方向上与所述一端相对的另一端在所述第二方向上伸出。
  22. 根据权利要求1所述的半导体装置，其中，所述第二半导体器件是顶层的器件，所述第二半导体器件的第一源/漏层、第二源/漏层和栅堆叠形成所述第二台阶。
  23. 根据权利要求1所述的半导体装置，其中，所述第一半导体器件的第 一源/漏层和第二源/漏层在竖直方向上的厚度大于所述第二半导体器件的第一源/漏层和第二源/漏层在竖直方向上的厚度。
  24. 根据权利要求1所述的半导体装置，其中，所述第一半导体器件的沟道层在竖直方向上的高度不同于所述第二半导体器件的沟道层在竖直方向上的高度。
  25. 一种制造半导体装置的方法，包括：
    在衬底上设置包括n个器件层的堆叠，每个器件层包括依次叠置的第一源/漏层、沟道限定层和第二源/漏层，其中，n是大于或等于2的整数；
    在所述堆叠在第一方向的一侧形成阶梯结构：下层的器件层相对于上层的器件层形成台阶；
    在所述第一方向上的相对两侧，使各器件层中的沟道限定层相对于第一源/漏层和第二源/漏层在所述第一方向上凹进，并在由此得到的第一空隙中形成第一牺牲栅；
    在所述堆叠在与所述第一方向相交的第二方向上的一侧，使各器件层中的沟道限定层相对于第一源/漏层和第二源/漏层在所述第二方向上凹进，并得到第二空隙；
    在各沟道限定层的凹进的侧壁上形成沟道层；
    在所述第二空隙中形成所述沟道层之后的空间中形成第二牺牲栅；
    在所述堆叠在所述第二方向上的所述一侧，在各器件层中形成阶梯结构：各第二牺牲栅相对于相应器件层中的第二源/漏层形成子台阶；
    在所述堆叠在所述第二方向上与所述一侧相对的另一侧，通过选择性刻蚀，去除所述沟道限定层，并在由此得到的第三空隙中形成第三牺牲栅；
    在所述堆叠在所述第二方向上的所述另一侧，在各器件层中形成阶梯结构：同一器件层中的第一源/漏层相对于第二源/漏层和沟道限定层形成子台阶，所述子台阶在相应器件层所形成的台阶上；以及
    将所述第一牺牲栅、所述第二牺牲栅和所述第三牺牲栅替换为栅堆叠。
  26. 根据权利要求25所述的方法，其中，所述堆叠通过外延生长来设置。
  27. 根据权利要求25所述的方法，其中，每个器件层还包括隔离限定层，所述第一源/漏层、所述沟道限定层和所述第二源/漏层设于所述隔离限定层上，
    该方法还包括：在所述堆叠在所述第二方向上的所述另一侧，通过选择性刻蚀，去除所述隔离限定层，并在由此得到的空隙中填充隔离材料以形成隔离层。
  28. 根据权利要求27所述的方法，其中，所述隔离限定层在竖直方向上的厚度小于所述沟道限定层在竖直方向上的厚度。
  29. 根据权利要求25所述的方法，其中，形成阶梯结构包括：
    (a)在所述堆叠上形成沿所述第二方向延伸的条形垫层；
    (b)在所述堆叠上形成沿所述第二方向延伸的条形光刻胶，所述光刻胶在所述第一方向上的边缘部分与所述垫层交迭；
    (c)以所述垫层和所述光刻胶为刻蚀掩模，将所述堆叠刻蚀一定深度；
    (d)修整所述光刻胶，使其在第一方向上的宽度缩减；
    (e)以所述垫层和修整后的所述光刻胶为刻蚀掩模，将所述堆叠刻蚀一定深度；以及
    (f)重复(d)和(e)，直至形成所述阶梯结构。
  30. 根据权利要求29所述的方法，其中，在(c)中，刻蚀的深度为D 1+D STI，且在(f)中重复(e)时，每次刻蚀的深度依次为D 2、...、D n，其中，D i表示从下往上第i器件层在竖直方向上的厚度，i为从1到n的整数，D STI表示要形成的浅沟槽隔离的深度。
  31. 根据权利要求29所述的方法，其中，至少在最后一次修整之前，修整后的光刻胶与所述垫层在第一方向上不分离。
  32. 根据权利要求31所述的方法，其中，最后一次修整包括去除所述光刻胶。
  33. 根据权利要求29所述的方法，其中，
    所述垫层在所述第一方向上的宽度为W，在竖直方向上的高度为H，满足(H+W)＞(W 1-W n-1)，其中，W 1表示在形成所述阶梯结构之后从下往上第1器件层在所述第一方向上的宽度，W n-1表示在形成所述阶梯结构之后从下往上第(n-1)器件层在所述第一方向上的宽度，
    所述光刻胶在竖直方向上的厚度大于(H+W)。
  34. 根据权利要求25所述的方法，还包括：
    通过所述第二空隙，将所述沟道限定层以及第一源/漏层和第二源/漏层刻蚀一定深度，以加大所述第二空隙，
    其中，形成的沟道层的厚度实质上等于被刻蚀的所述深度。
  35. 根据权利要求25所述的方法，其中，在各器件层中形成阶梯结构包括：
    通过选择性刻蚀，去除各器件层的第二源/漏层的暴露部分在所述第二方向上的端部区域，并去除由于所述端部区域的去除而露出的第三牺牲栅的部分，以露出下方的第一源/漏层。
  36. 一种电子设备，包括如权利要求1至24中任一项所述的半导体装置。
  37. 根据权利要求36所述的电子设备，其中，所述电子设备包括智能电话、个人计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
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