A7 416143 B7_____ 五、發明說明（/) 發明領域： 本發明係關於一種電容器接觸節點的製作方法，尤其是 指一種摻雜濃度具梯度分佈之複晶砂節點插塞的製作方法。 發明背景： 近年來’隨著積體電路積集密度的快速增加及元件體積 的縮小，明顯改善了半導體元件的性能，並減少電子產品的 生產成本，故傳統常被用於製作積體電路元件的製程方法， 不斷的被許多相關領域的硏究人員加以改進或更新。積體電 路元件中積集度高的動態隨機存取記憶體（DRAM)，對於 製程中的每一步驟要求皆非常嚴格，致力於提高元件電性動 作速度及產品的良率以降低其生產成本。 一般在一個DRAM晶片上，除了記憶體元件區外，尙有 與記憶元件緊密排列並負責讀/寫功能之電路環繞在周圍， DRAM晶片中之記憶細胞（cell)係包含一存取電晶體（通 常爲場效應電晶體）與一儲存電容器，而所述之儲存電容器 係有一接觸節點，一端接於場效應電晶體之汲極或源極區 域。在習知DRAM晶片之電容結構製程中，所述接觸節點具 有多種不同之製作方法，以下將利用圖一習知技藝製作動態 隨機存取記憶體元件之結構剖面示意圖來說明習知技藝中電 容器接觸節點的製作方法。首先，提供一已具有可隔離各個 元件的淺渠溝隔離（ShallowTrench Isolation; STI)區域（圖 中未示）及電晶體結構的半導體基板10，所述電晶體結構係 包含：於基板10上形成一個由閘氧化層12、複晶矽閘極結構 14、氮化矽層16、已接雜源極/汲極區域（圖中未示）及閘 2 ------------- 裝--------訂· (請V ,f背面之注意事項再填寫本頁) 緩濟部智慧財產局員工消費合作社印裂 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) 416143 A7 ____B7 _ 五、發明說明（J ) 極間隙壁18所共同組成，接著’丨几積~~'介電層20，並於所述 介電層20中之所述電晶體間定義出電容器接觸節點窗口 (node contact window);然後，依序形成—重接雜複晶;^層 22及一輕接雜複晶砂層24，並回飽亥||移除所述介電層2〇上之 所述輕摻雜複晶砍層24及所述重摻雜複晶政層22，得到一電 容器接觸節點插塞；再接著，完成位元線（bit line)(圖中 未不）及第—接觸節點插塞28的製作；最後，依序完成電容 器下層電極32、電容器介電層及電容器上層電極的製作。其 中所述摻雜雜質之複晶砂複層結構22,24可以單一之輕摻雜 複晶矽層或單一之重摻雜複晶矽層取代，亦可利用離子佈植 法（ion implant)將雜質植入所述複晶砂材質之接觸節點插 塞中，然而，當利用重摻雜複晶矽製作所述接觸節點插塞時， 雖然可提供較佳之導電性，但所述重摻雜複晶矽插塞表面於 大氣中卻容易氧化，使得其與後續製作之導電層界面接觸不 良；反之，當利用輕摻雜複晶矽製作所述接觸節點插塞時， 則會因所述複晶矽僅爲輕摻雜，故導電彳生較差，使得所述接 觸卽點插塞之接觸電阻（contactresistance)因而提高；而對 利用離子佈植法將雜質植入所述接觸節點插塞之方式，則因 所述接觸節麵塞中之雜質僅分佈在某段區域’撕述接觸 節點插塞中主要仍爲輕摻雜狀態，所以其接觸電阻亦過高， Jit外’離子佈植法將會破壞所述接觸節點插塞表面之晶格結 構’導致較高的氧化現象，是以上述習知技藝之電容器接觸 節點差之製作方法皆非極佳之選擇，故本發明揭露一種摻雜 濃度具梯度分佈之複晶矽節點插塞的製作方法，可以同時具 ____3 _ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請讀背面之注意事項再填寫本頁) 裝： 訂· 組濟部智慧財產局員工消費合作杜印製 416143 A7 __B7___ 五、發明說明（$ ) 有重摻雜複晶矽導電性較佳及輕摻雜複晶矽表面不易氧化的 優點。 發明之槪述： 本發明之主要目的是提供一種摻雜濃度具梯度分佈之複 晶矽電容器接觸節點插塞的製作方法。 本發明之次要目的是提供一具較佳導電性之電容器接觸 節點插塞的製作方法。 本發明之又一目的是提供一表面不易氧化之電容器接觸 節麵塞的製作方法。 經濟部智慧財產局員工消費合作社印製 -----------'裝--------訂· <先閲讀背面之注意事項再填寫本頁) 本發明係使用下列步驟來達到上述之各項目的：首先’ 提供一半導體基板，所述基板上已形成有用來隔離各個元件 的淺渠溝隔離及電晶體結構；接著，沉積一介電層，並於所 述介電層中之所述電晶體間定義出第一電容器接觸節點窗 口；然後，依序形成一重摻雜複晶矽層塡滿所述第一電容器 接觸節點窗口，及一輕摻雜複晶矽層於所述重摻雜複晶矽層 上；再接著，利用熱處理使雜質由高濃度摻雜之複晶矽層向 低濃度摻雜之複晶矽層擴散，並回蝕刻移除所述介電層上之 所述輕摻雜複晶砂層及所述重摻雜複晶矽層；再接著，完成 位元線及第二接觸節點插塞的製作；最後，依序完成電容器 下層電極、電容器介電層及電容器上層電極的製作。 圖式簡要說明： 圖一爲習知技藝製作動態隨機存取記憶體元件中電 容器接觸節點插塞結構之剖面示意圖。 圖二A爲本發明實施例中於一已完成半導體前段製程並 4 各紙張尺度適用中國國家標準（CNSXA4規格（210 X 297公釐） 416143 A7 __B7_ 五、發明說明（+) 定義出接觸窗口之基板上依序沉積一第一複晶矽 層及一第二複晶矽層之剖面示意圖。 {請先閱讀背面之注意事項再填寫本頁) 圖二B爲本發明實施例中所述基板經熱處理後，回蝕刻 移除所述介電層表面上方之所述第一複晶矽層及 一第二複晶矽層之剖面示意圖。 圖二C爲本發明實施例中於第一電容器接觸節點插塞上 形成第二電容器接觸節點插塞及電容器下層電極 之剖面示意圖。 圖號說明： 10-基板 14-複晶矽閘極結構 18-閘極間隙壁 22-重摻雜複晶政層 26-介電層 30-介電層 40-基板 經濟部智慧財產局員工消費合作社印製 12·閘氧化層 16-氮化矽層* 20-介電層 24-輕摻雜複晶矽層 28-第二接觸節點插塞 32-電容器下層電極 42-閘氧化層 46-氮化矽層 50-介電層 52a-第一複晶矽插塞 56-介電層 60-介電層 44-複晶矽閘極結構 48-閘極間隙壁 52-第一複晶矽層 54-第二複晶矽層 58-第__複晶砂插塞 62·電容器下層電極 發明詳細說明： 以下之實施例將闡述本發明之詳細實施內容，請同時參 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） A7 416143 _B7_____ 五、發明說明（欠） 閱圖二A〜圖二C幫助瞭解本發明： 首先，請參閱圖二A，提供一已完成前段製程的半導體 基板40，所述基板40上形成有用來隔離各個記憶體元件的淺 渠溝隔離（圖中未示）及電晶體結構，其中所述電晶體結構 係爲一個由閘氧化層42、複晶砂鬧極結構44、氦化砂層46、 已摻雜源極/汲極區域（圖中未示）及閘極間隙壁48所組成； 然後，於所述基板40上形成一第一介電層50，並於所述第一 介電層50中之所述電晶體間定義出一接觸窗口爲化學氣相沉 積法（Chemical Vapor Deposition; CVD)形成之氧化砂結 構或其他低介電係數（low 1〇材質；所述第一介電層50之 厚度係介於4000A至10000A之間；。 接下來係爲本發明之重要特徵，係利用化學氣相讎法 (Chemical Vapor Deposition; CVD)先形成一第一複晶砂層 52於所述第一介電層50上並塡滿所述接觸窗口，再形成一第 二複晶矽層54，其中所述第一複晶矽層52係爲一具高濃度雜 質之重摻雜（heavily doped)複晶矽層，其摻雜濃度係介於 1E19原子/平方公分至1E22原子/平方公分之間，厚度係介於 4000A至8000A之間，而所述第二複晶矽層54則爲一未摻雜 複晶矽層或一具低濃度雜質之輕摻雜（lightly doped)複晶 矽層，其摻雜濃度係介於1E17原子/平方公分至1E20原子/平 方公分之間，厚度係介於2000A至4000A ;然後，利用快速 退火（rapid thermal anneal; RTA)或高溫爐管退火（fUmace anneal)進行熱處理，所述熱處理之主要目的在使雜質由高 濃度摻雜之所述第一複晶矽層52向低濃度摻雜之所述第二複 __ 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） (氣先Μ讀背面之注意事項再填寫本頁) 裝： -5j. 經濟部智慧財產局員工消费合作社印^ 416143 A7 __B7____ 五、發明說明（t) 晶矽層54擴散，故所述第一複晶矽層52中摻雜之雜質濃度將 呈現一梯度（gradient)分佈’所述雜質濃度係由所述第一 複晶矽層52之表面向所述基板40方向逐漸增加，其中若選擇 快速退火處理’則其溫度係介於7CKTC至800°C之間，時間係 介於30秒至2分鐘之間，而若選擇高溫爐管退火處理，則其 溫度係介於7〇〇°C至800°C之間’時間係介於30分鐘至2小時 之間。 再接著，請參閱圖一B ’利用化學機械硏磨法（Chemical Mechanical Polish; CMP)硏磨移除所述介電層5〇上之所述第 經濟部智慧財產局員工消費合作社印製 ------------裝--------訂- - ' (請先閱讀背面之注意事項再填寫本頁) 二複晶矽層54及所述第一複晶矽層52，得到第一複晶砂插塞 52a，其中所述第一複晶矽插塞52a即爲所謂之電容器接觸節 點插塞（node contact plug)，此第一複晶砍插塞52a之特徵在 於能同時具有重摻雜複晶矽導電性較佳及輕摻雜複晶矽表面 不易氧化的優點，因爲所述雜質濃度呈梯度分佈之第一複晶 矽插塞52a本身主要仍爲一重摻雜複晶矽層，所以其插塞接 觸電阻（plug contact resistance)較低，可減少電阻造成之 熱累積（thermal budget)程度，亦可具有較佳之導電性；此 外，由於製程中作爲雜質濃度調節層（dosage adjustment layer)之第二複晶矽層54的存在，故在進行所述熱處理製程 時所述第一複晶矽層52表面之雜質將往所述第二複晶矽層54 擴散，使得所述第一複晶矽層52表面之雜質濃度降低，因此 所述第一複晶砍插塞52樣面接觸大氣之部份較不容易被氧 化，減少其與後續製作之導電層界面接觸不良的情形。 最後，請參閱圖二C，在完成位元線（圖中未示）及第 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 416143 _____B7_______ 五、發明說明（7 ) 二複晶矽插塞58的製作後：接著依序完成電容器結構之 製作及，電容器下層電極62、電容器介電層及電容器上層電 極（圖中皆未示）的製作。 以上所述係利用較佳實施例詳細說明本發明，而非限制 本發明的範圍，因此熟知此技藝的人士應tg明瞭，適當而作 些微的改變與調整，仍將不失本發明之要義所在，亦不脫離 本發明之精神和範圍，故都應視爲本發明的進一步實施狀 況。謹請貴審查委員明鑑，並祈惠准，是所至禱。 lll]!llltl. --裝·！— II 訂· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員Η消費合作杜印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）A7 416143 B7_____ V. Description of the invention (/) Field of the invention: The present invention relates to a method for manufacturing a capacitor contact node, and particularly to a method for manufacturing a polycrystalline sand node plug with a gradient distribution of doping concentration. Background of the invention: In recent years, with the rapid increase in the density of integrated circuits and the shrinking of the component volume, the performance of semiconductor components has been significantly improved, and the production cost of electronic products has been reduced. Therefore, it is often used to make integrated circuit components The process method has been continuously improved or updated by researchers in many related fields. The integrated dynamic random access memory (DRAM) in integrated circuit components has very strict requirements for each step in the manufacturing process. It is committed to improving the electrical operating speed of components and the yield of products to reduce their production costs. . Generally on a DRAM chip, in addition to the memory element area, there is a circuit closely arranged with the memory element and responsible for read / write functions. The memory cell in the DRAM chip contains an access transistor ( Usually a field effect transistor) and a storage capacitor, and the storage capacitor has a contact node with one end connected to the drain or source region of the field effect transistor. In the capacitor structure manufacturing process of the conventional DRAM chip, the contact node has a variety of different manufacturing methods. The following is a schematic diagram of the structure of a dynamic random access memory device using the conventional technique to illustrate the capacitor contact in the conventional technique. How to make a node. First, a semiconductor substrate 10 having a Shallow Trench Isolation (STI) region (not shown) that can isolate each element and a transistor structure is provided. The transistor structure includes: formed on the substrate 10 A gate oxide layer 12, a complex silicon gate structure 14, a silicon nitride layer 16, a connected source / drain region (not shown), and a gate 2 ----------- -Packing -------- Order · (please fill in the notes on the back of V and f), please fill in this page (210 X 297 mm) 416143 A7 ____B7 _ V. Description of the invention (J) The electrode spacers 18 are collectively composed, followed by '丨 Jiji ~~' the dielectric layer 20 and the place in the dielectric layer 20 A capacitor contact node window is defined between the transistors described above; then, sequentially formed-re-doped complex crystal; ^ layer 22 and a light-doped complex crystal sand layer 24, and back to full saturation || Remove all The lightly doped polycrystalline cleaved layer 24 and the heavily doped polycrystalline political layer 22 on the dielectric layer 20 are used to obtain a capacitor contact node plug; The production of bit line (not shown in the figure) and the first-contact node plug 28 is completed; finally, the fabrication of the capacitor lower layer electrode 32, the capacitor dielectric layer and the capacitor upper layer electrode are sequentially completed. The impurity-doped polycrystalline sand multi-layer structure 22, 24 may be replaced by a single lightly doped polycrystalline silicon layer or a single heavily doped polycrystalline silicon layer, or an ion implantation method may be used Impurities are implanted into the contact node plugs of the compound sand material. However, when the contact node plugs are made of heavily doped polycrystalline silicon, although the better conductivity is provided, the heavily doped complex The surface of the crystalline silicon plug is easily oxidized in the atmosphere, which makes it in poor contact with the conductive layer produced later. On the contrary, when the contact node plug is made of lightly doped polycrystalline silicon, the polycrystalline silicon plug will Silicon is only lightly doped, so the conductivity is poor, so that the contact resistance of the contact plug is increased; and for the method of implanting impurities into the contact node plug by ion implantation, Because the impurities in the contact surface plug are only distributed in a certain area, the contact node plug is mainly lightly doped, so its contact resistance is too high. Destroy the contact node plug table The “lattice structure” leads to a higher oxidation phenomenon, and the manufacturing method of the poor contact points of capacitors based on the above-mentioned conventional techniques is not an excellent choice. Therefore, the present invention discloses a polycrystalline silicon node insert with a gradient distribution of doping concentration. The production method of the plug can also have ____3 _ This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the precautions on the back and fill in this page). Consumption cooperation with employees of the Property Bureau Du printed 416143 A7 __B7___ 5. Description of the invention ($) There is the advantage that the heavily doped polycrystalline silicon has better conductivity and the surface of the lightly doped polycrystalline silicon is not easily oxidized. Summary of the Invention: The main object of the present invention is to provide a method for manufacturing a contact plug for a polycrystalline silicon capacitor with a doped concentration gradient distribution. A secondary object of the present invention is to provide a method for manufacturing a capacitor contact node plug with better conductivity. Another object of the present invention is to provide a method for manufacturing a capacitor contact plug with a surface that is not easily oxidized. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ----------- 'Installation -------- Order < Read the precautions on the back before filling this page) This invention is used The following steps are to achieve the above-mentioned items: first, a semiconductor substrate is provided, on which a shallow trench isolation and a transistor structure for isolating various elements have been formed; then, a dielectric layer is deposited, and A first capacitor contact node window is defined between the transistors in the dielectric layer; then, a heavily doped polycrystalline silicon layer is sequentially formed to fill the first capacitor contact node window, and a lightly doped polycrystalline silicon is formed. Layer on the heavily doped polycrystalline silicon layer; then, heat treatment is used to diffuse impurities from the high-concentration doped polycrystalline silicon layer to the low-concentration doped polycrystalline silicon layer, and etch back to remove the dielectric The lightly doped polycrystalline sand layer and the heavily doped polycrystalline silicon layer on the electrical layer; then, the bit line and the second contact node plug are completed; finally, the capacitor lower electrode and the capacitor are sequentially completed Fabrication of dielectric layer and capacitor upper electrode. Brief description of the drawings: Figure 1 is a schematic cross-sectional view of a plug structure of a contact node of a capacitor in a dynamic random access memory device produced by a conventional technique. Fig. 2A shows a semiconductor front-end process that has been completed in an embodiment of the present invention and 4 paper sizes are applicable to Chinese national standards (CNSXA4 specification (210 X 297 mm)) 416143 A7 __B7_ V. Description of the invention (+) Define the contact window A schematic cross-sectional view of a first polycrystalline silicon layer and a second polycrystalline silicon layer sequentially deposited on the substrate. {Please read the precautions on the back before filling this page.) Figure 2B shows the substrate process described in the embodiment of the present invention. After the heat treatment, the cross-sectional schematic diagram of the first polycrystalline silicon layer and a second polycrystalline silicon layer above the surface of the dielectric layer is etched back. FIG. 2C is a schematic cross-sectional view of forming a second capacitor contact node plug and a capacitor lower electrode on a first capacitor contact node plug according to an embodiment of the present invention. Description of drawing number: 10-substrate 14-polycrystalline silicon gate structure 18-gate spacer 22-heavy doped polycrystalline layer 26-dielectric layer 30-dielectric layer 40-substrate Intellectual Property Bureau of the Ministry of Economic Affairs employee consumption Cooperative printed 12 · gate oxide layer 16-silicon nitride layer * 20-dielectric layer 24-lightly doped polycrystalline silicon layer 28-second contact node plug 32-capacitor lower layer electrode 42-gate oxide layer 46-nitrogen Siliconized layer 50-dielectric layer 52a-first polycrystalline silicon plug 56-dielectric layer 60-dielectric layer 44-polycrystalline silicon gate structure 48-gate spacer 52-first polycrystalline silicon layer 54 -Second polycrystalline silicon layer 58 -__ polycrystalline sand plug 62 · Detailed description of capacitor lower electrode invention: The following examples will explain the detailed implementation of the present invention. Please also refer to this paper to apply Chinese national standards ( CNS) A4 specification (210x 297 mm) A7 416143 _B7_____ 5. Description of the invention (under) Please refer to Figure 2A to Figure 2C to help understand the invention: First, please refer to Figure 2A to provide a semiconductor substrate that has completed the previous process 40. A shallow trench isolation (not shown) and a transistor junction for isolating each memory element are formed on the substrate 40. Wherein, the transistor structure is a gate oxide layer 42, a polycrystalline sand anode structure 44, a helium sand layer 46, a doped source / drain region (not shown), and a gate spacer 48. And then forming a first dielectric layer 50 on the substrate 40 and defining a contact window between the transistors in the first dielectric layer 50 as a chemical vapor deposition method (Chemical Vapor Deposition) Vapor Deposition; CVD) or other low-dielectric-constant (low 10) materials; the thickness of the first dielectric layer 50 is between 4000A and 10000A. The following is an important aspect of the present invention. A feature is that a first chemical compound sand layer 52 is first formed on the first dielectric layer 50 and filled with the contact window by using a chemical vapor deposition (CVD) method, and then a second compound crystal is formed. Silicon layer 54, wherein the first polycrystalline silicon layer 52 is a heavily doped polycrystalline silicon layer with a high concentration of impurities, and its doping concentration ranges from 1E19 atoms / cm2 to 1E22 atoms / Between the square centimeters, the thickness is between 4000A and 8000A, and the second polycrystalline silicon 54 is an undoped polycrystalline silicon layer or a lightly doped polycrystalline silicon layer with a low concentration of impurities, and its doping concentration is between 1E17 atoms / cm 2 to 1E20 atoms / cm 2 The thickness is between 2000A and 4000A; then, rapid thermal annealing (RTA) or high temperature furnace annealing (fUmace anneal) is used for heat treatment. The main purpose of the heat treatment is to make impurities doped from high concentration. The second complex of the first polycrystalline silicon layer 52 is doped to a low concentration __ 6 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 cm). (Fill in this page) Pack: -5j. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy ^ 416143 A7 __B7____ V. Description of the Invention (t) The crystalline silicon layer 54 diffuses, so the impurity in the first polycrystalline silicon layer 52 is doped The concentration will show a gradient distribution. The impurity concentration is gradually increased from the surface of the first polycrystalline silicon layer 52 to the substrate 40. If a rapid annealing process is selected, the temperature is between 7CKTC. Time to 800 ° C Between 30-2 seconds, and if the selected temperature furnace annealing process, a temperature of which is interposed between 7〇〇 ° C to 800 ° C 'between time lines 30-2 minutes. Then, please refer to FIG. 1B. “Chemical Mechanical Polish (CMP) honing method is used to remove the dielectric layer 50. The printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economy- ---------- Installation -------- Order--'(Please read the precautions on the back before filling this page) The second polycrystalline silicon layer 54 and the first polycrystalline silicon Layer 52 to obtain a first polycrystalline sand plug 52a, wherein the first polycrystalline silicon plug 52a is a so-called capacitor contact node plug, and features of the first polycrystalline cutting plug 52a It has the advantages of better conductivity of heavily doped polycrystalline silicon and less oxidation of the surface of lightly doped polycrystalline silicon, because the first polycrystalline silicon plug 52a with a gradient distribution of the impurity concentration is still mainly a heavily doped Heteropoly silicon layer, so its plug contact resistance is low, which can reduce the degree of thermal budget caused by resistance, and it can also have better conductivity; In addition, it is used as an impurity concentration adjustment during the manufacturing process. Layer (dosage adjustment layer) of the second polycrystalline silicon layer 54 During the heat treatment process, impurities on the surface of the first polycrystalline silicon layer 52 will diffuse toward the second polycrystalline silicon layer 54, so that the impurity concentration on the surface of the first polycrystalline silicon layer 52 will be reduced. The part of a polycrystalline cleave plug 52 that is in contact with the atmosphere is less likely to be oxidized, which reduces the poor contact with the conductive layer produced later. Finally, please refer to Figure 2C. The completed bit line (not shown) and the 7th paper size are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 416143 _____B7_______ V. Description of the invention (7) After the fabrication of the double-crystal silicon plug 58: the fabrication of the capacitor structure and the fabrication of the capacitor lower layer electrode 62, the capacitor dielectric layer, and the capacitor upper layer electrode (not shown) are sequentially completed. The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention. Therefore, those skilled in the art should understand that making small changes and adjustments appropriately will still lose the essence of the present invention. Without departing from the spirit and scope of the present invention, it should be regarded as a further implementation status of the present invention. I would like to ask your reviewers to make a clear reference and pray for your sincere prayer. lll]! llltl. --Equipped! — Order II · (Please read the notes on the back before filling this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumption Cooperation. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)