WO2023221187A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2023221187A1
WO2023221187A1 PCT/CN2022/096758 CN2022096758W WO2023221187A1 WO 2023221187 A1 WO2023221187 A1 WO 2023221187A1 CN 2022096758 W CN2022096758 W CN 2022096758W WO 2023221187 A1 WO2023221187 A1 WO 2023221187A1
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Prior art keywords
word line
groove
word lines
forming
substrate
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PCT/CN2022/096758
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English (en)
French (fr)
Inventor
肖德元
蒋懿
邵光速
苏星松
邱云松
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长鑫存储技术有限公司
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Priority to US17/940,923 priority Critical patent/US20230005919A1/en
Publication of WO2023221187A1 publication Critical patent/WO2023221187A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or writing data information into the capacitor.
  • the semiconductor structure and its formation method provided by some embodiments of the present disclosure are used to reduce the coupling effect between adjacent word lines, thereby improving the performance of the memory and increasing the yield of the memory.
  • the present disclosure provides a semiconductor structure, including: a substrate; a plurality of active pillars located in the substrate, the plurality of active pillars arranged in an array along a first direction and a second direction. cloth, the first direction and the second direction are both directions parallel to the top surface of the substrate, and the first direction intersects the second direction; a plurality of word lines, a plurality of the The word lines are arranged at intervals along the first direction, and each of the word lines extends along the second direction and continuously covers part of the sidewalls of the plurality of active pillars arranged along the second direction. , in a direction perpendicular to the top surface of the substrate, any two adjacent word lines are at least partially staggered.
  • some of the word lines among the plurality of word lines are first word lines, and some of the word lines are second word lines; for the plurality of word lines arranged along the first direction, The active pillar, the first word line covers part of the sidewall of the active pillar of the first parity sequence, and the second word line covers part of the active pillar of the second parity sequence. side walls.
  • the top surface of the first word line is located below the bottom surface of the second word line; or, the top surface of the first word line is located above the bottom surface of the second word line. And the top surface of the first word line is located below the top surface of the second word line.
  • the top surface of the first word line is located below the bottom surface of the second word line, and there is a predetermined gap between the top surface of the first word line and the bottom surface of the second word line. gap, and in a direction perpendicular to the top surface of the substrate, the width of the preset gap is 1/4 to 1/2 of the size of the first word line.
  • the active pillar includes a source region, a channel region and a drain region sequentially arranged in a direction perpendicular to the top surface of the substrate, and each of the word lines continuously covers an edge along the the channel region of the plurality of active pillars arranged in the second direction;
  • the semiconductor structure also includes: a plurality of bit lines located in the substrate, the plurality of bit lines along the The bit lines are arranged at intervals in the second direction, and each of the bit lines extends along the first direction and is electrically connected to the source regions of the plurality of active pillars arranged along the first direction.
  • it further includes: an insulating layer covering the sidewalls of the source region; a gate dielectric layer covering the sidewalls of the channel region and the sidewalls of the drain region,
  • the word line is located on the surface of the gate dielectric layer on the channel region;
  • an isolation layer is located between the adjacent active pillars and covers the surface of the insulating layer, the surface of the word line and The surface of the gate dielectric layer on the sidewall of the drain region.
  • the word lines are all equal in size in a direction perpendicular to the top surface of the substrate.
  • some of the word lines among the plurality of word lines are first word lines, some of the word lines are second word lines, and some of the word lines are third word lines; for A plurality of the active pillars are arranged in the first direction, the first word line covers part of the sidewall of the active pillar at the 3nth position, and the second word line covers the 3n+1th The third word line covers part of the sidewall of the active pillar of the 3n+2th bit, where n is an integer greater than or equal to 0.
  • the present disclosure also provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of active pillars in the substrate, the plurality of active pillars extending along a first direction and The second direction is arranged in an array, the first direction and the second direction are both directions parallel to the top surface of the substrate, and the first direction intersects the second direction; and a plurality of A plurality of word lines are arranged at intervals along the first direction. Each of the word lines extends along the second direction and continuously covers a plurality of the word lines arranged along the second direction. On part of the sidewalls of the active pillar, any two adjacent word lines are at least partially staggered in a direction perpendicular to the top surface of the substrate.
  • forming the plurality of active pillars in the substrate includes etching the substrate to form a plurality of first trenches along the first trench. Arranged at intervals in two directions, each of the first trenches extends along the first direction; forming a first filling layer filling the plurality of first trenches; and etching the substrate to form a plurality of Second grooves, the plurality of second grooves are arranged at intervals along the first direction, and each of the second grooves extends along the second direction.
  • the method further includes: forming an insulating layer covering top surfaces and side surfaces of the plurality of active pillars; A plurality of bit lines are formed in the substrate, and the plurality of bit lines are arranged at intervals along the second direction. Each of the bit lines extends along the first direction and is arranged along the first direction. The bottom contacts of a plurality of the active posts are electrically connected.
  • the material of the active pillar is silicon, and a silicon metallization process is used to form the plurality of bit lines.
  • some of the word lines among the plurality of word lines are first word lines, and some of the word lines are second word lines; for the plurality of word lines arranged along the first direction, The active pillar, the first word line covers part of the sidewall of the active pillar of the first parity sequence, and the second word line covers part of the active pillar of the second parity sequence. side walls.
  • forming the plurality of word lines includes: forming the plurality of word lines includes: forming an isolation layer that fills the second trench and covers the surface of the insulating layer; etching a portion The insulating layer forms a second groove between the active pillar of the second parity sequence and the isolation layer; forming a second word line located in the second groove; and etching The insulating layer of the first parity sequence is etched to form a first groove between the active pillar of the first parity sequence and the isolation layer. The depth of the first groove is consistent with that of the second groove. The depths of the grooves are different; a first word line is formed in the first groove, and the second word line is staggered from the first word line in a direction perpendicular to the top surface of the substrate. .
  • forming a second word line located in the second groove includes: forming an initial second word line that fills the second groove; and etching back a portion of the initial second word line. line to form the second word line and a third groove located above the second word line; forming a second filling layer that fills the third groove.
  • the bottom surface of the first groove is located above the bottom surface of the second groove, and the bottom surface of the first groove is located below the top surface of the second word line; or, The bottom surface of the first groove is located above the top surface of the second word line.
  • forming the first word line located in the first groove includes: forming an initial first word line that fills the first groove; and etching back a portion of the initial first word line. lines to form the first word line and a fourth groove located above the first word line; forming a third filling layer that fills the fourth groove.
  • forming the plurality of word lines includes: forming an isolation layer that fills the second trench and covers the surface of the insulating layer; etching the insulating layer to form an isolation layer located on the second trench; a second groove between the active pillars of the parity sequence and the isolation layer, and a first groove between the active pillars of the first parity sequence and the isolation layer, The first groove and the second groove have different depths; a second word line is formed in the second groove, and a first word line is formed in the first groove, with an edge perpendicular to the In the direction of the top surface of the substrate, the second word line and the first word line are staggered.
  • the second groove is formed between the active pillars of the second parity sequence and the isolation layer, and the active pillars of the first parity sequence and the first groove between the isolation layer, including: etching the insulating layer between the active pillar of the second parity sequence and the isolation layer to form an initial second Grooves; etching the insulating layer between the active pillars of the first parity sequence and the isolation layer and the insulating layer at the bottom of the initial second groove to respectively form the the first groove and the second groove.
  • forming a first word line in the first groove and forming a second word line in the second groove includes depositing and filling the first groove and the second word line. Conductive material layers in two grooves; etching back the conductive material layer in the second groove; etching back the conductive material layer in the second groove and the first groove again, The conductive material layer remaining in the second groove forms the second word line, and the conductive material layer remaining in the first groove forms the first word line.
  • Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.
  • any two adjacent word lines By controlling any two adjacent word lines to be at least partially staggered in a direction perpendicular to the top surface of the substrate, such that any adjacent word lines are at least partially staggered.
  • the heights of the two word lines are different to reduce the facing area between adjacent word lines, so as to achieve the effect of reducing the capacitive coupling effect between the two adjacent word lines.
  • the present disclosure only needs to adjust the number of etching processes to make any two adjacent word lines at least partially staggered. The manufacturing process is simple and easy to implement and control.
  • FIG. 1 is a schematic top view of a semiconductor structure in a specific embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of a semiconductor structure in a specific embodiment of the present disclosure
  • FIG. 3 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure
  • FIG. 4 is a schematic top view of a semiconductor structure formed according to specific embodiments of the present disclosure.
  • 5A-5N are schematic diagrams of the main processes in the process of forming a semiconductor structure according to an embodiment of the present disclosure
  • 6A-6H are schematic diagrams of main processes in the process of forming a semiconductor structure according to another embodiment of the present disclosure.
  • FIGS. 1 and 2 the semiconductor structure includes: a substrate 20 , a plurality of active pillars 12 and a plurality of word lines.
  • the plurality of active pillars 12 are located in the substrate 20 .
  • the plurality of active pillars 12 are arranged in an array along the first direction and the second direction.
  • the first direction a-a' and the third direction are arranged in an array.
  • the two directions c-c' are both directions parallel to the top surface 201 of the substrate 20, and the first direction a-a' intersects the second direction c-c'.
  • a plurality of the word lines are arranged at intervals along the first direction a-a', each of the word lines extends along the second direction c-c', and continuously covers the second direction c- c'
  • any two adjacent word lines are at least partially staggered in a direction perpendicular to the top surface 201 of the substrate 20 .
  • the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment will be described by taking the substrate as a silicon substrate as an example. In other embodiments, the substrate 20 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI.
  • the substrate 20 includes the top surface 201 and a bottom surface 202 opposite to the top surface.
  • a plurality of active pillars 12 are arranged in an array along the first direction a-a' and the second direction c-c' in the substrate 20, and each active pillar 12 is arranged along a vertical direction. Extending in the direction of the top surface 201 of the substrate 20 .
  • a plurality of the word lines are located inside the substrate 20 , each of the word lines extends along the second direction c-c', and continuously covers the words arranged along the second direction c-c'.
  • a plurality of partial sidewalls of the active pillars 12 and a plurality of word lines are arranged at intervals along the first direction a-a'.
  • the intersection may be a vertical intersection or an oblique intersection. In this specific embodiment, the intersection is a vertical intersection as an example for description.
  • any two adjacent word lines are at least partially staggered in a direction perpendicular to the top surface 201 of the substrate 20 so that any two adjacent word lines are at Different horizontal heights, thereby reducing the facing area between any two adjacent word lines, thereby reducing the capacitive coupling effect between any adjacent word lines, so that the two adjacent word lines
  • the other word line will not be turned on due to the capacitive coupling effect, reducing or even avoiding leakage problems between adjacent memory cells, thus improving the quality of the semiconductor structure. electrical properties.
  • some of the word lines among the plurality of word lines are first word lines 111, and some of the word lines are second word lines 112; for along the first direction a-a' A plurality of the active pillars 12 are arranged, the first word line 111 covers part of the sidewall of the active pillar 12 of the first parity sequence, and the second word line 112 covers the second parity sequence. part of the sidewall of the active column 12 of the sexual sequence.
  • the first parity sequence may be an odd sequence
  • the second parity sequence may be an even sequence
  • the first word line 111 covers part of the sidewall of the active pillar 12 of the first parity sequence
  • the second word line 112 covers the active pillar 12 of the second parity sequence.
  • the partial sidewalls refer to that, after sequentially sorting the plurality of active pillars 12 arranged along the first direction a-a', the partial sidewalls of the active pillars 12 located at odd-numbered positions are The first word line 111 covers, and part of the sidewall of the active pillar 12 located at the even numbered position is covered by the second word line 112 .
  • the first word line 111 and the second word line 112 are at least partially offset.
  • the first parity sequence may also be an even sequence
  • the second parity sequence may also be an odd sequence.
  • the projection of the first word line 111 in a direction perpendicular to the top surface 201 of the substrate 20 and the projection of the second word line 112 in a direction perpendicular to the top surface 201 of the substrate 20 can be The alternate arrangement helps to simplify the formation process of the word lines and reduce the manufacturing difficulty of the semiconductor structure.
  • the top surface of the first word line 111 is located below the bottom surface of the second word line 112; or, the top surface of the first word line 111 is located below the second word line 112. Above the bottom surface, and the top surface of the first word line 111 is located below the top surface of the second word line 112 .
  • the top surface of the first word line 111 is located below the bottom surface of the second word line 112 , that is, the first word line 111 and the second word line 112 are in a vertical direction.
  • the first word line 111 and the second word line 112 are completely offset in the direction perpendicular to the top surface 201 of the substrate 20 . overlap, thereby minimizing the capacitive coupling effect between the adjacent first word line 111 and the second word line 112 .
  • the top surface of the first word line 111 is located on the bottom surface of the second word line 112
  • the top surface of the first word line 111 is located on the bottom surface of the second word line 112 .
  • the first word line 111 and the second word line 112 are partially staggered in a direction perpendicular to the top surface 201 of the substrate 20 .
  • the second word lines 112 partially overlap in a direction perpendicular to the top surface 201 of the substrate 20, thereby reducing the capacitance between the adjacent first word lines 111 and the second word lines 112.
  • the coupling effect also helps reduce the size of the semiconductor structure.
  • the word lines are all equal in size in a direction perpendicular to the top surface 201 of the substrate 20 .
  • all the first word lines 111 have the same size
  • all the second word lines 112 have the same size
  • any one of the first word lines 111 has the same size.
  • the size of the first word line 111 is also equal to the size of any of the second word lines 112 .
  • the top surface of the first word line 111 and the second word line 112 do not overlap at all.
  • the width of the preset gap between the bottom surfaces of the two word lines 112 should not be too large, otherwise the size and manufacturing cost of the semiconductor structure will increase.
  • the top surface of the first word line 111 is located below the bottom surface of the second word line 112 , and the top surface of the first word line 111 and the bottom surface of the second word line 112 are between There is a preset gap between them, and in a direction perpendicular to the top surface 201 of the substrate 20 , the width of the preset gap is 1/4 to 1/2 of the size of the first word line 111 .
  • the size of the first word line 111 may be the height of the first word line 111 in a direction perpendicular to the top surface 201 of the substrate 20 .
  • the active pillar 12 includes a source region, a channel region and a drain region sequentially arranged in a direction perpendicular to the top surface 201 of the substrate 20 , and each of the word lines is continuous.
  • the channel region covering the plurality of active pillars 12 arranged along the second direction c-c'; the semiconductor structure also includes: a plurality of bit lines 10 located in the substrate 20 , the plurality of bit lines 10 are arranged at intervals along the second direction c-c', each of the bit lines 10 extends along the first direction a-a', and is similar to that along the first direction a.
  • the source regions of the plurality of active pillars 12 arranged in -a' are contacted and electrically connected.
  • the substrate 20 includes a plurality of bit lines 10 , and the bit lines 10 are located below the word lines.
  • Each of the bit lines 10 extends along the first direction a-a', and a plurality of the bit lines 10 are arranged at intervals along the second direction c-c'.
  • Each bit line 10 is electrically connected to the source regions of a plurality of active pillars 12 arranged along the first direction a-a'.
  • the semiconductor structure further includes: an insulating layer 15 covering the sidewalls of the source region; a gate dielectric layer 14 covering the sidewalls of the channel region and the drain region.
  • the sidewalls of the word line are located on the surface of the gate dielectric layer 14 on the channel region; the isolation layer 13 is located between the adjacent active pillars 12 and covers the insulating layer 15 , the surface of the word line and the surface of the gate dielectric layer 14 of the sidewalls of the drain region.
  • the isolation layer 13 is used to electrically isolate adjacent word lines.
  • the isolation layer 13 is used to electrically isolate the first word lines 111 adjacent along the first direction a-a'. and the second word line 112.
  • the material of the isolation layer 13 may be, but is not limited to, a nitride material, such as silicon nitride.
  • the insulating layer 15 covers the sidewalls of the source region and part of the top surface of the bit line 10, and the isolation layer 13 covers the surface of the insulating layer 15 and part of the top surface of the bit line 10,
  • the word line and the bit line 10 are electrically isolated by the insulating layer 15 and the isolation layer 13 .
  • the material of the insulating layer 15 may be, but is not limited to, an oxide material, such as silicon dioxide.
  • word lines among the plurality of word lines are first word lines
  • some of the word lines are second word lines
  • some of the word lines are third word lines; for A plurality of active pillars 12 are arranged along the first direction, the first word line covers part of the sidewall of the active pillar 12 at the 3nth position, and the second word line covers the Part of the sidewall of the active pillar 12 at position 3n+1, and the third word line covers part of the sidewall of the active pillar 12 at position 3n+2, where n is greater than or equal to 0. integer.
  • the first word line, the second word line and the third word line, and the first word line, the second word line, the third word line Three word lines are alternately arranged along the first direction.
  • the first word line, the second word line, and the third word line Any two of them are at least partially staggered, that is, in a direction perpendicular to the top surface 201 of the substrate 20 , the horizontal levels of the first word line, the second word line and the third word line are The heights are all different.
  • the first word line, the second word line and the third word line with different horizontal heights, the coupling effect between the word lines on adjacent active pillars 12 is reduced. At the same time, it also helps to improve the integration level of the semiconductor structure.
  • FIG. 3 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure.
  • Figure 4 is a schematic top view of a semiconductor structure formed in a specific embodiment of the present disclosure.
  • 5A-5N are schematic diagrams of the main processes in the process of forming a semiconductor structure according to an embodiment of the present disclosure.
  • FIGS. 6A-6H are schematic diagrams of the main processes in the process of forming a semiconductor structure according to another embodiment of the present disclosure. Main process diagram.
  • Figures 5A to 5N and Figures 6A to 6H respectively show the four directions of a-a', b-b', c-c' and d-d' in Figure 4.
  • FIGS. 1 and 2 A schematic cross-sectional view of the main process during the formation of the semiconductor structure to clearly illustrate the formation process of the semiconductor structure.
  • Schematic diagrams of the semiconductor structure formed in this specific embodiment can be seen in FIGS. 1 and 2 .
  • the semiconductor structure described in this specific embodiment may be, but is not limited to, a memory, such as DRAM.
  • the method of forming a semiconductor structure includes the following steps S31 to S33.
  • step S31 a substrate 20 is provided, as shown in FIG. 5A.
  • the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment will be described by taking the substrate as a silicon substrate as an example. In other embodiments, the substrate 20 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI.
  • the substrate 20 includes the top surface 201 and a bottom surface 202 opposite to the top surface.
  • Step S32 Form a plurality of active pillars 12 in the substrate 20.
  • the plurality of active pillars 12 are arranged in an array along the first direction a-a' and the second direction c-c'.
  • the first direction a-a' and the second direction c-c' are both directions parallel to the top surface 201 of the substrate 20 , and the first direction a-a' and the second direction c- c' intersects.
  • forming the plurality of active pillars 12 in the substrate 20 includes: etching the substrate 20 to form a plurality of first trenches along which the plurality of first trenches are formed.
  • the second directions c-c' are arranged at intervals, and each of the first trenches extends along the third direction bb'; forming a first filling layer 21 filled with the plurality of first trenches, such as As shown in Figure 5B; and etching the substrate 20 to form a plurality of second trenches 23, the plurality of second trenches are arranged at intervals along the first direction a-a', each of the first The two grooves extend along the fourth direction d-d', as shown in Figure 5C.
  • the first trench and the second trench intersect to define a plurality of active pillars 12, as shown in FIG. 5C.
  • the third direction b-b' is parallel to the first direction a-a'
  • the fourth direction d-d' is parallel to the second direction c-c'. Therefore, it can also be said that each of the first grooves extends along the first direction a-a’, and each of the second grooves extends along the second direction c-c’.
  • the SADP Self-aligned Double Patterning, self-aligned dual patterning
  • the SAQP Self-aligned Quardruple Patterning, self-aligned quadruple patterning
  • the substrate 20 is etched in the direction of the top surface 201 of the bottom 20 to form the first trench for isolating adjacent bit lines.
  • the plurality of first grooves are arranged at intervals along the second direction c-c’, and each of the first grooves extends along the first direction a-a’.
  • an insulating material such as an oxide material (such as silicon dioxide) is deposited in the first trench to form the first filling layer 21, as shown in FIG. 5B.
  • the first filling layer 21 is subsequently used to electrically isolate adjacent bit lines.
  • a patterned first mask layer 22 is formed on the top surface 201 of the substrate 20 , and the substrate 20 is etched downward along the first mask layer 22 to form an isolation phase.
  • the second trench 23 adjacent to the word line is shown in FIG. 5C.
  • the depth of the first trench is greater than the depth of the second trench 23 (that is, the bottom surface of the second trench 23 is located below the bottom surface of the first trench).
  • the method further includes: forming an insulating layer 15 covering the top and side surfaces of the plurality of active pillars 12 ;
  • a plurality of bit lines 10 are formed in the substrate 20.
  • the plurality of bit lines 10 are arranged at intervals along the second direction c-c', and each of the bit lines 10 is arranged along the first direction a.
  • -a' extends and is electrically connected to the bottom contacts of the plurality of active pillars 12 arranged along the first direction a-a', as shown in FIG. 5D.
  • the material of the active pillar 12 is silicon, and a silicon metallization process is used to form the plurality of bit lines 10 .
  • the insulating layer 15 covering the top and side surfaces of the active pillar 12 is deposited, wherein the material of the insulating layer 15 may be but is not limited to an oxide material. (e.g. silica).
  • the insulating layer 15 is used to protect the active pillar 12 during the subsequent process of forming the bit line 10 and prevent the active pillar from being damaged.
  • the substrate 20 is continuously etched along the second trench 23 to form a bit line groove located below the second trench 23 and connected to the second trench 23 .
  • the width of the bit line groove is greater than the width of the second trench 23.
  • a metal layer made of materials such as titanium, cobalt, and nickel is deposited in the bit line groove, and then a silicon metallization process is used to form the bit line 10 extending along the first direction a-a'.
  • Step S33 Form a plurality of word lines.
  • the plurality of word lines are arranged at intervals along the first direction a-a'.
  • Each of the word lines extends along the second direction c-c' and continuously includes Covering part of the sidewalls of the plurality of active pillars 12 arranged along the second direction c-c', in the direction perpendicular to the top surface 201 of the substrate 20, any two adjacent ones
  • the word lines are at least partially staggered.
  • some of the word lines among the plurality of word lines are first word lines 111, and some of the word lines are second word lines 112; for along the first direction a-a' A plurality of the active pillars 12 are arranged, the first word line 111 covers part of the sidewall of the active pillar 12 of the first parity sequence, and the second word line 112 covers the second parity sequence. part of the sidewall of the active column 12 of the sexual sequence.
  • the first parity sequence may be an odd sequence
  • the second parity sequence may be an even sequence
  • the first word line 111 covers part of the sidewall of the active pillar 12 of the first parity sequence
  • the second word line 112 covers the active pillar 12 of the second parity sequence.
  • the partial sidewalls refer to that, after sequentially sorting the plurality of active pillars 12 arranged along the first direction a-a', the partial sidewalls of the active pillars 12 located at odd-numbered positions are The first word line 111 covers, and part of the sidewall of the active pillar 12 located at the even numbered position is covered by the second word line 112 .
  • the first word line 111 and the second word line 112 are at least partially offset.
  • the first parity sequence may also be an even sequence
  • the second parity sequence may also be an odd sequence.
  • the projection of the first word line 111 in a direction perpendicular to the top surface 201 of the substrate 20 and the projection of the second word line 112 in a direction perpendicular to the top surface 201 of the substrate 20 can be The alternate arrangement helps to simplify the formation process of the word lines and reduce the manufacturing difficulty of the semiconductor structure.
  • forming the plurality of word lines includes: forming an isolation layer 13 that fills the second trench 23 and covers the surface of the insulating layer 15, as shown in FIG. 5E; etching part of the The insulating layer 15 forms a second groove 25 between the active pillar 12 of the second parity sequence and the isolation layer 13, as shown in FIG. 5G; The second word line 112 in the trench 25, as shown in FIG. 5I; etching part of the insulating layer 15 to form a gap between the active pillar 12 of the first parity sequence and the isolation layer 13.
  • the depth of the first groove 30 is different from the depth of the second groove 25, as shown in FIG. 5L; forming a first word line 111 located in the first groove 30 , in a direction perpendicular to the top surface 201 of the substrate 20 , the second word line 112 is staggered from the first word line 111 .
  • forming the second word line 112 located in the second groove 25 includes: forming an initial second word line 26 that fills the second groove 25, as shown in FIG. 5H; Part of the initial second word line 26 is etched to form the second word line 112 and a third groove 27 located above the second word line 112, as shown in FIG. 5I; The second filling layer 28 of the third groove 27 is shown in Figure 5J.
  • forming the first word line 111 located in the first groove 30 includes: forming an initial first word line that fills the first groove 30; and etching back a portion of the initial word line.
  • the first word line forms the first word line 111 and the fourth groove 31 located above the first word line 111, as shown in FIG. 5M; forming a third word line filled with the fourth groove 31.
  • Fill layer 32 is shown in Figure 5N.
  • a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process may be used to deposit an insulating material such as nitride (such as silicon nitride) in the second trench 23 to form the second trench 23 .
  • an insulating material such as nitride (such as silicon nitride)
  • CMP chemically mechanically polished
  • the structure shown in Figure 5E is obtained.
  • a second mask layer 24 is formed on the top surface 201 of the substrate 20, as shown in FIG. 5F.
  • the second mask layer 24 has a third layer that exposes a portion of the insulating layer 15 , at least a portion of the isolation layer 13 and the top surface of a plurality of active pillars 12 arranged in the second parity sequence.
  • the second mask layer 24 may be made of organic mask material such as carbon.
  • a selective wet etching process is used to etch part of the insulating layer 15 downward along the first etching window 241 to form the active pillar 12 and the second parity sequence.
  • the second groove 25 between the isolation layers 13 is as shown in FIG. 5G.
  • an in-situ oxidation process is used to oxidize the sidewalls of the second groove 25 to form a gate dielectric layer 14 on the side surfaces of the plurality of active pillars 12 arranged according to the second parity sequence.
  • Conductive materials such as TiN are deposited in the second groove 25 using methods such as atomic layer deposition to form sidewalls that fill the second groove 25 and cover the gate dielectric layer 14 and the isolation layer 13
  • the initial second word line 26 on the sidewall is formed into a structure as shown in FIG. 5H after undergoing a chemical mechanical polishing process.
  • a portion of the initial second word line 26 is etched back to form the second word line 112 and a third groove 27 located above the second word line 112, as shown in FIG. 5I.
  • the third groove 27 is filled with an insulating material such as nitride (eg, silicon nitride), and the second filling layer 28 is formed as shown in FIG. 5J after chemical mechanical polishing.
  • nitride eg, silicon nitride
  • a third mask layer 29 is formed on the top surface of the substrate 20, as shown in FIG. 5K.
  • the third mask layer 29 has a third mask layer 29 that exposes a portion of the insulating layer 15 , at least a portion of the isolation layer 13 and a top surface of a plurality of active pillars 12 arranged in the first parity sequence.
  • a selective wet etching process is used to etch part of the insulating layer 15 downward along the second etching window 291 to form the active pillar 12 located in the first parity sequence and the The first groove 30 between the isolation layers 13 is shown in FIG. 5L.
  • an in-situ oxidation process is used to oxidize the sidewalls of the first groove 30 to form a gate dielectric layer 14 on the side surfaces of the plurality of active pillars 12 arranged according to the first parity sequence.
  • Conductive materials such as TiN are deposited in the first groove 30 using methods such as atomic layer deposition to form sidewalls that fill the first groove 30 and cover the gate dielectric layer 14 and the isolation layer 13
  • the top surface of the initial first word line is flush with the top surface of the isolation layer 13 .
  • a portion of the initial first word line is etched back to form the first word line 111 and the fourth groove 31 located above the first word line 111, as shown in FIG. 5M.
  • the fourth groove 31 is filled with an insulating material such as nitride (eg, silicon nitride), and the third filling layer 32 is formed as shown in FIG. 5N after chemical mechanical polishing.
  • nitride eg, silicon nitride
  • the bottom surface of the first groove 30 is located on the bottom surface of the second groove 25
  • the bottom surface of the first groove 25 is located on the top surface of the second word line 112 .
  • the bottom surface of the first word line 111 is located below the top surface of the second word line 112 , that is, the first word line 111 and the second word line 112 only partially overlap.
  • the bottom surface of the first groove 25 is located above the top surface of the second word line 112 , so that the bottom surface of the first word line is located on the bottom surface of the second word line 112 Above, that is, the first word line 111 and the second word line 112 do not overlap.
  • forming the plurality of word lines includes: forming an isolation layer 23 that fills the second trench 23 and covers the surface of the insulating layer 15; etching the insulating layer 23 to form The second groove 25 is located between the active pillar 12 and the isolation layer 23 of the second parity sequence, and the active pillar 12 and the isolation layer of the first parity sequence. 23, the first groove 30 and the second groove 25 have different depths, as shown in FIG. 6C; a second word line 112 is formed in the second groove 25. , and form a first word line 111 in the first groove 30. In a direction perpendicular to the top surface 201 of the substrate 20, the second word line 112 and the first word line 111 Stagger the settings as shown in Figure 6G.
  • the second groove 25 is formed between the active pillar 12 of the second parity sequence and the isolation layer 23, and the second groove 25 of the first parity sequence is formed.
  • the first groove 30 between the active pillar 12 and the isolation layer 23 includes: etching all the areas between the active pillar 12 and the isolation layer 23 of the second parity sequence.
  • the insulating layer 15 forms an initial second groove 65, as shown in FIG. 6B; etching the insulating layer 15 between the active pillar 12 of the first parity sequence and the isolation layer 23 and the insulating layer 15 at the bottom of the initial second groove 65 to form the first groove 30 and the second groove 25 respectively, as shown in FIG. 6C .
  • forming the first word line 111 in the first groove 30 and forming the second word line 112 in the second groove 25 includes: filling the first groove with deposition. 30 and the conductive material layer 60 of the second groove 25; etch back the conductive material layer 60 in the second groove 25; etch back the second groove 25 and the first
  • the conductive material layer 60 in the groove 30 , the conductive material layer 60 remaining in the second groove 25 forms the second word line 112 , and the conductive material layer 60 remaining in the first groove 30
  • the conductive material layer 60 forms the first word line 111 .
  • a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process may be used to deposit insulating materials such as nitride (such as silicon nitride) in the second trench 23 to form
  • nitride such as silicon nitride
  • CMP chemically mechanically polished
  • the top surface of the isolation layer 13 is flush with the top surface of the active pillar 12 .
  • a second mask layer 24 is formed on the top surface 201 of the substrate 20, as shown in FIG. 6A.
  • the second mask layer 24 has a third layer that exposes a portion of the insulating layer 15 , at least a portion of the isolation layer 13 and the top surface of a plurality of active pillars 12 arranged in the second parity sequence.
  • the second mask layer 24 may be made of organic mask material such as carbon.
  • a selective wet etching process is used to etch part of the insulating layer 15 downward along the first etching window 241 to form the active pillar 12 and the second parity sequence.
  • the initial second groove 65 between the isolation layers 13 is shown in FIG. 6B.
  • the second mask layer 24 is removed, and a selective wet etching process is used to etch the insulating layer between the active pillar 12 of the first parity sequence and the isolation layer 23 15. And continue to etch the insulating layer 15 at the bottom of the initial second groove 65 to form the first groove 30 and the second groove 25 respectively, as shown in FIG. 6C .
  • an in-situ oxidation process is used to oxidize the sidewalls of the first groove 30 and the sidewalls of the second groove 25, on the plurality of active pillars arranged according to the first parity sequence.
  • the gate dielectric layer 14 is formed on the side surfaces and the side surfaces of the plurality of active pillars 12 arranged according to the second parity sequence.
  • conductive materials such as TiN are deposited in the first groove 30 and the second groove 25 to form the conductive material layer 60 filled with the first groove 30 and the second groove 25 .
  • the top surface of the conductive material layer 60 is flush with the top surface of the active pillar 12 , as shown in FIG. 6D .
  • a fourth mask layer 62 is formed on the top surface 201 of the substrate 20 .
  • the fourth mask layer 62 has a plurality of active pillars 12 arranged in the second parity sequence and exposed therein. , part of the conductive material layer 60 and at least part of the third etching window 621 of the isolation layer 23, as shown in FIG. 6E.
  • the portion of the conductive material layer 60 located in the second groove 25 is etched back along the third etching window 621 to form a fifth groove 63 in the second groove 25 , as shown in FIG. 6F Show.
  • the conductive material layer 60 in the first groove 30 is etched back, and at the same time, the conductive material layer 60 at the bottom of the fifth groove 63 is continued to be etched to form a layer located in the first groove.
  • the third groove 27 above the second word line 112 is shown in FIG. 6G.
  • insulating materials such as nitride (such as silicon nitride) are deposited on the fourth groove 31 and the third groove 27 at the same time, and a second filling layer 28 is formed in the third groove 27, and at the same time A third filling layer 32 is formed in the fourth groove 31 .
  • any two adjacent word lines are at least partially staggered in a direction perpendicular to the top surface of the substrate, so that any The heights of two adjacent word lines are different to reduce the facing area between adjacent word lines, so as to achieve the effect of reducing the capacitive coupling effect between the two adjacent word lines.
  • the present disclosure only needs to adjust the number of etching processes to make any two adjacent word lines at least partially staggered. The process is simple and easy to implement and control.

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Abstract

本公开涉及一种半导体结构及其形成方法。所述半导体结构包括：衬底；多个有源柱，位于所述衬底内，所述多个有源柱沿第一方向和第二方向呈阵列排布，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；多条字线，多条所述字线沿所述第一方向间隔排布，每条所述字线沿所述第二方向延伸、且连续包覆沿所述第二方向排布的多个所述有源柱的部分侧壁，在沿垂直于所述衬底的顶面的方向上，任意相邻的两条所述字线至少部分错开设置。该半导体结构可以降低相邻两条字线之间电容耦合效应，且制程工艺简单，易于实现和控制。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2022年05月20日递交的中国专利申请号202210550340.6、申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
但是，在动态随机存储器等半导体结构中，所有的字线都位于同一水平高度，由于相邻字线之间的间隔较窄，从而导致相邻字线之间耦合效应较强。当一条字线被选定开启时，由于强烈的耦合效应，会导致相邻字线的瞬间开启，最终可能引起电容泄露、甚至是读写失败等问题，严重影响存储器的性能。
因此，如何降低相邻字线之间的耦合效应，从而改善存储器的性能，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体结构及其形成方法，用于降低相邻字线之间的耦合效应，从而改善存储器的性能，提高存储器的良率。
根据一些实施例，本公开提供了一种半导体结构，包括：衬底；多个有源柱，位于所述衬底内，所述多个有源柱沿第一方向和第二方向呈阵列排布，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；多条字线，多条所述字线沿所述第一方向间隔排布，每条所述字线沿所述第二方向延伸、且连续包覆沿所述第二方向排布的多个所述有源柱的部分侧壁，在沿垂直于所述衬底的顶面的方向上，任意相邻的两条所述字线至少部分错开设置。
在一些实施例中，所述多条字线中的部分所述字线为第一字线、且部分所述字线为第二字线；对于沿所述第一方向排布的多个所述有源柱，所述第一字线包覆第一奇偶性序列的所述有源柱的部分侧壁，所述第二字线包覆第二奇偶性序列的所述有源柱的部分侧壁。
在一些实施例中，所述第一字线的顶面位于所述第二字线的底面之下；或者，所述第一字线的顶面位于所述第二字线的底面之上、且所述第一字线的顶面位于所述第二字线的顶面之下。
在一些实施例中，所述第一字线的顶面位于所述第二字线的底面之下，所述第一字线的顶面与所述第二字线的底面之间具有预设间隙，且在沿垂直于所述衬底的顶面的方向上，所述预设间隙的宽度为所述第一字线的尺寸的1/4～1/2。
在一些实施例中，所述有源柱包括沿垂直于所述衬底的顶面的方向依次排布的源极区、沟道区和漏极区，每条所述字线连续包覆沿所述第二方向排布的多个所述有源柱的所述沟道区；所述半导体结构还包括：多条位线，位于所述衬底内，所述多条位线沿所述第二方向间隔排布，每条所述位线沿所述第一方向延伸、且与沿所述第一方向排布的多个所述有源柱的所述源极区接触电连接。
在一些实施例中，还包括：绝缘层，覆盖于所述源极区的侧壁；栅极介质层，覆盖于所述沟道区的侧壁和所述漏极区的侧壁，所述字线位于所述沟道区上的所述栅极介质层的表面；隔离层，位于相邻的所述有源柱之间，且覆盖所述绝缘层的表面、所述字线的表面和所述漏极区侧壁的所述栅极介质层的表面。
在一些实施例中，在沿垂直于所述衬底的顶面的方向上，多条所述字线的尺寸均相等。
在一些实施例中，多条所述字线中的部分所述字线为第一字线、部分所述字线为第二字线、且部分所述字线为第三字线；对于沿所述第一方向排布的多个所述有源柱，所述第一字线包覆第3n位的所述有源柱的部分侧壁，所述第二字线包覆第3n+1位的所述有源柱的部分侧壁，所述第三字线包覆第3n+2位的所述有源柱的部分侧壁，其中，n为大于或者等于0的整数。
根据另一些实施例，本公开还提供了一种半导体结构的形成方法，包括：提供衬底；于所述衬底内形成多个有源柱，所述多个有源柱沿第一方向和第二方向呈阵列排布，所述第一方向和所述第二方向均 为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；以及形成多条字线，多条所述字线沿所述第一方向间隔排布，每条所述字线沿所述第二方向延伸、且连续包覆沿所述第二方向排布的多个所述有源柱的部分侧壁，在沿垂直于所述衬底的顶面的方向上，任意相邻的两条所述字线至少部分错开设置。
在一些实施例中，于所述衬底内形成所述多个有源柱，包括：刻蚀所述衬底，形成多个第一沟槽，所述多个第一沟槽沿所述第二方向间隔排布，每个所述第一沟槽沿所述第一方向延伸；形成填充满所述多个第一沟槽的第一填充层；以及刻蚀所述衬底，形成多个第二沟槽，所述多个第二沟槽沿所述第一方向间隔排布，每个所述第二沟槽沿所述第二方向延伸。
在一些实施例中，在形成所述多个有源柱之后，在形成所述多条字线之前，还包括：形成覆盖所述多个有源柱的顶面和侧面的绝缘层；于所述衬底内形成多条位线，所述多条位线沿所述第二方向间隔排布，每条所述位线沿所述第一方向延伸、且与沿所述第一方向排布的多个所述有源柱的底部接触电连接。
在一些实施例中，所述有源柱的材料为硅，采用硅金属化工艺形成所述多条位线。
在一些实施例中，所述多条字线中的部分所述字线为第一字线、且部分所述字线为第二字线；对于沿所述第一方向排布的多个所述有源柱，所述第一字线包覆第一奇偶性序列的所述有源柱的部分侧壁，所述第二字线包覆第二奇偶性序列的所述有源柱的部分侧壁。
在一些实施例中，形成所述多条字线，包括：形成所述多条字线，包括：形成填充满所述第二沟槽、并覆盖所述绝缘层表面的隔离层；刻蚀部分的所述绝缘层，形成位于所述第二奇偶性序列的所述有源柱与所述隔离层之间的第二凹槽；形成位于所述第二凹槽内的第二字线；刻蚀部分的所述绝缘层，形成位于所述第一奇偶性序列的所述有源柱与所述隔离层之间的第一凹槽，所述第一凹槽的深度与所述第二凹槽的深度不同；形成位于所述第一凹槽内的第一字线，在沿垂直于所述衬底的顶面的方向上，所述第二字线与所述第一字线错开设置。
在一些实施例中，形成位于所述第二凹槽内的第二字线，包括：形成填充满所述第二凹槽的初始第二字线；回刻蚀部分的所述初始第二字线，形成所述第二字线、以及位于所述第二字线上方的第三凹槽；形成填充满所述第三凹槽的第二填充层。
在一些实施例中，所述第一凹槽的底面位于所述第二凹槽的底面之上，且所述第一凹槽的底面位于所述第二字线的顶面之下；或者，所述第一凹槽的底面位于所述第二字线的顶面之上。
在一些实施例中，形成位于所述第一凹槽内的第一字线，包括：形成填充满所述第一凹槽的初始第一字线；回刻蚀部分的所述初始第一字线，形成所述第一字线、以及位于所述第一字线上方的第四凹槽；形成填充满所述第四凹槽的第三填充层。
在一些实施例中，形成所述多条字线，包括：形成填充满所述第二沟槽、并覆盖所述绝缘层表面的隔离层；刻蚀所述绝缘层，形成位于所述第二奇偶性序列的所述有源柱与所述隔离层之间的第二凹槽、以及所述第一奇偶性序列的所述有源柱与所述隔离层之间的第一凹槽，所述第一凹槽与所述第二凹槽的深度不同；于所述第二凹槽内形成第二字线、并于所述第一凹槽内形成第一字线，在沿垂直于所述衬底的顶面的方向上，所述第二字线与所述第一字线错开设置。
在一些实施例中，形成位于所述第二奇偶性序列的所述有源柱与所述隔离层之间的所述第二凹槽、以及所述第一奇偶性序列的所述有源柱与所述隔离层之间的所述第一凹槽，包括：刻蚀位于所述第二奇偶性序列的所述有源柱与所述隔离层之间的所述绝缘层，形成初始第二凹槽；刻蚀位于所述第一奇偶性序列的所述有源柱与所述隔离层之间的所述绝缘层以及所述初始第二凹槽底部的所述绝缘层，以分别形成所述第一凹槽和所述第二凹槽。
在一些实施例中，于所述第一凹槽内形成第一字线、并于所述第二凹槽内形成第二字线，包括：沉积填充满所述第一凹槽和所述第二凹槽的导电材料层；回刻蚀所述第二凹槽内的所述导电材料层；再次回刻蚀所述第二凹槽和所述第一凹槽内的所述导电材料层，残留于所述第二凹槽内的所述导电材料层形成所述第二字线、且残留于所述第一凹槽内的所述导电材料层形成所述第一字线。
本公开一些实施例提供的半导体结构及其形成方法，通过控制在沿垂直于所述衬底的顶面的方向上，任意相邻的两条所述字线至少部分错开设置，使得任意相邻的两条字线的高度不同，以减小相邻字线之间的正对面积，以达到降低相邻两条字线之间电容耦合效应的效果。另外，本公开仅需调整刻蚀工艺的 次数，即可使得任意相邻的两条所述字线至少部分错开设置，制程工艺简单，易于实现和控制。
附图说明
附图1是本公开具体实施方式中半导体结构的俯视示意图；
附图2是本公开具体实施方式中半导体结构的截面示意图；
附图3是本公开具体实施方式中半导体结构的形成方法流程图；
附图4是本公开具体实施方式形成的半导体结构的俯视示意图；
附图5A-5N是本公开具体实施方式的一实施例在形成半导体结构的过程中主要的工艺示意图；
附图6A-6H是本公开具体实施方式的另一实施例在形成半导体结构的过程中主要的工艺示意图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构，附图1是本公开具体实施方式中半导体结构的俯视示意图，附图2是本公开具体实施方式中半导体结构的截面示意图，图2是图1沿a-a’方向的截面示意图。本具体实施方式中所述的半导体结构可以是但不限于存储器，例如DRAM。如图1和图2所示，所述半导体结构，包括：衬底20、多个有源柱12和多条字线。所述多个有源柱12位于所述衬底20内，所述多个有源柱12沿第一方向和第二方向呈阵列排布，所述第一方向a-a’和所述第二方向c-c’均为平行于所述衬底20的顶面201的方向，且所述第一方向a-a’与所述第二方向c-c’相交。多条所述字线沿所述第一方向a-a’间隔排布，每条所述字线沿所述第二方向c-c’延伸、且连续包覆沿所述第二方向c-c’排布的多个所述有源柱12的部分侧壁，在沿垂直于所述衬底20的顶面201的方向上，任意相邻的两条所述字线至少部分错开设置。
例如，所述衬底20可以是但不限于硅衬底，本具体实施方式以所述衬底为硅衬底为例进行说明。在其他实施例中，所述衬底20还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底20包括所述顶面201、以及与所述顶面相对的底面202。多个所述有源柱12在所述衬底20内沿所述第一方向a-a’和所述第二方向c-c’呈阵列排布，每个所述有源柱12沿垂直于所述衬底20的顶面201的方向延伸。多条所述字线均位于所述衬底20内部，每条所述字线沿所述第二方向c-c’延伸、且连续包覆沿所述第二方向c-c’排布的多个所述有源柱12的部分侧壁，多条所述字线沿所述第一方向a-a’间隔排布。所述的相交可以是垂直相交，也可以是倾斜相交，本具体实施方式以所述相交为垂直相交为例进行说明。
本具体实施方式通过控制在沿垂直于所述衬底20的顶面201的方向上，任意相邻的两条所述字线至少部分错开设置，使得任意相邻的两条所述字线处于不同的水平高度，从而减小任意相邻的两条所述字线之间的正对面积，从而降低了任意相邻字线之间的电容耦合效应，使得在相邻的两条所述字线中的一条所述字线被选定开启时、另一条所述字线不会因电容耦合效应而开启，减少甚至是避免了相邻存储单元之间的漏电问题，从而改善了半导体结构的电性能。
在一些实施例中，所述多条字线中的部分所述字线为第一字线111、且部分所述字线为第二字线112；对于沿所述第一方向a-a’排布的多个所述有源柱12，所述第一字线111包覆第一奇偶性序列的所述有源柱12的部分侧壁，所述第二字线112包覆第二奇偶性序列的所述有源柱12的部分侧壁。
例如，所述第一奇偶性序列可以是奇数序列，所述第二奇偶性序列可以是偶数序列。相应地，所述第一字线111包覆第一奇偶性序列的所述有源柱12的部分侧壁，所述第二字线112包覆第二奇偶性序列的所述有源柱12的部分侧壁是指，在对沿所述第一方向a-a’排布的多个所述有源柱12依次排序之后，位于奇数位的所述有源柱12的部分侧壁被所述第一字线111包覆，位于偶数位的所述有源柱12的部分侧壁被所述第二字线112包覆。在沿垂直于所述衬底20的顶面201的方向上，所述第一字线111与所述第二字线112至少部分错开设置。当然，所述第一奇偶性序列也可以是偶数序列，所述第二奇偶性序列也可以是奇数序列。例如，所述第一字线111沿垂直于所述衬底20的顶面201方向上的投影与所述第二字线112沿垂直于所述衬底20的顶面201方向上的投影可以交替排布，从而有助于简化所述字线的形成工艺，降低所述半导体结构的制造难度。
在一些实施例中，所述第一字线111的顶面位于所述第二字线112的底面之下；或者，所述第一字线111的顶面位于所述第二字线112的底面之上、且所述第一字线111的顶面位于所述第二字线112的顶面之下。
例如，在一些实施例中，所述第一字线111的顶面位于所述第二字线112的底面之下，即所述第一字线111与所述第二字线112在沿垂直于所述衬底20的顶面201的方向上完全错开设置，所述第一字线111与所述第二字线112在沿垂直于所述衬底20的顶面201的方向上完全不重叠，从而最大程度降低相邻的所述第一字线111与所述第二字线112之间的电容耦合效应。在另一些实施例中，所述第一字线111的顶面位于所述第二字线112的底面之上、且所述第一字线111的顶面位于所述第二字线112的顶面之下，即所述第一字线111与所述第二字线112在沿垂直于所述衬底20的顶面201的方向上部分错开设置，所述第一字线111与所述第二字线112在沿垂直于所述衬底20的顶面201的方向上部分重叠，从而在降低相邻的所述第一字线111与所述第二字线112之间的电容耦合效应的同时，有助于减小所述半导体结构的尺寸。
在一些实施例中，在沿垂直于所述衬底20的顶面201的方向上，多条所述字线的尺寸均相等。
例如，在沿垂直于所述衬底20的顶面201的方向上，所有所述第一字线111的尺寸均相等，所有所述第二字线112的尺寸也均相等，且任意一条所述第一字线111的尺寸与任意一条所述第二字线112的尺寸也相等。通过控制所有所述字线的尺寸均相等，能够控制所有所述字线的内阻相等，从而简化所述半导体结构的控制操作。
当所述第一字线111与所述第二字线112在沿垂直于所述衬底20的顶面201的方向上完全不重叠，所述第一字线111的顶面与所述第二字线112的底面之间的所述预设间隙的宽度不宜过大，否则会导致所述半导体结构的尺寸以及制造成本的增加。在一些实施例中，所述第一字线111的顶面位于所述第二字线112的底面之下，所述第一字线111的顶面与所述第二字线112的底面之间具有预设间隙，且在沿垂直于所述衬底20的顶面201的方向上，所述预设间隙的宽度为所述第一字线111的尺寸的1/4～1/2。此处，所述第一字线111的尺寸可以是所述第一字线111沿垂直于所述衬底20的顶面201的方向上的高度。
在一些实施例中，所述有源柱12包括沿垂直于所述衬底20的顶面201的方向依次排布的源极区、沟道区和漏极区，每条所述字线连续包覆沿所述第二方向c-c’排布的多个所述有源柱12的所述沟道区；所述半导体结构还包括：多条位线10，位于所述衬底20内，所述多条位线10沿所述第二方向c-c’间隔排布，每条所述位线10沿所述第一方向a-a’延伸、且与沿所述第一方向a-a’排布的多个所述有源柱12的所述源极区接触电连接。
例如，如图1和图2所示，所述衬底20内包括多条所述位线10，所述位线10位于所述字线的下方。每条所述位线10沿所述第一方向a-a’延伸，多条所述位线10沿所述第二方向c-c’间隔排布。每条所述位线10与沿所述第一方向a-a’排布的多个所述有源柱12的所述源极区接触电连接。
在一些实施例中，所述半导体结构还包括：绝缘层15，覆盖于所述源极区的侧壁；栅极介质层14，覆盖于所述沟道区的侧壁和所述漏极区的侧壁，所述字线位于所述沟道区上的所述栅极介质层14的表面；隔离层13，位于相邻的所述有源柱12之间，且覆盖所述绝缘层15的表面、所述字线的表面和所述漏极区侧壁的所述栅极介质层14的表面。
例如，所述隔离层13用于电性隔离相邻的所述字线，例如通过所述隔离层13电性隔离沿所述第一方向a-a’相邻的所述第一字线111和所述第二字线112。所述隔离层13的材料可以是但不限于氮化物材料，例如氮化硅。所述绝缘层15覆盖于所述源极区的侧壁以及所述位线10的部分顶面，所述隔离层13覆盖所述绝缘层15的表面和所述位线10的部分顶面，通过所述绝缘层15和所述隔离层13电性隔离所述字线和所述位线10。所述绝缘层15的材料可以是但不限于氧化物材料，例如二氧化硅。
本具体实施方式是以多条所述字线中的部分所述字线为第一字线、部分所述字线为第二字线为例进行说明。在其他具体实施方式中，多条所述字线中的部分所述字线为第一字线、部分所述字线为第二字线、且部分所述字线为第三字线；对于沿所述第一方向排布的多个所述有源柱12，所述第一字线包覆第3n位的所述有源柱12的部分侧壁，所述第二字线包覆第3n+1位的所述有源柱12的部分侧壁，所述第三字线包覆第3n+2位的所述有源柱12的部分侧壁，其中，n为大于或者等于0的整数。
例如，在其他具体实施方式中，通过设置所述第一字线、所述第二字线和所述第三字线，且所述第一字线、所述第二字线、所述第三字线沿所述第一方向交替排布，在沿垂直于所述衬底20的顶面201的方向上，所述第一字线、所述第二字线、所述第三字线中任意两者均至少部分错开设置，即在沿垂直 于所述衬底20的顶面201的方向上，所述第一字线、所述第二字线和所述第三字线的水平高度均不同。通过设置水平高度均不同的所述第一字线、所述第二字线和所述第三字线，在减小相邻所述有源柱12上的所述字线之间的耦合效应的同时，还有助于提高所述半导体结构的集成度。
本具体实施方式还提供了一种半导体结构的形成方法，附图3是本公开具体实施方式中半导体结构的形成方法流程图，附图4是本公开具体实施方式形成的半导体结构的俯视示意图，附图5A-5N是本公开具体实施方式的一实施例在形成半导体结构的过程中主要的工艺示意图，附图6A-6H是本公开具体实施方式的另一实施例在形成半导体结构的过程中主要的工艺示意图。图5A-图5N、以及图6A-图6H分别从图4中的a-a’方向、b-b’方向、c-c’方向和d-d’方向这四个方向示出了所述半导体结构在形成过程中的主要工艺截面示意图，以清楚的表明所述半导体结构的形成工艺。本具体实施方式形成的半导体结构的示意图可以参见图1和图2。本具体实施方式中所述的半导体结构可以是但不限于存储器，例如DRAM。如图3-图4、图5A-图5N、以及图6A-图6H所示，所述半导体结构的形成方法，包括以下步骤S31至步骤S33。
步骤S31，提供衬底20，如图5A所示。
例如，所述衬底20可以是但不限于硅衬底，本具体实施方式以所述衬底为硅衬底为例进行说明。在其他实施例中，所述衬底20还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底20包括所述顶面201、以及与所述顶面相对的底面202。
步骤S32，于所述衬底20内形成多个有源柱12，所述多个有源柱12沿第一方向a-a’和第二方向c-c’呈阵列排布，所述第一方向a-a’和所述第二方向c-c’均为平行于所述衬底20的顶面201的方向，且所述第一方向a-a’与所述第二方向c-c’相交。
在一些实施例中，于所述衬底20内形成所述多个有源柱12，包括：刻蚀所述衬底20，形成多个第一沟槽，所述多个第一沟槽沿所述第二方向c-c’间隔排布，每个所述第一沟槽沿第三方向b-b’延伸；形成填充满所述多个第一沟槽的第一填充层21，如图5B所示；以及刻蚀所述衬底20，形成多个第二沟槽23，所述多个第二沟槽沿所述第一方向a-a’间隔排布，每个所述第二沟槽沿第四方向d-d’延伸，如图5C所示。由此，第一沟槽和第二沟槽交叉定义出多个有源柱12，如图5C所示。其中，所述第三方向b-b’与所述第一方向a-a’平行，所述第四方向d-d’与所述第二方向c-c’平行。因此，也可以说，每个所述第一沟槽沿第一方向a-a’延伸，每个所述第二凹槽沿所述第二方向c-c’延伸。
例如，可以采用SADP(Self-aligned Double Patterning，自对准双重图形)工艺或者是SAQP(Self-aligned Quardruple Patterning，自对准四重图形)工艺、结合干法刻蚀工艺沿垂直于所述衬底20的顶面201的方向刻蚀所述衬底20，形成用于隔离相邻位线的所述第一沟槽。所述多个第一沟槽沿所述第二方向c-c’间隔排布，每个所述第一沟槽沿所述第一方向a-a’延伸。之后，沉积氧化物材料(例如二氧化硅)等绝缘材料于所述第一沟槽内，形成所述第一填充层21，如图5B所示。所述第一填充层21后续用于电性隔离相邻的所述位线。接着，形成图案化的第一掩膜层22于所述衬底20的所述顶面201，沿所述第一掩膜层22继续向下刻蚀所述衬底20，形成用于隔离相邻字线的所述第二沟槽23，如图5C所示。由于后续形成的所述位线位于所述字线下方，因此，为了便于后续充分隔离相邻的所述位线，在一实施例中，在沿垂直于所述衬底20的顶面201的方向上，所述第一沟槽的深度大于所述第二沟槽23的深度(即所述第二沟槽23的底面位于所述第一沟槽的底面之下)。
在一些实施例中，在形成所述多个有源柱12之后，在形成所述多条字线之前，还包括：形成覆盖所述多个有源柱12的顶面和侧面的绝缘层15；于所述衬底20内形成多条位线10，所述多条位线10沿所述第二方向c-c’间隔排布，每条所述位线10沿所述第一方向a-a’延伸、且与沿所述第一方向a-a’排布的多个所述有源柱12的底部接触电连接，如图5D所示。
在一些实施例中，所述有源柱12的材料为硅，采用硅金属化工艺形成所述多条位线10。
例如，在形成所述第二沟槽23之后，沉积覆盖所述有源柱12的顶面和侧面的所述绝缘层15，其中，所述绝缘层15的材料可以是但不限于氧化物材料(例如二氧化硅)。所述绝缘层15用于在后续形成所述位线10的过程中保护所述有源柱12，避免所述有源柱遭受损伤。然后，沿所述第二沟槽23继续刻蚀所述衬底20，形成位于所述第二沟槽23下方、且与所述第二沟槽23连通的位线凹槽。在沿所述第一方向a-a’上，所述位线凹槽的宽度大于所述第二沟槽23的宽度。然后，在所述位线凹槽内沉积钛、钴、镍等 材料形成的金属层，进而，采用硅金属化工艺形成沿所述第一方向a-a’延伸的所述位线10。
步骤S33，形成多条字线，多条所述字线沿所述第一方向a-a’间隔排布，每条所述字线沿所述第二方向c-c’延伸、且连续包覆沿所述第二方向c-c’排布的多个所述有源柱12的部分侧壁，在沿垂直于所述衬底20的顶面201的方向上，任意相邻的两条所述字线至少部分错开设置。
在一些实施例中，所述多条字线中的部分所述字线为第一字线111、且部分所述字线为第二字线112；对于沿所述第一方向a-a’排布的多个所述有源柱12，所述第一字线111包覆第一奇偶性序列的所述有源柱12的部分侧壁，所述第二字线112包覆第二奇偶性序列的所述有源柱12的部分侧壁。
例如，所述第一奇偶性序列可以是奇数序列，所述第二奇偶性序列可以是偶数序列。相应地，所述第一字线111包覆第一奇偶性序列的所述有源柱12的部分侧壁，所述第二字线112包覆第二奇偶性序列的所述有源柱12的部分侧壁是指，在对沿所述第一方向a-a’排布的多个所述有源柱12依次排序之后，位于奇数位的所述有源柱12的部分侧壁被所述第一字线111包覆，位于偶数位的所述有源柱12的部分侧壁被所述第二字线112包覆。在沿垂直于所述衬底20的顶面201的方向上，所述第一字线111与所述第二字线112至少部分错开设置。当然，所述第一奇偶性序列也可以是偶数序列，所述第二奇偶性序列也可以是奇数序列。例如，所述第一字线111沿垂直于所述衬底20的顶面201方向上的投影与所述第二字线112沿垂直于所述衬底20的顶面201方向上的投影可以交替排布，从而有助于简化所述字线的形成工艺，降低所述半导体结构的制造难度。
在一些实施例中，形成所述多条字线，包括：形成填充满所述第二沟槽23、并覆盖所述绝缘层15表面的隔离层13，如图5E所示；刻蚀部分的所述绝缘层15，形成位于所述第二奇偶性序列的所述有源柱12与所述隔离层13之间的第二凹槽25，如图5G所示；形成位于所述第二凹槽25内的第二字线112，如图5I所示；刻蚀部分的所述绝缘层15，形成位于所述第一奇偶性序列的所述有源柱12与所述隔离层13之间的第一凹槽30，所述第一凹槽30的深度与所述第二凹槽25的深度不同，如图5L所示；形成位于所述第一凹槽30内的第一字线111，在沿垂直于所述衬底20的顶面201的方向上，所述第二字线112与所述第一字线111错开设置。
在一些实施例中，形成位于所述第二凹槽25内的第二字线112，包括：形成填充满所述第二凹槽25的初始第二字线26，如图5H所示；回刻蚀部分的所述初始第二字线26，形成所述第二字线112、以及位于所述第二字线112上方的第三凹槽27，如图5I所示；形成填充满所述第三凹槽27的第二填充层28，如图5J所示。
在一些实施例中，形成位于所述第一凹槽30内的第一字线111，包括：形成填充满所述第一凹槽30的初始第一字线；回刻蚀部分的所述初始第一字线，形成所述第一字线111、以及位于所述第一字线111上方的第四凹槽31，如图5M所示；形成填充满所述第四凹槽31的第三填充层32如图5N所示。
举例来说，在一些实施例中，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺沉积氮化物(例如氮化硅)等绝缘材料于所述第二沟槽23内，形成所述隔离层13，经化学机械研磨(CMP)之后，得到如图5E所示的结构。之后，形成第二掩膜层24于所述衬底20的顶面201，如图5F所示。所述第二掩膜层24中具有暴露部分所述绝缘层15、至少部分所述隔离层13和按照所述第二奇偶性序列排布的多个所述有源柱12的顶面的第一刻蚀窗口241。所述第二掩膜层24的材料可以是碳等有机掩膜材料。接着，采用选择性湿法刻蚀工艺、沿所述第一刻蚀窗口241向下刻蚀部分的所述绝缘层15，形成位于所述第二奇偶性序列的所述有源柱12与所述隔离层13之间的第二凹槽25，如图5G所示。之后，采用原位氧化工艺氧化所述第二凹槽25的侧壁，于按照所述第二奇偶性序列排布的多个所述有源柱12的侧面形成栅极介质层14。采用原子层沉积等方法沉积TiN等导电材料于所述第二凹槽25内，形成填充满所述第二凹槽25、并覆盖所述栅极介质层14的侧壁和所述隔离层13的侧壁的所述初始第二字线26，经化学机械研磨工艺之后，形成如图5H所示的结构。然后，回刻蚀部分的所述初始第二字线26，形成所述第二字线112、以及位于所述第二字线112上方的第三凹槽27，如图5I所示。之后，填充氮化物(例如氮化硅)等绝缘材料于所述第三凹槽27，经化学机械研磨之后形成如图5J所示的所述第二填充层28。
接着，形成第三掩膜层29于所述衬底20的顶面，如图5K所示。所述第三掩膜层29中具有暴露部分所述绝缘层15、至少部分所述隔离层13和按照所述第一奇偶性序列排布的多个所述有源柱12的顶面的第二刻蚀窗口291。接着，采用选择性湿法刻蚀工艺、沿所述第二刻蚀窗口291向下刻蚀部分的所述 绝缘层15，形成位于所述第一奇偶性序列的所述有源柱12与所述隔离层13之间的第一凹槽30，如图5L所示。之后，采用原位氧化工艺氧化所述第一凹槽30的侧壁，于按照所述第一奇偶性序列排布的多个所述有源柱12的侧面形成栅极介质层14。采用原子层沉积等方法沉积TiN等导电材料于所述第一凹槽30内，形成填充满所述第一凹槽30、并覆盖所述栅极介质层14的侧壁和所述隔离层13的侧壁的所述初始第一字线，经化学机械研磨工艺之后，使得所述初始第一字线的顶面与所述隔离层13的顶面平齐。然后，回刻蚀部分的所述初始第一字线，形成所述第一字线111、以及位于所述第一字线111上方的第四凹槽31，如图5M所示。之后，填充氮化物(例如氮化硅)等绝缘材料于所述第四凹槽31，经化学机械研磨之后形成如图5N所示的所述第三填充层32。
在一些实施例中，所述第一凹槽30的底面位于所述第二凹槽25的底面之上，且所述第一凹槽25的底面位于所述第二字线112的顶面之下，从而使得形成的所述第一字线111的底面位于所述第二字线112的底面之上、且所述第一字线111的底面位于所述第二字线112的顶面下，即所述第一字线111与所述第二字线112仅部分重叠。在另一些实施例中，所述第一凹槽25的底面位于所述第二字线112的顶面之上，从而使得所述第一字线的底面位于所述第二字线112的底面之上，即所述第一字线111与所述第二字线112不重叠。
在另一些实施例中，形成所述多条字线，包括：形成填充满所述第二沟槽23、并覆盖所述绝缘层15表面的隔离层23；刻蚀所述绝缘层23，形成位于所述第二奇偶性序列的所述有源柱12与所述隔离层23之间的第二凹槽25、以及所述第一奇偶性序列的所述有源柱12与所述隔离层23之间的第一凹槽30，所述第一凹槽30与所述第二凹槽25的深度不同，如图6C所示；于所述第二凹槽25内形成第二字线112、并于所述第一凹槽30内形成第一字线111，在沿垂直于所述衬底20的顶面201的方向上，所述第二字线112与所述第一字线111错开设置，如图6G所示。
在一些实施例中，形成位于所述第二奇偶性序列的所述有源柱12与所述隔离层23之间的所述第二凹槽25、以及所述第一奇偶性序列的所述有源柱12与所述隔离层23之间的所述第一凹槽30，包括：刻蚀位于所述第二奇偶性序列的所述有源柱12与所述隔离层23之间的所述绝缘层15，形成初始第二凹槽65，如图6B所示；刻蚀位于所述第一奇偶性序列的所述有源柱12与所述隔离层23之间的所述绝缘层15以及所述初始第二凹槽65底部的所述绝缘层15，以分别形成所述第一凹槽30和所述第二凹槽25，如图6C所示。
在一些实施例中，于所述第一凹槽30内形成第一字线111、并于所述第二凹槽25内形成第二字线112，包括：沉积填充满所述第一凹槽30和所述第二凹槽25的导电材料层60；回刻蚀所述第二凹槽25内的所述导电材料层60；再次回刻蚀所述第二凹槽25和所述第一凹槽30内的所述导电材料层60，残留于所述第二凹槽25内的所述导电材料层60形成所述第二字线112、且残留于所述第一凹槽30内的所述导电材料层60形成所述第一字线111。
举例来说，在另一些实施例中，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺沉积氮化物(例如氮化硅)等绝缘材料于所述第二沟槽23内，形成所述隔离层13，经化学机械研磨(CMP)之后，使得所述隔离层13的顶面与所述有源柱12的顶面平齐。之后，形成第二掩膜层24于所述衬底20的顶面201，如图6A所示。所述第二掩膜层24中具有暴露部分所述绝缘层15、至少部分所述隔离层13和按照所述第二奇偶性序列排布的多个所述有源柱12的顶面的第一刻蚀窗口241。所述第二掩膜层24的材料可以是碳等有机掩膜材料。接着，采用选择性湿法刻蚀工艺、沿所述第一刻蚀窗口241向下刻蚀部分的所述绝缘层15，形成位于所述第二奇偶性序列的所述有源柱12与所述隔离层13之间的初始第二凹槽65，如图6B所示。接着，去除所述第二掩膜层24，采用选择性湿法刻蚀工艺刻蚀位于所述第一奇偶性序列的所述有源柱12与所述隔离层23之间的所述绝缘层15、并继续刻蚀所述初始第二凹槽65底部的所述绝缘层15，以分别形成所述第一凹槽30和所述第二凹槽25，如图6C所示。之后，采用原位氧化工艺氧化所述第一凹槽30的侧壁和所述第二凹槽25的侧壁，于按照所述第一奇偶性序列排布的多个所述有源柱的侧面、以及按照所述第二奇偶性序列排布的多个所述有源柱12的侧面均形成栅极介质层14。
同时沉积TiN等导电材料于所述第一凹槽30内和所述第二凹槽25内，形成填充满所述第一凹槽30和所述第二凹槽25的所述导电材料层60，经化学机械研磨之后，使得所述导电材料层60的顶面与所述 有源柱12的顶面平齐，如图6D所示。接着，形成第四掩膜层62于所述衬底20的顶面201，所述第四掩膜层62中具有暴露按照所述第二奇偶性序列排布的多个所述有源柱12、部分所述导电材料层60和至少部分所述隔离层23的第三刻蚀窗口621，如图6E所示。沿所述第三刻蚀窗口621回刻蚀位于所述第二凹槽25内的部分所述导电材料层60，于所述第二凹槽25内形成第五凹槽63，如图6F所示。之后，回刻蚀所述第一凹槽30内的所述导电材料层60、并同时继续刻蚀所述第五凹槽63底部的所述导电材料层60，形成位于所述第一凹槽30底部的所述第一字线111、位于所述第一字线111上方的第四凹槽31、以及位于所述第二凹槽25底部的所述第二字线112、位于所述第二字线112上方的第三凹槽27，如图6G所示。之后，同时沉积氮化物(例如氮化硅)等绝缘材料于所述第四凹槽31和所述第三凹槽27，于所述第三凹槽27中形成第二填充层28、并同时于所述第四凹槽31中形成第三填充层32。
本具体实施方式一些实施例提供的半导体结构及其形成方法，通过控制在沿垂直于所述衬底的顶面的方向上，任意相邻的两条所述字线至少部分错开设置，使得任意相邻的两条字线的高度不同，以减小相邻字线之间的正对面积，以达到降低相邻两条字线之间电容耦合效应的效果。另外，本公开仅需调整刻蚀工艺的次数，即可使得任意相邻的两条所述字线至少部分错开设置，制程工艺简单，易于实现和控制。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和-润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种半导体结构，包括：
    衬底；
    多个有源柱，位于所述衬底内，所述多个有源柱沿第一方向和第二方向呈阵列排布，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；
    多条字线，多条所述字线沿所述第一方向间隔排布，每条所述字线沿所述第二方向延伸、且连续包覆沿所述第二方向排布的多个所述有源柱的部分侧壁，在沿垂直于所述衬底的顶面的方向上，任意相邻的两条所述字线至少部分错开设置。
  2. 根据权利要求1所述的半导体结构，其中，所述多条字线中的部分所述字线为第一字线、且部分所述字线为第二字线；
    对于沿所述第一方向排布的多个所述有源柱，所述第一字线包覆第一奇偶性序列的所述有源柱的部分侧壁，所述第二字线包覆第二奇偶性序列的所述有源柱的部分侧壁。
  3. 根据权利要求2所述的半导体结构，其中，所述第一字线的顶面位于所述第二字线的底面之下；或者，
    所述第一字线的顶面位于所述第二字线的底面之上、且所述第一字线的顶面位于所述第二字线的顶面之下。
  4. 根据权利要求2所述的半导体结构，其中，所述第一字线的顶面位于所述第二字线的底面之下，所述第一字线的顶面与所述第二字线的底面之间具有预设间隙，且在沿垂直于所述衬底的顶面的方向上，所述预设间隙的宽度为所述第一字线的尺寸的1/4～1/2。
  5. 根据权利要求1所述的半导体结构，其中，所述有源柱包括沿垂直于所述衬底的顶面的方向依次排布的源极区、沟道区和漏极区，每条所述字线连续包覆沿所述第二方向排布的多个所述有源柱的所述沟道区；所述半导体结构还包括：
    多条位线，位于所述衬底内，所述多条位线沿所述第二方向间隔排布，每条所述位线沿所述第一方向延伸、且与沿所述第一方向排布的多个所述有源柱的所述源极区接触电连接。
  6. 根据权利要求5所述的半导体结构，还包括：
    绝缘层，覆盖于所述源极区的侧壁；
    栅极介质层，覆盖于所述沟道区的侧壁和所述漏极区的侧壁，所述字线位于所述沟道区上的所述栅极介质层的表面；
    隔离层，位于相邻的所述有源柱之间，且覆盖所述绝缘层的表面、所述字线的表面和所述漏极区侧壁的所述栅极介质层的表面。
  7. 根据权利要求1所述的半导体结构，其中，在沿垂直于所述衬底的顶面的方向上，多条所述字线的尺寸均相等。
  8. 根据权利要求1所述的半导体结构，其中，多条所述字线中的部分所述字线为第一字线、部分所述字线为第二字线、且部分所述字线为第三字线；
    对于沿所述第一方向排布的多个所述有源柱，所述第一字线包覆第3n位的所述有源柱的部分侧壁，所述第二字线包覆第3n+1位的所述有源柱的部分侧壁，所述第三字线包覆第3n+2位的所述有源柱的部分侧壁，其中，n为大于或者等于0的整数。
  9. 一种半导体结构的形成方法，包括：
    提供衬底；
    于所述衬底内形成多个有源柱，所述多个有源柱沿第一方向和第二方向呈阵列排布，所述第一方向和所述第二方向均为平行于所述衬底的顶面的方向，且所述第一方向与所述第二方向相交；以及
    形成多条字线，多条所述字线沿所述第一方向间隔排布，每条所述字线沿所述第二方向延伸、且连续包覆沿所述第二方向排布的多个所述有源柱的部分侧壁，在沿垂直于所述衬底的顶面的方向上，任意相邻的两条所述字线至少部分错开设置。
  10. 根据权利要求9所述的半导体结构的形成方法，其中，于所述衬底内形成所述多个有源柱，包括：
    刻蚀所述衬底，形成多个第一沟槽，所述多个第一沟槽沿所述第二方向间隔排布，每个所述第一沟槽沿所述第一方向延伸；
    形成填充满所述多个第一沟槽的第一填充层；以及
    刻蚀所述衬底，形成多个第二沟槽，所述多个第二沟槽沿所述第一方向间隔排布，每个所述第二沟槽沿所述第二方向延伸。
  11. 根据权利要求9所述的半导体结构的形成方法，其中，在形成所述多个有源柱之后，在形成所述多条字线之前，还包括：
    形成覆盖所述多个有源柱的顶面和侧面的绝缘层；
    于所述衬底内形成多条位线，所述多条位线沿所述第二方向间隔排布，每条所述位线沿所述第一方向延伸、且与沿所述第一方向排布的多个所述有源柱的底部接触电连接。
  12. 根据权利要求11所述的半导体结构的形成方法，其中，所述有源柱的材料为硅，采用硅金属化工艺形成所述多条位线。
  13. 根据权利要求11所述的半导体结构的形成方法，其中，所述多条字线中的部分所述字线为第一字线、且部分所述字线为第二字线；对于沿所述第一方向排布的多个所述有源柱，所述第一字线包覆第一奇偶性序列的所述有源柱的部分侧壁，所述第二字线包覆第二奇偶性序列的所述有源柱的部分侧壁。
  14. 根据权利要求13所述的半导体结构的形成方法，其中，形成所述多条字线，包括：
    形成填充满所述第二沟槽、并覆盖所述绝缘层表面的隔离层；
    刻蚀部分的所述绝缘层，形成位于所述第二奇偶性序列的所述有源柱与所述隔离层之间的第二凹槽；
    形成位于所述第二凹槽内的第二字线；
    刻蚀部分的所述绝缘层，形成位于所述第一奇偶性序列的所述有源柱与所述隔离层之间的第一凹槽，所述第一凹槽的深度与所述第二凹槽的深度不同；
    形成位于所述第一凹槽内的第一字线，在沿垂直于所述衬底的顶面的方向上，所述第二字线与所述第一字线错开设置。
  15. 根据权利要求14所述的半导体结构的形成方法，其中，形成位于所述第二凹槽内的第二字线，包括：
    形成填充满所述第二凹槽的初始第二字线；
    回刻蚀部分的所述初始第二字线，形成所述第二字线、以及位于所述第二字线上方的第三凹槽；
    形成填充满所述第三凹槽的第二填充层。
  16. 根据权利要求14所述的半导体结构的形成方法，其中，所述第一凹槽的底面位于所述第二凹槽的底面之上，且所述第一凹槽的底面位于所述第二字线的顶面之下；或者，
    所述第一凹槽的底面位于所述第二字线的顶面之上。
  17. 根据权利要求14所述的半导体结构的形成方法，其中，形成位于所述第一凹槽内的第一字线，包括：
    形成填充满所述第一凹槽的初始第一字线；
    回刻蚀部分的所述初始第一字线，形成所述第一字线、以及位于所述第一字线上方的第四凹槽；
    形成填充满所述第四凹槽的第三填充层。
  18. 根据权利要求13所述的半导体结构的形成方法，其中，形成所述多条字线，包括：
    形成填充满所述第二沟槽、并覆盖所述绝缘层表面的隔离层；
    刻蚀所述绝缘层，形成位于所述第二奇偶性序列的所述有源柱与所述隔离层之间的第二凹槽、以及
    所述第一奇偶性序列的所述有源柱与所述隔离层之间的第一凹槽，所述第一凹槽与所述第二凹槽的深度不同；
    于所述第二凹槽内形成第二字线、并于所述第一凹槽内形成第一字线，在沿垂直于所述衬底的顶面的方向上，所述第二字线与所述第一字线错开设置。
  19. 根据权利要求18所述的半导体结构的形成方法，其中，形成位于所述第二奇偶性序列的所述有源柱与所述隔离层之间的所述第二凹槽、以及所述第一奇偶性序列的所述有源柱与所述隔离层之间的所述第一凹槽，包括：
    刻蚀位于所述第二奇偶性序列的所述有源柱与所述隔离层之间的所述绝缘层，形成初始第二凹槽；
    刻蚀位于所述第一奇偶性序列的所述有源柱与所述隔离层之间的所述绝缘层以及所述初始第二凹槽底部的所述绝缘层，以分别形成所述第一凹槽和所述第二凹槽。
  20. 根据权利要求19所述的半导体结构的形成方法，其中，于所述第一凹槽内形成第一字线、并于所述 第二凹槽内形成第二字线，包括：
    沉积填充满所述第一凹槽和所述第二凹槽的导电材料层；
    回刻蚀所述第二凹槽内的所述导电材料层；
    再次回刻蚀所述第二凹槽和所述第一凹槽内的所述导电材料层，残留于所述第二凹槽内的所述导电材料层形成所述第二字线、且残留于所述第一凹槽内的所述导电材料层形成所述第一字线。
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CN114141712A (zh) * 2021-11-30 2022-03-04 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构
CN114156236A (zh) * 2021-11-30 2022-03-08 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构

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US20120119286A1 (en) * 2010-11-11 2012-05-17 Samsung Electronics Co., Ltd. Semiconductor devices having vertical channel transistors and methods for fabricating the same
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