WO2021233111A1 - 存储器的形成方法及存储器 - Google Patents

存储器的形成方法及存储器 Download PDF

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Publication number
WO2021233111A1
WO2021233111A1 PCT/CN2021/091113 CN2021091113W WO2021233111A1 WO 2021233111 A1 WO2021233111 A1 WO 2021233111A1 CN 2021091113 W CN2021091113 W CN 2021091113W WO 2021233111 A1 WO2021233111 A1 WO 2021233111A1
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WIPO (PCT)
Prior art keywords
layer
bit line
top surface
forming
protective layer
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PCT/CN2021/091113
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English (en)
French (fr)
Inventor
李冉
Original Assignee
长鑫存储技术有限公司
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Priority to US17/455,518 priority Critical patent/US11856749B2/en
Publication of WO2021233111A1 publication Critical patent/WO2021233111A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • This application relates to the field of semiconductors, and in particular to a method for forming a memory and a memory.
  • the manufacturing method of dynamic random access memory mainly involves the storage node contact (Storage Node Contact) in the storage array area, the connection layer between the capacitor and the capacitive contact pad (landing pad), and the capacitor contact Fabrication of isolation structures between structures.
  • the memory manufacturing process technology is integrated below 20nm, and the semiconductor manufacturing process integration is increasing, making it more and more difficult to reduce the component size.
  • the embodiments of the present application provide a method for forming a memory and a memory, which simplifies the current manufacturing process of the memory, thereby improving the production efficiency of the memory and reducing the production and operation cost of the memory.
  • an embodiment of the present application provides a method for forming a memory, including: providing a substrate on which a bit line structure and a first protection layer located on the top surface of the bit line structure are formed; forming a dielectric layer to fill adjacent In the gap between the bit line structure, the top surface of the dielectric layer is flush with the top surface of the first protection layer; the second protection layer is formed to cover the top surface of the first protection layer and the top surface of the dielectric layer; In the direction, part of the dielectric layer and part of the second protective layer are removed to form capacitive contact holes, and in the direction perpendicular to the extension of the bit line structure, the first protective layer located between adjacent capacitive contact holes is exposed; a conductive layer is formed Fill the capacitive contact hole and cover the exposed top surface of the first protective layer, and the top surface of the conductive layer is flush with the top surface of the second protective layer; part of the conductive layer is etched to form a discrete capacitive contact structure.
  • the embodiment of the present application adjusts the process flow of the memory manufacturing process.
  • a first protection layer is formed on the top of the bit line stack, and a second protection layer is formed on the top of the first protection layer in the subsequent manufacturing process.
  • etching a part of the conductive layer to form a discrete capacitive contact structure includes: forming a contact mask layer on the top surface of the conductive layer and the second protective layer; the contact mask layer exposes the conductive layer with a predetermined width in a predetermined direction And a second protective layer.
  • the contact mask layer and the exposed conductive layer and the second protective layer are alternately arranged in a direction perpendicular to the predetermined direction; the predetermined direction and the direction in which the bit line structure extends is an angle ⁇ , ⁇ is greater than 0° and ⁇ is not equal to 90°; the exposed conductive layer is etched until a part of the top surface of the first protective layer is exposed; the contact mask layer is removed, and the remaining conductive layer is used as a capacitive contact structure.
  • bit line structure and a first protective layer on the top surface of the bit line structure are formed on the substrate, including: forming a bit line stack on the substrate, forming a first protective film on top of the bit line stack; A patterned bit line mask layer is formed on the top surface. Using the bit line mask layer as a mask, the first protection film and the bit line stack are etched to form a bit line structure and a first protection on the top surface of the bit line structure Layer; remove the bit line mask layer.
  • forming a bit line stack on the substrate includes: forming a separate bit line contact layer connected to the active area in the substrate on the substrate; forming a bottom dielectric layer on the substrate that fills the gap between the bit line contact layers, The top surface of the bottom dielectric layer is flush with the top surface of the bit line contact layer; a metal layer is formed on the top surface of the bottom dielectric layer and the top surface of the bit line contact layer; and a top dielectric layer is formed on the top surface of the metal layer.
  • removing part of the dielectric layer and part of the second protective layer to form a capacitive contact hole includes: forming a dielectric mask layer on the top surface of the second protective layer; taking the dielectric mask layer as Mask, in the direction perpendicular to the extension of the bit line structure, etch part of the second protective layer until part of the top surface of the first protective layer and part of the dielectric layer are exposed; remove part of the exposed dielectric layer to form a capacitor contact hole .
  • the capacitor contact hole and before forming the conductive layer to fill the capacitor contact hole includes: forming an isolation film on the substrate, the isolation film covering the second protective layer and the exposed first protective layer, and the capacitor contact hole Sidewalls and bottom; removing the isolation film located on the top surface of the second protection layer, the exposed top surface of the first protection layer and the bottom of the capacitor contact hole to form an isolation layer on the sidewall of the capacitor contact hole.
  • the conductive layer includes a first conductive layer and a second conductive layer.
  • the materials of the first conductive layer and the second conductive layer are different, and the top surface of the second conductive layer is flush with the top surface of the second protective layer and is perpendicular to In the direction in which the bit line structure extends, the second conductive layer also covers the top surface.
  • forming a conductive layer to fill the capacitive contact hole includes: forming a first conductive layer in the capacitive contact hole, the top surface of the first conductive layer is lower than the top surface of the first protective layer; on the top surface of the first conductive layer, the first protective layer A top conductive film is formed on the top surface and the top surface of the second protective layer; the top conductive film is etched to form a second conductive layer.
  • the discrete capacitive contact structure includes: forming an isolation mask layer on the top surface of the second protective layer; using the isolation mask layer as a mask, patterning is located on the capacitive contact in the direction in which the bit line structure extends.
  • the second protective layer on the top of the structure exposes the dielectric layer between the capacitor contact structures; the dielectric layer between the capacitor contact structures is removed to form an air gap; a sealing layer is formed, and the sealing layer seals the top of the air gap.
  • an air gap is formed to reduce the dielectric constant between the capacitive contact structures, thereby reducing the parasitic capacitance between the capacitive contact structures And the air gap is crucial to the reduction of memory integration.
  • forming a dielectric layer to fill the gaps between adjacent bit line structures includes: forming a dielectric film filling the gaps between adjacent bit line structures, the dielectric film covering the bit line structure; removing the dielectric film higher than the top surface of the bit line structure , The remaining dielectric film forms a dielectric layer.
  • the embodiment of the present application also provides a memory, including: a substrate, and a bit line structure on the substrate; a first protection layer on the top surface of the bit line structure; a capacitive contact structure and an isolation structure between the bit line structures In the direction in which the bit line structure extends, the capacitive contact structure and the isolation structure are arranged alternately; the second protection layer is located between the adjacent bit line structures and the top surface of the isolation structure.
  • the extension direction is different from the extension direction of the bit line structure; the top of the capacitive contact structure has bumps, and the bumps extend in a preset direction.
  • the bumps are also located on the top surface of part of the first protective layer, and the preset direction is the same as the bit line.
  • the direction in which the structure extends has an angle.
  • the angle between the preset direction and the direction in which the bit line structure extends is ⁇ , which is greater than 0° and ⁇ is not equal to 90°.
  • extension direction of the second protection layer is perpendicular to the extension direction of the bit line structure.
  • the memory further includes an isolation layer, which is located on the sidewall of the isolation structure. Through the isolation layer between the isolation structure and the capacitive contact structure, the parasitic capacitance between the capacitive contact structures is reduced.
  • the isolation structure includes a dielectric layer or an air gap.
  • the dielectric layer is used as the isolation structure. Since the dielectric layer is formed when filling the gaps between the bit line structures, no additional manufacturing process is required, thereby improving the production efficiency of the memory; the use of air gaps as the isolation structure can effectively reduce the capacitance contact The dielectric constant between the structures reduces the parasitic capacitance between the capacitive contact structures, thereby improving the performance of the memory.
  • the top part of the capacitive contact structure formed in the present application is located on the top surface of the first protective layer, which changes the arrangement of the original capacitive contact structure, so that the subsequently formed capacitor and the capacitive contact structure are connected It becomes simple, thereby improving the current process flow of the memory manufacturing process, thereby improving the production efficiency of the memory and reducing the production and operation cost of the memory.
  • FIGS. 1 and 2 are schematic diagrams of the formation of a bit line structure and a first protective layer in an embodiment of the application;
  • 3 to 5 are schematic diagrams of the formation of the dielectric layer and the second protective layer in the embodiments of the application;
  • FIGS. 6 to 8 are schematic diagrams of the formation of capacitor contact holes in the embodiments of the application.
  • 9 to 14 are schematic diagrams of the formation of the conductive layer in the embodiment of the application.
  • 15 to 17 are schematic diagrams of the formation of a capacitive contact structure in an embodiment of the application.
  • an embodiment of the present application provides a method for forming a memory, including: providing a substrate on which a bit line structure and a first protection layer on the top surface of the bit line structure are formed; forming a dielectric layer to fill adjacent In the gap between the bit line structure, the top surface of the dielectric layer is flush with the top surface of the first protection layer; the second protection layer is formed to cover the top surface of the first protection layer and the top surface of the dielectric layer; In the direction, part of the dielectric layer and part of the second protective layer are removed to form capacitive contact holes, and in the direction perpendicular to the extension of the bit line structure, the first protective layer located between adjacent capacitive contact holes is exposed; a conductive layer is formed Fill the capacitor contact hole and cover the exposed top surface of the first protective layer, and the top surface of the conductive layer is flush with the top surface of the second protective layer; part of the conductive layer is etched to form a discrete capacitive contact structure.
  • Figures 1 and 2 are schematic diagrams of the formation of the bit line structure and the first protective layer in this embodiment
  • Figures 3 to 5 are schematic diagrams of the formation of the dielectric layer and the second protective layer in this embodiment
  • Figures 6 to 8 are Figures 9 to 14 are schematic views of the formation of the conductive layer in this embodiment
  • Figures 15 to 17 are schematic views of the formation of the capacitive contact structure in this embodiment
  • Figures 18 to 19 are A schematic diagram of the formation of the air gap in the embodiment; the method for forming the memory provided by this embodiment will be described in detail below with reference to the accompanying drawings, and the details are as follows:
  • FIG. 1 and FIG. 2 are schematic cross-sectional views perpendicular to the direction in which the bit line structure extends.
  • a substrate 10 is provided on which a bit line structure 15 and a first located on the top surface of the bit line structure 15 are formed.
  • Protective layer 12 is provided on which a bit line structure 15 and a first located on the top surface of the bit line structure 15 are formed.
  • a substrate 10 is provided.
  • the substrate 10 includes an array region 20 (refer to FIG. 7) and a peripheral region 21 (refer to FIG. 7), and the substrate 10 includes buried word lines, shallow trench isolation structures, and Source area and other structures.
  • bit line stack 11 is formed on the substrate 10, and the bit line stack 11 includes a bit line contact layer 111, a bottom dielectric layer 112, a metal layer 113 and a top dielectric layer stacked on the substrate 10.
  • the process flow of forming the bit line stack 11 on the substrate 10 specifically includes: forming a separate bit line contact layer 111 connected to the active area in the substrate 10 on the substrate 10, and forming a filled bit line contact layer on the substrate 10 111 between the bottom dielectric layer 112, the top surface of the bottom dielectric layer 112 is flush with the top surface of the bit line contact layer 111, and a metal layer 113 is formed on the top surface of the bottom dielectric layer 112 and the top surface of the bit line contact layer 111.
  • the top surface of the metal layer 113 forms a top dielectric layer 114.
  • the material of the bit line contact layer 111 includes tungsten or polysilicon
  • the material of the bottom dielectric layer 112 and the top dielectric layer 114 includes silicon nitride, silicon dioxide or silicon oxynitride
  • the metal layer 113 is made of one conductive material or multiple conductive materials. Material formation, such as doped polysilicon, titanium, titanium nitride, tungsten and tungsten composites, etc.
  • a first protective film 115 is formed on the top of the bit line stack 11; the first protective film 115 is used to protect the bit line structure from being etched in the subsequent etching process.
  • the material of the first protective film 115 is silicon oxynitride; in other embodiments, the material of the first protective film is formed of an insulating material, such as silicon nitride or silicon oxide.
  • a patterned bit line mask layer 13 is formed on the top surface of the first protective film 115; it should be noted that the bit line mask layer 13 in FIG. 1 takes a single-layer structure as an example for illustration, which is clear to those skilled in the art In the actual etching process, the bit line mask layer 13 may also be a laminated structure.
  • the first protection film 115 and the bit line stack 11 are etched to form the bit line structure 15 and the first protection layer 12 on the top surface of the bit line structure 15 and remove Bit line mask layer 15.
  • bit line contact layer 111 is connected to the active area in the substrate 10.
  • the one shown in FIG. 2 is to the left
  • the bit line structure 15 and the bit line structure 15 to the right are connected to the active area in the substrate 10 through the bit line contact layer 111.
  • only the bit line structure 15 in the middle may pass through the bit line contact layer.
  • 111 is connected to the active area in the substrate 10.
  • FIGS. 3 and 4 are schematic cross-sectional views parallel to the direction in which the bit line structure extends
  • FIG. 5 is a schematic view of the three-dimensional structure of the memory, forming a dielectric layer 16 that fills the gap between adjacent bit line structures 15 , The top surface of the dielectric layer 16 is flush with the top surface of the first protection layer 12, and a second protection layer 17 is formed on the top surface of the first protection layer 12 and the top surface of the dielectric layer 16.
  • a dielectric film (not shown) that fills the gap between adjacent bit line structures and covers the bit line structure 15 is formed, and the dielectric film (not shown) is etched to form the dielectric layer 16; specifically , The dielectric film (not shown) above the top surface of the bit line structure 15 is removed, and the remaining dielectric film (not shown) forms the dielectric layer 16.
  • the material of the dielectric layer 16 is silicon oxide. In other embodiments, the material of the dielectric layer 16 is formed of other insulating materials, such as silicon nitride or silicon oxynitride.
  • the dielectric film (not shown) is formed by a spin coating process, and the dielectric film (not shown) formed by the spin coating method has the advantage of good filling properties.
  • a second protective layer 17 is formed on the top surface of the first protective layer 12 and the top surface of the dielectric layer 16; in this embodiment, the material of the second protective layer 17 is the same as that of the first protective layer 12; In an embodiment, the material of the second protective layer may be different from the material of the first protective layer.
  • the top structure formed by the first protection layer 12 and the second protection layer 17 effectively improves the arrangement of the top of the capacitor contact structure in the subsequent process of forming the capacitor contact structure, so that the capacitor contact structure is directly connected to the capacitor that needs to be formed later.
  • the bottom electrode plate is connected, which effectively improves the formation process of the memory.
  • the embodiment of the present application does not limit the thickness of the first protective layer 12 and the second protective layer 17, and the thickness of the first protective layer 12 and the second protective layer 17 can be set according to specific process requirements.
  • FIG. 6 and FIG. 7 are cross-sectional schematic diagrams parallel to the direction in which the bit line structure extends
  • FIG. 8 is a schematic diagram of the three-dimensional memory structure.
  • part of the dielectric layer is removed 16 and part of the second protection layer 17 form a capacitor contact hole 18, and in a direction perpendicular to the extension of the bit line structure 15, the capacitor contact hole 18 exposes the first protection layer 12 between adjacent capacitor contact holes 18.
  • a dielectric mask layer 19 is formed on the top surface of the second protection layer 17.
  • the dielectric mask layer 19 in FIG. 6 is illustrated by taking one layer as an example. It is clear to those skilled in the art that in an actual etching process, the dielectric mask layer 19 may have a laminated structure.
  • the second protection layer 17 is etched until a part of the first protection layer 12 and a part of the dielectric layer 16 are exposed, and the exposure is removed. Part of the dielectric layer 16 that is left out forms a capacitor contact hole 18.
  • FIG. 8 for a schematic diagram of the three-dimensional structure of the memory formed at this time.
  • the capacitor contact hole 18 after forming the capacitor contact hole 18 and before forming the conductive layer to fill the capacitor contact hole 18, it further includes: forming an isolation film (not shown) on the substrate 10, an isolation film (not shown) (Shown) are located on the top surface of the second protective layer 17 and the first protective layer 12, and the surface of the substrate 10 on the sidewall and bottom of the capacitor contact hole 18.
  • the isolation film (not shown) is formed by atomic layer deposition.
  • Atomic layer deposition has the characteristics of slow deposition rate, high density of the deposited film and good step coverage; in this way, the isolation film (not shown) (Shown) can effectively isolate and protect under the condition of a thinner thickness, and prevent the isolation film (not shown) from occupying a small space between adjacent bit line structures 15.
  • the isolation film (not shown) on the top surface of the second protection layer 17, the top surface of the first protection layer 12 and the surface of the substrate 10 is removed to form an isolation layer 30 on the sidewall of the capacitor contact hole 18.
  • part of the substrate 10 needs to be etched away until the surface of the active area in the substrate 10 is exposed, so as to facilitate the bottom of the conductive layer and the active area to be formed later. Connected.
  • the isolation layer 30 is only shown in the schematic cross-sectional view parallel to the bit line structure. In the specific three-dimensional structure diagram, in order for those skilled in the art to intuitively see the top shape For the difference, the structure of the isolation layer 30 is not given. Those skilled in the art should know that the isolation layer 30 should be included in the three-dimensional structure diagram of the present application.
  • FIGS. 10-12 are schematic cross-sectional views parallel to the direction in which the bit line structure extends.
  • FIG. 13 is a schematic diagram of the three-dimensional structure of the memory.
  • FIG. 14 is a schematic top view of the memory.
  • the capacitor contact hole 18 is filled to form a conductive layer.
  • the top surface of the conductive layer is flush with the top surface of the second protection layer 17, and in the direction perpendicular to the bit line structure 15, the conductive layer also covers the top surface of the first protection layer 12 exposed by the remaining second protection layer 17, The conductive layer is used to subsequently form a capacitive contact structure.
  • the conductive layer includes a first conductive layer 31 and a second conductive layer 33.
  • the materials of the first conductive layer 31 and the second conductive layer 33 are different, and the top surface of the second conductive layer 33 and the second protective layer
  • the top cladding surface of 17 is flush, and in the direction perpendicular to the extension of the bit line structure 15, the second conductive layer 15 covers the top surface of the first protection layer 12.
  • the material of the first conductive layer 31 is a semiconductor conductive material, such as polysilicon, and the top conductive material is a metal conductive material, such as tungsten, silver, and other metal materials with low resistivity.
  • the conductive layer in this embodiment is illustrated in a two-layer manner, which does not constitute a limitation to this embodiment. In other embodiments, the conductive layer may also have a single-layer structure. The steps of forming the conductive layer are described below in conjunction with the drawings:
  • a first conductive layer 31 is formed in the capacitor contact hole 18, and the height of the top surface of the first conductive layer 31 is lower than the height of the top surface of the first protective layer 12.
  • a top conductive film 32 is formed on the top surface of the first conductive layer 31, the top surface of the first protective layer 12, and the top surface of the second protective layer 17.
  • the top conductive film 32 is formed by a spin coating process, and the top conductive film (not shown) formed by the spin coating method has the advantage of good filling properties.
  • the top conductive film 32 is etched to form the second conductive layer 33.
  • the top conductive film 32 is etched to form the second conductive layer 33 by chemical mechanical polishing; the top surface of the top conductive film 32 is planarized by chemical mechanical polishing, and chemical mechanical polishing is relative to etching.
  • the process has a higher removal rate, which is beneficial to shorten the process cycle.
  • FIG. 13 for a schematic diagram of the three-dimensional structure of the formed memory
  • FIG. 14 for the top view of its top morphology.
  • the capacitor contact holes are arranged in a square shape for subsequent filling to form a capacitor contact structure.
  • the capacitor contact holes and the dielectric layer 16 are alternately arranged;
  • the capacitor contact holes and the bit line structure 15 are alternately arranged.
  • the capacitor contact holes are arranged in a square shape.
  • the arrangement of the capacitor contact holes and the bottom electrode of the capacitor is different, and it is usually necessary to form an additional layer of dislocation contact pads to connect the bottom electrode plate of the capacitor to the capacitor contact structure. The process is complicated and the progress is slow.
  • the first protective layer 12 and the second protective layer 17 have a height difference structure, and the capacitive contact structure formed by etching changes the arrangement of the top of the capacitive contact structure.
  • the capacitive contact structure formed by etching changes the arrangement of the top of the capacitive contact structure.
  • FIG. 8 and FIG. 13 because of the The height difference between a protection layer 12 and a second protection layer 17, and the formed conductive layer is used to fill the capacitor contact hole and the top surface of the first protection layer 12. In the direction perpendicular to the extension of the bit line structure 15, adjacently fill the capacitor The conductive layer of the contact hole is connected through the top surface of the first protective layer 12.
  • the top morphology of the capacitive contact structure formed by etching the contact mask layer 40 as a mask refers to FIG. 17, the top surface of the etched conductive layer 41 and The top surface of the first protection layer 12 is flush, and the top surface of the conductive layer 42 that is not etched is flush with the second protection layer 17.
  • the original capacitive contact structure alternately arranged with the bit line structure 15 in the direction perpendicular to the bit line structure 15, at this time, the top part is located on the top surface of the first protection layer 12, and the direction is preset There is a certain angle with the direction in which the bit line structure 15 extends, which changes the arrangement of the top of the capacitor contact structure and is closer to the smallest hexagonal arrangement of the capacitors that need to be formed subsequently, thereby optimizing the space utilization and allowing subsequent
  • the size of the formed capacitor is larger, and the process step of making a dislocation contact is omitted, which greatly optimizes the method of forming the memory.
  • FIG. 15 is a schematic cross-sectional view parallel to the extending direction of the bit line structure
  • FIG. 16 and FIG. 17 are schematic top views of the memory.
  • Part of the conductive layer 34 is etched to form a separate capacitive contact structure.
  • a contact mask layer 40 is formed on the top surface of the conductive layer 34 and the second protective layer 17; the contact mask layer 40 exposes the conductive layer 34 and the second protective layer with a predetermined width in a predetermined direction.
  • the angle of the extension direction of 15 is ⁇ , ⁇ is greater than 0° and ⁇ is not equal to 90°; based on the preset direction, the exposed conductive layer 34 is etched until a part of the first protective layer 12 is exposed; the contact mask layer is removed 40.
  • the remaining conductive layer serves as a capacitive contact structure.
  • the preset direction is that there is a certain included angle ⁇ ( ⁇ is greater than 0° and ⁇ is not equal to 90°) with the direction in which the bit line structure 15 extends, and the conductive layer 34 exposed by the contact mask layer 40 is etched until it is exposed.
  • the first protective layer 12 is removed, and the contact mask layer 40 is removed.
  • the height of the etched remaining conductive layer 41 (the dot-filled part in the figure) is the same as the height of the first protective layer 12, and the unetched The height of the remaining conductive layer 42 is consistent with the height of the second protective layer 17.
  • the remaining conductive layer 41 that is etched is not electrically connected to the remaining conductive layer 42 that is not etched; and the second protective layer 12 is not exposed.
  • the remaining conductive layer 41 that is etched is electrically connected to the remaining conductive layer 42 that is not etched. That is, the conductive layers are separated from each other by the position of the exposed first protective layer 12 to form a separate capacitive contact structure (the etched remaining conductive layer 41 that is not separated by the first protective layer 12 and the unetched remaining conductive layer 42).
  • the square arrangement of the top of the capacitor contact structure that is consistent with the capacitor contact holes is changed, and it is directly connected with the subsequent capacitor bottom electrode plate, which eliminates the process step of making misaligned contact pads. Optimized the formation method of the memory.
  • the method further includes: removing the dielectric layer 16 to form an air gap 50.
  • the method further includes: removing the dielectric layer 16 to form an air gap 50.
  • an isolation mask layer (not shown) on the top surface of the second protective layer 17 is formed, based on the isolation mask layer (not shown), patterned in a direction parallel to the bit line structure 15
  • the second protective layer 17 on the top of the capacitor structure is removed to expose the dielectric layer 16 between the capacitor contact structures, and the dielectric layer 16 between the capacitor contact structures is removed to form an air gap 50.
  • a sealing layer 51 is formed, and the sealing layer 51 seals the top of the air gap 50.
  • the sealing layer 51 is formed by a rapid sealing process, and the sealing layer 51 seals the air gap 50 to form an air gap isolation structure, which greatly improves the parasitic capacitance between the capacitor contact structures, and makes the structure of the formed memory more excellent. .
  • the sealing layer 51 is formed by a rapid sealing process, which has the effect of rapid deposition.
  • the formed sealing layer 51 is used to seal the top of the air gap 50 to form an air isolation structure.
  • the material of the sealing layer 51 is silicon nitride.
  • the material of the sealing layer is an insulating semiconductor material, such as silicon oxynitride or silicon oxide.
  • the first protective layer is formed on the top of the bit line stack, and the second protective layer is formed on the top of the first protective layer in the subsequent manufacturing process;
  • a high- and low-level interlaced protective layer is formed on the top of the line structure, which not only helps to reduce the loss of the bit line structure during the etching process;
  • Another embodiment of the present application relates to a memory, which can be formed by the above-mentioned forming method.
  • FIG. 2 FIG. 12, and FIG. 17, the memory provided in this embodiment will be described in detail below in conjunction with the accompanying drawings. The parts that are the same as or corresponding to the above embodiment will not be described in detail below.
  • the memory includes: a substrate 10 and a bit line structure 15 located on the substrate 10; a first protection layer 12 located on the top surface of the bit line structure 15; a capacitive contact structure and an isolation structure located between the bit line structures 15 in place In the direction in which the line structure 15 extends, the capacitive contact structure and the isolation structure are alternately arranged; the second protection layer 17, the first protection layer 12 located between the adjacent bit line structures 15 and the top surface of the isolation structure, the second protection layer
  • the extension direction of 17 is perpendicular to the extension direction of the bit line structure 15; the top of the capacitive contact structure has protrusions, and the protrusions extend at intervals in a preset direction.
  • the protrusions are also located on a part of the top surface of the first protective layer 12, and
  • the angle between the direction and the direction in which the bit line structure 15 extends is ⁇ , which is greater than 0° and ⁇ is not equal to 90°.
  • the substrate 10 includes an array region and a peripheral region, and the substrate 10 includes structures such as buried word lines, shallow trench isolation structures, and active regions.
  • the bit line structure 15 includes a bit line contact layer 111 or a bottom layer matrix layer 112, a metal layer 113 and a top layer dielectric layer 114 sequentially stacked on the substrate 10; wherein the material of the bit line contact layer 111 includes tungsten or polysilicon, The material of the bottom dielectric layer 112 and the top dielectric layer 114 includes silicon nitride, silicon dioxide or silicon oxynitride, and the metal layer 113 is formed of one conductive material or multiple conductive materials, such as doped polysilicon, titanium, titanium nitride, Tungsten and tungsten composites, etc.
  • the first protection layer 112 is used to protect the bit line structure from being etched in a subsequent etching process.
  • the material of the first protective layer 112 is silicon oxynitride; in other embodiments, the material of the first protective layer is formed of an insulating material, such as silicon nitride or silicon oxide.
  • bit line contact layer 111 only one of the adjacent bit line structures 15 is connected to the active area in the substrate 10 through the bit line contact layer 111.
  • the isolation structure includes a dielectric layer or an air gap.
  • the isolation structure between the capacitive contact structures is the dielectric layer 16.
  • the material of the dielectric layer 16 is silicon oxide.
  • the material of the dielectric layer 16 is formed of an insulating material, such as silicon nitride or silicon oxynitride.
  • the second protective layer 17 extends perpendicular to the direction in which the bit line structure 15 extends, and is located on the top surface of the first protective layer 12 and the isolation structure between adjacent bit line structures; in this embodiment, the second protective layer 17
  • the material of is the same as the material of the first protective layer 12; in other embodiments, the material of the second protective layer is formed of an insulating material, such as silicon nitride or silicon oxide.
  • the second protection layer 17 is located in a direction perpendicular to the extending direction of the bit line structure 15.
  • the top structure formed by the first protective layer 12 and the second protective layer 17 effectively improves the arrangement of the capacitive contact structure in the subsequent process of forming the capacitive contact structure, and is directly connected to the lower electrode plate of the capacitor to be formed later. Connected, effectively improving the formation process of the memory.
  • the embodiment of the present application does not limit the thickness of the first protective layer 12 and the second protective layer 17, and the thickness of the first protective layer 12 and the second protective layer 17 can be set according to specific process requirements.
  • the capacitive contact structure and the isolation structure located between the bit line structure 15 are alternately arranged in the direction in which the bit line structure extends; and in the preset direction, the capacitive contact structure has protrusions and protrusions. It is also located on the top surface of part of the first protection layer, and the preset direction has an angle with the direction in which the bit line structure 15 extends; wherein, the bottom of the capacitive contact structure is connected to the active area in the substrate 10.
  • the included angle is ⁇ , ⁇ is greater than 0° and ⁇ is not equal to 90°.
  • the position of the first protective layer 12 is exposed, and the remaining conductive layer 41 that is etched is not electrically connected to the remaining conductive layer 42 that is not etched (that is, the bump on the top of the capacitive contact structure) ; Where the second protective layer 12 is not exposed, the remaining conductive layer 41 that is etched is electrically connected to the remaining conductive layer 42 that is not etched (that is, the bump on the top of the capacitive contact structure).
  • the conductive layers are separated from each other by the position of the exposed first protective layer 12 to form a separate capacitive contact structure (the etched remaining conductive layer 41 that is not separated by the first protective layer 12 and the unetched remaining conductive layer 42)
  • the original square arrangement of the capacitor contact structure is changed, and it is directly connected to the subsequently formed capacitor bottom electrode plate, eliminating the process step of making misaligned contacts, and greatly improving the formation method of the memory.
  • the memory further includes an isolation layer, and the isolation layer is located on the sidewall of the isolation structure.
  • the isolation structure between the capacitive contact structures is an air gap.
  • the top part of the formed capacitive contact structure is located on the top surface of the first protective layer, which changes the arrangement of the original capacitive contact structure, so that the connection between the subsequently formed capacitor and the capacitive contact structure becomes Simple, thereby improving the current process flow of the memory manufacturing process, thereby improving the production efficiency of the memory and reducing the production and operation cost of the memory.

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Abstract

一种存储器的形成方法及存储器，存储器的形成方法包括：提供基底(10)，基底(10)上形成有位线结构(15)以及第一保护层(12)；形成介质层(16)填充相邻位线结构(15)之间的间隙；形成第二保护层(17)覆盖第一保护层(12)顶部表面和介质层(16)的顶部表面；去除部分介质层(16)以及部分第二保护层(17)，形成电容接触孔(18)，暴露出位于相邻电容接触孔(18)之间的第一保护层(12)；形成导电层填充电容接触孔(18)并覆盖暴露出的第一保护层(12)的顶部表面，且导电层(31, 33)顶部表面与第二保护层(17)顶部表面齐平；刻蚀部分导电层(34)形成分立的电容接触结构。

Description

存储器的形成方法及存储器
交叉引用
本申请引用于2020年5月22日递交的名称为“存储器的形成方法及存储器”的第202010440404.8号中国专利申请，其通过引用被全部并入本申请。
技术领域
本申请涉及半导体领域，特别涉及一种存储器的形成方法及存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory,DRAM)的制造方法中主要涉及存储阵列区中的存储节点接触(Storage Node Contact)、电容与电容接触垫(landing pad)之间的连接层以及电容接触结构之间的隔离结构的制造。
随着半导体集成电路器件技术的不断发展，如何优化工艺流程可以有效的提高存储器的生产效率和降低存储器生产运营成本变得至关重要。存储器制程技术集成到20nm以下，半导体制程工艺集成度增加，缩小元件尺寸的难度越来越大。
尤其在存储器的阵列区的制程工艺过程中，各器件的工艺流程需要克服一系列的工艺难题以及工艺流程衔接时可避免的一些问题，是当前亟待解决的问题。
发明内容
本申请实施例提供一种存储器的形成方法及存储器，简化了目前存储器的制程工艺，进而提高存储器的生产效率和降低存储器生产运营成本。
为解决上述技术问题，本申请实施例提供了一种存储器的形成方法，包 括：提供基底，基底上形成有位线结构以及位于位线结构顶部表面的第一保护层；形成介质层填充相邻位线结构之间的间隙，介质层的顶部表面与第一保护层顶部表面齐平；形成第二保护层覆盖第一保护层顶部表面和介质层的顶部表面；在垂直于位线结构延伸的方向上，去除部分介质层以及部分第二保护层，形成电容接触孔，且在垂直于位线结构延伸的方向上，暴露出位于相邻电容接触孔之间的第一保护层；形成导电层填充电容接触孔并覆盖暴露出的第一保护层的顶部表面，且导电层顶部表面与第二保护层顶部表面齐平；刻蚀部分导电层形成分立的电容接触结构。
本申请实施例通过调整存储器的制程工艺的流程，在形成位线叠层时，在位线叠层顶部形成第一保护层，在后续的制程工艺中于第一保护层顶部形成第二保护层；巧妙的在位线结构顶部形成高低层次交错的保护层，这不仅有利于降低蚀刻过程中对位线结构的损耗；并且利用存在高低层次交错的保护层形成的顶层架构，经过一步刻蚀，巧妙的形成电容与电容接触结构之间的连接层。简化了目前存储器的制程工艺的流程，进而提高存储器的生产效率和降低存储器生产运营成本。
另外，刻蚀部分导电层形成分立的电容接触结构，包括：在导电层以及第二保护层的顶部表面形成接触掩膜层；接触掩膜层于预设方向上暴露出预设宽度的导电层以及第二保护层，且于垂直于预设方向上，接触掩膜层与被暴露出的导电层以及第二保护层交替排布；预设方向与位线结构延伸的方向夹角为α，α大于0°且α不等于90°；刻蚀被暴露出的导电层，直至暴露出部分第一保护层的顶部表面；去除接触掩膜层，剩余导电层作为电容接触结构。
另外，基底上形成有位线结构以及位于位线结构顶部表面的第一保护层， 包括：在基底上形成位线叠层，在位线叠层顶部形成第一保护膜；在第一保护膜顶部表面形成已图案化的位线掩膜层，以位线掩膜层为掩膜，刻蚀第一保护膜以及位线叠层，形成位线结构以及位于位线结构顶部表面的第一保护层；去除位线掩膜层。
另外，在基底上形成位线叠层，包括：在基底上形成与基底中的有源区相连且分立的位线接触层；在基底上形成填充位线接触层之间间隙的底层介质层，底层介质层的顶部表面与位线接触层的顶部表面齐平；在底层介质层顶部表面以及位线接触层顶部表面形成金属层；在金属层顶部表面形成顶层介质层。
另外，在垂直于位线结构延伸的方向上，去除部分介质层以及部分第二保护层，形成电容接触孔，包括：在第二保护层顶部表面形成介质掩膜层；以介质掩膜层为掩膜，在垂直于位线结构延伸的方向上，刻蚀部分第二保护层直至暴露出部分第一保护层以及部分介质层的顶部表面；去除被暴露出的部分介质层，形成电容接触孔。
另外，在形成电容接触孔之后，且在形成导电层填充电容接触孔之前，包括：在基底上形成隔离膜，隔离膜覆盖第二保护层和被暴露出的第一保护层，以及电容接触孔侧壁和底部；去除位于第二保护层顶部表面、被暴露出的第一保护层顶部表面以及电容接触孔底部的隔离膜，形成位于电容接触孔侧壁的隔离层。通过形成介质层与后续形成的电容接触结构之间的隔离层，降低后续形成的电容接触结构间的寄生电容。
另外，导电层包括第一导电层和第二导电层，第一导电层与第二导电层的材料不相同，且第二导电层顶部表面与第二保护层顶部表面齐平，且于垂直于位线结构延伸的方向上，第二导电层还覆盖的顶部表面。
另外，形成导电层填充电容接触孔，包括：在电容接触孔中形成第一导电层，第一导电层顶部表面低于第一保护层顶部表面；在第一导电层顶部表面、第一保护层顶部表面以及第二保护层顶部表面形成顶部导电膜；刻蚀顶部导电膜，形成第二导电层。
另外，在形成分立的电容接触结构之后，包括：形成位于第二保护层顶部表面的隔离掩膜层；以隔离掩膜层为掩膜，于位线结构延伸的方向上，图案化位于电容接触结构顶部的第二保护层，暴露出位于电容接触结构之间的介质层；去除位于电容接触结构之间的介质层，形成空气间隙；形成封口层，封口层密封空气间隙的顶部。通过在第一保护层和第二保护层上定位去除电容接触结构之间的介质层，形成空气间隙，以减小电容接触结构之间的介电常数，从而降低电容接触结构之间的寄生电容，并且空气间隙对存储器集成度的缩小至关重要。
另外，形成介质层填充相邻位线结构之间的间隙，包括：形成填充相邻位线结构之间间隙的介质膜，介质膜覆盖位线结构；去除高于位线结构顶部表面的介质膜，剩余介质膜形成介质层。
本申请实施例还提供了一种存储器，包括：基底，以及位于基底上的位线结构；第一保护层，位于位线结构的顶部表面；位于位线结构之间的电容接触结构以及隔离结构，在位线结构延伸的方向上，电容接触结构与隔离结构交替排布；第二保护层，位于相邻位线结构之间的第一保护层以及隔离结构的顶部表面，第二保护层的延伸方向不同于位线结构延伸的方向；电容接触结构的顶部具有凸起，且凸起在预设方向上间隔延伸，凸起还位于部分第一保护层的顶部表面，预设方向与位线结构延伸的方向具有夹角。
另外，预设方向与位线结构延伸的方向夹角为α，α大于0°且α不等于90°。
另外，第二保护层的延伸方向垂直于位线结构延伸的方向。
另外，存储器还包括：隔离层，隔离层位于隔离结构侧壁。通过隔离结构与电容接触结构之间的隔离层，降低电容接触结构间的寄生电容。
另外，隔离结构包括介质层或空气间隙。通过介质层作为隔离结构，由于介质层是在填充位线结构之间的间隙时形成，无需额外进行制程流程，从而提高存储器的生产效率；采用空气间隙作为隔离结构，能有效的减小电容接触结构之间的介电常数，降低电容接触结构之间的寄生电容，从而提高存储器的性能。
相比于相关技术，本申请形成的电容接触结构的顶部部分位于第一保护层的顶部表面，改变了原有电容接触结构的排布方式，使得后续形成的电容与电容接触结构之间的连接变得简单，从而改善了目前存储器的制程工艺的流程，进而提高存储器的生产效率和降低存储器生产运营成本。
附图说明
图1和图2为本申请实施例中位线结构以及第一保护层的形成示意图；
图3至图5为本申请实施例中介质层以及第二保护层的形成示意图；
图6至图8为本申请实施例中电容接触孔的形成示意图；
图9至图14为本申请实施例中导电层的形成示意图；
图15至图17为本申请实施例中电容接触结构的形成示意图；
图18至图19为本申请实施例中空气间隙的形成示意图。
具体实施方式
目前，存储器的制造流程较为复杂，严重影响了存储器的生产效率和降低存储器生产运营成本。
为解决上述问题，本申请一实施例提供了一种存储器的形成方法，包括：提供基底，基底上形成有位线结构以及位于位线结构顶部表面的第一保护层；形成介质层填充相邻位线结构之间的间隙，介质层的顶部表面与第一保护层顶部表面齐平；形成第二保护层覆盖第一保护层顶部表面和介质层的顶部表面；在垂直于位线结构延伸的方向上，去除部分介质层以及部分第二保护层，形成电容接触孔，且在垂直于位线结构延伸的方向上，暴露出位于相邻电容接触孔之间的第一保护层；形成导电层填充电容接触孔并覆盖被暴露出的第一保护层顶部表面，且导电层顶部表面与第二保护层顶部表面齐平；刻蚀部分导电层形成分立的电容接触结构。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1和图2为本实施例中位线结构以及第一保护层的形成示意图，图3至图5为本实施例中介质层以及第二保护层的形成示意图，图6至图8为本实施例中电容接触孔的形成示意图，图9至图14为本实施例中导电层的形成示意图，图15至图17为本实施例中电容接触结构的形成示意图，图18至图19为 本实施例中空气间隙的形成示意图；下面结合附图对本实施例提供的存储器的形成方法进行详细说明，具体如下：
参考图1和图2，图1和图2为垂直于位线结构延伸的方向上的剖面示意图，提供基底10，基底10上形成有位线结构15以及位于位线结构15顶部表面的第一保护层12。
具体地，参考图1，提供基底10，基底10包括阵列区20(参考图7)以及外围区21(参考图7)，且基底10内包括埋入式字线、浅沟槽隔离结构、有源区等结构。
在基底10上形成位线叠层11，位线叠层11包括在基底10上堆叠形成的位线接触层111、底层介质层112、金属层113和顶层介质层。
在基底10上形成位线叠层11的工艺流程，具体包括：在基底10上形成与基底10中的有源区相连且分立的位线接触层111，在基底10上形成填充位线接触层111之间空隙的底层介质层112，底层介质层112的顶部表面与位线接触层111的顶部表面齐平，在底层介质层112顶部表面以及位线接触层111顶部表面形成金属层113，在金属层113顶部表面形成顶层介质层114。
其中，位线接触层111的材料包括钨或多晶硅，底层介质层112和顶层介质层114的材料包括氮化硅、二氧化硅或氮氧化硅，金属层113由一种导电材料或者多种导电材料形成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等。
在位线叠层11顶部形成第一保护膜115；第一保护膜115用于保护位线结构在后续的刻蚀工艺中不被刻蚀。
在本实施例中，第一保护膜115的材料为氮氧化硅；在其他实施例中， 第一保护膜的材料采用绝缘材料形成，例如氮化硅或氧化硅等材料。
在第一保护膜115顶部表面形成已图案化的位线掩膜层13；需要说明的是，图1中的位线掩膜层13以单层结构为例进行举例说明，本领域技术人员清楚，在实际的刻蚀工艺中，位线掩膜层13也可以为叠层结构。
参考图2，以位线掩膜层13为掩膜，刻蚀第一保护膜115以及位线叠层11，形成位线结构15以及位线结构15顶部表面的第一保护层12，并去除位线掩膜层15。
需要说明的是，在同一位线结构的截面上，相邻的位线结构15只有一个通过位线接触层111与基底10中的有源区相连，附图2中给出的是靠左的位线结构15与靠右的位线结构15通过位线接触层111与基底10中的有源区相连，在其他的截面附图中，可能仅为中间的位线结构15通过位线接触层111与基底10中的有源区相连。
参考图3至图5，图3和图4为平行于位线结构延伸的方向上的剖面示意图，图5为存储器立体结构示意图，形成填充相邻位线结构15之间的间隙的介质层16，介质层16的顶部表面与第一保护层12顶部表面齐平，在第一保护层12顶部表面和介质层16顶部表面形成第二保护层17。
具体地，参考图3，形成填充相邻位线结构之间的间隙，且覆盖位线结构15的介质膜(未图示)，刻蚀介质膜(未图示)形成介质层16；具体地，去除高于位线结构15顶部表面的介质膜(未图示)，剩余介质膜(未图示)形成介质层16。
在本实施例中，介质层16的材料为氧化硅，在其他实施例中，介质层16的材料采用其他绝缘材料形成，例如，氮化硅或氮氧化硅等材料。
另外，在本实施例中，介质膜(未图示)采用旋转涂覆工艺形成，采用旋转涂覆的方式形成的介质膜(未图示)具有填充性好的优点。
参考图4，在第一保护层12顶部表面和介质层16顶部表面形成第二保护层17；在本实施例中，第二保护层17的材料与第一保护层12的材料相同；在其他实施例中，第二保护层的材料可以与第一保护层的材料不相同。
第一保护层12与第二保护层17构成的顶层架构，在后续形成电容接触结构的过程中，有效地改善了电容接触结构顶部的排布方式，使得电容接触结构直接与后续需要形成的电容的下电极板相连，有效地改善了存储器的形成工艺。
需要说明的是，本申请实施例并不对第一保护层12和第二保护层17的厚度进行限定，第一保护层12和第二保护层17的厚度可根据具体的工艺需求进行设定。
第二保护层17沉积完成后，此时存储器的空间结构如图5所示。
参考图6至图8，图6和图7为平行于位线结构延伸的方向上的剖面示意图，图8为存储器立体结构示意图，在垂直于位线结构15延伸的方向上，去除部分介质层16以及部分第二保护层17，形成电容接触孔18，且在垂直于位线结构15延伸的方向上，电容接触孔18暴露出位于相邻电容接触孔18之间的第一保护层12。
具体地，参考图6，在第二保护层17顶部表面形成介质掩膜层19。
需要说明的是，图6中的介质掩膜层19以一层为例进行举例说明，本领域技术人员清楚，在实际的刻蚀工艺中，介质掩膜层19可以为叠层结构。
参考图7，以介质掩膜层19为掩膜，在垂直于位线结构15延伸的方向 上，刻蚀第二保护层17直至暴露出部分第一保护层12以及部分介质层16，去除暴露出的部分介质层16形成电容接触孔18。
此时形成的存储器的立体结构示意图参考图8。
参考图9，在本实施例中，在形成电容接触孔18之后，且在形成导电层填充电容接触孔18之前，还包括：在基底10上形成隔离膜(未图示)，隔离膜(未图示)位于第二保护层17和第一保护层12的顶部表面，以及电容接触孔18侧壁和底部的基底10表面。
具体地，采用原子层沉积的方式形成隔离膜(未图示)，原子层沉积具有沉积速率慢，沉积形成的膜层致密性高和阶梯覆盖率好等特点；如此，能够使得隔离膜(未图示)能够在厚度较薄的条件下进行有效地隔离保护，避免隔离膜(未图示)占据相邻位线结构15之间较小的空间。
去除位于第二保护层17顶部表面、第一保护层12顶部表面以及基底10表面的隔离膜(未图示)，形成位于电容接触孔18侧壁的隔离层30。
在去除基底10表面的隔离膜(未图示)的过程中，需要刻蚀掉部分基底10，直至暴露出基底10中有源区的表面，以便于后续形成的导电层的底部与有源区相连。
需要说明的是，后续的附图中仅在平行于位线结构的剖面示意图中给出了隔离层30，在具体的立体结构图中，为了本领域技术人员可以直观的看出顶部形貌的差异，并没有给出隔离层30的结构示意，本领域技术人员应该知晓，在本申请的立体结构示意图中应该包括隔离层30。
参考图10～图14，图10至图12为平行于位线结构延伸的方向上的剖面示意图，图13为存储器立体结构示意图，图14为存储器的俯视示意图，填充 电容接触孔18形成导电层，导电层顶部表面与第二保护层17顶部表面齐平，且于垂直于位线结构15方向上，导电层还覆盖由剩余第二保护层17暴露出的第一保护层12的顶部表面，导电层用于后续形成电容接触结构。
在本实施例中，导电层包括第一导电层31和第二导电层33，第一导电层31与第二导电层33的材料不相同，且第二导电层33顶部表面与第二保护层17顶部包面齐平，且于垂直于位线结构15延伸的方向上，第二导电层15覆盖第一保护层12的顶部表面。
其中，第一导电层31的材料为半导体导电材料，例如多晶硅等材料；顶部导电材料为金属导电材料，例如钨、银等电阻率较小的金属材料。需要说明的是，本实施例中导电层以两层的方式进行举例说明，并不构成对本实施例的限定，在其他实施例中，导电层也可以仅为单层结构。以下结合附图对导电层的形成步骤进行说明：
参考图10，在电容接触孔18中形成第一导电层31，第一导电层31顶部表面的高度低于第一保护层12顶部表面的高度。
参考图11，在第一导电层31顶部表面、第一保护层12顶部表面和第二保护层17顶部表面形成顶部导电膜32。
具体地，在本实施例中，顶部导电膜32采用旋转涂覆工艺形成，采用旋转涂覆的方式形成的顶部导电膜(未图示)具有填充性好的优点。
参考图12，刻蚀顶部导电膜32形成第二导电层33。
在本实施例中，刻蚀顶部导电膜32形成第二导电层33采用化学机械研磨的方式；采用化学机械研磨的方式将顶部导电膜32顶部表面进行平坦化处理，化学机械研磨相对于刻蚀工艺具有较高的去除速率，有利于缩短工艺周期。
此时，形成的存储器的立体结构示意图参考图13，其顶部形貌的俯视图参考图14。
参考图8，电容接触孔呈四方排布，用于后续填充形成电容接触结构，在平行于位线结构15延伸的方向上，电容接触孔与介质层16交替排布；在垂直于位线结构15延伸的方向上，电容接触孔与位线结构15交替排布，此时，从存储器的顶部来看，电容接触孔呈四方排布。电容接触孔与电容的下电极之间的排布方式不同，通常需要额外形成一层错位接触垫，以使电容的下电极板与电容接触结构相连，工艺复杂且进度缓慢。
本申请实施例通过第一保护层12和第二保护层17存在高度差的架构，刻蚀形成的电容接触结构，改变了电容接触结构顶部的排布方式，参考图8以及图13，由于第一保护层12和第二保护层17的高度差，形成的导电层用于填充电容接触孔以及第一保护层12的顶部表面，在垂直于位线结构15延伸的方向上，相邻填充电容接触孔的导电层通过第一保护层12的顶部表面相连。结合图16在预设方向上形成的接触掩膜层40，以接触掩膜层40作为掩膜刻蚀形成的电容接触结构的顶部形貌参考图17，被刻蚀的导电层41顶部表面与第一保护层12顶部表面齐平，未被刻蚀的导电层42顶部表面与第二保护层17齐平。
相比于相关技术，原本在垂直于位线结构15延伸的方向上与位线结构15交替排布的电容接触结构，此时，顶部部分位于第一保护层12的顶部表面，且预设方向与位线结构15延伸的方向存在一定夹角，从而改变了电容接触结构顶部的排布方式，更加接近于与后续需要形成的电容的最小六方的排布方式，从而优化空间利用率，让后续形成的电容尺寸更大，而且，还省去了制作错位接触电的这一工艺步骤，极大的优化了存储器的形成方法。
参考图15至图17，图15为平行于位线结构延伸的方向上的剖面示意图，图16和图17为存储器的俯视示意图，刻蚀部分导电层34形成分离的电容接触结构。
参考图15及图16，在导电层34以及第二保护层17的顶部表面形成接触掩膜层40；接触掩膜层40于预设方向上暴露出预设宽度的导电层34以及第二保护层17，且于垂直于预设方向上，接触掩膜层40与暴露出的导电层34以及第二保护层17交替排布；预设方向(参考图17中的虚线22)与位线结构15延伸的方向夹角为α，α大于0°且α不等于90°；基于预设方向上，刻蚀暴露出的导电层34，直至暴露出部分第一保护层12；去除接触掩膜层40，剩余的导电层作为电容接触结构。
具体地，预设方向为与位线结构15延伸的方向存在一定的夹角α(α大于0°且α不等于90°)，刻蚀接触掩膜层40暴露出的导电层34，直至暴露出第一保护层12，去除接触掩膜层40，此时，被刻蚀的剩余导电层41(图中的点填充部分)的高度与第一保护层12的高度一致，未被刻蚀的剩余导电层42的高度与第二保护层17的高度一致。
此时，从俯视图上看，暴露出第一保护层12的位置，被刻蚀的剩余导电层41与未被刻蚀的剩余导电层42没有电连接；而在没有暴露出第二保护层12的位置，被刻蚀的剩余导电层41与未被刻蚀的剩余导电层42有电连接。即导电层通过暴露出的第一保护层12的位置相互分离，形成分立的电容接触结构(未被第一保护层12分离的被刻蚀的剩余导电层41以及未被刻蚀的剩余导电层42)，改变了电容接触结构顶部原本与电容接触孔保持一致的四方排布的方式，与后续形成的电容下电极板直接相连，省去了制作错位接触垫的这一工艺 步骤，极大的优化了存储器的形成方法。
另外，参考图18及图19，在本实施例中，形成分立的电容接触结构之后，还包括：去除介质层16形成空气间隙50。通过在第一保护层12和第二保护层17上定位去除电容接触结构之间的介质层16，形成空气间隙，以减小电容接触结构之间的介电常数，从而降低电容接触结构之间的寄生电容，并且空气间隙对存储器集成度的缩小至关重要。
具体地，参考图18，形成位于第二保护层17顶部表面的隔离掩膜层(未图示)，基于隔离掩膜层(未图示)，在平行于位线结构15方向上，图案化并去除位于电容结构顶部的第二保护层17，暴露出位于电容接触结构之间的介质层16，去除位于电容接触结构之间的介质层16，形成空气间隙50。
参考图19，形成封口层51，封口层51密封空气间隙50的顶部。
采用快速封口工艺形成封口层51，封口层51对空气间隙50进行封口处理，以形成空气间隙隔离结构，极大的改善电容接触结构之间的寄生电容，使得形成的存储器的结构性能更为优异。
具体地，采用快速封口工艺的方式形成封口层51，具有快速沉积的作用，形成的封口层51用于对空气间隙50的顶部进行封口，以形成空气隔离结构。在本实施例中，封口层51的材料为氮化硅，在其他实施例中，封口层的材料为绝缘的半导体材料，例如氮氧化硅或氧化硅等。
与相关技术相比，本申请在形成位线叠层时，在位线叠层顶部形成第一保护层，在后续的制程工艺中于第一保护层顶部形成第二保护层；巧妙的在位线结构顶部形成高低层次交错的保护层，这不仅有利于降低蚀刻过程中对位线结构的损耗；并且利用存在高低层次交错的保护层形成的顶层架构，经过一步 刻蚀，巧妙的形成电容与电容接触结构之间的连接层。简化了目前存储器的制程工艺的流程，进而提高存储器的生产效率和降低存储器生产运营成本。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请另一实施例涉及一种存储器，该存储器可采用上述的形成方法形成。
参考图2、图12以及图17，以下将结合附图对本实施例提供的存储器进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
存储器，包括：基底10，以及位于基底10上的位线结构15；第一保护层12，位于位线结构15的顶部表面；位于位线结构15之间的电容接触结构以及隔离结构，在位线结构15延伸的方向上，电容接触结构与隔离结构交替排布；第二保护层17，位于相邻位线结构15之间的第一保护层12以及隔离结构的顶部表面，第二保护层17的延伸方向垂直于位线结构15延伸的方向；电容接触结构的顶部具有凸起，且凸起在预设方向上间隔延伸，凸起还位于部分第一保护层12的顶部表面，预设方向与位线结构15延伸的方向夹角为α，α大于0°且α不等于90°。
具体地，基底10包括阵列区以及外围区，且基底10内包括埋入式字线、浅沟槽隔离结构、有源区等结构。
参考图2，位线结构15包括在基底10上依次堆叠的位线接触层111或者底层基质层112、金属层113和顶层介质层114；其中，位线接触层111的材 料包括钨或多晶硅，底层介质层112和顶层介质层114的材料包括氮化硅、二氧化硅或氮氧化硅，金属层113由一种导电材料或者多种导电材料形成，例如掺杂多晶硅、钛、氮化钛、钨以及钨的复合物等。
第一保护层112用于保护位线结构在后续的刻蚀工艺中被刻蚀。在本实施例中，第一保护层112的材料为氮氧化硅；在其他实施例中，第一保护层的材料采用绝缘材料形成，例如氮化硅或氧化硅等材料。
需要说明的是，在同一位线结构的截面上，相邻的位线结构15只有其中一个通过位线接触层111与基底10中的有源区相连。
相应的，隔离结构包括介质层或空气间隙。参考图12，在本实施例中，电容接触结构之间的隔离结构为介质层16。介质层16的材料为氧化硅，在其他实施例中，介质层16的材料采用绝缘材料形成，例如氮化硅或氮氧化硅等材料。
第二保护层17，延伸方向垂直于位线结构15延伸的方向，位于相邻位线结构之间的第一保护层12以及隔离结构的顶部表面；在本实施例中，第二保护层17的材料与第一保护层12的材料相同；在其他实施例中，第二保护层的材料采用绝缘材料形成，例如氮化硅或氧化硅等材料。
在一个具体的例子中，第二保护层17位于垂直于位线结构15延伸的方向上。
第一保护层12与第二保护层17一同构成的顶层架构，在后续形成电容接触结构的过程中，有效地改善了电容接触结构的排布方式，直接与后续需要形成的电容的下电极板相连，有效地改善了存储器的形成工艺。
需要说明的是，本申请实施例并不对第一保护层12和第二保护层17的 厚度进行限定，第一保护层12和第二保护层17的厚度可根据具体的工艺需求进行设定。
位于位线结构15之间的电容接触结构与隔离结构，在位线结构延伸的方向上，电容接触结构与隔离结构交替排布；且沿预设方向上，电容接触结构具有凸起，凸起还位于部分第一保护层的顶部表面，预设方向与位线结构15延伸的方向具有夹角；其中，电容接触结构的底部与基底10中的有源区相连。在一个例子中，夹角为α，α大于0°且α不等于90°。
参考图17，从俯视图上看，暴露出第一保护层12的位置，被刻蚀的剩余导电层41与未被刻蚀的剩余导电层42(即电容接触结构顶部的凸起)没有电连接；而在没有暴露出第二保护层12的位置，被刻蚀的剩余导电层41与未被刻蚀的剩余导电层42(即电容接触结构顶部的凸起)有电连接。即导电层通过暴露出的第一保护层12的位置相互分离，形成分立的电容接触结构(未被第一保护层12分离的被刻蚀的剩余导电层41以及未被刻蚀的剩余导电层42)，改变了电容接触结构原本四方排布的方式，与后续形成的电容下电极板直接相连，省去了制作错位接触电的这一工艺步骤，极大的改善了存储器的形成方法。
另外，在其他实施例中，存储器还包括隔离层，隔离层位于隔离结构的侧壁。
另外，在其他实施例中，电容接触结构之间的隔离结构为空气间隙。
与相关技术相比，形成的电容接触结构的顶部部分位于第一保护层的顶部表面，改变了原有电容接触结构的排布方式，使得后续形成的电容与电容接触结构之间的连接变得简单，从而改善了目前存储器的制程工艺的流程，进而提高存储器的生产效率和降低存储器生产运营成本。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (15)

  1. 一种存储器的形成方法，其特征在于，包括：
    提供基底，所述基底上形成有位线结构以及位于所述位线结构顶部表面的第一保护层；
    形成介质层填充相邻所述位线结构之间的间隙，所述介质层的顶部表面与所述第一保护层顶部表面齐平；
    形成第二保护层覆盖所述第一保护层顶部表面和所述介质层的顶部表面；
    在垂直于所述位线结构延伸的方向上，去除部分所述介质层以及部分所述第二保护层，形成电容接触孔，且在垂直于所述位线结构延伸的方向上，暴露出位于相邻所述电容接触孔之间的所述第一保护层；
    形成导电层填充所述电容接触孔并覆盖被暴露出的所述第一保护层的顶部表面，且所述导电层顶部表面与所述第二保护层顶部表面齐平；
    刻蚀部分所述导电层形成分立的电容接触结构。
  2. 根据权利要求1所述的存储器的形成方法，其特征在于，所述刻蚀部分所述导电层形成分立的电容接触结构，包括：
    在所述导电层以及所述第二保护层的顶部表面形成接触掩膜层；
    所述接触掩膜层于预设方向上暴露出预设宽度的所述导电层以及所述第二保护层，且于垂直于所述预设方向上，所述接触掩膜层与被暴露出的所述导电层以及所述第二保护层交替排布；所述预设方向与所述位线结构延伸的方向夹角为α，α大于0°且α不等于90°；
    刻蚀被暴露出的所述导电层，直至暴露出部分所述第一保护层的顶部表面；
    去除所述接触掩膜层，剩余所述导电层作为所述电容接触结构。
  3. 根据权利要求1所述的存储器的形成方法，其特征在于，所述基底上形成有位线结构以及位于所述位线结构顶部表面的第一保护层，包括：
    在所述基底上形成位线叠层，在所述位线叠层顶部形成第一保护膜；
    在所述第一保护膜顶部表面形成已图案化的位线掩膜层，以所述位线掩膜层为掩膜，刻蚀所述第一保护膜以及所述位线叠层，形成所述位线结构以及位于所述位线结构顶部表面的第一保护层；
    去除所述位线掩膜层。
  4. 根据权利要求3所述的存储器的形成方法，其特征在于，在所述基底上形成位线叠层，包括：
    在所述基底上形成与所述基底中的有源区相连且分立的位线接触层；
    在所述基底上形成填充所述位线接触层之间间隙的底层介质层，所述底层介质层的顶部表面与所述位线接触层的顶部表面齐平；
    在所述底层介质层顶部表面以及所述位线接触层顶部表面形成金属层；
    在所述金属层顶部表面形成顶层介质层。
  5. 根据权利要求1所述的存储器的形成方法，其特征在于，所述在垂直于所述位线结构延伸的方向上，去除部分所述介质层以及部分所述第二保护层，形成电容接触孔，包括：
    在所述第二保护层顶部表面形成介质掩膜层；
    以所述介质掩膜层为掩膜，在垂直于所述位线结构延伸的方向上，刻蚀部分所述第二保护层直至暴露出部分所述第一保护层以及部分所述介质层的顶部表面；
    去除被暴露出的部分所述介质层，形成所述电容接触孔。
  6. 根据权利要求1所述的存储器的形成方法，其特征在于，在形成所述电容接触孔之后，且在形成所述导电层填充所述电容接触孔之前，包括：
    在所述基底上形成隔离膜，所述隔离膜覆盖所述第二保护层和被暴露出的所述第一保护层，以及所述电容接触孔侧壁和底部；
    去除位于所述第二保护层顶部表面、被暴露出的所述第一保护层顶部表面以及所述电容接触孔底部的所述隔离膜，形成位于所述电容接触孔侧壁的隔离层。
  7. 根据权利要求1所述的存储器的形成方法，其特征在于，所述导电层包括第一导电层和第二导电层，所述第一导电层与所述第二导电层的材料不相同，且所述第二导电层顶部表面与所述第二保护层顶部表面齐平，且于所述垂直于所述位线结构延伸的方向上，所述第二导电层还覆盖所述第一保护层的顶部表面。
  8. 根据权利要求7所述的存储器的形成方法，其特征在于，所述形成导电层填充所述电容接触孔，包括：
    在所述电容接触孔中形成所述第一导电层，所述第一导电层顶部表面低于所述第一保护层顶部表面；
    在所述第一导电层顶部表面、所述第一保护层顶部表面以及所述第二保护层顶部表面形成顶部导电膜；
    刻蚀所述顶部导电膜，形成所述第二导电层。
  9. 根据权利要求1所述的存储器的形成方法，其特征在于，在所述形成分立的电容接触结构之后，包括：
    形成位于所述第二保护层顶部表面的隔离掩膜层；
    以所述隔离掩膜层为掩膜，于位线结构延伸的方向上，图案化位于所述电 容接触结构顶部的所述第二保护层，暴露出位于所述电容接触结构之间的所述介质层；
    去除位于所述电容接触结构之间的所述介质层，形成空气间隙；
    形成封口层，所述封口层密封所述空气间隙的顶部。
  10. 根据权利要求1所述的存储器的形成方法，其特征在于，形成介质层填充相邻所述位线结构之间的间隙，包括：
    形成填充相邻位线结构之间间隙的介质膜，所述介质膜覆盖所述位线结构；
    去除高于所述位线结构顶部表面的所述介质膜，剩余所述介质膜形成所述介质层。
  11. 一种存储器，其特征在于，包括：
    基底，以及位于所述基底上的位线结构；
    第一保护层，位于所述位线结构的顶部表面；
    位于所述位线结构之间的电容接触结构以及隔离结构，在位线结构延伸的方向上，所述电容接触结构与所述隔离结构交替排布；
    第二保护层，位于相邻所述位线结构之间的所述第一保护层以及所述隔离结构的顶部表面，所述第二保护层的延伸方向不同于所述位线结构延伸的方向；
    所述电容接触结构的顶部具有凸起，所述凸起在预设方向上间隔延伸，所述凸起还位于部分所述第一保护层的顶部表面，所述预设方向与所述位线结构延伸的方向具有夹角。
  12. 根据权利要求11所述的存储器，其特征在于，所述预设方向与所述位线结构延伸的方向夹角为α，α大于0°且α不等于90°。
  13. 根据权利要求11所述的存储器，其特征在于，所述第二保护层的延伸方向 垂直于所述位线结构延伸的方向。
  14. 根据权利要求11所述的存储器，其特征在于，所述存储器还包括：隔离层，所述隔离层位于所述隔离结构侧壁。
  15. 根据权利要求11所述的存储器，其特征在于，所述隔离结构包括介质层或空气间隙。
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