TW201705298A - 具有金屬閘極之半導體元件及其製作方法 - Google Patents

具有金屬閘極之半導體元件及其製作方法 Download PDF

Info

Publication number
TW201705298A
TW201705298A TW104123810A TW104123810A TW201705298A TW 201705298 A TW201705298 A TW 201705298A TW 104123810 A TW104123810 A TW 104123810A TW 104123810 A TW104123810 A TW 104123810A TW 201705298 A TW201705298 A TW 201705298A
Authority
TW
Taiwan
Prior art keywords
layer
barrier layer
bottom barrier
metal gate
work function
Prior art date
Application number
TW104123810A
Other languages
English (en)
Other versions
TWI663656B (zh
Inventor
賴建銘
蔡雅卉
Original Assignee
聯華電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 聯華電子股份有限公司 filed Critical 聯華電子股份有限公司
Priority to TW104123810A priority Critical patent/TWI663656B/zh
Priority to US14/836,966 priority patent/US9524968B1/en
Priority to US15/339,945 priority patent/US9679898B2/en
Publication of TW201705298A publication Critical patent/TW201705298A/zh
Application granted granted Critical
Publication of TWI663656B publication Critical patent/TWI663656B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本發明提供一種具有金屬閘極之半導體元件之製作方法，包括提供一基底，於該基底表面依序形成一閘極介電層與一底部阻障層，再形成一功函數層覆蓋該底部阻障層。接著移除該功函數層，於該底部阻障層上形成一頂部阻障層，其中該頂部阻障層直接與該底部阻障層相接觸，之後於該頂部阻障層上形成一金屬層。

Description

具有金屬閘極之半導體元件及其製作方法
本發明係關於一種具有金屬閘極之半導體元件及其製作方法，尤指閘極材料具有較佳填洞表現的一種具有金屬閘極之半導體元件及其製作方法。
隨著半導體元件持續地微縮，功函數金屬已逐漸取代傳統多晶矽作為匹配高介電常數介電層的控制電極。目前常見的功函數金屬閘極之製作方法係先形成一多晶矽虛置閘極（dummy gate）或置換閘極（replacement gate），然後依序完成多道的金屬氧化物半導體（MOS）電晶體製作步驟，例如形成側壁子與汲極/源極等，接著再將多晶矽虛置閘極移除而形成一閘極溝渠（gate trench），最後依電性需求於閘極溝渠內填入複數層材料膜層，例如閘極介電層、功函數層與金屬層等。然而，由於閘極溝渠的高寬比日益提高，造成閘極溝渠內膜層填洞的困難度也不斷提高，因此在填洞時容易在閘極溝渠中產生縫隙，嚴重影響電晶體的電性表現。再者，在習知製程中，為了改善膜層的填洞表現，還需要進行溝渠內膜層截角製程，以增加溝渠內表面的開口尺寸，然而上述方法亦使整體製程更加繁複。因此，如何以簡單化的製程提升金屬閘極的良率仍為業界的重要課題。
因此，本發明之一目的係在於提供一種具有金屬閘極之半導體元件的製作方法以及具有金屬閘極之半導體元件，其金屬閘極具有較佳的填洞效果，且金屬閘極結構中不具有功函數材料層。
根據本發明之實施例，其提供一種具有金屬閘極之半導體元件之製作方法，該方法包含先提供一基底，然後於該基底表面形成一閘極介電層，再於該閘極介電層上形成一底部阻障層，接著於該底部阻障層上形成一功函數層覆蓋該底部阻障層。之後，移除該功函數層，再於該底部阻障層上形成一頂部阻障層，使該頂部阻障層直接與該底部阻障層相接觸，然後於該頂部阻障層上形成一金屬層。
根據本發明之實施例，其另提供一種具有金屬閘極之半導體元件，該半導體元件包括一基底、一第一金屬閘極結構以及一第二金屬閘極結構。該第一金屬閘極結構設置於該基底上之一第一元件區內，包括一閘極介電層以及一第一底部阻障層依序設於該基底上、一頂部阻障層設於該第一底部阻障層表面且直接與該第一底部阻障層相接觸、以及一金屬層設於該頂部阻障層上。該第二金屬閘極結構設置於該基底上之一第二元件區內，包括該閘極介電層以及一第二底部阻障層依序設於該基底上、該頂部阻障層設於該第二底部阻障層上且直接與該第二底部阻障層相接觸、以及該金屬層設於該頂部阻障層上。其中，該第一底部阻障層與該第二底部阻障層的雜質成分含量不相同。
根據本發明，具有金屬閘極之半導體元件的第一金屬閘極結構與第二金屬閘極結構內皆不具有功函數材料層，因此不需要進行功函數材料層的截角製程，使製程簡化，還可以降低後續膜層製作時閘極溝渠的高寬比，有效提高頂部阻障層與金屬層的填洞效果，改善閘極結構的電性表現。再者，第一金屬閘極結構與第二金屬閘極結構具有類似或相同的膜層堆疊結構，可以提高後續製程的製程寬裕度，能進一步改善良率與簡化製程。
為使熟習本發明所屬技術領域之一般技藝者能更進一步瞭解本發明，下文特列舉本發明之較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。
請參考第1圖與第2圖至第11圖，其中第1圖為本發明具有金屬閘極之半導體元件之製作方法的流程步驟圖，而第2圖至第10圖為本發明具有金屬閘極之半導體元件的製作方法的一實施例之元件製程示意圖，其中第10圖也繪示了本發明具有金屬閘極之半導體元件的結構剖面示意圖。需注意的是，本實施例係介紹本發明應用於後閘極（gate-last）製程的半導體元件製作，但本發明亦可應用於前閘極（gate-first）製程。根據本實施例，首先進行第1圖所示之步驟200，提供一基底102，如第2圖所示，基底102可以例如是矽基底、含矽基底（例如SiC）、三五族基底（例如GaN）、三五族覆矽基底（例如GaN-on-silicon）、石墨烯覆矽基底（graphene-on-silicon）、矽覆絕緣（silicon-on-insulator, SOI）基底、含磊晶層之基底或其他合適的半導體基底等，但不以此為限。基底102表面包含一第一元件區106與一第二元件區104，本實施例係預定在第一元件區106與第二元件區104中分別形成P型電晶體（或稱P型場效應電晶體：P-type field effect transistor，PFET）與N型電晶體（或稱N型場效應電晶體：N-type field effect transistor，NFET），但不以此為限，例如在其他實施例中，本發明製程可應用於僅製作（或單獨製作）NFET或PFET之情況。由於本實施例是後閘極製程，因此可使用多晶矽材料在基底102表面的第一元件區106與第二元件區104分別形成圖案化的虛置閘極（圖未示），然後再進行電晶體中其他元件的製程，例如，在虛置閘極側壁形成側壁子112、進行輕摻雜汲極（light doped drain，LDD）離子佈植與汲極/源極的埋入磊晶製程（圖未示）、形成接觸洞蝕刻停止層（contact etch stop layer，CESL）、進行離子佈植製程以形成汲極/源極150、形成層間介電（inter-layer dielectric，ILD）層154以及化學機械研磨（chemical mechanical polishing，CMP）製程等，接著再將多晶矽虛置閘極移除而在第一元件區106與第二元件區104分別形成至少一閘極溝渠（gate trench），如第2圖所示之第一閘極溝渠110與第二閘極溝渠108。
接著請參考第3圖與第1圖，進行如第1圖所示之步驟202，在基底102表面形成一閘極介電層120，本實施例之閘極介電層120係形成在第一閘極溝渠110與第二閘極溝渠108的底部與側壁表面以及ILD層154表面。閘極介電層120可選擇性地包括一氧化層116與一高介電常數（high dielectric constant，high-k）介電層118。氧化層116舉例為二氧化矽層，例如以熱氧化製程製作而僅形成在第一閘極溝渠110與第二閘極溝渠108的底表面。高介電常數介電層118可以沉積方式形成，其覆蓋氧化層118表面和第一閘極溝渠110與第二閘極溝渠108的側壁。高介電常數介電層118可包含介電常數約大於4的材料，可以是稀土金屬氧化物或鑭系金屬氧化物，例如氧化鉿（hafnium oxide，HfO2 ）、矽酸鉿氧化合物（hafnium silicon oxide，HfSiO4 ）、矽酸鉿氮氧化合物（hafnium silicon oxynitride，HfSiON）、氧化鋁（aluminum oxide，Al2 O3 ）、氧化鑭（lanthanum oxide，La2 O3 ）、氧化鉭（tantalum oxide，Ta2 O5 ）、氧化釔（yttrium oxide，Y2 O3 ）、氧化鋯（zirconium oxide，ZrO2 ）、鈦酸鍶（strontium titanate oxide， SrTiO3 ）、矽酸鋯氧化合物（zirconium silicon oxide，ZrSiO4 ）、鋯酸鉿（hafnium zirconium oxide，HfZrO4 ）、鍶鉍鉭氧化物（strontium bismuth tantalate, SrBi2 Ta2 O9 , SBT）、鋯鈦酸鉛（lead zirconate titanate, PbZrx Ti1-x O3 , PZT）與鈦酸鋇鍶（barium strontium titanate, Bax Sr1-x TiO3 , BST）等，但不限於此。
請再參考第4圖與第1圖，進行第1圖所示之步驟204，在閘極介電層120表面形成至少一底部阻障層126，覆蓋第一閘極溝渠110與第二閘極溝渠108的底部與側壁表面。本實施例的底部阻障層126係為一複合層，包括下底部阻障層122與上底部阻障層124，兩者可具有相同或不同的材料。在較佳實施例中，底部阻障層126包含金屬化合物材料，本實施例之下底部阻障層122的材料舉例為氮化鈦（titanium nitride，TiN），而上底部阻障層124的材料舉例為氮化鉭（tantalum nitride，TaN），亦即底部阻障層126為一氮化鈦/氮化鉭疊層但不以此為限，底部阻障層126也可包含其他材料，例如鈦矽氮（titanium silicon nitride，TiSiN）。在其他實施例中，底部阻障層126也可為單一膜層。
接著請參考第5圖與第1圖，進行第1圖所示之步驟206，於底部阻障層126上形成一功函數層並覆蓋底部阻障層126。由於本實施例係預定在基底102上製作N型電晶體與P型電晶體，因此需要分別製作不同導電型的功函數層。如第5圖所示，先在基底102表面形成一第一功函數層128，沿著第一閘極溝渠110與第二閘極溝渠108的表面形狀覆蓋底部阻障層126。第一功函數層128可藉由一化學氣相沈積（chemical vapor deposition，CVD）製程或一物理氣相沈積（physical vapor deposition，PVD）製程所製作。再者，第一功函數層128為P型功函數金屬層，其功函數範圍為約4.8電子伏特（eV）至5.2 eV，材料舉例為氮化鈦、碳化鈦（titanium carbide，TiC）、氮化鉭或碳化鉭（tantalum carbide，TaC）、碳化鎢（tungsten carbide，WC）、或氮化鋁鈦（aluminum titanium nitride，TiAlN），但不以此為限。然後請參考第6圖，移除第二元件區104內的第一功函數層128，其方法例如先在第一元件區106上形成圖案化的遮罩層（圖未示），覆蓋第一元件區106內的第一功函數層128，其中圖案化的遮罩層例如為一圖案化光阻層，然後進行蝕刻製程，移除未被遮罩層覆蓋的第一功函數層128，亦即將第二元件區104中基底102表面的第一功函數層128移除。
接著，請參考第7圖，沿著基底102表面形狀形成一第二功函數層130，於第二元件區104填入第二閘極溝渠108中直接覆蓋上底部阻障層124而與其接觸，並同時於第一元件區106填入第一閘極溝渠110中直接覆蓋第一功函數層128並與其接觸。本實施例之第二功函數層130為N型功函數金屬層，可以CVD或PVD製程所形成，其功函數範圍為約3.9 eV至4.3 eV，材料舉例為鋁化鈦（titanium aluminide，TiAl）、鋁化鋯（zirconium aluminide，ZrAl）、鋁化鎢（tungsten aluminide，WAl）、鋁化鉭（tantalum aluminide，TaAl）或鋁化鉿（hafnium aluminide，HfAl），但不限於此。然後，可選擇性地進行一功函數調整製程152，例如一熱處理製程、一離子佈植製程或一氮化製程，但不以此為限，上述功函數調整製程152的作用在於抑制第一功函數層128與第二功函數層130中的原子擴散或是驅使第一功函數層128與第二功函數層130中的原子擴散至其所覆蓋的膜層中。
然後請參考第8圖與第1圖，進行步驟208，移除所有功函數層，包括第一功函數層128與第二功函數層130。移除功函數層的方法舉例為濕蝕刻製程，所選擇的蝕刻劑對第一功函數層128和第二功函數層130之材料與底部阻障層126之材料較佳具有高蝕刻選擇比，但不以此為限，也可使用乾蝕刻或其他已知的膜層移除製程。在移除第一功函數層128與第二功函數層130之後，第一元件區106與第二元件區104中的底部阻障層係曝露於第一閘極溝渠110與第二閘極溝渠108的底部與側壁表面。需注意的是，由於第一閘極溝渠110與第二閘極溝渠108在步驟208之前分別經歷不同的製程且具有不同的膜層結構，因此在步驟208之後所曝露出的底部阻障層所包含的雜質成分亦會不同，所以，在第8圖分別以不同符號表示第一元件區106與第二元件區104中雜質成分與含量不同的底部阻障層，其中第一元件區106具有第一底部阻障層1261，其具有下底部阻障層1221與上底部阻障層1241，而第二元件區104具有第二底部阻障層1262，其具有下底部阻障層1222與上底部阻障層1242。
接著請參考第9圖與第1圖，進行步驟210，於第一底部阻障層1261與第二底部阻障層1262上形成一頂部阻障層132，使頂部阻障層132直接覆蓋在第一底部阻障層1261與第二底部阻障層1262表面並與其相接觸，頂部阻障層132可以PVD或CVD製程製作，其材料舉例為TiN，但不以此為限。接著，進行第1圖所示之步驟212，在頂部阻障層132上形成金屬層134填入第一閘極溝渠110與第二閘極溝渠108中。金屬層134較佳選擇低阻值金屬材料，例如，鎢（tungsten，W），但不以此為限，例如也可選擇鋁（aluminum，Al）、鋁化鈦（titanium aluminide，TiAl）或氧化鋁鈦（titanium aluminum oxide，TiAlO）等其他具有優良填洞能力與較低阻值的金屬或金屬氧化物。
請參考第10圖，隨後可進行平坦化製程，例如一CMP製程，以將ILD層154上多餘的金屬層134、頂部阻障層132、第一與第二底部阻障層1261、1262、閘極介電層120（高介電常數介電層118）移除，分別形成第一金屬閘極結構140與一第二金屬閘極結構138，以完成第一電晶體136與第二電晶體144之製作，其中設於第一元件區106之第一電晶體136為P型電晶體，第一金屬閘極結構140為P型閘極結構，而設於第二元件區104的第二電晶體144為N型電晶體，第二金屬閘極結構138為N型金屬閘極。之後，本實施例可選擇性地去除ILD層154與CESL 114，然後重新形成CESL與層間介電層，以有效提升半導體元件的電性表現。此外，在製作完第一電晶體136與第二電晶體144之後，可進行自動對準接觸（self-alignment contact，SAC）製程以形成接觸洞與接觸元件。由於上述CMP製程、再製作CESL與層間介電層以及SAC製程等步驟係為本發明技術領域中具通常知識者所知，故不再贅述。
由前述可知，根據本發明具金屬閘極之半導體元件的製作方法，其可製作如第10圖所述之具有金屬閘極之半導體元件142，其包括一基底102、一第一金屬閘極結構140及一第二金屬閘極結構138。基底102包含一第一元件區106與一第二元件區104，而第一金屬閘極結構140與第二金屬閘極結構138分別設置在第一元件區106與第二元件區104內。第一金屬閘極結構140包括一閘極介電層120以及一第一底部阻障層1261依序設於基底102上、一頂部阻障層132設於第一底部阻障層1261表面且直接與第一底部阻障層1261相接觸、以及一金屬層134設於頂部阻障層132上。第二金屬閘極結構138包括閘極介電層120與一第二底部阻障層1262依序設於基底102上、頂部阻障層132設於第二底部阻障層1262上且直接與第二底部阻障層1262相接觸、以及金屬層134設於頂部阻障層132上。需注意的是，由於前述在第一閘極溝渠110與第二閘極溝渠108內製作與移除第一功函數層128與第二功函數層130的手段不同，因此第一金屬閘極結構140與第二金屬閘極結構138的第一底部阻障層1261與第二底部阻障層1262的雜質成分含量不相同。
請參考第11圖，第11圖為本發明具有金屬閘極之半導體元件142的能量色散型X射線光譜（energy-dispersive X-ray spectroscope，EDS）圖，其中曲線Al1 與曲線Al2 分別表示第一電晶體136與第二電晶體144中的鋁原子含量，其中橫軸中的區段A表示電晶體之高介電常數介電層的鋁原子含量，區段B表示下底部阻障層的鋁原子含量，而區段C表示上底部阻障層的鋁原子含量。由第11圖可知，在區段B與區段C中，曲線Al1 與曲線Al2 並沒有重疊與相交，且曲線Al1 皆在曲線Al2 下方，因此第一底部阻障層1261與第二底部阻障層1262所包含的鋁原子含量不同，其中第一底部阻障層1261的鋁原子含量小於第二底部阻障層1262的鋁原子含量。再者，區段B與區段C中曲線Al1 與曲線Al2 的曲線走向也極為不同，曲線Al1 較為平緩，而曲線Al2 的走向具有較陡峭的坡度，因此第一底部阻障層1261與第二底部阻障層1262的鋁原子濃度踢度也不相同。由上述可知，第一底部阻障層1261與第二底部阻障層1262具有不同的雜質成分，其提供了金屬閘極結構不同的功函數功能，因此即使在最後形成的第一金屬閘極結構140與第二金屬閘極結構138都不具有功函數材料層，且雖然第一金屬閘極結構140與第二金屬閘極結構138中的膜層數量和堆疊方式看似相同，但第一金屬閘極結構140與第二金屬閘極結構138卻提供了不同導電型之金屬閘極，能應用於不同導電型之電晶體中，亦即可分別應用在P型電晶體與N型電晶體中。
需注意的是，上述本發明實施例係應用在後閘極製程中，但本發明亦可應用於前閘極製程中，例如先依序在基底上形成閘極介電層、底部阻障層以及功函數層，再選擇性進行功函數調整製程，然後移除功函數層，再依序製作頂部阻障層和金屬層於底部阻障層表面。之後，才進行金屬閘極結構的圖案化製程，再於金屬閘極結構的側壁形成側壁子、LDD、源極/汲極與CESL等其他電晶體元件。再者，在前述後閘極製程的實施例中，高介電常數介電層係在閘極溝渠形成後才製作，但在其他變化形中，也可先在基底表面形成高介電常數介電層，然後才形成虛置閘極、側壁子、LDD、源極/汲極與CESL等電晶體元件，之後再移除虛置閘極以形成閘極溝渠，曝露出先形成的高介電常數介電層，然後再如前述實施例所述，在高介電常數介電層表面依序製作底部阻障層與功函數層、移除功函數層等製程，不再贅述。
根據本發明具有金屬閘極之半導體元件的製作方法，係在製作金屬閘極結構時，在底部阻障層上先形成功函數層，再選擇性地對功函數層進行功函數調整製程，之後再移除功函數層而曝露出底部阻障層，隨後所依序製作的頂部阻障層與金屬層會直接形成在底部阻障層表面，使頂部阻障層與底部阻障層直接相接觸。由於在形成頂部阻障層與金屬層時，閘極溝渠內不具有功函數層，因此可以有效改善金屬層填洞時的閘極溝渠高寬比，增加金屬層填洞效果，改善金屬閘極的電性表現，例如降低電阻率。此外，根據本發明方法，在金屬閘極的製程中不須另外進行功函數層或其他膜層的截角製程，可以有效簡化整體製程。再者，由於N型電晶體與P型電晶體的金屬閘極結構具有相同的膜層堆疊設計，因此可以進一步提高後續製程的製程寬裕度（process window），能達到同時簡化製程與提高製程良率之效果。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
102‧‧‧基底
104‧‧‧第二元件區
106‧‧‧第一元件區
108‧‧‧第二閘極溝渠
110‧‧‧第一閘極溝渠
112‧‧‧側壁子
114‧‧‧CESL
116‧‧‧氧化層
118‧‧‧高介電常數介電層
120‧‧‧閘極介電層
122、1221、1222‧‧‧下底部阻障層
124、1241、1242‧‧‧上底部阻障層
126‧‧‧底部阻障層
1261‧‧‧第一底部阻障層
1262‧‧‧第二底部阻障層
128‧‧‧第一功函數層
130‧‧‧第二功函數層
132‧‧‧頂部阻障層
134‧‧‧金屬層
136‧‧‧第一電晶體
138‧‧‧第二金屬閘極結構
140‧‧‧第一金屬閘極結構
142‧‧‧金屬閘極之半導體元件
144‧‧‧第二電晶體
150‧‧‧汲極/源極
152‧‧‧功函數調整製程
154‧‧‧ILD層
200～212‧‧‧步驟
A、B、C‧‧‧區段
Al1、Al2‧‧‧曲線
第1圖為本發明具有金屬閘極之半導體元件之製作方法的流程步驟圖。 第2圖至第10圖為本發明具有金屬閘極之半導體元件的製作方法的一實施例之元件製程示意圖，其中第10圖繪示了本發明具有金屬閘極之半導體元件的結構剖面示意圖。 第11圖為本發明具有金屬閘極之半導體元件142的能量色散型X射線光譜圖。
102‧‧‧基底
104‧‧‧第二元件區
106‧‧‧第一元件區
108‧‧‧第二閘極溝渠
110‧‧‧第一閘極溝渠
112‧‧‧側壁子
114‧‧‧CESL
116‧‧‧氧化層
118‧‧‧高介電常數介電層
120‧‧‧閘極介電層
1221、1222‧‧‧下底部阻障層
1241、1242‧‧‧上底部阻障層
1261‧‧‧第一底部阻障層
1262‧‧‧第二底部阻障層
132‧‧‧頂部阻障層
134‧‧‧金屬層
136‧‧‧第一電晶體
138‧‧‧第二金屬閘極結構
140‧‧‧第一金屬閘極結構
142‧‧‧金屬閘極之半導體元件
144‧‧‧第二電晶體
150‧‧‧汲極/源極
154‧‧‧ILD層

Claims (17)

  1. 一種具有金屬閘極之半導體元件之製作方法，包含有：        提供一基底；        於該基底表面形成一閘極介電層；        於該閘極介電層上形成一底部阻障層；        於該底部阻障層上形成一功函數層覆蓋該底部阻障層；        移除該功函數層；        於該底部阻障層上形成一頂部阻障層，該頂部阻障層直接與該底部阻障層相接觸；以及 於該頂部阻障層上形成一金屬層。
  2. 如請求項第1項所述之具有金屬閘極之半導體元件之製作方法，其中該基底表面包含至少一閘極溝渠（gate trench），且該閘極介電層、該底部阻障層、該功函數層、該頂部阻障層以及該金屬層至少形成於該閘極溝渠內。
  3. 如請求項第2項所述之具有金屬閘極之半導體元件之製作方法，其中該基底具有一第一元件區與一第二元件區，且該基底表面包含一第一閘極溝渠與一第二閘極溝渠，分別位於該第一元件區與該第二元件區。
  4. 如請求項第3項所述之具有金屬閘極之半導體元件之製作方法，其中形成該功函數層之步驟包括： 於該基底表面全面形成一第一功函數層，覆蓋該第一閘極溝渠與該第二閘極溝渠之底部與側壁表面； 移除該第二閘極溝渠中的該第一功函數層；以及 於該基底表面全面形成一第二功函數層，覆蓋該第一閘極溝渠與該第二閘極溝渠之底部與側壁表面。
  5. 如請求項第4項所述之具有金屬閘極之半導體元件之製作方法，其中該第一功函數層係為一P型功函數金屬層，而該第二功函數層係為一N型功函數金屬層。
  6. 如請求項第1項所述之具有金屬閘極之半導體元件之製作方法，其另包含在移除該功函數層之前，先進行一功函數調整製程。
  7. 如請求項第6項所述之具有金屬閘極之半導體元件之製作方法，其中該功函數調整製程係為一熱處理製程、一離子佈植製程或一氮化製程。
  8. 如請求項第1項所述之具有金屬閘極之半導體元件之製作方法，其中該底部阻障層係為一複合層。
  9. 如請求項第8項所述之具有金屬閘極之半導體元件之製作方法，其中該複合層係為一氮化鈦/氮化鉭（TiN/TaN）疊層，該頂部阻障層係為一氮化鈦層。
  10. 如請求項第1項所述之具有金屬閘極之半導體元件之製作方法，其中移除該功函數層之步驟包含一濕蝕刻製程。
  11. 如請求項第10項所述之具有金屬閘極之半導體元件之製作方法，其中該濕蝕刻製程所使用的蝕刻劑對該功函數層之材料與該底部阻障層之材料具有高蝕刻選擇比。
  12. 一種具有金屬閘極之半導體元件，包含有：        一基底；        一第一金屬閘極結構，設置於該基底上之一第一元件區內，該第一金屬閘極結構包括： 一閘極介電層以及一第一底部阻障層依序設於該基底上； 一頂部阻障層，設於該第一底部阻障層表面且直接與該第一底部阻障層相接觸；以及 一金屬層設於該頂部阻障層上；以及        一第二金屬閘極結構，設置於該基底上之一第二元件區內，該第二金屬閘極結構包括： 該閘極介電層以及一第二底部阻障層依序設於該基底上，其中該第一底部阻障層與該第二底部阻障層的雜質成分含量不相同； 該頂部阻障層，設於該第二底部阻障層上且直接與該第二底部阻障層相接觸；以及 該金屬層設於該頂部阻障層上。
  13. 如請求項第12項所述之具有金屬閘極之半導體元件，其中該第一底部阻障層與該第二底部阻障層所包含的鋁原子含量不同。
  14. 如請求項第12項所述之具有金屬閘極之半導體元件，其中該第一底部阻障層與該第二底部阻障層的鋁原子濃度梯度不同。
  15. 如請求項第12項所述之具有金屬閘極之半導體元件，其中該第一底部阻障層與該第二底度阻障層分別為一複合層。
  16. 如請求項第15項所述之具有金屬閘極之半導體元件，其中各該複合層分別為一氮化鈦/氮化鉭疊層，該頂部阻障層係為一氮化鈦層。
  17. 如請求項第12項所述之具有金屬閘極之半導體元件，其中該第一金屬閘極結構係為一P型電晶體中的一P型金屬閘極，該第二金屬閘極結構係為一N型電晶體中的一N型金屬閘極，且該第一底部阻障層之鋁原子含量小於該第二底部阻障層之鋁原子含量。
TW104123810A 2015-07-23 2015-07-23 具有金屬閘極之半導體元件及其製作方法 TWI663656B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW104123810A TWI663656B (zh) 2015-07-23 2015-07-23 具有金屬閘極之半導體元件及其製作方法
US14/836,966 US9524968B1 (en) 2015-07-23 2015-08-27 Semiconductor device having metal gate and fabrication method thereof
US15/339,945 US9679898B2 (en) 2015-07-23 2016-11-01 Semiconductor device having metal gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW104123810A TWI663656B (zh) 2015-07-23 2015-07-23 具有金屬閘極之半導體元件及其製作方法

Publications (2)

Publication Number Publication Date
TW201705298A true TW201705298A (zh) 2017-02-01
TWI663656B TWI663656B (zh) 2019-06-21

Family

ID=57538720

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104123810A TWI663656B (zh) 2015-07-23 2015-07-23 具有金屬閘極之半導體元件及其製作方法

Country Status (2)

Country Link
US (2) US9524968B1 (zh)
TW (1) TWI663656B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106024893B (zh) * 2016-05-30 2019-03-19 上海华力微电子有限公司 高k金属栅器件及其制备方法
CN108074815B (zh) * 2016-11-17 2021-04-02 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US9685520B1 (en) * 2016-11-17 2017-06-20 United Microelectronics Corp. Manufacturing method of semiconductor device
US11114347B2 (en) * 2017-06-30 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Self-protective layer formed on high-k dielectric layers with different materials
KR102481284B1 (ko) 2018-04-10 2022-12-27 삼성전자주식회사 반도체 장치의 제조 방법
CN109119477B (zh) * 2018-08-28 2021-11-05 上海华虹宏力半导体制造有限公司 沟槽栅mosfet及其制造方法
US11264478B2 (en) * 2019-10-31 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors with reduced defect and methods forming same
US20220208974A1 (en) * 2020-12-30 2022-06-30 Changxin Memory Technologies, Inc. Method for manufacturing semiconductor structure and semiconductor structure

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7439113B2 (en) 2004-07-12 2008-10-21 Intel Corporation Forming dual metal complementary metal oxide semiconductor integrated circuits
US7390709B2 (en) 2004-09-08 2008-06-24 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US20080067604A1 (en) * 2006-09-18 2008-03-20 Lars Bach Field effect transistor arrangement, memory device and methods of forming the same
US8324661B2 (en) * 2009-12-23 2012-12-04 Intel Corporation Quantum well transistors with remote counter doping
US8933488B2 (en) * 2010-12-03 2015-01-13 The Board Of Trustees Of The Leland Stanford Junior Univerity Heterostructure field effect transistor with same channel and barrier configuration for PMOS and NMOS
US9166020B2 (en) * 2011-03-01 2015-10-20 United Microelectronics Corp. Metal gate structure and manufacturing method thereof
US8324118B2 (en) * 2011-03-28 2012-12-04 United Microelectronics Corp. Manufacturing method of metal gate structure
US20120264284A1 (en) * 2011-04-14 2012-10-18 Wang shao-wei Manufacturing method for metal gate structure
US8753968B2 (en) * 2011-10-24 2014-06-17 United Microelectronics Corp. Metal gate process
US8691681B2 (en) * 2012-01-04 2014-04-08 United Microelectronics Corp. Semiconductor device having a metal gate and fabricating method thereof
US8975666B2 (en) * 2012-08-22 2015-03-10 United Microelectronics Corp. MOS transistor and process thereof
US20150061042A1 (en) * 2013-09-03 2015-03-05 United Microelectronics Corp. Metal gate structure and method of fabricating the same
US9230864B1 (en) * 2014-10-16 2016-01-05 United Microelectronics Corp. Method of forming a semiconductor device having a metal gate

Also Published As

Publication number Publication date
US20170047330A1 (en) 2017-02-16
US9524968B1 (en) 2016-12-20
TWI663656B (zh) 2019-06-21
US9679898B2 (en) 2017-06-13

Similar Documents

Publication Publication Date Title
US9875901B2 (en) Manufacturing method of metal oxide semiconductor transistor
US9384962B2 (en) Oxygen treatment of replacement work-function metals in CMOS transistor gates
US9018086B2 (en) Semiconductor device having a metal gate and fabricating method thereof
US9024393B2 (en) Manufacturing method for semiconductor device having metal gate
CN106684041B (zh) 半导体元件及其制作方法
US9685383B2 (en) Method of forming semiconductor device
TWI663656B (zh) 具有金屬閘極之半導體元件及其製作方法
US8765588B2 (en) Semiconductor process
US9773887B2 (en) Semiconductor device and method for fabricating the same
US20130062701A1 (en) Semiconductor device and manufacturing method thereof
US11901437B2 (en) Semiconductor device and method for fabricating the same
TWI625792B (zh) 半導體元件及其製作方法
TWI609430B (zh) 具有金屬閘極之半導體元件及其製作方法
TWI544551B (zh) 具有金屬閘極之半導體元件與其製造方法
TWI524394B (zh) 具有金屬閘極之半導體元件之製作方法
TWI515830B (zh) 一種製作半導體元件的方法
TWI530991B (zh) 具有金屬閘極之半導體元件及其製作方法
TWI527125B (zh) 具有金屬閘極之半導體元件之製作方法
TW201318068A (zh) 具有金屬閘極之半導體元件及其製作方法
TWI493603B (zh) 具有金屬閘極之半導體元件之製作方法
TW201320336A (zh) 金氧半導體電晶體與其形成方法