TWI624863B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI624863B
TWI624863B TW103135423A TW103135423A TWI624863B TW I624863 B TWI624863 B TW I624863B TW 103135423 A TW103135423 A TW 103135423A TW 103135423 A TW103135423 A TW 103135423A TW I624863 B TWI624863 B TW I624863B
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work function
function layer
layer
gate structure
gate
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TW103135423A
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TW201614717A (en
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楊智偉
劉玉峯
柯建村
許家福
劉恩銓
傅思逸
許啟茂
何念葶
楊玉如
王裕平
賴建銘
陳奕文
曾于庭
蔡雅卉
黃建中
謝宗殷
吳宏益
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聯華電子股份有限公司
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Priority to US14/543,914 priority patent/US9349822B2/en
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Abstract

本發明揭露一種製作半導體元件的方法。首先提供一基底，該基底具有一層間介電層設於其上，然後形成一第一凹槽、一第二凹槽以及一第三凹槽於層間介電層中，形成一材料層於層間介電層上並填入第一凹槽、第二凹槽及第三凹槽，對第一凹槽內之材料層進行一第一處理製程以及對第一凹槽內與第二凹槽內之材料層進行一第二處理製程。

Description

半導體元件及其製作方法
本發明是關於一種半導體元件，尤指一種利用具有不同晶粒方向比例之閘極結構來達到不同臨界電壓之金氧半導體電晶體。
在習知半導體產業中，多晶矽係廣泛地應用於半導體元件如金氧半導體(metal-oxide-semiconductor，MOS)電晶體中，作為標準的閘極填充材料選擇。然而，隨著MOS電晶體尺寸持續地微縮，傳統多晶矽閘極因硼穿透(boron penetration)效應導致元件效能降低，及其難以避免的空乏效應(depletion effect)等問題，使得等效的閘極介電層厚度增加、閘極電容值下降，進而導致元件驅動能力的衰退等困境。因此，半導體業界更嘗試以新的閘極填充材料，例如利用功函數(work function)金屬來取代傳統的多晶矽閘極，用以作為匹配高介電常數(High-K)閘極介電層的控制電極。
一般而言，傳統平面型金屬閘極電晶體通常採用離子佈植的方式來同時調整電晶體的臨界電壓。然而隨著場效電晶體(field effect transistors,FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor,Fin FET)元件來取代平面電晶體元件已成為目 前之主流發展趨勢。然而現今鰭狀場效電晶體的製程已無法單純藉由離子佈植來調整電晶體的臨界電壓，因此如何在鰭狀電晶體的架構下改良此缺點即為現今一重要課題。
本發明較佳實施例揭露一種製作半導體元件的方法。首先提供一基底，該基底具有一層間介電層設於其上，然後形成一第一凹槽、一第二凹槽以及一第三凹槽於層間介電層中，形成一材料層於層間介電層上並填入第一凹槽、第二凹槽及第三凹槽，對第一凹槽內之材料層進行一第一處理製程以及對第一凹槽內與第二凹槽內之材料層進行一第二處理製程。
本發明另一實施例揭露一種製作半導體元件的方法。首先提供一基底，該基底具有一層間介電層設於其上，然後形成一第一凹槽、一第二凹槽以及一第三凹槽於層間介電層中，形成一第一功函數層、一第二功函數層以及一第三功函數層於第一凹槽、第二凹槽及第三凹槽，其中第一功函數層、第二功函數層及第三功函數層分別由不同沉積溫度所形成。
本發明又一實施例揭露一種半導體元件，其包含一基底以及一第一閘極結構、一第二閘極結構以及一第三閘極結構設於該基底上以及一層間介電層環繞該第一閘極結構、該第二閘極結構及該第三閘極結構，其中第一閘極結構、第二閘極結構及第三閘極結構分別具有不同晶粒方向比例(orientation ratio)。
12‧‧‧基底
14‧‧‧鰭狀結構
18‧‧‧電晶體區
20‧‧‧電晶體區
22‧‧‧電晶體區
24‧‧‧側壁子
26‧‧‧源極/汲極區域
30‧‧‧接觸洞蝕刻停止層
32‧‧‧層間介電層
34‧‧‧功函數層
36‧‧‧低阻抗金屬層
44‧‧‧高介電常數介電層
46‧‧‧底部金屬阻隔層
48‧‧‧材料層
54‧‧‧閘極結構
56‧‧‧閘極結構
58‧‧‧閘極結構
60‧‧‧圖案化光阻
62‧‧‧圖案化光阻
64‧‧‧P型功函數層
66‧‧‧N型功函數層
68‧‧‧低阻抗金屬層
第1圖至第3圖為本發明較佳實施例製作一半導體元件之方法示意圖。
第4圖至第6圖為本發明另一實施例製作一半導體元件之方法示意圖。
第7圖為本發明另一實施例製作一半導體元件之示意圖。
請參照第1圖至第3圖，第1圖至第3圖為本發明較佳實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上定義有三個電晶體區。在本實施例中，三個電晶體區較佳為相同導電型式之電晶體區18、20、22，例如一PMOS電晶體區或NMOS電晶體區，且三個電晶體區18、20、22分別預定為後續製作不同臨界電壓之閘極結構。基底12上具有至少一鰭狀結構14及一絕緣層(圖未示)，其中鰭狀結構14之底部係被絕緣層，例如氧化矽所包覆而形成淺溝隔離。
上述鰭狀結構14之形成方式可以包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中。接著，對應三閘極電晶體元件及雙閘極鰭狀電晶體元件結構特性的不同，而可選擇性去除或留下圖案化遮罩，並利用沈積、化學機械研磨(chemical mechanical polishing,CMP)及回蝕刻製程而形成一環繞鰭狀結構14底部之絕緣層，例如為淺溝隔離 (STI)。除此之外，鰭狀結構14之形成方式另也可以是先製作一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出半導體層，此半導體層即可作為相對應的鰭狀結構14。同樣的，另可以選擇性去除或留下圖案化硬遮罩層，並透過沈積、CMP及回蝕刻製程形成一絕緣層以包覆住鰭狀結構14之底部。另外，當基底12為矽覆絕緣(SOI)基板時，則可利用圖案化遮罩來蝕刻基底上之一半導體層，並停止於此半導體層下方的一底氧化層以形成鰭狀結構，故可省略前述製作絕緣層的步驟。
然後可進行一金屬閘極製程以於基底上形成三個金屬閘極，其中金屬閘極之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先閘極介電層(high-k first)製程以及後閘極製程之後閘極介電層(high-k last)製程等方式製作完成。以本實施例之後閘極介電層製程為例，可先於鰭狀結構14與絕緣層上形成三個較佳包含一由二氧化矽(SiO2)、氮化矽(SiN)或氮氧化矽(SiON)所構成的介質層與多晶矽材料所構成的虛置閘極(圖未示)，然後於各虛置閘極側壁形成襯層、輕摻雜汲極(圖未示)、側壁子24。接著於側壁子24兩側的鰭狀結構14以及/或基底12中分別形成一源極/汲極區域26與磊晶層(圖未示)、形成一接觸洞蝕刻停止層30覆蓋虛置閘極，並形成一由四乙氧基矽烷(Tetraethyl orthosilicate,TEOS)所組成的層間介電層(圖未示)於接觸洞蝕刻停止層30上。
然後平坦化部分之層間介電層32及接觸洞蝕刻停止層30，並進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide,NH4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide,TMAH)等蝕刻溶液來去除虛置閘 極中的多晶矽材料，以於層間介電層32中形成三個凹槽38、40、42。
接著可選擇性重新去除並形成介質層，再依序形成一高介電常數介電層44、一底部金屬阻隔層46以及一材料層48於層間介電層32上並填入凹槽38、40、42。
在本實施例中，高介電常數介電層44較佳包含介電常數大於4的介電材料，例如係選自氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧化合物(hafnium silicon oxide，HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化鋁(aluminum oxide，Al2O3)、氧化鑭(lanthanum oxide，La2O3)、氧化鉭(tantalum oxide，Ta2O5)、氧化釔(yttrium oxide，Y2O3)、氧化鋯(zirconium oxide，ZrO2)、鈦酸鍶(strontium titanate oxide，SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide，ZrSiO4)、鋯酸鉿(hafnium zirconium oxide，HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)、鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其組合所組成之群組。底部金屬阻隔層46可為一單層或雙層結構，其較佳包含氮化鈦(TiN)以及/或氮化鉭(TaN)，但不侷限於此。
其次，本實施例的材料層48較佳為一形成於功函數層之前之一材料層，例如一由TaN或TiN所構成的底部金屬阻隔層。需注意的是，以下實施例雖以材料層48為一底部金屬阻隔層進行說明，但材料層48又可依據製程需求直接由一功函數層所構成，此實施例也屬本發明所涵蓋的範圍。
若材料層48為一用來調整金屬閘極之功函數的功函數層，使其組成較佳依據適用之電晶體的型態而不同。例如，若電晶體為N型電晶體，功函數金屬層可選用功函數為3.9電子伏特(eV)~4.3eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC(碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層可選用功函數為4.8eV~5.2eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。
接著形成一圖案化遮罩，例如一圖案化光阻50，覆蓋電晶體區20、22，並利用圖案化光阻50為遮罩對被暴露之凹槽38內的材料層48進行一處理製程，藉此改變材料層48的表面能量，使後續成長於材料層上48的功函數層可具有不同晶粒方向比例。在本實施例中，處理製程包括以氣體對材料層48進行一離子轟擊(plasma bombardment)，且離子轟擊步驟中所使用的氣體較佳選自由氨氣、氫氣及氮氣所構成的群組。
如第2圖所示，接著去除圖案化光阻50，形成另一圖案化光阻52覆蓋電晶體區22，並利用圖案化光阻52為遮罩對被暴露之凹槽38、40內的材料層48進行另一次處理製程，其中處理製程所使用的氣體與能量等參數可等同於前一次處理製程所使用氣體與能量，但不侷限於此。
然後如第3圖所示，去除圖案化光阻52，依序形成一功函數層34與一低阻抗金屬層36於材料層48上，然後搭配進行一平 坦化製程以形成三個閘極結構54、56、58。功函數層34與低阻抗金屬層36之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層36則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。
依據本發明之較佳實施例，閘極結構較54、56、58佳為相同導電型式，例如均為N型閘極或均為P型閘極，且由於凹槽38內的材料層48經過兩次處理製程，凹槽40內的材料層48經過一次處理製程而凹槽42內的材料層48則未經過任何處理製程，後續於各凹槽38、40、42所形成之功函數層34較佳個別包含不同晶粒方向比例(orientation ratio)，使閘極結構54、56、58可藉此分別具有不同臨界電壓。例如在本實施例中，經過兩次處理製程的閘極結構54係為一低臨界電壓(low threshold voltage,LVT)閘極，經過一次處理製程的閘極結構56為一標準臨界電壓(standard threshold voltage,SVT)閘極，而未經過任何處理製程的閘極結構58則為一高臨界電壓(high threshold voltage,HVT)閘極。
請繼續參照第4圖至第6圖，第4圖至第6圖為本發明另一實施例製作一半導體元件之示意圖。如第4圖所示，提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上定義有三個電晶體區。在本實施例中，三個電晶體區較佳為相同導電型式之電晶體區18、20、22，例如一PMOS電晶體區或NMOS電晶體區，且三個電晶體區18、20、22分別預定為後續製作不同臨界電壓之閘極結構。然後比照第1圖於基底12上形成三個虛置閘極(圖未示)，於基底12中形成源極/汲極區域26等電晶體標準元件，形成一層間介電層32 覆蓋虛置閘極，然後去除虛置閘極中的多晶矽材料以於電晶體區18、20、22分別形成三個凹槽38、40、42。
接著形成一高介電常數介電層44以及一底部金屬阻隔層46於層間介電層32上並填入凹槽38、40、42。其中高介電常數介電層44及底部金屬阻隔層46之組成可比照第一實施例，在此不另加贅述。
隨後形成一功函數層(圖未示)於電晶體區18、20、22，形成一圖案化遮罩，例如一圖案化光阻60並覆蓋電晶體區18，並利用圖案化光阻60為遮罩去除電晶體區20、22的功函數層，以形成一功函數層34於電晶體區18的凹槽38內。
如第5圖所示，接著去除圖案化光阻60，形成另一功函數層(圖未示)於電晶體區18、20、22，形成另一圖案化光阻62覆蓋電晶體區20，並利用圖案化光阻62為遮罩去除電晶體區18的部分功函數層及電晶體區22的功函數層，以形成另一功函數層34於電晶體區20的凹槽40內。
然後如第6圖所示，重複上述步驟，去除圖案化光阻62，形成另一功函數層(圖未示)於電晶體區18、20、22，形成另一圖案化光阻(圖未示)覆蓋電晶體區22，並利用圖案化光阻為遮罩去除電晶體區18、20的部分功函數層，以形成另一功函數層34於電晶體區22的凹槽42內。接著去除設於電晶體區22的圖案化光阻，形成一低阻抗金屬層36於功函數層34上並搭配進行一平坦化製程以形成三個閘極結構54、56、58。
值得注意的是，本實施例之閘極結構54、56、58較佳為相同導電型式，例如均為N型閘極或均為P型閘極，因此第4圖至第6圖所示之沉積製程，係藉由調整不同溫度、偏壓製程參數，使其欲形成之功函數層實為相同材質，但卻具有不同臨界電壓。例如設置於凹槽38、40、42中的功函數層34分別由不同沉積溫度所形成，各凹槽38、40、42中所形成之功函數層34較佳個別包含不同晶粒方向比例(orientation ratio)，進而使閘極結構54、56、58分別具有不同臨界電壓。以製作P型閘極為例，採用較低沉積溫度所形成之閘極結構較佳為一低臨界電壓(low threshold voltage,LVT)閘極。反之，採用較高沉積溫度所形成之閘極結構則為為一標準臨界電壓(standard threshold voltage,SVT)閘極或一高臨界電壓(high threshold voltage,HVT)閘極。
請再參照第7圖，第7圖為本發明另一實施例製作一半導體元件之示意圖。如第7圖所示，先比照第1圖於基底12上形成三個虛置閘極(圖未示)，於基底12中形成源極/汲極區域26等電晶體標準元件，形成一層間介電層32覆蓋虛置閘極，然後去除虛置閘極中的多晶矽材料以於電晶體區18、20、22分別形成三個凹槽(圖未示)。需注意的是，本實施例中三個電晶體區18、20、22的電晶體區18、20較佳為相同導電型式之電晶體區而電晶體區22則為不同導電型式之電晶體區，例如電晶體區18、20為一PMOS電晶體區而電晶體區22為一NMOS電晶體區。
接著形成一高介電常數介電層44以及一底部金屬阻隔層46於層間介電層32上並填入各凹槽。其中高介電常數介電層44及 底部金屬阻隔層46之組成可比照第一實施例，在此不另加贅述。
隨後形成不同厚度的P型功函數層於電晶體區18、20及電晶體區22的凹槽內，例如先形成一第一P型功函數層(圖未示)於電晶體區18、20、22，形成一圖案化遮罩(圖未示)，例如一圖案化光阻並覆蓋電晶體區18、20，並利用圖案化光阻為遮罩進行一蝕刻製程去除電晶體區22的P型功函數層，使剩餘的第一P型功函數層(圖未示)形成於電晶體區18、20。
接著去除圖案化光阻，形成一第二P型功函數層(圖未示)於電晶體區18、20、22的凹槽內，至此於電晶體區18、20形成一較厚的P型功函數層64以及於電晶體區22形成較薄的P型功函數層64。隨後依序沉積一N型功函數層66與一低阻抗金屬層68於電晶體區18、20、22的P型功函數層64上並搭配進行一平坦化製程以形成三個閘極結構54、56、58。
值得注意的是，在本實施例中，電晶體區22(或NMOS電晶體區)之P型功函數層64的厚度較佳低於電晶體區18、20(或PMOS電晶體區)之P型功函數層64的厚度，或PMOS電晶體區之P型功函數層64的厚度高於NMOS電晶體區之P型功函數層64的厚度，而本發明則較佳利用兩個電晶體區中P型功函數層的不同厚度來使PMOS電晶體區之閘極結構54、56與NMOS電晶體區之閘極結構58分別具有不同臨界電壓。另外，PMOS電晶體區的P型功函數層64與NMOS電晶體區的P型功函數層64又可依據製程需求選擇為相同材料或不同材料，此變化型也屬本發明所涵蓋的範圍。
綜上所述，本發明較佳於製作三顆或以上之閘極結構時對功函數層或功函數層之前一層材料層進行一處理製程，使後續完成之閘極結構分別具有不同的晶粒方向比例(orientation ratio)，並藉此使各閘極結構分別具有不同臨界電壓。依據上述之實施例，本發明對功函數層或沉積於功函數層前一層之材料層所進行的處理製程可包含離子轟擊(plasma bombardment)或調整沉積溫度，另外本發明又可直接調整不同電晶體區之功函數層厚度來使各閘極結構具有不同臨界電壓。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。

Claims (17)

  1. 一種製作半導體元件的方法，包含：提供一基底，該基底具有一層間介電層設於其上；形成一第一凹槽、一第二凹槽以及一第三凹槽於該層間介電層中；形成一材料層於該層間介電層上並填入該第一凹槽、該第二凹槽及該第三凹槽；對該第一凹槽內之該材料層進行一第一處理製程但不對該第二凹槽以及該第三凹槽內之該材料層進行該第一處理製程；以及對該第一凹槽內與該第二凹槽內之該材料層進行一第二處理製程。
  2. 如申請專利範圍第1項所述之方法，其中該材料層包含一功函數層。
  3. 如申請專利範圍第1項所述之方法，另包形成一功函數層於形成該材料層之後。
  4. 如申請專利範圍第3項所述之方法，另包含：形成一低阻抗金屬層於該功函數層上；以及平坦化該低阻抗金屬層及該功函數層以形成三個閘極結構。
  5. 如申請專利範圍第4項所述之方法，其中該等三個閘極結構包含相同導電型式。
  6. 如申請專利範圍第4項所述之方法，其中該等三個閘極結構之功 函數層包含不同晶粒方向比例(orientation ratio)。
  7. 如申請專利範圍第1項所述之方法，其中該等三個閘極結構分別包含不同臨界電壓。
  8. 一種製作半導體元件的方法，包含：提供一基底，該基底具有一層間介電層設於其上；形成一第一凹槽、一第二凹槽以及一第三凹槽於該層間介電層中；形成一第一功函數層、一第二功函數層以及一第三功函數層於該第一凹槽、該第二凹槽及該第三凹槽，其中該第一功函數層、該第二功函數層及該第三功函數層分別由不同沉積溫度所形成。
  9. 如申請專利範圍第8項所述之方法，另包含：形成一低阻抗金屬層於該第一功函數層、該第二功函數層及該第三功函數層上；以及平坦化該低阻抗金屬層及該第一功函數層、該第二功函數層及該第三功函數層以形成三個閘極結構。
  10. 如申請專利範圍第9項所述之方法，其中該等三個閘極結構包含相同導電型式。
  11. 如申請專利範圍第9項所述之方法，其中該等三個閘極結構之該第一功函數層、該第二功函數層及該第三功函數層分別包含不同晶粒方向比例(orientation ratio)。
  12. 如申請專利範圍第9項所述之方法，其中該等三個閘極結構分 別包含不同臨界電壓。
  13. 一種半導體元件，包含：一基底；以及一第一閘極結構、一第二閘極結構以及一第三閘極結構設於該基底上以及一層間介電層環繞該第一閘極結構、該第二閘極結構及該第三閘極結構，其中該第一閘極結構包含一第一功函數層，該第二閘極結構包含一第二功函數層，該第三閘極結構包含一第三功函數層，且該第一功函數層、該第二功函數層及該第三功函數層分別具有不同晶粒方向比例；以及一第四功函數層設於該第一功函數層、該第二功函數層以及該第三功函數層上。
  14. 如申請專利範圍第13項所述之半導體元件，其中該第一閘極結構、該第二閘極結構以及該第三閘極結構分別包含不同臨界電壓。
  15. 一種半導體元件，包含：一基底；以及一第一閘極結構、一第二閘極結構以及一第三閘極結構設於該基底上以及一層間介電層環繞該第一閘極結構、該第二閘極結構及該第三閘極結構，其中該第一閘極結構、該第二閘極結構及該第三閘極結構分別具有不同晶粒方向比例，該第一閘極結構包含一第一功函數層，該第二閘極結構包含一第二功函數層且該第一功函數層及該第二功函數層包含不同厚度，以及該第一功函數層包含一P型功函數層，該第二功函數層包含一N型功函數層，且該N型功函數層之厚度低於該P型功函數層之厚度。
  16. 如申請專利範圍第15項所述之半導體元件，其中該第一功函數層及該第二功函數層包含相同導電型式。
  17. 如申請專利範圍第16項所述之半導體元件，其中該第一功函數層及該第二功函數層包含相同材料。
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