CN109994472B - 半导体元件与其制作方法 - Google Patents

半导体元件与其制作方法 Download PDF

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CN109994472B
CN109994472B CN201810004058.1A CN201810004058A CN109994472B CN 109994472 B CN109994472 B CN 109994472B CN 201810004058 A CN201810004058 A CN 201810004058A CN 109994472 B CN109994472 B CN 109994472B
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metal layer
layer
bottom barrier
barrier metal
active region
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CN109994472A (zh
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许智凯
傅思逸
邱淳雅
陈金宏
吴骐廷
林毓翔
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US15/866,489 priority patent/US10249488B1/en
Priority to US16/273,003 priority patent/US10755919B2/en
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Abstract

本发明公开一种半导体元件与其制作方法。该半导体元件具有三种相同的导体类型但不同阈值电压的晶体管，其中的第一晶体管含有一高介电常数层、一第一底屏障金属层、一第二底屏障金属层、一功函数金属层、以及一低阻值金属。第二晶体管含有该高介电常数层、该第一底屏障金属层、该第二底屏障金属层以及该低阻值金属。而第三晶体管含有该高介电常数层、该第一底屏障金属层以及该低阻值金属。

Description

半导体元件与其制作方法
技术领域
本发明涉及一种半导体元件及其制造方法，特别是涉及一种具有相同导体类型但不同阈值电压的半导体元件及其制造方法。
背景技术
现今的半导体业广泛地在金属氧化物半导体晶体管(MOS)的栅极制作中使用多晶硅在作为填隙材料。然而，现有的多晶硅栅极因为硼穿透与栅极空乏等会增加栅介电层等效厚度、降低栅极电容值、使元件驱动力劣化的效应而开始面临了效能不足的问题。为了取代传统的多晶硅栅极，业界已开发出高介电常数层搭配功函数金属作为控制栅的设计。
在互补式金属氧化物半导体(CMOS)元件中，NMOS元件与PMOS元件会分别采用不同类型的功函数金属层。目前业界已知双重功函数金属制作工艺相较于一般现有半导体制作工艺而言在制作工艺的控制与相容性方面较为复杂。在双重功函数栅极中必须要精确控制材料的厚度与成分，这种情形在现今晶体管的栅极临界尺寸(critical feature,CD)微缩到20纳米以下还会变得更为严苛。金属栅极晶体管的构成部件，包含高介电常数层、底阻障金属层、p型功函数金属、n型功函数金属、顶阻障金属层以及栅极填充金属等，在如此微细的尺度下会变得难以填入栅极沟槽中。这类沟槽空间不足的问题限制了栅极中所能设置的功函数金属层厚度以及其调整阈值电压(Vth)的能力。
除了用来设置栅极元件的空间不足外，现今的电子产品应用为了优化元件运作时的延迟和能耗，具有多重阈值电压的晶体管变得越来越必要。金属氧化物半导体场效晶体管(MOSFET)的阈值电压是能在晶体管的栅极介电层与基底之间的介面形成一反转层的电压。低阈值电压的元件会用在注重切换速度的逻辑电路应用中，高阈值电压的元件则会连接到电源线或虚拟电源线，其在主动模式下会呈开路态，在睡眠模式下则呈断路态，以此高阈值电压的元件适合做为睡眠晶体管来减少元件的静态功耗。NMOS或PMOS栅极中金属层所使用的材料大多会影响其功函数，最终影响了整个产品的效能表现。故此，半导体制造商都在找寻更佳更好的制作方法，以期在跟上现今半导体技术蓝图的演进的同时提供具有良好功函数表现以及多重阈值电压特性的MOS元件。
发明内容
下面的段落将进行本发明的概要说明，让阅者对本发明的各个面向有基本的了解。此概要并不能尽览本发明，其并未意欲要在此判定本发明的必要元件或特征，或是划定本发明的范畴，其目的仅作为说明书的前言，以在进行后续的细节描述之前先以简化的形式来呈现本发明的某些概念。
为了解决前述金属栅极部件填充空间不足的问题并达成具有多重阈值电压特性的晶体管元件需求，本发明提出了一种创新的晶体管设计，其具有相同的导体类型但不同的层组成结构。本发明具有多重阈值电压的晶体管是在相同的半导体制作工艺中制作而成，但其各别具有额外的制作工艺步骤来形成用来调整功函数的不同层结构，以此达到调出多种不同阈值电压的功效。
在结构方面，本发明提出了一种半导体元件，其结构包含了一基底、一第一晶体管位于该基底上，其中该第一晶体管包含高介电常数层、一第一底阻障金属层位于该高介电常数层上、一第二底阻障金属层位于该第一底阻障金属层上、一功函数金属层位于该第二底阻障金属层上、以及一低阻值金属位于该功函数金属层上。元件中另包含了一第二晶体管位于该基底上，其中该第二晶体管包含该高介电常数层、该第一底阻障金属层位于该高介电常数层上、该第二底阻障金属层位于该第一底阻障金属层上、以及该低阻值金属位于该第二底阻障金属层上。元件中还包含了一第三晶体管位于该基底上，其中该第三晶体管包含该高介电常数层、该第一底阻障金属层位于该高介电常数层上、以及该低阻值金属位于该第一底阻障金属层上。该第一晶体管、该第二晶体管、以及该第三晶体管具有相同的导体类型但不同的阈值电压。
在方法方面，本发明提出了一种半导体元件的制造方法，其步骤包含：提供一基底，其上具有第一主动区域、第二主动区域、以及第三主动区域，在三个主动区域上分别形成一虚置栅极，移除该些虚置栅极以在三个主动区域上形成栅极沟槽，在栅极沟槽中依序形成高介电常数层、第一底阻障金属层、第二底阻障金属层、以及第一功函数金属层，移除第二主动区域与第三主动区域上的第一功函数金属层、移除第三主动区域上的第二底阻障金属层，以及用低阻值金属填满每个沟槽。
本发明的这类目的与其他目的在阅者读过下文中以多种图示与绘图来描述的优选实施例细节说明后必然会变得更为明了易懂。
附图说明
本说明书含有附图并于文中构成了本说明书的一部分，使阅者对本发明实施例有进一步的了解。该些图示描绘了本发明一些实施例并连同本文描述一起说明了其原理。在该些图示中：
图1至图7为根据本发明优选实施例中制作具有相同导体类型但不同阈值电压的半导体元件的制作工艺范例的截面示意图。
需注意本说明书中的所有图示都为图例性质，为了清楚与方便图示说明之故，图示中的各部件在尺寸与比例上可能会被夸大或缩小地呈现，一般而言，图中相同的参考符号会用来标示修改后或不同实施例中对应或类似的元件特征。
主要元件符号说明
100 基底
102 浅沟槽绝缘结构
103 接触蚀刻停止层
104 层间介电层
106 高介电常数层
108 第一底阻障金属层
110 第二底阻障金属层
112 p型功函数金属层
114 掩模
116 n型功函数金属层
118 低阻值金属层
200 第一主动(有源)区域
200a 沟槽
202 虚置栅极
204 介(界)面层
206 第一牺牲栅极
208 第一顶盖层
210 第一间隔壁
212 第一轻掺杂漏极
214 第一源极/漏极
216 晶体管
300 第二主动区域
300a 沟槽
302 虚置栅极
304 介面层
306 第二牺牲栅极
308 第二顶盖层
310 第二间隔壁
312 第二轻掺杂漏极
314 第二源极/漏极
316 晶体管
400 第三主动区域
400a 沟槽
402 虚置栅极
404 介面层
406 第三牺牲栅极
408 第三顶盖层
410 第三间隔壁
412 第三轻掺杂漏极
414 第三源极/漏极
416 晶体管
具体实施方式
在本发明下文的细节说明中，元件符号会标示在随附的图示中作为其中的一部分，并且以可实行该实施例的特例描述方式来表示。这类的实施例会说明足够的细节，使本领域的一般技术人士得具以实施。为了图例清楚之故，图示中可能有部分元件的厚度会加以夸大。阅者需了解到本发明中也可利用其他的实施例或是在不悖离所述实施例的前提下作出结构性、逻辑性、及电性上的改变。因此，下文的细节描述将不欲被视为是一种限定，反之，其中所包含的实施例将由随附的权利要求来加以界定。
在说明优选实施例之前，通篇说明书中会使用特定的词汇来进行描述。例如文中所使用的「蚀刻」一词一般是用来描述图形化一材料的制作工艺，如此制作工艺完成后至少会有部分的该材料余留下来。需了解蚀刻硅材料的制作工艺都会牵涉到在硅材料上图形化一光致抗蚀剂层的步骤，并在之后移除未被光致抗蚀剂层保护的硅区域。如此，被光致抗蚀剂层保护的硅区域会在蚀刻制作工艺完成后保留下来。然而在其他例子中，蚀刻动作也可能指的是不使用光致抗蚀剂层的制作工艺，但其在蚀刻制作工艺完成后仍然会余留下来至少部分的目标材料层。上述说明的用意在于区别「蚀刻」与「移除」两词。当蚀刻某材料时，制作工艺完成后至少会有部分的该材料于留下来。相较之下，当移除某材料时，基本上所有的该材料在该制作工艺中都会被移除。然而在某些实施例中，「移除」一词也可能会有含括蚀刻意涵的广义解释。
文中的描述可能会提到多种/多个位于基底上用来制作场效晶体管元件的区域，需了解这类区域可以存在于基底上的任意位置。再者，这类区域并未互相独立，意即在某些实施例中一或多个这类区域部位可能会重叠。尽管文中仅说明了至多三个不同的区域，需了解基底上是可能存在任意数目的区域的，其也可能将某区域界定为具有特定的元件类型或材质。这些区域一般是用来方便说明基底上有那些具有相似元件类型的区域，其并未要局限所描述实施例的精神与范畴。
文中所用的“形成”、“沉积”、或“设置”等词是用来描述在基底上覆上一层材料的动作。这类词汇是要描述任何可能用来形成层结构的技术，其包含但不限定为，热生长、溅镀、蒸镀、化学气相沉积、外延生长、电镀等。根据多种实施例的不同，沉积的动作可以任何已知的合适方法来进行。例如，沉积动作可包含任何将材料生长、涂布、或转移到一个基底上的制作工艺。一些已知的这类技术包含物理气相沉积(PVD)、化学气相沉积(CVD)、电化学沉积(ECD)、分子束外延(MBE)、原子层沉积(ALD)、以及等离子体增强型化学气相沉积(PECVD)等。
通篇说明书中所使用的“基底”一词一般都认为是硅基底。然而，基底也可以广泛地使用任何其他合适的基材，例如锗(Ge)、砷化镓(GaAs)、磷化铟(InP)等。在其他实施例中，基底也可以是非导电性的，例如玻璃基底或蓝宝石基底。
鳍式场效晶体管(fin field-effect transistor,FinFET)的名称来自于其所使用的场效晶体管整体看起来像是一组鱼鳍，其主要特性在于用来导通的通道被一根根薄细的硅鳍状结构所围绕，故因此得名。鳍结构的厚度决定了其元件的有效通道长度。鳍式场效晶体管的结构一般是一根根垂直的鳍结构位于基底上的源极与漏极区域之间。这些垂直突出于基底外的结构称之为鳍部。这类型的栅极结构可改善对于通道导通的控制并减少漏电流的程度，用于克服短通道效应。
现在请参照图1至图7。图1至图7依序绘示出根据本发明优选实施例中制作具有相同导体类型但不同阈值电压的半导体元件(如鳍式场效晶体管)的制作工艺范例的截面示意图。需注意，就算下列的优选实施例属于鳍式场效晶体管制作工艺，它也可以用在平面式的金属氧化物半导体晶体管制作工艺中，其也含括在本发明的范畴中。
如图1所示，首先提供一基底100，例如一硅基底、一含硅底、或是一硅覆绝缘基底(SOI)，但不限于此。对于FinFET制作工艺而言，基底100会是鳍(条)结构，其较佳是以现有的侧壁影像转移(sidewall image transfer,SIT)制作工艺形成的。多个由氧化硅构成的浅沟槽绝缘结构(shallow trench isolation,STI)102设置在基底100上。根据浅沟槽绝缘结构102所含括的区域，基底100上会界定出由浅沟槽绝缘结构102彼此隔绝的第一主动区域200、第二主动区域300、以及第三主动区域400，其上预定要形成具有相同导体类型但不同阈值电压的半导体元件，如分别具有标准阈值电压(SVT)、低阈值电压(LVT)、以及超低阈值电压(uLVT)的p型场效晶体管(后文中称为pFET)。由于在现今的半导体制作中，pFET会需要较大的栅极沟槽空间来供填入其中的功函数金属层的厚度调配之用，以达成调整n型场效晶体管(后文中称为nFET)与pFET的阈值电压之效，故此相较于nFET而言，pFET较容易有栅极沟槽空间不足的问题。也因此故，此实施例中所描述的晶体管会以pFET为主，以彰显出本发明的优点与诉求。
结合取代性金属栅极(replacement metal gate,RMG)制作工艺，每个所界定出的主动区域上都会先形成一虚置晶体管202,302,402。需注意此优选实施例中所界定出的三个主动区域都具有相同的导电类型，例如都是PMOS区域，且都预定在后续制作工艺中在其上制作出具有不同阈值电压的栅极结构。故此，制作工艺中预计会在将虚置栅极转换成金属栅极的制作工艺期间在该些区域中形成厚度不同或不同数目的底屏障金属(bottombarrier metal,BBM)及/或功函数金属(work function metal,WFM)层等结构。制作工艺中可进行光学邻近修正(optical proximity correction,OPC)来调整或预先界定出栅极沟槽的大小或宽度，如此用来设置栅极的栅极沟槽会比一般的栅极沟槽来得宽，以设置较厚与/或较多的底屏障金属层或是功函数金属层。
在图1所示的实施例中，第一虚置晶体管202含有一第一介面层204、一第一牺牲栅极206、一第一顶盖层208、第一间隔壁210、第一轻掺杂漏极(lightly doped drains,LDD)212以及第一源极/漏极214。在本发明优选实施例中，第一介面层204可以是二氧化硅层。第一介面层204与第一牺牲栅极206之间可选择性地设置一蚀刻停止层(未示出)，如一氮化钛层。第一牺牲栅极206是多晶硅栅极。在另一实施例中，第一牺牲栅极206是多层栅极结构，如包含多晶硅层、非晶硅层、或锗层等。第一顶盖层208可为氮化硅层。第一间隔壁210可以是多层结构，例如包含高温氧化物(HTO)、氮化硅(SiN)、氮氧化硅(SiON)、氮碳化硅(SiCN)等。第一轻掺杂漏极212与第一源极/漏极214可以合适的杂质掺杂制作工艺来形成。在一些实施例中，第一介面层204与第一蚀刻停止层可加以忽略。
同样地，第二虚置晶体管302可包含一第二介面层304、一第二牺牲栅极306、一第二顶盖层308、第二间隔壁310、第二轻掺杂漏极312以及第二源极/漏极214。此实施例中第二晶体管302的元件与第一晶体管202类似，故此不再重复叙述。第三虚置晶体管402可包含一第三介面层404、一第三牺牲栅极406、一第三顶盖层408、第三间隔壁410、第三轻掺杂漏极412以及第三源极/漏极414。此实施例中第三晶体管402的元件与第一晶体管202以及第二晶体管302类似，故不再重复叙述。需注意由于第一主动区域200、第二主动区域300、以及第三主动区域400是界定来在其上形成具有不同阈值电压的半导体元件，故这些晶体管中的某些部件可能会不同。例如，第一源极/漏极214、第二源极/漏极314以及第三源极/漏极414会具有相同导体类型的掺质，然而其注入能量与掺值剂量可能会不同。此外，第一虚置晶体管202、第二虚置晶体管302、第三虚置晶体管402还可能含有其他图1未具体示出的其他半导体结构，如硅化物层、或是以选择性外延成长(selective epitaxial growth,SEG)制作工艺所形成的外延层，其材质如硅锗(SiGe),碳化硅(SiC)或是磷化硅(SiP)，或是其他保护层等。
在第一虚置晶体管202、第二虚置晶体管302、以及第三虚置晶体管402形成后，基底300上还会形成接触蚀刻停止层(contact etch stop layer,CESL)103以及层间介电层(inter-layer dielectric,ILD)104覆盖住第一虚置晶体管202、第二虚置晶体管302、以及第三虚置晶体管402等结构。在一实施例中，接触蚀刻停止层103可在第一主动区域200、第二主动区域300、以及第三主动区域400中生成不同应力来分别在第一虚置晶体管202、第二虚置晶体管302、以及第三虚置晶体管402上达到选择性应变的效果。
现在请参照图2。进行一平坦化制作工艺，如化学机械研磨、回蚀制作工艺或其组合，来移除部分的层间介电层104、接触蚀刻停止层103、第一间隔壁210、第二间隔壁310、第三间隔壁410，并完全移除第一顶盖层208、第二顶盖层308、第三顶盖层408等，直到由多晶硅构成的第一牺牲栅极206、第二牺牲栅极306、以及第三牺牲栅极406裸露出来。
请参照图3。第一牺牲栅极206、第二牺牲栅极306、以及第三牺牲栅极406裸露出来后会进行取代性金属栅极制作工艺来将虚置栅极换成金属栅极。例如，可先进行一选择性干蚀刻制作工艺或是湿蚀刻制作工艺，其使用氨水(NH4OH)或是四甲基氢氧化铵(TMAH)为蚀刻剂来移除第一牺牲栅极206、第二牺牲栅极306、以及第三牺牲栅极406，直到第一介面层204、第二介面层304、第三介面层404裸露出来，如此第一主动区域200、第二主动区域300以及第三主动区域400上会分别形成栅极沟槽200a,300a,400a，其将作为金属栅极的填充空间。在某些实施例中移除牺牲栅极的蚀刻步骤也有可能会直接连介面层204,304,404一起移除。需注意由于基底上的虚置栅极可能具有不同的大小，其移除虚置栅极后所形成的栅极沟槽200a,300a,400a也可能具有不同的大小。
复参照图3。在栅极沟槽形成后，基底和栅极沟槽的表面会形成一层共形的高介电常数层106。此高介电常数层106的介电常数大于4，其材料可能包含了稀土金属氧化物或是镧系金属氧化物，如HfO2,HfSiO4,HfSiON,Al2O3,La2O3,LaAlO,Ta2O5,ZrO2,ZrSiO4,HfZrO,Yb2O3,YbSiO,ZrAlO,HfAlO,AlN,TiO2,ZrON,HfON,ZrSiON,HfSiON,SrBi2Ta2O9(SBT),PbZrxTi1-xO3(PZT)或是BaxSr1-xTiO3(BST)，但不限于此。
仍参照图3。在高介电常数层106形成后，每个主动区域的高介电常数层106表面都会依序形成一共形的第一底阻障金属层108以及一第二底阻障金属层110。底阻障金属层108与110可作为屏障来保护其所邻接的金属不会因为交互热扩散或电迁移而变质。此两层底阻障金属层的材料可包含Ti,TiN,Ta,TaN或WN。在晶体管预定是p型的优选实施例中，第一底阻障金属层108的材料是氮化钛而第二底阻障金属层110的材料是氮化钽。第一底阻障金属层108与第二底阻障金属层110可具有不同的厚度。
现在请参照图4。形成高介电常数层106、第一底阻障金属层108以及第二底阻障金属层110后，用来调整pFET阈值电压的一功函数金属层(后文中会称为p型功函数金属层)112会共形地形成在第二底阻障金属层110的表面上。p型功函数金属层112的厚度可介于约
Figure GDA0003276890050000091
之间。对于pFET元件而言，功函数金属层的功函数需在4.8ev至5.2eV之间，此区间合适的材料可包含但不限于TiN,Ru,Ir,Pt,WN,Mo2N,TaN,TaC。
就现今栅极特征尺寸微缩到低于20纳米的半导体晶体管来说，p型功函数金属层112连同其高介电常数层106以及底阻障金属层108,110等会一起占掉原本就狭窄的栅极沟槽一大部分的空间，这样会使得后续制作工艺中的其他栅极部件更难以填入沟槽。为了要有更多的空间来设置这些栅极部件，制作工艺中会对p型功函数金属层112进行一下拉(pull down)的动作，通过移除其一预定高度上的部位来腾出空间。此下拉制作工艺可包含在栅极沟槽的p型功函数金属层112上形成一掩模114的步骤。掩模114的表面会控制在一预定高度水平。掩模114填入后会进行一蚀刻制作工艺来移除p型功函数金属层112。在此蚀刻制作工艺中，p型功函数金属层112位于该掩模114预定高度上的部位会被移除，如此仅剩ㄩ字形的p型功函数金属层112部位会余留在栅极沟槽中。p型功函数金属层112的下拉动作可经由选择性的方向性蚀刻制作工艺来达成，像是反应性离子蚀刻(reactive-ion etching,RIE)制作工艺，其调整成针对p型功函数金属层112的材料来反应。因为选择性蚀刻制作工艺的结果，制作工艺中p型功函数金属层112只有不需要的部位会被移除，其下方的底阻障金属层110实质上保持不变。移除预定高度上的p型功函数金属层112部位可以增加沟槽的开口大小，让后续制作工艺中的其他栅极部件，如n型功函数金属以及低阻值金属等，可以更容易地填入沟槽中。
现在请参照图5。在ㄩ字形p型功函数金属层112形成后，掩模114会被拔除以裸露出p型功函数金属层112的表面。之后用来调整nFET阈值电压的一共形n型功函数金属层116会被形成在ㄩ字形p型功函数金属层112与第二底阻障金属层110的表面。栅极沟槽的开口因为移除部分上方的p型功函数金属层112之故而扩大，让n型功函数金属层116更容易形成在栅极沟槽中。请注意，本发明是特别用来解决pFET栅极部件填充空间不足的问题并且要彰显具有不同阈值电压的pFET特性，故此，为了发明书的简明之故，图中将不会示出nFET元件。此步骤所形成的n型功函数金属层116只是要用来强调本发明的制作工艺可以同时制作出pFET元件与nFET元件。在一些实施例中，n型功函数金属层116的厚度可介于约
Figure GDA0003276890050000101
之间。对于nFET元件而言，功函数金属层的功函数需在3.9ev至4.3eV之间，此区间合适的材料可包含但不限于TiAl,ZrAl,WAl,TaAl,HfAl或TiAlC。
现在请参照图6。在ㄩ字形p型功函数金属层112以及n型功函数金属层116形成后，每个预定的主动区域200,300,400都会进行个别不同的步骤来改变预定设置在该些区域中的栅极部件，进而赋予它们不同的阈值电压特性。在优选实施例中，主动区域200,300,400被分别界定成SVT,LVT以及uLVT区域。首先，由于只有nFET区域(未示出)需要用到n型功函数金属层116，故主动区域200,300,400上的n型功函数金属层116都要加以移除。此步骤可包含在所有的nFET主动区域上涂布上一层光致抗蚀剂作为蚀刻掩模，然后进行一选择性蚀刻制作工艺来移除pFET主动区域上的n型功函数金属层116。n型功函数金属层116移除后，主动区域200,300,400上的ㄩ字形p型功函数金属层112会裸露出来。
在本发明优选实施例中，由于主动区域被界定成具有标准阈值电压的pFET区域，故此区域中必须要有ㄩ字形p型功函数金属层112来将电压调成标准电压，而主动区域300与400被界定成具有低阈值电压与超低阈值电压的pFET区域，它们会需要多一点的沟槽空间来将电压调成低电压。为了达到上述目的，主动区域300与400中的ㄩ字形p型功函数金属层112要加以移除。此制作工艺步骤包含在主动区域200上涂布一层光致抗蚀剂作为蚀刻掩模，之后进行一选择性蚀刻制作工艺来移除主动区域300与400上的p型功函数金属层112。p型功函数金属层112移除后，主动区域300与400上的第二(上层的)底阻障金数层110会完全裸露出来，而主动区域200上的ㄩ字形p型功函数金属层112则仍保留着。
尽管主动区域300与400中的p型功函数金属层112已被移除，相较于主动区域300来说，主动区域400仍需要更多的沟槽空间来将电压调成超低阈值电压。为了上述需求，实施例中会进行其他的制作工艺来移除主动区域400上栅极沟槽400a中的第二(上层的)底阻障金数层110。此制作工艺步骤可包含在主动区域200与主动区域300上涂布一层光致抗蚀剂作为蚀刻掩模，之后进行一选择性蚀刻制作工艺移除主动区域400上栅极沟槽400a中的第二底阻障金属层110。主动区域400上栅极沟槽400a外的第二底阻障金属层110可以不加以移除。重点在于要在栅极沟槽中腾出更多的空间来调整电压。
在如同上述LVT主动区域300以及uLVT主动区域的例子中，需注意第二底阻障金属层110与第一底阻障金属层108最好是以氮化钨(WN)来形成，但不限于此。在本发明实施例中，以氮化钨为主的底阻障金属层108与110可同时作为功函数金属层之用，其功函数约为5eV，对于低阈值电压元件来说是个不错的数值。这也是为什么在本发明中主动区域300或主动区域400不需要具备ㄩ字形p型功函数金属层112的原因，因为这类底阻障金属层可同时达到扩散阻障与功函数调整的功效。对具有较多沟槽空间的主动区域400而言，形成较厚、以氮化钨为主的第一(下层)底阻障金属层108可以将其功函数调降到至uLVT的水准。在本发明实施例中，较宽的沟槽空间可让主动区域400有较多的调压空间。
现在请参照图7。在准备好每一区域中调整功函数的栅极部件后，每一栅极沟槽中会形成并填满低阻值金属118，之后会再进行一平坦化制作工艺，如CMP，来移除位于栅极沟槽外的低阻值金属118、第二底阻障金属层110、第一底阻障金属层108以及高介电常数层106等，如此即完成了主动区域200,300,400上晶体管216,316,416的制作。低阻值金属118的材料可包含Al,Ti,Ta,W,Nb,Mo,TiN,TiC,TaN,Ti/W or Ti/TiN等，但不限于此。
就现有技术来说，低阻值金属与下层的功函数金属层之间还会形成一顶阻障金属(top barrier metal,TBM，为示出)来避免其间的扩散变质。然而，由于金属栅极302,402并不具备常规的功函数金属层，而是改用以氮化钨为主的底阻障金属层作为功函数金属层，故其金属栅极302与402中可以不具备顶阻障金属层。
由于晶体管216,316,416具有不同的结构组成，它们会有不同的电性表现。具体言之，晶体管216的阈值电压(SVT)最大，晶体管316的阈值电压(LVT)次之，而晶体管416的阈值电压(uLVT)最小。在一实施例中，晶体管216的阈值电压约介于0.3V～0.6V之间，晶体管316的阈值电压约介于0.2V～0.3V之间，而晶体管416的阈值电压约介于0.1V～0.2V之间。
综合以上说明，本发明提出了一种具有多种晶体管的半导体结构与其制作方法，其特点在于所形成晶体管具有相同的导体类型但是不同的栅极部件。例如在优选实施例中，半导体元件包含第一晶体管216、第二晶体管316、以及第三晶体管416，其中第一晶体管216包含一高介电常数层106、一第一底阻障金属层108位于高介电常数层106上、一第二底阻障金属层110位于第一底阻障金属层108上、一功函数金属层112位于第二底阻障金属层110上、以及一低阻值金属118位于功函数金属层112上。第二晶体管316包含高介电常数层106、第一底阻障金属层108位于高介电常数层106上、第二底阻障金属层110位于第一底阻障金属层108上、以及低阻值金属118位于第二底阻障金属层110上。第三晶体管416则包含高介电常数层106、第一底阻障金属层108位于高介电常数层106上、以及低阻值金属118位于第一底阻障金属层108上。因为具有这样不同的栅极组成，因而能调整该些晶体管各自的电性表现并提供它们不同的阈值电压。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (13)

1.一种半导体元件，其特征在于，包含：
基底；
第一晶体管，位于该基底上，其中该第一晶体管包含高介电常数层、第一底阻障金属层位于该高介电常数层上、第二底阻障金属层位于该第一底阻障金属层上、功函数金属层位于该第二底阻障金属层上、以及低阻值金属位于该功函数金属层上并与该功函数金属层直接接触；
第二晶体管，位于该基底上，其中该第二晶体管包含该高介电常数层、该第一底阻障金属层位于该高介电常数层上、该第二底阻障金属层位于该第一底阻障金属层上、以及该低阻值金属位于该第二底阻障金属层上并与该第二底阻障金属层直接接触；以及
第三晶体管，位于该基底上，其中该第三晶体管包含该高介电常数层、该第一底阻障金属层位于该高介电常数层上、以及该低阻值金属位于该第一底阻障金属层上并与该第一底阻障金属层直接接触，其中该第一晶体管、该第二晶体管以及该第三晶体管具有相同的导体类型但不同的阈值电压。
2.如权利要求1所述的半导体元件，其中该第一晶体管、该第二晶体管、以及该第三晶体管是p型晶体管。
3.如权利要求1所述的半导体元件，其中该第一底阻障金属层的材料是氮化钨。
4.如权利要求1所述的半导体元件，其中该第二底阻障金属层的材料是氮化钨。
5.如权利要求1所述的半导体元件，其中该第一底阻障金属层与该第二底阻障金属层的材料分别是氮化钛与氮化钽。
6.如权利要求1所述的半导体元件，其中该功函数金属层呈ㄩ字形且其顶面低于该低阻值金属的顶面。
7.如权利要求1所述的半导体元件，还包含顶阻障金属层，位于该功函数金属层与该低阻值金属之间。
8.如权利要求1所述的半导体元件，还包含介面层，位于该基底与该高介电常数层之间。
9.一种制作半导体元件的方法，其特征在于，包含：
提供一具有第一主动区域、第二主动区域、以及第三主动区域的基底；
在该第一主动区域、该第二主动区域、以及该第三主动区域中分别形成虚置栅极；
移除该些虚置栅极以在该第一主动区域、该第二主动区域、以及该第三主动区域中分别形成沟槽；
在该沟槽中形成一高介电常数层、一第一底阻障金属层位于该高介电常数层上、一第二底阻障金属层位于该第一底阻障金属层上、以及一第一功函数金属层位于该第二底阻障金属层上；
移除该第二主动区域以及该第三主动区域上的该第一功函数金属层；
移除该第三主动区域上的该第二底阻障金属层；以及
在该沟槽中填满一低阻值金属，该低阻值金属分别与该第一主动区域上的该第一功函数金属层、该第二主动区域上的该第二底阻障金属层、以及该第三主动区域上的该第一底阻障金属层直接接触。
10.如权利要求9所述的制作半导体元件的方法，还包含进行一蚀刻制作工艺来移除一预定高度上的第一功函数金属层，使该第一功函数金属层呈ㄩ字形。
11.如权利要求10所述的制作半导体元件的方法，还包含在该ㄩ字形的第一功函数金属层上形成一第二功函数金属层，其中该第二功函数金属层与该第一功函数金属层分别用于具有不同导体类型的晶体管中。
12.如权利要求11所述的制作半导体元件的方法，还包含移除该第一主动区域、该第二主动区域、以及该第三主动区域上的该第二功函数金属层。
13.如权利要求9所述的制作半导体元件的方法，还包含进行一化学机械研磨制作工艺来移除该沟槽外的该高介电常数层、该第一底阻障金属层、该第二底阻障金属层。
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US11728171B2 (en) * 2020-06-25 2023-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with metal gate fill structure
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105514105A (zh) * 2014-09-26 2016-04-20 联华电子股份有限公司 集成电路与其形成方法
CN105826265A (zh) * 2015-01-09 2016-08-03 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
KR20160099773A (ko) * 2015-02-12 2016-08-23 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN106033745A (zh) * 2015-03-19 2016-10-19 联华电子股份有限公司 半导体元件及其形成方法
US9502416B1 (en) * 2015-06-04 2016-11-22 Samsung Electronics Co., Ltd. Semiconductor device including transistors having different threshold voltages
CN106409830A (zh) * 2015-07-27 2017-02-15 联华电子股份有限公司 具有金属栅极的半导体元件及其制作方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8704294B2 (en) * 2011-06-13 2014-04-22 United Microelectronics Corp. Semiconductor device having metal gate and manufacturing method thereof
US8847333B2 (en) * 2011-09-01 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Techniques providing metal gate devices with multiple barrier layers
JP5816539B2 (ja) * 2011-12-05 2015-11-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN103187367B (zh) * 2011-12-29 2017-06-23 联华电子股份有限公司 具有金属栅极的半导体元件的制作方法
US9012319B1 (en) * 2013-11-01 2015-04-21 Globalfoundries Inc. Methods of forming gate structures with multiple work functions and the resulting products
KR102212267B1 (ko) * 2014-03-19 2021-02-04 삼성전자주식회사 반도체 장치 및 그 제조 방법
TWI624863B (zh) * 2014-10-13 2018-05-21 聯華電子股份有限公司 半導體元件及其製作方法
TWI635535B (zh) * 2015-03-10 2018-09-11 聯華電子股份有限公司 具有不同臨界電壓的金屬閘極的半導體製程及半導體結構
KR102376503B1 (ko) * 2015-04-23 2022-03-18 삼성전자주식회사 집적회로 장치 및 이의 제조 방법
KR102358318B1 (ko) * 2015-06-04 2022-02-04 삼성전자주식회사 멀티 일함수 게이트 패턴들을 갖는 반도체 소자
CN107305866A (zh) * 2016-04-25 2017-10-31 联华电子股份有限公司 半导体元件及其制作方法
US9899264B2 (en) * 2016-06-30 2018-02-20 International Business Machines Corporation Integrated metal gate CMOS devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105514105A (zh) * 2014-09-26 2016-04-20 联华电子股份有限公司 集成电路与其形成方法
CN105826265A (zh) * 2015-01-09 2016-08-03 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
KR20160099773A (ko) * 2015-02-12 2016-08-23 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN106033745A (zh) * 2015-03-19 2016-10-19 联华电子股份有限公司 半导体元件及其形成方法
US9502416B1 (en) * 2015-06-04 2016-11-22 Samsung Electronics Co., Ltd. Semiconductor device including transistors having different threshold voltages
CN106409830A (zh) * 2015-07-27 2017-02-15 联华电子股份有限公司 具有金属栅极的半导体元件及其制作方法

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