TWI773873B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI773873B
TWI773873B TW108102399A TW108102399A TWI773873B TW I773873 B TWI773873 B TW I773873B TW 108102399 A TW108102399 A TW 108102399A TW 108102399 A TW108102399 A TW 108102399A TW I773873 B TWI773873 B TW I773873B
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gate electrode
semiconductor device
fin structure
dielectric layer
sides
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TW202029300A (zh
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張仲甫
陳冠宏
羅廣鈺
陳俊嘉
陸俊岑
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聯華電子股份有限公司
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Priority to US16/282,323 priority patent/US11631753B2/en
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Priority to US18/118,115 priority patent/US12009409B2/en
Priority to US18/118,154 priority patent/US20230207669A1/en
Priority to US18/653,933 priority patent/US20240282843A1/en

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Abstract

本發明揭露一種製作半導體元件的方法。首先形成一鰭狀結構於一基底上，然後形成一閘極介電層於鰭狀結構上，形成一閘極電極於該鰭狀結構上，進行一氮化製程將離子植入閘極電極兩側的閘極介電層內並將閘極介電層分隔為一第一部分設於閘極電極正下方以及一第二部分設於閘極電極兩側，再形成一磊晶層於閘極電極兩側。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種利用氮化製程將離子植入閘極介電層內的方法。
近年來，隨著場效電晶體(field effect transistors,FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor,Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering,DIBL)效應，並可以抑制短通道效應(short channel effect,SCE)。再者，由於鰭狀場效電晶體元件在同樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可 藉由調整閘極的功函數而加以調控。
在現行的鰭狀場效電晶體元件製程中，鰭狀結構經由分割後通常會填入絕緣物形成淺溝隔離。然而被分隔後之鰭狀結構與鰭狀結構之間的淺溝隔離通常會因製程的因素形成擴口並影響後續閘極結構的設置。因此如何改良現有鰭狀場效電晶體製程與架構即為現今一重要課題。
本發明一實施例揭露一種製作半導體元件的方法。首先形成一鰭狀結構於一基底上，然後形成一閘極介電層於鰭狀結構上，形成一閘極電極於該鰭狀結構上，進行一氮化製程將離子植入閘極電極兩側的閘極介電層內並將閘極介電層分隔為一第一部分設於閘極電極正下方以及一第二部分設於閘極電極兩側，再形成一磊晶層於閘極電極兩側。
本發明另一實施例揭露一種半導體元件，其特徵在於包含：一鰭狀結構沿著一第一方向延伸於一基底上，一閘極電極沿著一第二方向延伸於該鰭狀結構上以及一閘極介電層沿著該第一方向延伸於該鰭狀結構及該閘極電極之間，其中閘極介電層包含一第一部分設於閘極電極正下方以及一第二部分設於閘極電極兩側。
本發明又一實施例揭露一種半導體元件，其特徵在於包含一 鰭狀結構沿著一第一方向延伸於一基底上，一閘極電極沿著一第二方向延伸於鰭狀結構上以及一磊晶層設於閘極電極兩側，其中磊晶層包含一六角形以及一突出部。
12:基底
14:鰭狀結構
16:淺溝隔離
18:閘極介電層
20:閘極電極
22:第一部分
24:第二部分
26:側壁子
28:輕摻雜汲極
30:磊晶層
32:源極/汲極區域
34:六角形
36:突出部
38:高介電常數介電層
40:功函數金屬層
42:低阻抗金屬層
44:金屬閘極
46:氮化製程
第1圖至第4圖為本發明較佳實施例以上視角度製作一半導體元件之方法示意圖。
請參照第1圖至第4圖，第1圖至第4圖為本發明較佳實施例以上視角度製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上可定義有一電晶體區，例如一PMOS電晶體區或一NMOS電晶體區。基底12上具有至少一鰭狀結構14及一絕緣層(圖未示)，其中鰭狀結構14之底部係被絕緣層，例如氧化矽所包覆而形成淺溝隔離16。
依據本發明一實施例，鰭狀結構14較佳透過側壁圖案轉移(sidewall image transfer,SIT)技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層之各側壁形成側壁子。繼以去除圖案化犧牲 層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構14之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成鰭狀結構。另外，鰭狀結構之形成方式也可以先形成一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構。這些形成鰭狀結構的實施例均屬本發明所涵蓋的範圍。
接著可先進行一氧化製程例如現場蒸氣成長製程(in-situ steam generation,ISSG)製程於鰭狀結構14表面包括其上表面及側壁形成一由氧化矽所構成的閘極介電層18，再形成至少一由多晶矽所構成的閘極結構或閘極電極20橫跨鰭狀結構14。如第1圖的上視圖中所示，鰭狀結構14較佳沿著一第一方向例如X方向延伸於基底12上，閘極介電層18由於覆蓋於鰭狀結構14頂部及兩個側壁因此同樣如鰭狀結構14般沿著第一方向例如X方向延伸於基底12上，閘極電極20則沿著一第二方向例如Y方向跨在鰭狀結構14上方。
如第2圖所示，接著進行一氮化製程46將氮離子植入閘極電極20兩側的閘極介電層18甚至淺溝隔離16內。更具體而言，本實施例較佳在不形成任何圖案化遮罩的情況下直接利用已圖案化的閘極電極 20為遮罩進行前述氮化製程，將氮離子植入閘極電極20兩側的鰭狀結構14、閘極介電層18及淺溝隔離16內，藉此將閘極介電層18分隔為一第一部分22設於閘極電極20正下方以及一第二部分24設於閘極電極20兩側，其中第一部分22與第二部分24較佳包含不同材料。從細部來看，設於閘極電極20正下方的第一部分22由於未被植入氮離子因此在氮化製程後仍僅包含氧化矽，而設於閘極電極20兩側的第二部分24及淺溝隔離16由於被植入氮離子因此較佳在氮化製程後包含氮氧化矽(silicon oxynitride,SiON)。在本實施例中，氮化製程可包含但不侷限於遠端熱氮化(remote thermal nitridation,RTN)製程或去耦合電漿氮化(decoupled plasma nitridation,DPN)製程。
如第3圖所示，然後在閘極電極20側壁形成至少一側壁子26，並於側壁子26兩側的鰭狀結構14以及/或基底12中形成一輕摻雜汲極28。隨後可選擇性形成另一側壁子(圖未示)於側壁子26側壁，去除側壁子26兩側的閘極介電層18及部分鰭狀結構14以於側壁子26兩側形成一凹槽(圖未示)，再形成磊晶層30及源極/汲極區域32於凹槽內，並可選擇性於磊晶層30表面形成一金屬矽化物(圖未示)。值得注意的是，由於前述氮化製程可降低形成凹槽時稀釋氫氟酸(diluted hydrofluoric acid,dHF)或SiCoNi製程的蝕刻速率，使設於閘極電極20與磊晶層30之間的部分閘極介電層18(即前述之第二部分24)在凹槽形成時不致被完全去除進進而改善閘極結構與源極/汲極區域間的重疊電容值(capacitance overlap,Cov)，因此本實施例於閘極電極20兩側形成凹槽後利用磊晶成長製程所形成的磊晶層30由上視角度來看較佳包含一六角形34以及一突出部36設於六角形磊晶層30尾端並朝著閘極電 極20方向延伸。補充說明的是：SiCoNi製程主要是利用含氟氣體和氧化矽反應生成氟矽酸銨((NH4)2SiF6)，來選擇性移除原生氧化矽，其中前述含氟氣體可包含氟化氫(HF)或三氟化氮(NF3)。
在本實施例中，側壁子26可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子以及一主側壁子。其中偏位側壁子與主側壁子可包含相同或不同材料，且兩者均可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。輕摻雜汲極28與源極/汲極區域32可依據所置備電晶體的導電型式而包含不同摻質以及/或磊晶材料，例如NMOS區域的源極/汲極區域32可包含碳化矽(SiC)或磷化矽(SiP)而PMOS區域的源極/汲極區域32可包含鍺化矽(SiGe)，但均不限於此。
如第4圖所示，然後形成一層間介電層(圖未示)於閘極電極20上，並進行一平坦化製程，例如利用化學機械研磨去除部分層間介電層藉此暴露出由多晶矽材料所構成的閘極電極20，使閘極電極20上表面與層間介電層上表面齊平。
隨後進行一金屬閘極置換製程將閘極電極轉換為金屬閘極。舉例來說，可先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide,NH4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide,TMAH)等蝕刻溶液來去除多晶矽所構成的閘極電極20以於層間介電層中形成凹槽(圖未示)。之後依序形成一高介電常數介電層38、一功函數金屬層40以及一低阻抗金屬層42 於凹槽內，然後進行一平坦化製程，例如利用CMP去除部分低阻抗金屬層42、部分功函數金屬層40與部分高介電常數介電層38以形成由金屬閘極44所構成的閘極電極20。
以本實施例利用後高介電常數介電層製程所製作的閘極結構為例，所形成的金屬閘極44較佳包含閘極介電層18、高介電常數介電層38、功函數金屬層40以及低阻抗金屬層42，其中高介電常數介電層38與功函數金屬層40若由第4圖的上視角度來看較佳為環形。
在本實施例中，高介電常數介電層38包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧化合物(hafnium silicon oxide,HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化鋁(aluminum oxide,Al2O3)、氧化鑭(lanthanum oxide,La2O3)、氧化鉭(tantalum oxide,Ta2O5)、氧化釔(yttrium oxide,Y2O3)、氧化鋯(zirconium oxide,ZrO2)、鈦酸鍶(strontium titanate oxide,SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide,ZrSiO4)、鋯酸鉿(hafnium zirconium oxide,HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)、鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其組合所組成之群組。
功函數金屬層40較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層40可選用功函數為3.9電子伏特(eV)~4.3eV的金屬 材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC(碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層40可選用功函數為4.8eV~5.2eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層40與低阻抗金屬層42之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層42則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。
請再參照第3圖或第4圖，第3圖或第4圖為本發明一實施例之一半導體元件之上視結構圖。如第3圖或第4圖所示，半導體元件主要包含一鰭狀結構14沿著第一方向例如X方向延伸於基底12上，閘極電極20沿著第二方向例如Y方向延伸於鰭狀結構14上，側壁子26設於閘極電極20側壁，閘極介電層18沿著該第一方向延伸於鰭狀結構14與閘極電極20之間，以及磊晶層30設於閘極電極20兩側。
從本實施例的上視結構來看，閘極介電層18包含第一部分22設於閘極電極20正下方以及第二部分24設於閘極電極20兩側或更具體而言設於第一部分22及磊晶層30之間，其中第一部分22與第二部分24較佳包含不同材料，例如本實施例的第一部分22較佳包含氧化矽而第二部分24則包含氮氧化矽。此外磊晶層30較佳包含一六角形34以及一突出部36，其中突出部36是設於六角形34與鰭狀結構14之間並沿著第一方向朝鰭狀結構14延伸，同時六角形34及突出部36也較佳包含相同材料，例如兩者均由鍺化矽或碳化矽所構成。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底
14:鰭狀結構
16:淺溝隔離
18:閘極介電層
20:閘極電極
22:第一部分
24:第二部分
26:側壁子
28:輕摻雜汲極
30:磊晶層
32:源極/汲極區域
34:六角形
36:突出部

Claims (18)

  1. 一種製作半導體元件的方法，其特徵在於，包含：形成一鰭狀結構於一基底上；形成一閘極介電層於該鰭狀結構上；形成一閘極電極於該鰭狀結構上；進行一氮化製程將離子植入該閘極電極兩側之該閘極介電層內；以及形成一磊晶層於該閘極電極兩側。
  2. 如申請專利範圍第1項所述之方法，另包含進行該氮化製程將氮離子植入該閘極介電層內以將該閘極介電層分隔為一第一部分設於該閘極電極正下方以及一第二部分設於該閘極電極兩側。
  3. 如申請專利範圍第2項所述之方法，其中該第一部分及該第二部分包含不同材料。
  4. 如申請專利範圍第3項所述之方法，其中該第一部分包含氧化矽且該第二部分包含氮氧化矽。
  5. 如申請專利範圍第2項所述之方法，另包含：於進行該氮化製程後形成一輕摻雜汲極於該閘極電極兩側；去除部分該第二部分及部分該鰭狀結構以於該閘極電極兩側形成一凹槽；以及 形成該磊晶層於該凹槽內。
  6. 如申請專利範圍第1項所述之方法，其中該鰭狀結構以及該閘極介電層係沿著一第一方向延伸於該基底上且該閘極電極係沿著一第二方向延伸。
  7. 如申請專利範圍第6項所述之方法，其中該第一方向垂直該第二方向。
  8. 如申請專利範圍第1項所述之方法，其中該氮化製程包含遠端熱氮化(remote thermal nitridation,RTN)製程或去耦合電漿氮化(decoupled plasma nitridation,DPN)製程。
  9. 一種半導體元件，其特徵在於，包含：一鰭狀結構沿著一第一方向延伸於一基底上；一閘極電極沿著一第二方向延伸於該鰭狀結構上；二側壁子，分別設置於該閘極電極的二側壁；以及一閘極介電層沿著該第一方向延伸於該鰭狀結構及該閘極電極之間，其中該閘極介電層包含一第一部分設於該閘極電極正下方以及一第二部分設於該閘極電極兩側，且各該側壁子位於該第二部分及該閘極電極之間。
  10. 如申請專利範圍第9項所述之半導體元件，其中該第一部分及該第二部分包含不同材料。
  11. 如申請專利範圍第10項所述之半導體元件，其中該第一部分包含氧化矽且該第二部分包含氮氧化矽。
  12. 如申請專利範圍第9項所述之半導體元件，另包含一磊晶層設於該閘極電極兩側，其中該第二部分係設於該第一部分及該磊晶層之間。
  13. 如申請專利範圍第9項所述之半導體元件，其中該第一方向垂直該第二方向。
  14. 一種半導體元件，其特徵在於，包含：一鰭狀結構沿著一第一方向延伸於一基底上；一閘極電極沿著一第二方向延伸於該鰭狀結構上；以及一磊晶層設於該閘極電極兩側，其中該磊晶層包含一六角形以及一突出部。
  15. 如申請專利範圍第14項所述之半導體元件，其中該突出部係設於該六角形及該鰭狀結構之間。
  16. 如申請專利範圍第14項所述之半導體元件，其中該突出部係沿著該第一方向朝該鰭狀結構延伸。
  17. 如申請專利範圍第14項所述之半導體元件，其中該六角形 及該突出部包含相同材料。
  18. 如申請專利範圍第14項所述之半導體元件，其中該第一方向垂直該第二方向。
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