CN109728080B - 隧道场效应晶体管及其制作方法 - Google Patents

隧道场效应晶体管及其制作方法 Download PDF

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CN109728080B
CN109728080B CN201711026937.6A CN201711026937A CN109728080B CN 109728080 B CN109728080 B CN 109728080B CN 201711026937 A CN201711026937 A CN 201711026937A CN 109728080 B CN109728080 B CN 109728080B
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field effect
effect transistor
isolation structure
gate structure
disposed
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CN109728080A (zh
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林俊豪
唐俊荣
陈信宇
谢守伟
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United Microelectronics Corp
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United Microelectronics Corp
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Abstract

本发明公开一种隧道场效应晶体管及其制作方法，该隧穿场效晶体管主要包含：一第一栅极结构设于基底上、一源极区域具有第一导电型式设于第一栅极结构一侧、一漏极区域具有第二导电型式设于第一栅极结构另一侧、一第一隔离结构设于源极区域旁以及一第二隔离结构设于该漏极区域旁，其中该第一隔离结构以及该第二隔离结构包含相同材料以及不同深度。

Description

隧道场效应晶体管及其制作方法
技术领域
本发明涉及一种隧道场效应晶体管，尤其是涉及一种栅极结构两侧具有不同深度的隔离结构的隧道场效应晶体管。
背景技术
在过去的数十年间，半导体集成电路工业迅速发发展，且随着半导体材料和技术的持续演进，相应产生了日益微缩且复杂的电路。由于半导体技术的不断演进，半导体元件的尺寸得以逐渐缩小，单位面积的半导体基板可以容纳的半导体元件数量也持续增加。然而，即便半导体元件尺寸的微缩已成功增加了元件的积集度，其也伴随带来了其他技术问题。举例而言，由于元件间变得更加紧密，不但造成了漏电流的增加，不同信号间的干扰程度也相应产生。此外，如何更有效地使用电源也是另一个需要解决的课题。
为了解决上述问题，目前业界已提出利用隧道场效应晶体管(tunneling fieldeffect transistor,TFET)以取代现有金属氧化物半导体场效晶体管(metal-oxide-semiconductor field effect transistor)的作法。其中，隧道场效应晶体管的特点在于可以提供较高的次临界摆幅(subthreshold swing,SS)，例如可达到60mV/dec，其电流开关比(Ion/Ioff ratio)也高于现有的金属氧化物半导体场效晶体管，且其截止状态的漏电流也低于现有的金属氧化物半导体场效晶体管。
然而，现有的隧道场效应晶体管仍存有诸多问题需带克服，举例而言，现有的隧道场效应晶体管仍具有导通电流(Ion)过低的问题，而且其次临界摆幅仍存有改善的空间。
发明内容
本发明一实施利公开一种隧道场效应晶体管，其包含：一第一栅极结构设于基底上、一源极区域具有第一导电型式设于第一栅极结构一侧、一漏极区域具有第二导电型式设于第一栅极结构另一侧、一第一隔离结构设于源极区域旁以及一第二隔离结构设于该漏极区域旁，其中第一隔离结构以及第二隔离结构包含相同材料以及不同深度。
本发明另一实施利公开一种隧道场效应晶体管，其主要包含：一第一栅极结构设于基底上、一源极区域具有第一导电型式设于第一栅极结构一侧、一漏极区域具有第二导电型式设于第一栅极结构另一侧、一第一隔离结构设于源极区域旁以及一第二隔离结构设于漏极区域旁，其中第一隔离结构以及第二隔离结构包含不同材料以及不同深度。
附图说明
图1为本发明一实施例的一隧道场效应晶体管的结构示意图；
图2为图1中沿着切线AA’的剖面示意图；
图3为本发明一实施例的隧道场效应晶体管的结构示意图。
主要元件符号说明
12 基底 14 鳍状结构
16 鳍状结构 18 鳍状结构
20 隔离结构 22 隔离结构
24 隧道场效应晶体管 26 隧道场效应晶体管
28 隧道场效应晶体管 30 栅极结构
32 栅极结构 34 栅极结构
36 栅极结构 38 栅极结构
40 栅极结构 42 栅极结构
44 栅极结构 46 栅极介电层
48 高介电常数介电层 50 功函数金属层
52 低阻抗金属层 54 硬掩模
56 间隙壁 58 源极区域
60 漏极区域 62 通道区域
64 层间介电层 66 接触插塞
68 下半部 70 上半部
72 隔离结构
具体实施方式
请参照图1至图2，图1为本发明一实施例的一隧道场效应晶体管的结构示意图，图2则为图1中沿着切线AA’的剖面示意图。如图1至图2所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，然后形成至少一鳍状结构，例如鳍状结构14、16、18于基底12上，其中鳍状结构14、16、18的底部被绝缘材料所包覆而形成浅沟隔离或隔离结构20、22。
依据本发明一实施例，鳍状结构14、16、18较佳通过侧壁图案转移(sidewallimage transfer,SIT)技术制得，其程序大致包括：提供一布局图案至电脑系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，鳍状结构14、16、18的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成鳍状结构。另外，鳍状结构14、16、18的形成方式也可以先形成一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的鳍状结构。这些形成鳍状结构的实施例均属本发明所涵盖的范围。
接着可于鳍状结构14、16、18上形成多个隧道场效应晶体管24、26、28以及栅极结构36、38、40、42、44于隧道场效应晶体管24、26、28两侧，其中各隧道场效应晶体管24、26、28中的栅极结构30、32、34较佳为主动栅极结构而设于隧道场效应晶体管24、26、28两侧的栅极结构36、38、40、42、44则为虚置栅极。在本实施例中，各栅极结构30、32、34、36、38、40、42、44较佳为一金属栅极，其中各栅极结构30、32、34、36、38、40、42、44的制作方式可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-klast)制作工艺等方式制作完成。
以本实施例利用后高介电常数介电层制作工艺并搭配金属栅极置换制作工艺所制作出的栅极结构为例，各栅极结构30、32、34、36、38、40、42、44较佳包含一介质层或栅极介电层46、一U型高介电常数介电层48、一U型功函数金属层50以及一低阻抗金属层52，且各栅极结构30、32、34、36、38、40、42、44上方较加设有一由例如氮化硅所构成的硬掩模54。由于以高介电常数介电层制作工艺搭配金属栅极置换制作工艺将由多晶硅所构成的虚置栅极转换为金属栅极为本领域所熟知技术，在此不另加赘述。
在本实施例中，高介电常数介电层48包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层50较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层50可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层50可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层50与低阻抗金属层52之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层52则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。
值得注意的是，如图1的上视图所示，本实施例中的鳍状结构14、16、18较佳沿着一第一方向，例如X方向延伸，各栅极结构30、32、34、36、38、40、42、44较佳沿着与第一方向垂直(例如Y方向)的第二方向延伸，设于栅极结构38、44正下方的隔离结构20与栅极结构38、44般同样沿着第二方向延伸，而设于鳍状结构14、16、18尾端或鳍状结构16以及鳍状结构18之间的隔离结构22则环绕整个鳍状结构14、16、18。
如图2的剖面所示，各栅极结构30、32、34、36、38、40、42、44侧壁设有至少一间隙壁56，各栅极结构30、32、34一侧的鳍状结构14、16、18内设有一源极区域58，各栅极结构30、32、34另一侧的鳍状结构14、16、18内设有一漏极区域60，源极区域58以及漏极区60表面可选择性形成金属硅化物(图未示)，各栅极结构30、32、34正下方的鳍状结构14、16、18内设有一通道区域62，栅极结构30、32、34、36、38、40、42、44上方设有一层间介电层64以及多个接触插塞66设于层间介电层64内并电连接源极区域58、漏极区域60以及栅极结构30、32、34。
在本实施例中，间隙壁56可为单一间隙壁或复合式间隙壁，例如可细部包含一偏位间隙壁以及一主间隙壁。其中偏位间隙壁与主间隙壁可包含相同或不同材料，且两者均可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。层间介电层64较佳包含氧化物，接触插塞66可包含例如钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等阻障层以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。
以本实施例制作N型TFET为例，各隧道场效应晶体管24、26、28中的源极区域58较佳掺杂有第一导电型式的掺质例如硼离子，使源极区域58具有P型导电型态，且源极区域58较佳包含例如锗化硅(SiGe)等外延层。通道区域62以及漏极区域60则都掺杂有第二导电型式的掺质例如磷离子或砷离子，而具有N型导电型态，同时漏极区域60较佳包含例如磷化硅(SiP)等外延层。当N型TFET作动时，较佳将源极区域58接地，并施加正电压于栅极结构30、32、34。
此外，在其他实施例中，若所制备的隧道场效应晶体管为P型TFET，则源极区域58中包含有N型导电型态，而通道区域62以及漏极区域60都包含有P型导电型态。当P型TFET作动时，较佳将源极区域58接地，并施加负电压于栅极结构30、32、34。
值得注意的是，本实施例各隧道场效应晶体管24、26、28两侧的隔离结构20、22较佳选用不同材料特性以及/或可依据不同制作工艺来完成，例如位于隧道场效应晶体管24、26、28两侧的隔离结构20、22可依据产品需求包含不同材料且不同深度的组合或相同材料且不同深度的组合，由此提升整个元件开启时的电流。以图2所公开的隧道场效应晶体管26为例，源极区域58左侧的隔离结构20以及漏极区域60右侧的隔离结构22较佳包含不同介电材料，其中隔离结构20较佳包含一拉伸应力材料例如氮化硅而隔离结构22则较佳包含氧化硅。
需注意的是，隔离结构20以及隔离结构22较佳为不同制作工艺阶段所形成的隔离结构，其中隔离结构20较佳为一般鳍状结构形成于基底12之后利用另一道蚀刻将鳍状结构分隔为两部分(例如鳍状结构14以及鳍状结构16)，然后于分隔的鳍状结构14、16之间填入介电材料所形成的单扩散隔离(single diffusion break,SDB)结构。隔离结构22则为分隔出所有鳍状结构14、16、18后环绕所有鳍状结构14、16、18周围的隔离结构。
从细部来看，由具有拉伸应力氮化硅所构成的隔离结构20主要包含一下半部68埋设于基底12或鳍状结构14、16内以及一上半部70设于下半部68上方，其中上半部70宽度小于下半部68宽度，而由不具应力的氧化硅所构成的隔离结构22上表面则较佳为一平坦面。从深度来看，隔离结构20的深度较佳大于隔离结构22的深度，或从另一角度来看隔离结构20的底部较佳低于隔离结构22的底部。
在本实施例中，隔离结构20的下半部68上表面虽较佳切齐隔离结构22上表面，但依据本发明其他实施例，下半部68上表面又可略高或略低于隔离结构22上表面，这些变化型均属本发明所涵盖的范围。此外隔离结构20上半部70上表面虽较佳切齐鳍状结构14、16上表面，但依据本发明其他实施例，上半部70上表面又可略高或略低于鳍状结构14、16上表面，这些变化型也均属本发明所涵盖的范围。
另外需注意的是，本实施例的隔离结构20正上方仅设置单一栅极结构38但隔离结构22上方则同时设置两颗栅极结构40、42，其中隔离结构20两侧侧壁较佳切齐正上方的栅极结构38的两侧侧壁，隔离结构22上的栅极结构40、42则仅有部分跨在隔离结构22上。
请继续参照图3，图3为本发明一实施例的隧道场效应晶体管的结构示意图。如图3所示，相较于图2实施例中隧道场效应晶体管26两侧的隔离结构20、22包含不同材料，本实施例隧道场效应晶体管26的源极区域58左侧的隔离结构72以及漏极区域60右侧的隔离结构22较佳包含相同介电材料，例如两者均包含氧化硅。
如同前述实施例所公开的隔离结构20，本实施例的隔离结构72在制作工艺上同样较佳在一般鳍状结构形成于基底之后利用另一道蚀刻将鳍状结构分隔为两部分(例如鳍状结构14以及鳍状结构16)，然后于分隔的鳍状结构14、16之间填入介电材料所形成的单扩散隔离(single diffusion break,SDB)结构。相较于前述隔离结构20是由具有拉伸应力的氮化硅所构成，本实施例所填入的材料较佳为氧化硅因此隔离结构72上表面较佳如隔离结构22般呈现一平坦面，且由于此隔离结构72是以分隔鳍状结构后再填入介电材料的方式所形成，因此其底部深度较佳如前述实施例般大于隔离结构22的底部深度。
此外在本实施例中，隔离结构72的上表面虽较佳切齐隔离结构22上表面，但依据本发明其他实施例，隔离结构72上表面又可略高或略低于隔离结构22上表面，这些变化型均属本发明所涵盖的范围。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (17)

1.一种隧道场效应晶体管，包含：
鳍状结构，设于基底上；
第一栅极结构，设于该鳍状结构上；
第一源极区域，具有第一导电型式设于该第一栅极结构一侧；
第一漏极区域，具有第二导电型式设于该第一栅极结构另一侧；
第四栅极结构，设于该鳍状结构上；
第二源极区域，具有该第一导电型式设于该第四栅极结构一侧；
第二漏极区域，具有该第二导电型式设于该第四栅极结构另一侧；
第一隔离结构，将该鳍状结构分隔为第一部分及第二部分，其中该第一栅极结构设于该第一部分上，该第四栅极结构设于该第二部分上，且该第一源极区域及该第二源极区域对称设于该第一隔离结构的二侧；以及
第二隔离结构，设于该漏极区域旁，其中该第一隔离结构以及该第二隔离结构包含不同材料以及不同深度，该第一隔离结构的底部低于该第二隔离结构的底部；
该第一隔离结构的上表面为中心区高于周边区的凸表面。
2.如权利要求1所述的隧道场效应晶体管，还包含通道区域，设于该第一栅极结构正下方。
3.如权利要求2所述的隧道场效应晶体管，其中该通道区域包含该第二导电型式。
4.如权利要求1所述的隧道场效应晶体管，还包含第二栅极结构，设于该第一隔离结构上方。
5.如权利要求1所述的隧道场效应晶体管，还包含第三栅极结构，设于该第二隔离结构上方。
6.如权利要求1所述的隧道场效应晶体管，其中该第一隔离结构包含一拉伸应力材料。
7.如权利要求6所述的隧道场效应晶体管，其中该第一隔离结构包含氮化硅。
8.如权利要求7所述的隧道场效应晶体管，其中该第一隔离结构包含：
下半部，设于该基底内；以及
上半部，设于该下半部上方，其中该上半部宽度小于该下半部宽度。
9.如权利要求1所述的隧道场效应晶体管，其中该第二隔离结构包含氧化硅。
10.如权利要求9所述的隧道场效应晶体管，其中该第二隔离结构上表面为一平坦面。
11.一种隧道场效应晶体管，包含：
鳍状结构，设于基底上；
第一栅极结构，设于该鳍状结构上；
第一源极区域，具有第一导电型式设于该第一栅极结构一侧；
第一漏极区域，具有第二导电型式设于该第一栅极结构另一侧；
第四栅极结构，设于该鳍状结构上；
第二源极区域，具有该第一导电型式设于该第四栅极结构一侧；
第二漏极区域，具有该第二导电型式设于该第四栅极结构另一侧；
第一隔离结构，将该鳍状结构分隔为第一部分及第二部分，其中该第一栅极结构设于该第一部分上，该第四栅极结构设于该第二部分上，且该第一源极区域及该第二源极区域对称设于该第一隔离结构的二侧；以及
第二隔离结构，设于该漏极区域旁，其中该第一隔离结构以及该第二隔离结构包含相同材料以及不同深度，该第一隔离结构的底部低于该第二隔离结构的底部；
该第一隔离结构的上表面为中心区高于周边区的凸表面。
12.如权利要求11所述的隧道场效应晶体管，还包含通道区域，设于该第一栅极结构正下方。
13.如权利要求12所述的隧道场效应晶体管，其中该通道区域包含该第二导电型式。
14.如权利要求11所述的隧道场效应晶体管，还包含第二栅极结构，设于该第一隔离结构上方。
15.如权利要求11所述的隧道场效应晶体管，还包含第三栅极结构，设于该第二隔离结构上方。
16.如权利要求11所述的隧道场效应晶体管，其中该第一隔离结构包含一拉伸应力材料。
17.如权利要求16所述的隧道场效应晶体管，其中该第一隔离结构包含氮化硅。
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