CN106340540B - 半导体元件及填补图案的方法 - Google Patents

半导体元件及填补图案的方法 Download PDF

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CN106340540B
CN106340540B CN201510392020.2A CN201510392020A CN106340540B CN 106340540 B CN106340540 B CN 106340540B CN 201510392020 A CN201510392020 A CN 201510392020A CN 106340540 B CN106340540 B CN 106340540B
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CN106340540A (zh
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洪庆文
黄志森
陈意维
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及填补图案的方法，该半导体元件包含：一基底，该基底上具有一单元区，该单元区中包含一第一边缘以及一第二边缘，且第一边缘及第二边缘均沿着一第一方向延伸；以及多个图案设于基底上并沿着第一方向延伸。其中该多个图案包含多个第一图案及多个第二图案，且最靠近第一边缘的第一图案的一者与最靠近第二边缘的第二图案的一者为不同图案。

Description

半导体元件及填补图案的方法
技术领域
本发明涉及一种半导体元件，尤其是涉及一种于基底上的一单元区中具有不对称图案的半导体元件。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
一般而言，半导体基底上设有多个晶体管元件的单位晶格区(unit cell region)或单元区中包含多种图案，例如鳍状结构晶体管中的栅极图案与接触插塞图案。其中每个单元区中最靠近边缘的图案均为对称设计，例如每个单元区中最靠近左边边缘的图案与最靠近右边边缘的图案均为相同图案。然而，此对称的设计在多个单元区拼凑起来时容易在单元区与单元区的交界处产生过多的空旷区域并影响元件轮廓的平整性。因此，如何改善此问题即为现今一重要课题。
发明内容
本发明优选实施例揭露一种半导体元件，包含：一基底，该基底上具有一单元区，该单元区中包含一第一边缘以及一第二边缘，且第一边缘及第二边缘均沿着一第一方向延伸；以及多个图案设于基底上并沿着第一方向延伸。其中该多个图案包含多个第一图案及多个第二图案，且最靠近第一边缘的第一图案的一者与最靠近第二边缘的第二图案的一者为不同图案。
本发明另揭露一种填补图案的方法。首先提供一基底，该基底上具有一单元区，然后形成多个主图案于基底上并位于单元区内，然后填入多个第一虚置图案于主图案旁，其中各第一虚置图案具有沿着X方向延伸的一第一长度以及沿着Y方向延伸的一第二长度，该第一长度介于2微米至5微米且该第二长度介于3微米至5微米。
附图说明
图1为本发明一实施例的一半导体元件的结构上示图；
图2为图1中沿着切线AA'的剖面示意图；
图3为本发明另一实施例的一半导体元件的上示图；
图4为本发明一实施例填补图案的方法示意图。
主要元件符号说明
12 基底 14 单元区
15 浅沟隔离 16 第一边缘
18 第二边缘 20 NMOS区
22 PMOS区 24 图案
26 鳍状结构 28 栅极结构
30 栅极图案 32 接触插塞
34 接触插塞图案 36 第一端
38 第二端 40 掺杂区
42 层间介电层 44 高介电常数介电层
46 功函数金属层 48 低阻抗金属层
50 主图案 52 第一虚置图案
54 第二虚置图案 56 第三虚置图案
S1 最小间距
具体实施方式
请参照图1至图2，图1为本发明一实施例的一半导体元件的结构上示图，图2为图1中沿着切线AA'的剖面示意图。如图1至图2所示，本发明的半导体元件主要包含一基底12，例如一硅晶片或半导体材料所构成的硅基底，其中基底12上定义有一单位晶格区(unitcell region)或单元区(cell region)14，单元区14具有左右两个边缘，例如一第一边缘16与一第二边缘18，且第一边缘16与第二边缘18均沿着一第一方向延伸。
单元区14中定义有一N型金属氧化物半导体(NMOS)区20与一P型金属氧化物半导体(PMOS)区22，其中NMOS区20与PMOS区22均具有多个图案24沿着第一方向延伸以及多个鳍状结构26沿着一第二方向延伸且与部分图案24交错，其中第一方向例如Y方向而第二方向例如X方向。在本实施例中，图案24主要包含两种图案彼此平行交错排列，例如场效晶体管元件中由栅极结构28所构成的栅极图案30以及由接触插塞32所构成的接触插塞图案34，但不局限于此。
更具体而言，单元区14中最靠近第一边缘16的图案与最靠近第二边缘18的图案优选为不同图案。以图1所揭露的上示图为例，最靠近单元区14第一边缘16的图案为接触插塞图案34而最靠近单元区14第二边缘18的图案则为栅极图案30。需注意的是，本实施例虽选择于左边最靠近第一边缘16设置接触插塞图案34而于右边最靠近第二边缘18设置栅极图案30，但不局限于此排列方式，又可调整图案24所设置的顺序，例如可选择于左边最靠近第一边缘16设置栅极图案30而于右边最靠近第二边缘18设置接触插塞图案34，此实施例也属本发明所涵盖的范围。
其次，本实施例最靠近左边第一边缘16的接触插塞图案34虽直接切齐第一边缘16且最靠近右边第二边缘18的栅极图案30不切齐第二边缘18，但不排除使最左边的接触插塞图案34不切齐第一边缘16且两者之间插入一间隙(gap)，使最左边的接触插塞图案34与最右边的栅极图案30同时切齐第一边缘16与第二边缘18，或使最左边的接触插塞图案34与最右边的栅极图案30同时不切齐第一边缘16与第二边缘18，这些实施例均属本发明所涵盖的范围。
另外，本实施例单元区14中的两种图案24优选为交错设置，例如将栅极图案30与接触插塞图案34以沿着第一方向相互交错的方式排列。以图案24与鳍状结构26之间的关系来看，各鳍状结构26包含一第一端36与一第二端38，且由接触第一端36的图案24至第一边缘16之间的图案数量优选不同于由接触第二端38的图案24至第二边缘18之间的图案数量。以图1所揭露的上示图为例，由接触第一端36的图案24至第一边缘16之间的图案数量为四个图案，包括两个栅极图案30与两个接触插塞图案34，而由接触第二端38的图案24至第二边缘18的图案数量则为三个图案，包括两个栅极图案30与一个接触插塞图案34。
由本实施例半导体元件的细部结构来看，如图1的上示图与图2的剖视图所示，本发明的半导体元件包含多个鳍状结构26设于基底12上、多个栅极结构28设于基底12上且部分栅极结构28同时横跨于鳍状结构26上、多个掺杂区40设于栅极结构28两侧的鳍状结构26中做为源极/漏极区域、一层间介电层42设于基底12上并覆盖栅极结构28以及多个接触插塞32设于鳍状结构26与浅沟隔离15上，其中设于浅沟隔离15上而非鳍状结构26上的接触插塞32优选作为虚置接触插塞。另外虽未绘示于图2中，半导体元件又可包含一间隙壁(图未示)设于栅极结构28侧壁，一外延层(图未示)与硅化金属层(图未示)设于栅极结构28两侧的鳍状结构26中，以及一接触洞蚀刻停止层(图未示)设于基底12表面并覆盖栅极结构28。
栅极结构28的制作方式可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先栅极介电层(high-k first)制作工艺以及后栅极制作工艺的后栅极介电层(high-k last)制作工艺等方式制作完成。以本实施例的先栅极介电层制作工艺为例，栅极结构28可包含一介质层(图未示)设于基底12上、一高介电常数介电层44设于介质层上、一功函数金属层46设于高介电常数介电层44上以及一低阻抗金属层48设于功函数金属层46上，其中功函数金属层46优选为U型。
高介电常数介电层44可以是一层或多层的结构，其介电常数大致大于20，而本实施例的高介电常数介电层44可包含一金属氧化物层，例如一稀土金属氧化物层，且可选自由氧化铪(hafnium oxide,HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,AlO)、氧化镧(lanthanum oxide,La2O3)、铝酸镧(lanthanum aluminum oxide,LaAlO)、氧化钽(tantalum oxide,Ta2O3)、氧化锆(zirconium oxide,ZrO2)、硅酸锆氧化合物(zirconiumsilicon oxide,ZrSiO)、锆酸铪(hafnium zirconium oxide,HfZrO)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(lead zirconate titanate,PbZrxTi1-xO3,PZT)以及钛酸钡锶(barium strontium titanate,BaxSr1-xTiO3,BST)等所构成的群组。
在本实施例中，功函数金属层46优选用以调整形成栅极结构28的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层46可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层46可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层46与低阻抗金属层48之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层48则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合。由于上述具有金属栅极的结构是此领域者所熟知技术，在此不另加赘述。
接触插塞32可包含一选自钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等所构成的阻障层，以及一选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。
接着请参照图3，图3为本发明另一实施例的一半导体元件的上示图。如图中所示，半导体元件的基底上可定义有多个如图1所揭露的单元区14，其中各单元区14如同图1的实施例般具有一第一边缘16与一第二边缘18，多个图案24沿着第一方向例如Y方向延伸，多个鳍状结构26沿着一第二方向例如X方向延伸且与部分图案24交错，且最靠近第一边缘16的图案与最靠近第二边缘18的图案优选为不同图案。在本实施例中，最靠近单元区14第一边缘16的图案为接触插塞图案34而最靠近单元区14第二边缘18的图案为栅极图案30。整体来看，任两相邻的单元区14之间的边缘，例如第一边缘16或第二边缘18的左右两侧分别为不同图案。
接着请参照图4，图4为本发明一实施例填补图案的方法示意图。如图4所示，首先提供一基底12，且基底12上定义有一单元区14，然后形成多个主图案50于基底12上并位于单元区14内，其中主图案50可包含前述鳍状结构晶体管元件中的由栅极结构28所构成的栅极图案30或由接触插塞32所构成的接触插塞图案34，但不局限于此。
接着填入多个第一虚置图案52于主图案50旁，其中各第一虚置图案52不与主图案50相接触且各第一虚置图案52均彼此接触，且各第一虚置图案52具有沿着X方向延伸的一第一长度以及沿着Y方向延伸的一第二长度。在本实施例中，第一虚置图案的第一长度介于2微米至5微米且第二长度介于3微米至5微米。
迨填入第一虚置图案52后可选择性填入多个第二虚置图案54于第一虚置图案52旁，其中各第二虚置图案54相接触各第一虚置图案52但不与主图案50相接触，且各第二虚置图案54包含沿着X方向延伸的一第三长度以及沿着Y方向延伸的一第四长度。在本实施例中，第二虚置图案54的第三长度介于0.8微米至1.2微米且第四长度介于1微米至2微米。
最后，迨填入第二虚置图案54后若仍有多于空间可再选择性填入多个第三虚置图案56于第二虚置图案54旁，其中各第三虚置图案56相接触各第二虚置图案54但不与主图案50相接触，且各第三虚置图案56包含沿着X方向延伸的一第五长度以及沿着Y方向延伸的一第六长度。在本实施例中，第三虚置图案56的第五长度介于0.8微米至1.2微米而第六长度则介于0.6微米至1微米。另外需注意的是，无论第一虚置图案52、第二虚置图案54或第三虚置图案56与主图案50之间可具有一最小间距S1，其中最小间距S1优选介于0.2微米至0.8微米。
综上所述，本发明优选揭露一种半导体元件结构，其主要于基底上的一单元区中设置多个图案，且最靠近单元区的第一边缘的图案与最靠近第二边缘的图案优选为不同图案。依据本发明的优选实施例，单元区中所设置的图案主要包含栅极图案与接触插塞图案，其中栅极图案与接触插塞图案均沿着第一边缘与第二边缘的方向相互交错排列。依据本发明的优选实施例，以上述不对称方式将栅极图案与接触插塞图案排列于单元区可避免单元区与单元区交界处产生过多的空旷区域，进而提升元件轮廓的平整性。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (5)

1.一种半导体元件，包含：
基底，该基底上具有单元区，该单元区中包含第一边缘以及第二边缘，该第一边缘及该第二边缘均沿着一第一方向延伸；
多个图案设于该基底上并沿着该第一方向延伸，其中该多个图案包含多个第一图案及多个第二图案，且最靠近该第一边缘的该多个第一图案的一者与最靠近该第二边缘的该多个第二图案的一者为不同图案；以及
多个鳍状结构，沿着一第二方向延伸且与部分该多个图案交错，其中各该鳍状结构包含第一端与第二端，且由接触该第一端的图案至该第一边缘之间的图案数量不同于由接触该第二端的图案至该第二边缘之间的图案数量。
2.如权利要求1所述的半导体元件，其中该多个图案包含栅极图案及接触插塞图案。
3.如权利要求1所述的半导体元件，其中该多个第一图案包含栅极图案且该多个第二图案包含接触插塞图案。
4.如权利要求1所述的半导体元件，其中该多个第一图案包含接触插塞图案且该多个第二图案包含栅极图案。
5.如权利要求1所述的半导体元件，其中该多个第一图案及该多个第二图案交错设置。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9818875B1 (en) * 2016-10-17 2017-11-14 International Business Machines Corporation Approach to minimization of strain loss in strained fin field effect transistors
CN109390338B (zh) * 2017-08-08 2021-06-22 联华电子股份有限公司 互补式金属氧化物半导体元件及其制作方法
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Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6081272A (en) * 1997-09-30 2000-06-27 Intel Corporation Merging dummy structure representations for improved distribution of artifacts in a semiconductor layer
JP4836304B2 (ja) * 1999-12-15 2011-12-14 ルネサスエレクトロニクス株式会社 半導体装置
US6563148B2 (en) * 2000-04-19 2003-05-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with dummy patterns
JP2002158278A (ja) * 2000-11-20 2002-05-31 Hitachi Ltd 半導体装置およびその製造方法ならびに設計方法
JP3806016B2 (ja) * 2000-11-30 2006-08-09 富士通株式会社 半導体集積回路
JP2003324149A (ja) * 2002-04-26 2003-11-14 Nec Electronics Corp ダミーパターンの自動発生方法
US6961915B2 (en) * 2002-11-06 2005-11-01 Lsi Logic Corporation Design methodology for dummy lines
US7105894B2 (en) * 2003-02-27 2006-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts to semiconductor fin devices
JP4620942B2 (ja) * 2003-08-21 2011-01-26 川崎マイクロエレクトロニクス株式会社 半導体集積回路のレイアウト方法、そのレイアウト構造、およびフォトマスク
JP4248451B2 (ja) * 2004-06-11 2009-04-02 パナソニック株式会社 半導体装置およびそのレイアウト設計方法
US7667332B2 (en) * 2004-11-05 2010-02-23 Kabushiki Kaisha Toshiba Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program product
US20060228862A1 (en) * 2005-04-06 2006-10-12 International Business Machines Corporation Fet design with long gate and dense pitch
KR100665850B1 (ko) * 2005-07-22 2007-01-09 삼성전자주식회사 고집적 반도체 메모리 소자용 모오스 트랜지스터들의배치구조 및 그에 따른 배치방법
JP2007141971A (ja) * 2005-11-15 2007-06-07 Matsushita Electric Ind Co Ltd 半導体集積回路の設計方法
JP2007311500A (ja) * 2006-05-17 2007-11-29 Nec Electronics Corp 半導体装置の設計方法及びこれを実行するプログラム
KR100808605B1 (ko) * 2007-05-31 2008-02-29 주식회사 하이닉스반도체 주변회로지역의 반도체 소자
KR20090064747A (ko) * 2007-12-17 2009-06-22 주식회사 동부하이텍 멀티 핑거 타입의 반도체 소자
US9646958B2 (en) * 2010-03-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuits including dummy structures and methods of forming the same
US8597860B2 (en) * 2011-05-20 2013-12-03 United Microelectronics Corp. Dummy patterns and method for generating dummy patterns
US8946782B2 (en) * 2012-04-19 2015-02-03 International Business Machines Corporation Method for keyhole repair in replacement metal gate integration through the use of a printable dielectric
US9337318B2 (en) * 2012-10-26 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with dummy gate on non-recessed shallow trench isolation (STI)
KR102219096B1 (ko) * 2014-08-06 2021-02-24 삼성전자주식회사 성능 개선을 위한 패턴 구조가 적용된 반도체 장치
JP6449082B2 (ja) * 2014-08-18 2019-01-09 ルネサスエレクトロニクス株式会社 半導体装置
US9740092B2 (en) * 2014-08-25 2017-08-22 Globalfoundries Inc. Model-based generation of dummy features

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