TW202347452A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TW202347452A
TW202347452A TW111130976A TW111130976A TW202347452A TW 202347452 A TW202347452 A TW 202347452A TW 111130976 A TW111130976 A TW 111130976A TW 111130976 A TW111130976 A TW 111130976A TW 202347452 A TW202347452 A TW 202347452A
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李國興
林俊賢
邱永振
薛勝元
白啟宏
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聯華電子股份有限公司
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Abstract

本發明揭露一種製作半導體元件的方法，其主要先提供一基底包含一電阻區，然後形成第一閘極結構於該電阻區，形成第一層間介電層環繞第一閘極結構，將該第一閘極結構轉換為第一金屬閘極且第一金屬閘極包含一閘極電極設於基底上以及一硬遮罩設於閘極電極上，之後再形成一電阻於第一金屬閘極上。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種整合高壓元件、低壓元件以及電阻的方法。
以目前的半導體技術水準，業界已能將控制電路、記憶體、低壓操作電路以及高壓操作電路及元件同時整合製作在單一晶片上，藉此降低成本，同時提高操作效能，其中如垂直擴散金氧半導體(vertical double-diffusion metal-oxide-semiconductor, VDMOS)、絕緣閘極雙載子電晶體(insulated gate bipolar transistor, IGBT)以及橫向擴散金氧半導體(lateral-diffusion metal-oxide-semiconductor, LDMOS)等製作在晶片內的高壓元件，由於具有較佳的切換效率(power switching efficiency)，因此又較常被應用。如熟習該項技藝者所知，前述的高壓元件往往被要求能夠承受較高的崩潰電壓，並且能在較低的阻值下操作。
另外隨著元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor, Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering, DIBL)效應，並可以抑制短通道效應(short channel effect, SCE)。再者，由於鰭狀場效電晶體元件在同樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可藉由調整閘極的功函數而加以調控。
然而隨著元件尺寸持續縮小下現行高壓元件、鰭狀結構場效電晶體元件以及如電阻等被動元件的整合上仍存在許多挑戰，例如漏電流以及崩潰電壓的控制等等。因此，如何改良現有高壓元件架構即為現今一重要課題。
本發明一實施例揭露一種製作半導體元件的方法，其主要先提供一基底包含一電阻區，然後形成第一閘極結構於該電阻區，形成第一層間介電層環繞第一閘極結構，將該第一閘極結構轉換為第一金屬閘極且第一金屬閘極包含一閘極電極設於基底上以及一硬遮罩設於閘極電極上，之後再形成一電阻於第一金屬閘極上。
本發明另一實施利揭露一種半導體元件，其主要包含一基底包含一電阻區，第一閘極結構設於電阻區且第一閘極結構包含一閘極電極設於基底上以及一硬遮罩設於閘極電極上，一層間介電層環繞第一閘極結構以及一電阻設於第一閘極結構上。
請參照第1圖至第6圖，第1圖至第6圖為本發明一實施例製作半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上定義有三個或三個以上的電晶體區，例如包括一電阻區14、一低壓區16以及一高壓區18，其中電阻區14較佳用來製備高壓電阻，低壓區16較佳用來製備鰭狀結構場效電晶體，而高壓區18則用來製備高壓元件。在本實施例中，電阻區14、低壓區16以及高壓區18中可包含相同導電型式或不同導電型式之電晶體區，例如各為PMOS電晶體區以及/或NMOS電晶體區。
然後於低壓區16的基底12上形成複數個鰭狀結構20以及於高壓區18的基底12上形成基座22。依據本發明之較佳實施例，鰭狀結構20與基座22較佳透過側壁圖案轉移(sidewall image transfer, SIT)技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層或軸心體(mandrel)於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層的各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構20與基座22之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成鰭狀結構20與基座22。另外，鰭狀結構20與基座22之形成方式另也可以是先製作一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構20與基座22。這些形成鰭狀結構20與基座22的實施例均屬本發明所涵蓋的範圍。
然後進行一可流動式化學氣相沉積(flowable chemical vapor deposition, FCVD)製程形成一由氧化矽所構成的絕緣層28於鰭狀結構20與基座22上並填滿鰭狀結構20與基座22之間的凹槽，再進行一平坦化製程例如利用化學機械研磨(chemical mechanical polishing, CMP)去除部分絕緣層28使鰭狀結構20頂表面切齊絕緣層28頂表面。
隨後進行一離子佈植製程於高壓區18的基座22兩側內形成摻雜區24，其中摻雜區24較佳作為後續高壓元件的輕摻雜汲極。接著利用一圖案化遮罩(圖未示)為遮罩進行一蝕刻製程去除高壓區18的部分基座22形成凹槽(圖未示)，進行一氧化物成長製程或更具體而言一快速熱氧化(rapid thermal oxidation, RTO)製程以形成一由氧化矽所構成的閘極介電層26於高壓區18的基座22上，再完全去除圖案化遮罩。隨後進行一回蝕刻製程去除電阻區14、低壓區16以及高壓區18的部分絕緣層28，使剩餘的絕緣層28頂表面略低於低壓區16的鰭狀結構20頂表面以及高壓區18的基座22頂表面形成淺溝隔離(shallow trench isolation, STI)30。
接著可於電阻區14、低壓區16以及高壓區18的鰭狀結構20與基座22上分別形成閘極結構32、34、36、38、40、42或虛置閘極。在本實施例中，閘極結構32、34、36、38、40、42的製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先高介電常數介電層(high-k first)製程或後閘極製程之後高介電常數介電層(high-k last)製程等方式製作完成。
以本實施例之後高介電常數介電層製程為例，可先依序形成一由氧化矽所構成的閘極介電層44、一由多晶矽所構成的閘極材料層46以及一由氮化矽所構成的硬遮罩48於淺溝隔離30、鰭狀結構20以及基座22上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分硬遮罩48、部分閘極材料層46以及部分閘極介電層44，然後剝除圖案化光阻，以於各區域的基底12上形成由閘極介電層44、圖案化之閘極材料層46以及圖案化之硬遮罩48所構成的閘極結構32、34、36、38、40、42，其中圖案化之閘極材料層46較佳成為各區域的閘極電極。
如第2圖所示，隨後分別在閘極結構32、34、36、38、40、42側壁形成至少一側壁子50。在本實施例中，側壁子50可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子(圖未示)以及一主側壁子(圖未示)，偏位側壁子與主側壁子較佳包含不同材料，且兩者均可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組，但不侷限於此。
進行一乾蝕刻及/或濕蝕刻製程，沿著低壓區16的側壁子50向下單次或多次蝕刻鰭狀結構20，以於閘極結構38兩側的鰭狀結構20中形成凹槽(圖未示)。接著進行一選擇性磊晶成長(selective epitaxial growth, SEG)製程，以於凹槽中形成磊晶層52。需注意的是，本實施例僅於低壓區16的閘極結構38兩側形成磊晶層52但電阻區14與高壓區18均不形成任何磊晶層。
從剖面來看，低壓區16的磊晶層52於本實施例中雖以矩形為例，但又可與凹槽具有相同的截面形狀，如圓弧、六邊形(hexagon；又稱sigma Σ)或八邊形(octagon)等截面形狀。於本發明較佳實施例中，磊晶層52根據不同之金氧半導體(MOS)電晶體類型而可以具有不同的材質，舉例來說，若該金氧半導體電晶體為一P型電晶體(PMOS)時，磊晶層52可選擇包含矽化鍺(SiGe)、矽化鍺硼(SiGeB)或矽化鍺錫(SiGeSn)。而於本發明另一實施例中，若該金氧半導體電晶體為一N型電晶體(NMOS)時，磊晶層52可選擇包含碳化矽(SiC)、碳磷化矽(SiCP)或磷化矽(SiP)。此外，選擇性磊晶製程可以用單層或多層的方式來形成，且其異質原子(例如鍺原子或碳原子)亦可以漸層的方式改變，但較佳是使磊晶層52的表面較淡或者無鍺原子，以利後續金屬矽化物層的形成。
隨後可進行一道或一道以上離子佈植製程，以於高壓區18閘極結構42兩側的基座22內形成源極/汲極區域54。依據本發明一實施例，又可選擇性於低壓區16中磊晶層52的一部分或全部形成源極/汲極區域54。在一實施例中，低壓區16中源極/汲極區域54的形成亦可同步(in-situ)於選擇性磊晶成長製程進行，例如金氧半導體是PMOS時，形成矽化鍺磊晶層、矽化鍺硼磊晶層或矽化鍺錫磊晶層，可以伴隨著注入P型摻質；或是當金氧半導體是NMOS時，形成矽化碳磊晶層、矽化碳磷磊晶層或矽化磷磊晶層，可以伴隨著注入N型摻質。藉此可省略後續利用額外離子佈植步驟形成P型/N型電晶體之源極/汲極區域54。此外在另一實施例中，源極/汲極區域54的摻質亦可以漸層的方式形成。
然後如第3圖所示，可選擇性形成一由氮化矽所構成的接觸洞蝕刻停止層(contact etch stop layer, CESL)(圖未示)於基底12上並覆蓋電阻區14、低壓區16以及高壓區18的閘極結構32、34、36、38、40、42，再形成一層間介電層56於接觸洞蝕刻停止層上。接著進行一平坦化製程，例如利用化學機械研磨製程去除部分層間介電層56及部分接觸洞蝕刻停止層使硬遮罩48頂表面與層間介電層56頂表面齊平。
隨後進行一金屬閘極置換製程將電阻區14、低壓區16以及高壓區18的各閘極結構32、34、36、38、40、42轉換為金屬閘極。例如可先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide, NH 4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide, TMAH)等蝕刻溶液來去除硬遮罩48、閘極材料層46甚至閘極介電層44以於層間介電層56中形成凹槽(圖未示)。之後依序形成一高介電常數介電層62以及至少包含功函數金屬層64與低阻抗金屬層66的導電層於凹槽內，並再搭配進行一平坦化製程使U形高介電常數介電層62、U形功函數金屬層64與低阻抗金屬層66的表面與層間介電層56表面齊平，其中高介電常數介電層62、功函數金屬層64與低阻抗金屬層66較佳一同各電晶體或各元件的閘極電極。
在本實施例中，高介電常數介電層62包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide, HfO 2)、矽酸鉿氧化合物(hafnium silicon oxide, HfSiO 4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride, HfSiON)、氧化鋁(aluminum oxide, Al 2O 3)、氧化鑭(lanthanum oxide, La 2O 3)、氧化鉭(tantalum oxide, Ta 2O 5)、氧化釔(yttrium oxide, Y 2O 3)、氧化鋯(zirconium oxide, ZrO 2)、鈦酸鍶（strontium titanate oxide, SrTiO 3）、矽酸鋯氧化合物(zirconium silicon oxide, ZrSiO 4)、鋯酸鉿(hafnium zirconium oxide, HfZrO 4)、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi 2Ta 2O 9, SBT)、鋯鈦酸鉛(lead zirconate titanate,  PbZr xTi 1-xO 3, PZT)、鈦酸鋇鍶(barium strontium titanate, Ba xSr 1-xTiO 3, BST)、或其組合所組成之群組。
功函數金屬層64較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層64可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層64可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層64與低阻抗金屬層66之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層66則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。
接著如第4圖所示，可去除部分高介電常數介電層62、部分功函數金屬層64與部分低阻抗金屬層66形成凹槽(圖未示)，然後再填入一硬遮罩68於凹槽內並使硬遮罩68與層間介電層56表面齊平，其中硬遮罩68較佳包含氮化矽，但又可選自由氧化矽、氮氧化矽以及氮碳化矽所構成的群組。
隨後如第5圖所示，先形成另一層間介電層70於閘極結構32、34、36、38、40、42與層間介電層56上，再依序形成一金屬層72於層間介電層70表面及一遮蓋層74於金屬層72上。然後進行一微影曁蝕刻製程去除電阻區14以外的部分遮蓋層74與部分金屬層72，使被圖案化的金屬層72側壁切齊遮蓋層74側壁並形成一電阻元件。在本實施例中，金屬層72較佳包含金屬氮化物如氮化鈦而遮蓋層74則較佳包含介電材料如氮化矽，其中金屬層72的厚度較佳約40埃至60埃或更佳約50埃而遮蓋層厚度則約90埃至110埃或最佳約100埃。
之後如第6圖所示，形成另一層間介電層76於層間介電層70上，再進行一圖案轉移製程，例如可利用一圖案化遮罩去除閘極結構32、34、36、38、40、42旁的部分的層間介電層56、70、76包括電阻區14的部分層間介電層76、部分遮蓋層74、部分金屬層72、部分層間介電層70以及部分層間介電層56、低壓區16的部分層間介電層56、70、76以及高壓區18的部分層間介電層56、70、76以形成複數個接觸洞(圖未示)並暴露出低壓區16與高壓區18的源極/汲極區域54。然後再於各接觸洞中填入所需的導電材料，例如包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等的阻障層材料以及選自鎢(W)、銅(Cu)、鋁(Al)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合的低阻抗金屬層。之後進行一平坦化製程，例如以化學機械研磨去除部分導電材料以分別形成接觸插塞78於各接觸洞內電連接源極/汲極區域54以及/或閘極結構34。至此即完成本發明較佳實施例一半導體元件的製作。
請再參照第6圖，第6圖揭露本發明一實施例之一種半導體元件之結構示意圖，其主要包含一電阻設於電阻區14、至少一鰭狀結構場效電晶體設於低壓區16以及一高壓元件設於高壓區18，其中電阻區14、低壓區16以及高壓區18上分別設有閘極結構32、34、36、38、40、42且各閘極結構32、34、36、38、40、42頂表面如硬遮罩68頂表面較佳相互切齊。
從細部來看電阻區14的電阻元件主要包含一金屬層72設於層間介電層70表面以及一遮蓋層74設於金屬層72上，其中金屬層72側壁較佳切齊遮蓋層74側壁，金屬層72較佳包含金屬氮化物如氮化鈦而遮蓋層74則較佳包含介電材料如氮化矽，金屬層72的厚度較佳約40埃至60埃或更佳約50埃而遮蓋層厚度則約90埃至110埃或最佳約100埃。
此外電阻元件的金屬層72正下方設有一閘極結構32或虛置閘極位於淺溝隔離30上，金屬層72與閘極結構32之間設有層間介電層70使兩者不直接接觸，金屬層72底表面至閘極結構32頂表面之間的距離可約金屬層72本身厚度的兩倍、三倍、四倍甚至五倍，金屬層72與遮蓋層74較佳包含相同寬度，金屬層72寬度較佳大於閘極結構32寬度，金屬層72寬度可大於閘極結構32寬度一倍以上如兩倍甚至三倍但較佳不超過三倍。
另外電阻區14中又設有接觸插塞78貫穿遮蓋層74與金屬層72並深入層間介電層70以及層間介電層56內，其中接觸插塞78設於閘極結構32兩側且兩者之間不接觸，閘極結構32側壁至接觸插塞78側壁之間的距離較佳介於20奈米至40奈米或最佳30奈米，接觸插塞78底表面雖略低於閘極結構32頂表面例如低於硬遮罩68頂表面並切齊閘極電極如U形高介電常數介電層62、U形功函數金屬層64與低阻抗金屬層66頂表面，但不侷限於此，依據本發明其他實施例接觸插塞78底表面又可切齊或略高於閘極結構32頂表面但仍貫穿遮蓋層74與金屬層72並埋設於層間介電層70內。此外電阻區14中的接觸插塞78頂表面較佳切齊低壓區16與高壓區18中的接觸插塞78頂表面，電阻區14中的接觸插塞78底表面可切齊連接閘極結構34的接觸插塞78底表面但高於其他接觸插塞78底表面。
請再參照第7圖，第7圖揭露本發明一實施例之一種半導體元件之結構示意圖。如第7圖所示，相較於前述實施例中僅於電阻元件的金屬層72正下方設置閘極結構32但貫穿金屬層72的兩個接觸插塞78正下方並無任何閘極結構，本發明又可選擇於兩個接觸插塞78正下方的淺溝隔離30上也分別設置閘極結構80接觸接觸插塞78，其中閘極結構80較佳與閘極結構32、34、36、38、40、42一同形成因此其頂表面較佳切齊閘極結構32、34、36、38、40、42頂表面。
請再參照第8圖，第8圖揭露本發明一實施例之一種半導體元件之結構示意圖。如第8圖所示，相較於第6圖實施例中僅於電阻元件的金屬層72正下方設置單一一個閘極結構32，本發明另一實施例又可將金屬層72正下方的閘極結構32分隔為多個閘極結構32，其中閘極結構32之間可具有相同或不同寬度，且閘極結構32頂表面較佳切齊閘極結構34、36、38、40、42頂表面。此外本實施例中貫穿金屬層72的兩個接觸插塞78正下方雖無任何閘極結構，但接觸插塞78兩側的電阻區14內又可分別設置額外的閘極結構82提升整個區域的均勻性。由於閘極結構82較佳與閘極結構32、34、36、38、40、42一同形成因此閘極結構82頂表面較佳切齊閘極結構32、34、36、38、40、42頂表面。
請再參照第9圖，第9圖揭露本發明一實施例之一種半導體元件之結構示意圖。如第9圖所示，本發明除了可如第8圖於金屬層72正下方設置複數個閘極結構32以及接觸插塞78兩側的電阻區14內設置閘極結構82外，接觸插塞78正下方又可再設置閘極結構80接觸接觸插塞78，此變化型也屬本發明所涵蓋的範圍。
一般而言，現行整合高電阻元件、低壓元件以及高壓元件等元件時均僅會於低壓區與高壓區的基底上設置閘極結構如金屬閘極但電阻元件正下方的基底上則無任何閘極結構。換句話說，電阻區中的電阻元件較佳懸空設於層間介電層內且電阻元件正下方僅設有層間介電層但無任何閘極結構或金屬導線。由於現行設計不利於電阻元件正下方的均勻性(uniformity)，因此本發明主要於低壓區與高壓區形成金屬閘極時同樣於電阻區中也設置相同的金屬閘極，其中電阻區中的金屬閘極具有硬遮罩，電阻區的金屬閘極頂表面較佳切齊低壓區與高壓區的金屬閘極頂表面，且電阻區中的金屬閘極寬度略低於正上方電阻元件如金屬層72與遮蓋層74寬度。依據本發明之較佳實施例，依據此配置方式可有效改善電阻區中因金屬閘極密度不足影響元件效能的問題。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底 14:電阻區 16:低壓區 18:高壓區 20:鰭狀結構 22:基座 24:摻雜區 26:閘極介電層 28:絕緣層 30:淺溝隔離 32:閘極結構 34:閘極結構 36:閘極結構 38:閘極結構 40:閘極結構 42:閘極結構 44:閘極介電層 46:閘極材料層 48:硬遮罩 50:側壁子 52:磊晶層 54:源極/汲極區域 56:層間介電層 62:高介電常數介電層 64:功函數金屬層 66:低阻抗金屬層 68:硬遮罩 70:層間介電層 72:金屬層 74:遮蓋層 76:層間介電層 78:接觸插塞 80:閘極結構 82:閘極結構
第1圖至第6圖為本發明一實施例製作半導體元件之方法示意圖。 第7圖為本發明一實施例之一種半導體元件之結構示意圖。 第8圖為本發明一實施例之一種半導體元件之結構示意圖。 第9圖為本發明一實施例之一種半導體元件之結構示意圖。
12:基底
14:電阻區
16:低壓區
18:高壓區
20:鰭狀結構
22:基座
24:摻雜區
26:閘極介電層
28:絕緣層
30:淺溝隔離
32:閘極結構
34:閘極結構
36:閘極結構
38:閘極結構
40:閘極結構
42:閘極結構
44:閘極介電層
50:側壁子
52:磊晶層
54:源極/汲極區域
56:層間介電層
62:高介電常數介電層
64:功函數金屬層
66:低阻抗金屬層
68:硬遮罩
70:層間介電層
72:金屬層
74:遮蓋層
76:層間介電層
78:接觸插塞

Claims (20)

  1. 一種製作半導體元件的方法，其特徵在於，包含： 提供一基底包含一電阻區； 形成一第一閘極結構於該電阻區： 形成一第一層間介電層環繞該第一閘極結構； 將該第一閘極結構轉換為第一金屬閘極，其中該第一金屬閘極包含： 一閘極電極設於該基底上；以及 一硬遮罩設於該閘極電極上； 形成一電阻於該第一金屬閘極上。
  2. 如申請專利範圍第1項所述之方法，其中該基底包含一低壓區以及一高壓區，該方法包含： 形成該第一閘極結構於該電阻區、一第二閘極結構於該低壓區以及一第三閘極結構於該高壓區； 形成該第一層間介電層環繞該第一閘極結構、該第二閘極結構以及該第三閘極結構； 將該第一閘極結構、該第二閘極結構以及該第三閘極結構轉換為第一金屬閘極、第二金屬閘極以及第三金屬閘極； 形成一第二層間介電層於該第一金屬閘極、該第二金屬閘極以及該第三金屬閘極上； 形成該電阻於該電阻區之該第二層間介電層上；以及 形成第一接觸插塞與第二接觸插塞於該電阻兩側。
  3. 如申請專利範圍第2項所述之方法，其中該第一閘極結構頂表面切齊該第二閘極結構頂表面。
  4. 如申請專利範圍第2項所述之方法，其中該第一閘極結構頂表面切齊該第三閘極結構頂表面。
  5. 如申請專利範圍第2項所述之方法，其中形成該電阻包含： 形成一金屬層於該第二層間介電層上；以及 形成一遮蓋層於該金屬層上。
  6. 如申請專利範圍第5項所述之方法，其中該金屬層側壁切齊該遮蓋層側壁。
  7. 如申請專利範圍第5項所述之方法，其中該金屬層包含氮化鈦。
  8. 如申請專利範圍第2項所述之方法，另包含形成該第一接觸插塞並穿過該電阻。
  9. 如申請專利範圍第2項所述之方法，其中該第一閘極結構設於該第一接觸插塞以及該第二接觸插塞之間。
  10. 如申請專利範圍第1項所述之方法，其中該第一閘極結構寬度小於該電阻寬度。
  11. 一種半導體元件，其特徵在於，包含： 一基底包含一電阻區； 一第一閘極結構設於該電阻區，其中該第一閘極結構包含： 一閘極電極設於該基底上；以及 一硬遮罩設於該閘極電極上； 一層間介電層環繞該第一閘極結構；以及 一電阻設於該第一閘極結構上。
  12. 如申請專利範圍第11項所述之半導體元件，其中該基底包含一低壓區以及一高壓區，該半導體元件包含： 該第一閘極結構設於該電阻區、一第二閘極結構設於該低壓區以及一第三閘極結構設於該高壓區； 該第一層間介電層環繞該第一閘極結構、該第二閘極結構以及該第三閘極結構； 一第二層間介電層設於該第一金屬閘極、該第二金屬閘極以及該第三金屬閘極上； 該電阻設於該電阻區之該第二層間介電層上；以及 第一接觸插塞與第二接觸插塞設於該電阻兩側。
  13. 如申請專利範圍第12項所述之半導體元件，其中該第一閘極結構頂表面切齊該第二閘極結構頂表面。
  14. 如申請專利範圍第12項所述之半導體元件，其中該第一閘極結構頂表面切齊該第三閘極結構頂表面。
  15. 如申請專利範圍第12項所述之半導體元件，其中該電阻包含： 一金屬層設於該第二層間介電層上；以及 一遮蓋層設於該金屬層上。
  16. 如申請專利範圍第15項所述之半導體元件，其中該金屬層側壁切齊該遮蓋層側壁。
  17. 如申請專利範圍第15項所述之半導體元件，其中該金屬層包含氮化鈦。
  18. 如申請專利範圍第12項所述之半導體元件，其中該第一接觸插塞穿過該電阻。
  19. 如申請專利範圍第12項所述之半導體元件，其中該第一閘極結構設於該第一接觸插塞以及該第二接觸插塞之間。
  20. 如申請專利範圍第11項所述之半導體元件，其中該第一閘極結構寬度小於該電阻寬度。
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