WO2013043330A1 - Plasma activated conformal dielectric film deposition - Google Patents

Plasma activated conformal dielectric film deposition Download PDF

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Publication number
WO2013043330A1
WO2013043330A1 PCT/US2012/052769 US2012052769W WO2013043330A1 WO 2013043330 A1 WO2013043330 A1 WO 2013043330A1 US 2012052769 W US2012052769 W US 2012052769W WO 2013043330 A1 WO2013043330 A1 WO 2013043330A1
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WIPO (PCT)
Prior art keywords
film
dopant
reactant
plasma
method
Prior art date
Application number
PCT/US2012/052769
Other languages
French (fr)
Inventor
Shankar Swaminathan
Jon Henri
Dennis M. Hausmann
Pramod Subramonium
Mandyam Sriram
Vishwanathan Rangarajan
Kirthi K. Kattige
Bart J. Van Schravendijk
Andrew J. Mckerrow
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Novellus Systems, Inc.
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Publication date
Priority to US13/242,084 priority Critical patent/US8637411B2/en
Priority to US13/242,084 priority
Application filed by Novellus Systems, Inc. filed Critical Novellus Systems, Inc.
Publication of WO2013043330A1 publication Critical patent/WO2013043330A1/en

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    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
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Abstract

Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction.

Description

PLASMA ACTIVATED CONFORMAL DIELECTRIC

FILM DEPOSITION

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. § 120 as a continuation in part of US Patent Application No. 13/084,399, filed April 11, 2011, which claims benefit of US provisional patent application number 61/324,710, filed April 15, 2010, and US provisional patent application number 61/372,367, filed August 10, 2010, and US provisional patent application number 61/379,081, filed September 1, 2010, and US provisional patent application number 61/417,807, filed November 29, 2010. Each of the above patent applications is incorporated herein by reference in its entirety and for all purposes. This application is also a continuation in part of US Patent Application No. 13/084,305, filed April 11, 2011, and incorporated herein by reference in its entirety and for all purposes.

BACKGROUND

Various thin film layers for semiconductor devices may be deposited with atomic layer deposition (ALD) processes. However, existing ALD processes may not be suitable for depositing highly conformal dielectric films.

SUMMARY

Various aspects disclosed herein pertain to methods and apparatus for depositing a film on a substrate surface. In certain embodiments, the methods include depositing a film by surface mediated reactions in which the film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction. At some point, the dopant species may be driven across the substrate surface to dope regions of the substrate.

In one aspect, a disclosed method deposits a film on a substrate surface in a reaction chamber. The method may be characterized by the following operations: (a) introducing a first reactant into the reaction chamber under conditions allowing the first reactant to adsorb onto the substrate surface; (b) introducing a second reactant into the reaction chamber while the first reactant is adsorbed on the substrate surface; (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants on the substrate surface to form a portion of the film; (d) repeating (a)-(c) at least once; (e) introducing a dopant containing material, not introduced during (a)-(d), into the reaction chamber under conditions allowing the dopant containing material to contact an exposed surface of the film; and (f) introducing a dopant into the film from the dopant containing material. Introducing the dopant into the film may involve exposing the dopant containing material to a plasma.

In various implementations, the method additionally includes driving the dopant from the film into features of the substrate surface on which the film resides. Driving the dopant from the film may be accomplished by annealing the film. In some applications, the film resides on a three-dimensional feature of the substrate surface and driving the dopant from the film provides conformal diffusion of the dopant into the feature. In a specific application, the feature has a width of not greater than about 40 nanometers.

In certain implementations, the film is a dielectric film. In some cases, the total film thickness is between about 10 - 100 Angstroms. In various embodiments, the concentration of dopant in the film is between about 0.01 and 10 percent by weight.

In certain embodiments, the method of this aspect additionally includes repeating (a)-(c) after (e) or (f). In certain embodiments, the method of this aspect additionally includes repeating (a)-(e). In some implementations, the amount of film deposited during (a)-(c) is between about 0.5 to 1 Angstroms.

In certain embodiments, the method additionally includes purging the second reactant from the reaction chamber prior to exposing the substrate surface to plasma. The purging may be accomplished by flowing a gas containing an oxidant into the reaction chamber. In some implementations, the first and second reactants co-exist in vapor phase in the reaction chamber and the first and second reactants do not appreciably react with one another in the reaction chamber until exposure to plasma in (c).

In certain embodiments, the first reactant is an oxidizing agent, e.g., nitrous oxide. In certain embodiments, the second reactant is a dielectric precursor such as (i) an alkylamino silane (SiHx(NR2)4_x), where x = 1-3, and R includes alkyl groups, or (ii) a halosilane (SiHxY4_x), where x = 1-3, and Y includes CI, Br, and I). In a specific embodiment, the second reactant is BTBAS. In certain embodiments, the dopant containing material is phosphine, arsine, an alkylborane, an alkyl gallane, an alkylphosphine, a phosphorus halide, an arsenic halide, a gallium halide, a boron halide, an alkylborane, or diborane.

In another aspect, a disclosed method deposits a dielectric film on a substrate surface in a reaction chamber. This method may be characterized by the following operations: (a) flowing an oxidant into the reaction chamber under conditions allowing the first reactant to adsorb onto the substrate surface; (b) introducing a dielectric precursor into the reaction chamber while the oxidant continues to flow into the reaction chamber; (c) exposing the substrate surface to plasma to drive a reaction between the dielectric precursor and oxidant on the substrate surface to form a portion of the dielectric film; (d) introducing a dopant containing material, not introduced during (a)-(c), into the reaction chamber under conditions allowing the dopant containing material to contact an exposed surface of the film; and (e) causing a dopant from the containing material to integrate into the dielectric film. In one implementation, the dielectric precursor is BTBAS or another precursor as identified in the prior aspect.

Further, the method may require that operations (a)-(c) be repeated one or more times. In a specific example, the oxidant contains a first ratio of oxygen to nitrogen when (a) is initially performed but the oxidant contains a second ratio of oxygen to nitrogen when (a) is subsequently performed. The second ratio is smaller than the first ratio. For example, the oxidant may contain elemental oxygen when (a) is initially performed but contain nitrous oxide when (a) is repeated. In some embodiments, the substrate is at a first temperature when (c) is initially performed, and the substrate is at a second temperature, which is higher than the first temperature, when (c) is repeated. In some cases, the method further includes driving the dopant from the dielectric film into the substrate. In some embodiments, the method further includes contacting the substrate surface with the dopant containing material prior to (a).

In another aspect, a disclosed method deposits a dielectric film on a substrate surface in a reaction chamber according to the following operations: (a) introducing a dielectric precursor into the reaction chamber under conditions allowing the precursor to adsorb onto the substrate surface; (b) thereafter purging the dielectric precursor from the reaction chamber while the precursor remains adsorbed on the substrate surface; (c) exposing the substrate surface to plasma to drive a reaction of the dielectric precursor on the substrate surface to form a portion of the dielectric film; and (d) introducing a dopant precursor, not introduced during (a)-(c), into the reaction chamber under conditions allowing the dopant precursor to contact the portion of the dielectric film. In some implementations, the method additionally involves flowing an oxidant into the reaction chamber prior to and during (a)-(c). In some cases, the method additionally involves reacting the dopant precursor to incorporate a dopant into the film. Yet another aspect concerns an apparatus for depositing a doped film on a substrate surface. The apparatus may be characterized by the following features: a reaction chamber comprising a device for holding the substrate during deposition of the doped dielectric film; one or more process gas inlets coupled to the reaction chamber; and a controller. The controller is designed or configured to cause the apparatus to perform the following operations: (a) introducing a first reactant into the reaction chamber under conditions allowing the first reactant to adsorb onto the substrate surface; (b) introducing a second reactant into the reaction chamber while the first reactant is adsorbed on the substrate surface; (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants on the substrate surface to form a portion of the film; (d) repeating (a)-(c) at least once; (e) introducing a dopant containing material, not introduced during (a)-(d), into the reaction chamber under conditions allowing the dopant containing material to contact an exposed surface of the film; and (f) introducing a dopant into the film from the dopant containing material. The controller may be designed or configured to direct performance of other methods such as those discussed in accordance with other aspects.

In certain embodiments, the controller is further designed or configured to cause the apparatus to flow an oxidant into the reaction chamber prior to and during (a)-(d). In certain embodiments, the controller is further designed or configured to cause repeating (a)-(c) after (e) or (f). In certain embodiments, the controller is further designed or configured to cause driving the dopant from the film into features of the substrate surface on which the film resides. Driving the dopant from the film may be accomplished by annealing the film. In some implementations, the controller is further designed or configured to cause (e) to be performed at intervals between one or more repetitions of (a)-(d) and wherein said intervals are varied over the course of depositing the film.

In various implementations, the controller is further designed or configured to cause purging the second reactant from the reaction chamber prior to exposing the substrate surface to plasma. In one example, purging is accomplished by flowing a gas comprising an oxidant into the reaction chamber under the direction of the controller. These and other features will be described in more detail below with reference to the associated drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically shows a timing diagram for an example conformal film deposition (CFD) process according to an embodiment of the present disclosure.

FIG. 2 schematically shows a timing diagram for another example CFD process according to an embodiment of the present disclosure.

FIG. 3 schematically shows a timing diagram for another example CFD process according to an embodiment of the present disclosure.

FIG. 4 schematically shows a timing diagram for an example CFD process including a plasma treatment cycle according to an embodiment of the present disclosure.

FIG. 5 shows an example correlation between a wet etch rate ratio and a deposition temperature for films deposited according to an embodiment of the present disclosure.

FIG. 6 shows an example correlation between a wet etch rate ratio and a film stress for films deposited according to an embodiment the present disclosure.

FIG. 7 shows an example correlation between film contaminant concentration and deposition temperature for films deposited according to an embodiment of the present disclosure.

FIG. 8 schematically shows an example cross-section of a non-planar substrate comprising a plurality of gaps.

FIG. 9 schematically shows a timing diagram for an example CFD process including a transition to a PECVD process according to an embodiment of the present disclosure.

FIG. 10 schematically shows an example cross-section of a gap fill including a keyhole void.

FIG. 11 schematically shows a timing diagram for an example CFD process including an in-situ etch according to an embodiment of the present disclosure. FIG. 12A schematically shows an example cross-section of a re-entrant gap fill profile.

FIG. 12B schematically shows an example cross-section of the re-entrant gap fill profile of FIG. 12A during an in-situ etch process according to an embodiment of the present disclosure.

FIG. 12C schematically shows an example cross-section of the gap fill profile of FIG. 12B during a deposition process after an in-situ etch according to an embodiment of the present disclosure.

FIG. 13 schematically shows an example process station according to an embodiment of the present disclosure.

FIG. 14 schematically shows an example process tool including a plurality of process stations and a controller according to an embodiment of the present disclosure.

FIG. 15 schematically shows an example cross-sectional view of a through- silicon via during a CFD process including an in-situ etch according to an embodiment of the present disclosure.

Figure 16 illustrates a transistor having a three-dimensional gate structure, in which the source and drain are formed in thin vertical structures that are difficult to dope by conventional ion implantation techniques.

Figure 17 presents a baseline CFD sequence of operations from left to right with advancing time along the x axis.

Figures 18 and 19 depict embodiments in which dopant is deposited at the interface with the underlying substrate, followed by CFD cycles interspersed with a dopant delivery, and optionally topped off with an undoped protective "capping" layer may be a CFD oxide film.

Figure 20 shows a typical deposition block used to synthesize a CFD

BSG/PSG film.

Figure 21 shows step coverage for CFD films calculated to be -100% on dense and isolated structures.

Figure 22 presents SIMS data showing that the average boron concentration in CFD films can be tuned in a range of about 0.5 - 3.5wt% boron. DETAILED DESCRIPTION

Manufacture of semiconductor devices typically involves depositing one or more thin films on a non-planar substrate in an integrated fabrication process. In some aspects of the integrated process it may be useful to deposit thin films that conform to substrate topography. For example, a silicon nitride film may be deposited on top of an elevated gate stack to act as a spacer layer for protecting lightly-doped source and drain regions from subsequent ion implantation processes.

In spacer layer deposition processes, chemical vapor deposition (CVD) processes may be used to form a silicon nitride film on the non-planar substrate, which is then anisotropically etched to form the spacer structure. However, as a distance between gate stacks decreases, mass transport limitations of CVD gas phase reactions may cause "bread-loafing" deposition effects. Such effects typically exhibit thicker deposition at top surfaces of gate stacks and thinner deposition at the bottom corners of gate stacks. Further, because some die may have regions of differing device density, mass transport effects across the wafer surface may result in within- die and within-wafer film thickness variation. These thickness variations may result in over-etching of some regions and under-etching of other regions. This may degrade device performance and/or die yield.

Some approaches to addressing these issues involve atomic layer deposition (ALD). In contrast with a CVD process, where thermally activated gas phase reactions are used to deposit films, ALD processes use surface-mediated deposition reactions to deposit films on a layer-by-layer basis. In one example ALD process, a substrate surface, including a population of surface active sites, is exposed to a gas phase distribution of a first film precursor (PI). Some molecules of PI may form a condensed phase atop the substrate surface, including chemisorbed species and physisorbed molecules of PI . The reactor is then evacuated to remove gas phase and physisorbed PI so that only chemisorbed species remain. A second film precursor (P2) is then introduced to the reactor so that some molecules of P2 adsorb to the substrate surface. The reactor may again be evacuated, this time to remove unbound P2. Subsequently, thermal energy provided to the substrate activates surface reactions between adsorbed molecules of PI and P2, forming a film layer. Finally, the reactor is evacuated to remove reaction by-products and possibly unreacted PI and P2, ending the ALD cycle. Additional ALD cycles may be included to build film thickness. Depending on the exposure time of the precursor dosing steps and the sticking coefficients of the precursors, each ALD cycle may deposit a film layer of, in one example, between one -half and three angstroms thick. Thus, ALD processes may be time consuming when depositing films more than a few nanometers thick. Further, some precursors may have long exposure times to deposit a conformal film, which may also reduce wafer throughput time. Conformal films may also be deposited on planar substrates. For example, antireflective layers for lithographic patterning applications may be formed from planar stacks comprising alternating film types. Such antireflective layers may be approximately 100 to 1000 angstroms thick, making ALD processes less attractive than CVD processes. However, such anti -reflective layers may also have a lower tolerance for within- wafer thickness variation than many CVD processes may provide. For example, a 600-angstrom thick antireflective layer may tolerate a thickness range of less than 3 angstroms.

Accordingly, various embodiments are provided herein providing processes and equipment for plasma-activated conformal film deposition (CFD) on non-planar and planar substrates. These embodiments incorporate various features employed in some but not all CFD processes. Among these features are (1) eliminating or reducing the time required to "sweep" one or both reactants from the reaction chamber, (2) providing a continuous flow of at least one reactant while a different reactant is intermittently flowed into the reaction chamber, (3) igniting plasma while one of the reactants is present in the gas phase, rather than when all reactants are cleared from the reaction chamber, (4) treating deposited CFD films with a plasma to modify the film properties, (5) depositing a portion of a film by PECVD after depositing a first portion of the film by CFD, typically in the same reaction chamber, (6) etching a partially deposited film between CFD stages, and (7) doping the CFD film by interspersing dopant delivery cycles with film only deposition cycles. Of course, this list is not exhaustive. Various other CFD features will be apparent when considering the remainder of the specification.

The concept of a CFD "cycle" is relevant to the discussion of various embodiments herein. Generally a cycle is the minimum set of operations required to perform a surface deposition reaction one time. The result of one cycle is production of at least a partial film layer on a substrate surface. Typically, a CFD cycle will include only those steps necessary to deliver and adsorb each reactant to the substrate surface, and then react those adsorbed reactants to form the partial layer of film. Of course, the cycle may include certain ancillary steps such as sweeping one of the reactants or byproducts and/or treating the partial film as deposited. Generally, a cycle contains only one instance of a unique sequence of operations. As an example, a cycle may include the following operations: (i) delivery/adsorption of reactant A, (ii) delivery/adsorption of reactant B, (iii) sweep B out of the reaction chamber, and (iv) apply plasma to drive a surface reaction of A and B to form the partial film layer on the surface. The seven above-mentioned features will now be discussed further. In the following descriptions, consider a CFD reaction in which one more reactants adsorb to the substrate surface and then react to form a film on the surface by interaction with plasma.

Feature 1 (Continuous flow of a reactant) - Reactant A continues to flow to a reaction chamber during one or more portions of a CFD cycle when the reactant would not normally flow in conventional ALD. In conventional ALD, reactant A flows only for the purpose of having the reactant adsorb onto the substrate surface. At other phases of an ALD cycle, reactant A does not flow. In accordance with certain CFD embodiments described herein, however, reactant A flows not only during phases associated with its adsorption but also during phases of a CFD cycle that perform operations other than adsorption of A. For example, in many embodiments, reactant A flows into the reactor while the apparatus is dosing a second reactant (reactant B herein). Thus, during at least a portion of a CFD cycle, reactants A and B coexist in the gas phase. Further, reactant A may flow while plasma is applied to drive a reaction at the substrate surface. Note that the continuously flowing reactant may be delivered to the reaction chamber in conjunction with a carrier gas- e.g., argon.

One advantage of the continuous flow embodiment is that the established flow avoids the delays and flow variations caused by transient initialization and stabilization of flow associated with turning the flow on and off.

As a specific example, an oxide film may be deposited by a conformal film deposition process using a principal reactant (sometimes referred to as a "solid component" precursor or, in this example, simply "reactant B"). Bis(tert- butylamino)silane (BTBAS) is one such principal reactant. In this example, the oxide deposition process involves delivery of an oxidant such as oxygen or nitrous oxide, which flows initially and continuously during delivery of the principal reactant in distinct exposure phases. The oxidant also continues to flow during distinct plasma exposure phases. See for example the sequence depicted in FIG. 1. For comparison, in a conventional ALD process, the flow of oxidant would stop when the solid component precursor is delivered to the reactor. For example, the flow of reactant A would stop when reactant B is delivered. In some specific examples, the reactant that flows continuously is an "auxiliary" reactant. As used herein, an "auxiliary" reactant is any reactant that is not a principal reactant. As suggested above, a principal reactant contains an element that is solid at room temperature, which element is contributed to the film formed by CFD. Examples of such elements are metals (e.g., aluminum and titanium), semiconductors (e.g., silicon and germanium), and non-metals or metalloids (e.g., boron). Examples of auxiliary reactants include oxygen, ozone, hydrogen, carbon monoxide, nitrous oxide, ammonia, alkyl amines, and the like.

The continuously flowing reactant may be provided at a constant flow rate or at varied but controlled flow rate. In the latter case, as an example, the flow rate of an auxiliary reactant may drop during an exposure phase when the primary reactant is delivered. For example, in oxide deposition, the oxidant (e.g., oxygen or nitrous oxide) may flow continuously during the entire deposition sequence, but its flow rate may drop when the primary reactant (e.g., BTBAS) is delivered. This increases the partial pressure of BTBAS during its dosing, thereby reducing the exposure time needed to saturate the substrate surface. Shortly before igniting the plasma, the flow of oxidant may be increased to reduce the likelihood that BTBAS is present during the plasma exposure phase. In some embodiments, the continuously flowing reactant flows at a varied flow rate over the course of two or more deposition cycles. For example, the reactant may flow at a first flow rate during a first CFD cycle and at a second flow rate during a second CFD cycle.

When multiple reactants are employed and the flow of one of them is continuous, at least two of them will co-exist in the gas phase during a portion of the CFD cycle. Similarly, when no purge step is performed after delivery of the first reactant, two reactants will co-exist. Therefore, it may be important to employ reactants that do not appreciably react with one another in the gas phase absent application of activation energy. Typically, the reactants should not react until present on the substrate surface and exposed to plasma or another appropriate nonthermal activation condition. Choosing such reactants involves considerations of at least (1) the thermodynamic favorability (Gibb's free energy <0) of the desired reaction, and (2) the activation energy for the reaction, which should be sufficiently great so that there is negligible reaction at the desired deposition temperature.

Feature 2 (Reduce or eliminate a sweep step) - In certain embodiments, the process dispenses with or reduces the time associated with a sweep step that would normally be performed in conventional ALD. In conventional ALD, a separate sweep step is performed after each reactant is delivered and adsorbed onto the substrate surface. Little or no adsorption or reaction occurs in a conventional ALD sweep step. In a CFD cycle, the sweep step is reduced or eliminated after delivery of at least one of the reactants. An example of a process sequence in which a sweep step is removed is presented in FIG. 1. No sweep step is performed to sweep reactant A from the reaction chamber. In some cases, no sweep step is performed after delivery of the first reactant in a CFD cycle but a sweep step is optionally performed after delivery of the second or last delivered reactant.

The concept of a CFD "sweep" step or phase appears in the discussion various embodiments herein. Generally, a sweep phase removes or purges one of the vapor phase reactant from a reaction chamber and typically occurs only after delivery of such reactant is completed. In other words, that reactant is no longer delivered to the reaction chamber during sweep phase. However, the reactant remains adsorbed on the substrate surface during the sweep phase. Typically, the sweep serves to remove any residual vapor phase reactant in the chamber after the reactant is adsorbed on the substrate surface to the desired level. A sweep phase may also remove weakly adsorbed species (e.g., certain precursor ligands or reaction by-products) from the substrate surface. In ALD, the sweep phase has been viewed as necessary to prevent gas phase interaction of two reactants or interaction of one reactant with a thermal, plasma or other driving force for the surface reaction. In general, and unless otherwise specified herein, a sweep phase may be accomplished by (i) evacuating a reaction chamber, and/or (ii) flowing gas not containing the species to be swept out through the reaction chamber. In the case of (ii), such gas may be, for example, an inert gas or an auxiliary reactant such as a continuously flowing auxiliary reactant.

Elimination of the sweep phase may be accomplished with or without continuous flow of the other reactant. In the embodiment depicted in FIG. 1, reactant A is not swept away but rather continues to flow after its adsorption onto the substrate surface is completed (illustrated by reference number 130 in the figure).

In various embodiments where two or more reactants are employed, the reactant which has its sweep step eliminated or reduced is an auxiliary reactant. As an example, auxiliary reactant is an oxidant or a nitrogen source and the primary reactant is a silicon, boron, or germanium containing precursor. Of course, a sweep of the principal reactant may also be reduced or eliminated. In some examples, no sweep step is performed after delivery of an auxiliary reactant but a sweep step is optionally performed after delivery of a principal reactant. As mentioned, the sweep phase need not be fully eliminated but simply reduced in duration in comparison to sweep phases in conventional ALD processes. For example, the sweep phase of a reactant such as an auxiliary reactant during a CFD cycle may be performed for about 0.2 seconds or less, e.g., for about 0.001 to 0.1 seconds.

Feature 3 (Igniting plasma while one of the reactants is present in the gas phase) - With this feature, a plasma is ignited before all reactants have been cleared from the reaction chamber. This is contrary to conventional ALD, where the plasma activation or other reaction driving operation is provided only after the vapor phase reactants are no longer present in the reaction chamber. Note that this feature would necessarily occur when reactant A flows continuously during the plasma portion of a CFD cycle as depicted in FIG. 1. However, the disclosed embodiments are not limited in this manner. One or more reactants may flow during the plasma phase of a CFD cycle but need not flow continuously during a CFD cycle. Further, the reactant present in vapor phase during plasma activation may be a principal reactant or an auxiliary reactant (when two more reactants are employed in a CFD cycle). For example, a sequence might be (i) introduce reactant A, (ii) purge A, (iii) introduce reactant B and while B is flowing strike a plasma, and (iv) purge. In such embodiments, the process employs a plasma activated reactant species from the gas phase. This is a general example where CFD is not constrained to a sequence of sequential steps. If the activation plasma is provided during the time when the solid component precursor (primary reactant) is supplied to the reactor, the step coverage may become less conformal, but the deposition rate will typically increase. However if plasma activation occurs only during delivery of one an auxiliary reactant this is not necessarily the case. The plasma can activate the vapor phase auxiliary component to render it more reactive and thereby increase its reactivity in the conformal film deposition reaction. In certain embodiments, this feature is employed when depositing a silicon containing film such as an oxide, nitride, or carbide.

Feature 4 (Plasma treatment of deposited CFD films) - In these embodiments, the plasma may serve two or more roles in the conformal film deposition process. One of its roles is to activate or drive the film formation reaction during each CFD cycle. Its other role is to treat the film after the CFD film has been partially or fully deposited following one or more CFD cycles. The plasma treatment is intended to modify one or more film properties. Typically, though not necessarily, the plasma treatment phase is conducted under conditions that are different from those employed to activate the film formation reaction (i.e., to drive the film formation reaction). As an example, the plasma treatment may be performed in the presence of a reducing or oxidizing environment (e.g., in the presence of hydrogen or oxygen), while this need not be the case during the activation portion of a CFD cycle.

The plasma treatment operation may be performed during every cycle of the CFD process, during every other cycle, or on some less frequent basis. The treatment may be performed on regular intervals, tied to a fixed number of CFD cycles, or it may be performed variably (e.g., at varying intervals of CFD cycles) or even randomly. In a typical example, film deposition is performed for a few CFD cycles, to reach appropriate film thickness, and then the plasma treatment is employed. Thereafter, film deposition is again performed for a number of CFD cycles without plasma treatment before the treatment is again performed. This super-sequence of x number of CFD cycles, followed by plasma treatment (film modification) may be repeated until the film is completely formed by CFD.

In certain embodiments, the plasma treatment may be performed before initiation of CFD cycling to modify one or more properties of the surface on which the CFD film is deposited. In various embodiments, the surface is made from silicon (doped or undoped) or a silicon containing material. The modified surface may be better able to produce a high quality interface with the subsequently deposited CFD film. The interface may provide, e.g., good adhesion, reliable electrical properties through, e.g., defect reduction, etc. The pretreatment of the substrate prior to CFD is not limited to any particular plasma treatment. In certain embodiments, the pre-treatment involves exposure to hydrogen-plasma, nitrogen-plasma, nitrogen/hydrogen-plasma, ammonia-plasma, argon-plasma, helium-plasma, helium anneal, hydrogen-anneal, ammonia-anneal, and UV-cure in the presence of helium, hydrogen, argon, nitrogen, hydrogen/nitrogen- forming gas, and/or ammonia. Plasma processing may be enabled with various plasma generators including, though not limited to, microwave, ICP-remote, direct and others known to those in the art.

Overall, the treatment may occur before, during and after CFD cycling. When occurring during CFD cycling, the frequency of treatment may be chosen for the appropriate deposition conditions. Typically, the treatment will occur not more often than once per cycle.

As an example, consider a process for forming silicon nitride from precursors having some carbon present. Examples of such precursors include BTBAS. As a consequence of the carbon present in the precursor, the as deposited nitride film includes some carbon impurity, which may degrade the electrical properties of the nitride. To counteract this problem, after a few CFD cycles with the carbon- containing precursor, the partially deposited film is exposed to hydrogen in the presence of plasma to reduce and ultimately remove the carbon impurity.

The plasma conditions employed to modify the film surface may be chosen to effect a desired change in film properties and/or composition. Among the plasma conditions that can be selected and/or tailored for the desired modification are oxidizing conditions, reducing conditions, etching conditions, power used to generate the plasma, frequency used to generate the plasma, use of two or more frequencies to generate the plasma, plasma density, the distance between the plasma and the substrate, etc. Examples of CFD film properties that can be modified by plasma treatment include, internal film stress, etch resistance, density, hardness, optical properties (refractive index, reflectivity, optical density, etc.), dielectric constant, carbon content, electrical properties (Vfb spread, etc.), and the like.

In some embodiments, a treatment other than a plasma treatment is employed to modify the properties of the as deposited film. Such treatments include electromagnetic radiation treatments, thermal treatments (e.g., anneals or high temperature pulses), and the like. Any of these treatments may be performed alone or in combination with another treatment, including a plasma treatment. Any such treatment can be employed as a substitute for any of the above-described plasma treatments. In a specific embodiment, the treatment involves exposing the film to ultraviolet radiation. As described below, in a specific embodiment, the method involves the application of UV-radiation to an oxide CFD film in situ (i.e., during formation of the film) or post deposition of the oxide. Such treatment serves to reduce or eliminate defect structure and provide improved electrical performance. In certain specific embodiments, a UV treatment can be coupled with a plasma treatment. These two operations can be performed concurrently or sequentially. In the sequential option, the UV operation optionally takes place first. In the concurrent option, the two treatments may be provided from separate sources (e.g., an RF power source for the plasma and a lamp for the UV) or from a single source such as a helium plasma that produces UV radiation as a byproduct.

Feature 5 (Depositing by CFD and then transitioning to PECVD) - In such embodiments, the completed film is generated in part by CFD and in part by a CVD process such as PECVD. Typically, the CFD portion of the deposition process if performed first and the PECVD portion is performed second, although this need not be the case. Mixed CFD/CVD processes can improve the step coverage over that seen with CVD alone and additionally improve the deposition rate over that seen with CFD alone. In some cases, plasma or other activation is applied while one CFD reactant is flowing in order to produce parasitic CVD operations and thereby achieve higher deposition rates, a different class of films, etc.

In certain embodiments, two or more CFD phases may be employed and/or two or more CVD phases may be employed. For example, an initial portion of the film may be deposited by CFD, followed by an intermediate portion of the film being deposited by CVD, and a final portion of the film deposited by CFD. In such embodiments, it may be desirable to modify the CVD portion of the film, as by plasma treatment or etching, prior to depositing the later portion of the film by CFD. A transition phase may be employed between the CFD and CVD phases. The conditions employed during such transition phase different from those employed in either the CFD or the CVD phases. Typically, though not necessarily, the conditions permit simultaneous CFD surface reactions and CVD type gas phase reaction. The transition phase typically involves exposure to a plasma, which may be pulsed for example. Further, the transition phase may involve delivery of one or more reactants a low flow rate, i.e., a rate that is significantly lower than that employed in the corresponding CFD phase of the process.

Feature 6 (Deposit by CFD, etch, and then further deposit by CFD) - In such embodiments, CFD deposition is performed for one or more cycles (typically a number of cycles) and then the resulting film is etched to remove, for example, some excess film at or near a recess entrance (a cusp), followed by further cycles of CFD deposition. Other examples of structural features in the deposited film that may be etched in a similar manner. The etchant chosen for this process will depend on the material to be etched. In some cases, the etch operation may be performed with a fluorine containing etchant (e.g., NF3) or hydrogen.

In certain embodiments, a remote plasma is employed to produce the etchant. Generally, a remote plasma etches in a more isotropic fashion than a direct plasma. A remote plasma generally provides a relatively high fraction of radicals to the substrate. The reactivity of these radicals may vary with the vertical position within the recess. At the top of the feature, the radicals are more concentrated and consequently will etch at a higher rate, while further down the recess and at the bottom, some radicals will have been lost and therefore they will etch at a lower rate. This is of course a desirable reactivity profile for addressing the problem of too much deposition occurring at the recess opening. An additional benefit of using a remote plasma in etching is that the plasma is relatively gentle and hence unlikely to damage the substrate layer. This can be particularly beneficial when the underlying substrate layer is sensitive oxidation or other damage.

Feature 7 (Tailoring the film composition with additional reactant) - Many of the examples presented herein concern CFD processes employing one or two reactants. Further, many of the examples employ the same reactants in every CFD cycle. However, this need not be the case. First, many CFD processes may employ three or more reactants. Examples include (i) CFD of tungsten using as reactants diborane, tungsten hexafluoride, and hydrogen, and (ii) CFD of silicon oxide using as reactants diborane, BTBAS, and oxygen. The diborane can be removed from the growing film or it can be incorporated into the film if appropriate.

Further, some examples may employ additional reactants in only some CFD cycles. In such examples, a basic CFD process cycle employs only the reactants to create the base film composition (e.g., silicon oxide or silicon carbide). This basic process is performed in all or nearly all CFD cycles. However, some of the CFD cycles are executed as variant cycles and they deviate from the conditions of the normal deposition cycles. For example, they may employ one or more additional reactants. These variant cycles may also employ the same reactants employed in the basic CFD process, although this need not be the case.

Such CFD processes are particularly beneficial in preparing doped oxides or other doped materials as CFD films. In some implementations, dopant precursors are included as the "additional" reactant in only a small fraction of the CFD cycles. The frequency of adding the dopant is dictated by the desired concentration of dopant. For example, the dopant precursor may be included in every 10th cycle of the base material deposition. Unlike many other deposition processes, particularly those requiring thermal activation, the CFD process may be conducted at a relatively low temperature. Generally, the CFD temperature will be between about 20 and 400 C. Such temperature may be chosen to permit deposition in the context of a temperature sensitive process such as deposition on a photoresist core. In a specific embodiment, a temperature of between about 20 and 100 C is used for double patterning applications (using, e.g., photoresist cores). In another embodiment, a temperature of between about 200 and 350 C is employed for memory fabrication processing.

As suggested above, CFD is well suited for depositing films in advanced technology nodes. Thus, for example, CFD processing may be integrated in processes at the 32 nm node, the 22 nm node, the 16 nm node, the 11 nm node, and beyond any of these. These nodes are described in the International Technology Roadmap for Semiconductors (ITRS), the industry consensus on microelectronic technology requirements for many years. Generally they reference one -half pitch of a memory cell. In a specific example, the CFD processing is applied to "2X" devices (having device features in the realm of 20-29 nm) and beyond.

While most examples of CFD films presented herein concern silicon based microelectronic devices, the films may also find application in other areas. Microelectronics or optoelectronics using non-silicon semiconductors such as GaAs and other III-V semiconductors, as well as II-VI materials such as HgCdTe may profit from using the CFD processes disclosed herein. Applications for conformal dielectric films in the solar energy field, such as photovoltaic devices, in the electrochromics field, and other fields are possible.

FIG. 1 schematically shows a timing diagram 100 for an example embodiment of a plasma-activated CFD process. Two full CFD cycles are depicted. As shown, each includes an exposure to reactant A phase 120, directly followed by an exposure to reactant B phase 140, a sweep of reactant B phase 160, and finally a plasma activation phase 180. Plasma energy provided during plasma activation phases 180A and 180B activates a reaction between surface adsorbed reactant species A and B. In the depicted embodiments, no sweep phase is performed after one reactant (reactant A) is delivered. In fact, this reactant flows continuously during the film deposition process. Thus, plasma is ignited while reactant A is in the gas phase. Features 1-3 above are embodied in the example of FIG. 1.

In the depicted embodiment, reactant gases A and B may co-exist in the gas phase without reacting. Accordingly, one or more of the process steps described in the ALD process may be shortened or eliminated in this example CFD process. For example, sweep steps after A Exposure Phases 120 A and 120B may be eliminated.

The CFD process may be employed to deposit any of a number of different types of film. While most of the examples presented herein, concern dielectric materials, the disclosed CFD processes may be employed to form films of conductive and semiconductor materials as well. Nitrides and oxides are featured dielectric materials, but carbides, oxynitrides, carbon-doped oxides, borides, etc. may also be formed. Oxides include a wide range of materials including undoped silicate glass (USG), doped silicate glass. Examples of doped glasses included boron doped silicate glass (BSG), phosphorus doped silicate glass (PSG), and boron phosphorus doped silicate glass (BPSG). In some embodiments, a silicon nitride film may be formed by reaction of a silicon-containing reactant and one or more of a nitrogen-containing reactant and/or a nitrogen-containing reactant blend. Example silicon-containing reactants include, but are not limited to, bis(tertiarybutylamino)silane (SiH2(NHC(CH3)3)2 or BTBAS), dichlorosilane (SiH2Cl2), and chlorosilane (SiH3Cl). Example nitrogen-containing reactants include, but are not limited to, ammonia, nitrogen, and tert-butyl amine ((CH3)3CNH2 or t-butyl amine). An example nitrogen-containing reactant blend, includes, but is not limited to, a blend of nitrogen and hydrogen.

Selection of one or more reactants may be driven by various film and/or hardware considerations. For example, in some embodiments, a silicon nitride film may be formed from reaction of dichlorosilane and plasma-activated nitrogen. Chemisorption of dichlorosilane to a silicon nitride surface may create a silicon- hydrogen terminated surface, liberating hydrogen chloride (HCl). An example of this chemisorption reaction is schematically depicted in Reaction 1. Reaction 1 :

H H

\ /

Figure imgf000019_0001

The cyclic intermediate shown in Reaction 1 may then be transformed into amine terminated surface via reaction with plasma-activated nitrogen.

However, some molecules of dichlorosilane may chemisorb by alternative mechanisms. For example, surface morphology may hinder the formation of the cyclic intermediate depicted in Reaction 1. An example of another chemisorption mechanism is shown schematically in Reaction 2. Reaction 2:

CI H

\ /

Si

Figure imgf000020_0001

During subsequent plasma activation of nitrogen, the remaining chlorine atom of the intermediate species shown in Reaction 2 may be liberated and may become activated by the plasma. This may cause etching of the silicon nitride surface, potentially causing the silicon nitride film to become rough or hazy. Further, the residual chlorine atom may readsorb, physically and/or chemically, potentially contaminating the deposited film. This contamination may alter physical and/or electrical properties of the silicon nitride film. Further still, the activated chlorine atom may cause etch damage to portions of the process station hardware, potentially reducing the service life of portions of the process station.

Thus, in some embodiments, chlorosilane may be substituted for dichlorosilane. This may reduce film contamination, film damage, and/or process station damage. An example of the chemisorption of chlorosilane is schematically shown in Reaction 3.

Reaction 3 :

H H

I I

Figure imgf000020_0002

While the example depicted in Reaction 3 uses chlorosilane as the silicon- containing reactant, it will be appreciated that any suitable mono-substituted halosilane may be used. As explained above, the depicted intermediate structures may react with a nitrogen source to form a silicon amine terminated surface of silicon nitride. For example, ammonia may be activated by a plasma, forming various ammonia radical species. The radical species react with the intermediate, forming the silicon amine terminated surface.

However, ammonia may physisorb strongly to surfaces of the reactant delivery lines, process station, and exhaust plumbing, which may lead to extended purge and evacuation times. Further, ammonia may have a high reactivity with some gas phase silicon-containing reactants. For example gas-phase mixtures of dichlorosilane (SiH2Cl2) and ammonia may create unstable species such as diaminosilane (SiH2(NH2)2). Such species may decompose in the gas phase, nucleating small particles. Small particles may also be formed if ammonia reacts with hydrogen chloride generated during chemisorption of a halosilane. Such particles may accumulate in the process station where they may contaminate substrate surfaces, potentially leading to integrated device defects, and where they may contaminate process station hardware, potentially leading to tool down time and cleaning. The small particles may also accumulate in exhaust plumbing, may clog pumps and blowers, and may create a need for special environmental exhaust scrubbers and/or cold traps. Thus, in some embodiments, a substituted amine may be used as a nitrogen- containing reactant. For example, various radicals formed from plasma activation of an alkyl substituted amine, such as t-butyl amine, may be supplied to the process station. Substituted amines such as t-butyl amine may have a lower sticking coefficient on process hardware than ammonia, which may result in comparatively lower phyisorbption rates and comparatively lower process purge time.

Further, such nitrogen-containing reactants may form halogenated salts that are comparatively more volatile than ammonium chloride. For example, t- butylammonium chloride may be more volatile than ammonium chloride. This may reduce tool down time, device defect creation, and environmental abatement expense. Further still, such nitrogen-containing reactants may form other amine precursors via various byproduct reactions. For example, the reaction of t-butyl amine with dichlorosilane may form BTBAS. Thus, the side products may provide alternate routes to form silicon nitride, potentially increasing film yield. In another example, substituted amines may provide low temperature thermally activated routes to silicon nitride films. For example, t-butyl amine decomposes thermally at temperatures above 300 °C to form isobutylene and ammonia. While the illustrative example provided above describes silicon nitride film formation using t-butyl amine, it will be appreciated that any suitable substituted amine may be employed within the scope of the present disclosure. Suitable substituted amines may be selected, in some embodiments, based on thermodynamic characteristics and/or reactivity characteristics of the reactant. For example, the relative volatility of halogenated salts formed from the reactant may be considered, as may the existence and selectivity of various thermal decomposition paths at relevant temperatures.

Further, while the examples provided above describe the deposition of silicon nitride films, it will be appreciated that the principles discussed above apply generally to the deposition of other films. For example, some embodiments may use suitable halosilanes in combination with a suitable oxygen-containing reactant species, such as an oxygen plasma, to deposit silicon oxides.

A non-limiting list of reactants, product films, and film and process property ranges are provided in Table 1.

Figure imgf000022_0001
Figure imgf000023_0001

FIG. 1 also shows an embodiment of a temporal progression of example CFD process phases for various CFD process parameters. FIG. 1 depicts two example deposition cycles 11 OA and HOB, though it will be appreciated that any suitable number of deposition cycles may be included in a CFD process to deposit a desired film thickness. Example CFD process parameters include, but are not limited to, flow rates for inert and reactant species, plasma power and frequency, substrate temperature, and process station pressure. Non- limiting parameter ranges for an example silicon dioxide deposition cycle using BTBAS and oxygen are provided in Table 2.

Figure imgf000023_0002
Figure imgf000024_0001

A CFD cycle typically contains an exposure phase for each reactant. During this "exposure phase," a reactant is delivered to a process chamber to cause adsorption of the reactant on the substrate surface. Typically, at the beginning of an exposure phase, the substrate surface does not have any appreciable amount of the reactant adsorbed. In FIG. 1, at reactant A exposure phases 120A and B, reactant A is supplied at a controlled flow rate to a process station to saturate exposed surfaces of a substrate. Reactant A may be any suitable deposition reactant; e.g., a principal reactant or an auxiliary reactant. In one example where CFD produces a silicon dioxide film, reactant A may be oxygen. In the embodiment shown in FIG. 1, reactant A flows continuously throughout deposition cycles 110A and HOB. Unlike a typical ALD process, where film precursor exposures are separated to prevent gas phase reaction, reactants A and B are allowed to mingle in the gas phase of some embodiments of a CFD process. As indicated above, in some embodiments reactants A and B are chosen so that they can co-existence in the gas phase without appreciably reacting with one another under conditions encountered in the reactor prior to application of plasma energy or the activation of the surface reaction. In some cases, the reactants are chosen such that (1) a reaction between them is thermodynamically favorable (i.e., Gibb's free energy <0) and (2) the reaction has a sufficiently high activation energy that there is negligible reaction at the desired deposition temperature. Various reactant combinations meeting these criteria are identified at other locations in this disclosure. Many such combinations include a primary reactant, which contributes an element that is solid at room temperature, and an auxiliary reactant, which does not. Examples of auxiliary reactants used in some combinations include oxygen, nitrogen, alkyl amines, and hydrogen.

Continuously supplying reactant A to the process station may reduce or eliminate a reactant A flow rate turn-on and stabilization time compared to an ALD process where reactant A is first turned on, then stabilized and exposed to the substrate, then turned off, and finally removed from a reactor. While the embodiment shown in FIG. 1 depicts reactant A exposure phases 120A and B as having a constant flow rate, it will be appreciated that any suitable flow of reactant A, including a variable flow, may be employed within the scope of the present disclosure. Further, while FIG. 1 shows reactant A having a constant flow rate during the entire CFD cycle (deposition cycle 11 OA), this need not be the case. For example, the flow rate of reactant A may decrease during B exposure phases 140 A and 140B. This may increase the partial pressure of B and thereby increase the driving force of reactant B adsorbing on the substrate surface.

In some embodiments, reactant A exposure phase 120A may have a duration that exceeds a substrate surface saturation time for reactant A. For example, the embodiment of FIG. 1 includes a reactant A post-saturation exposure time 130 in reactant A exposure phase 120 A. Optionally, reactant A exposure phase 120 A includes a controlled flow rate of an inert gas. Example inert gases include, but are not limited to, nitrogen, argon, and helium. The inert gas may be provided to assist with pressure and/or temperature control of the process station, evaporation of a liquid precursor, more rapid delivery of the precursor and/or as a sweep gas for removing process gases from the process station and/or process station plumbing. At Reactant B exposure phase 140A of the embodiment shown in FIG. 1, reactant B is supplied at a controlled flow rate to the process station to saturate the exposed substrate surface. In one example silicon dioxide film, reactant B may be BTBAS. While the embodiment of FIG. 1 depicts reactant B exposure phase 140A as having a constant flow rate, it will be appreciated that any suitable flow of reactant B, including a variable flow, may be employed within the scope of the present disclosure. Further, it will be appreciated that reactant B exposure phase 140A may have any suitable duration. In some embodiments, reactant B exposure phase 140 A may have a duration exceeding a substrate surface saturation time for reactant B. For example, the embodiment shown in FIG. 1 depicts a reactant B post-saturation exposure time 150 included in reactant B exposure phase 140 A. Optionally, reactant B exposure phase 140 A may include a controlled flow of a suitable inert gas, which, as described above, may assist with pressure and/or temperature control of the process station, evaporation of a liquid precursor, more rapid delivery of the precursor and may prevent back-diffusion of process station gases. In the embodiment shown in FIG. 11, an inert gas is continually supplied to the process station throughout reactant B exposure phase 140 A.

In some embodiments, plasma activation of deposition reactions may result in lower deposition temperatures than in thermally-activated reactions, potentially reducing consumption of the available thermal budget of an integrated process. For example, in some embodiments, a plasma activated CFD process may occur at room temperature.

While the CFD process embodiment depicted in FIG. 1 is plasma activated, it will be appreciated that other non-thermal energy sources may be used within the scope of the present disclosure. Non-limiting examples of non-thermal energy sources include, but are not limited to, ultraviolet lamps, downstream or remote plasma sources, inductively-coupled plasmas, and microwave surface wave plasmas.

Further, while many examples discussed herein include two reactants (A and B), it will be appreciated that any suitable number of reactants may be employed within the scope of the present disclosure. In some embodiments, a single reactant and an inert gas used to supply plasma energy for a surface decomposition reaction of the reactant may be used. Alternatively, as discussed above in the context of feature 7, some embodiments may use three or more reactants to deposit a film.

In some scenarios, surface adsorbed B species may exist as discontinuous islands on the substrate surface, making it difficult to achieve surface saturation of reactant B. Various surface conditions may delay nucleation and saturation of reactant B on the substrate surface. For example, ligands released on adsorption of reactants A and/or B may block some surface active sites, preventing further adsorption of reactant B. Accordingly, in some embodiments, continuous adlayers of reactant B may be provided by modulating a flow of and/or discretely pulsing reactant B into the process station during reactant B exposure phase 140 A. This may provide extra time for surface adsorption and desorption processes while conserving reactant B compared to a constant flow scenario.

Additionally or alternatively, in some embodiments, one or more sweep phases may be included between consecutive exposures of reactant B. For example, the embodiment of FIG. 2 schematically shows an example CFD process timing diagram 200 for a deposition cycle 210. At reactant B exposure phase 240A, reactant B is exposed to the substrate surface. Subsequently, at sweep phase 260A, reactant B is turned off, and gas phase species of reactant B are removed from the process station. In one scenario, gas phase reactant B may be displaced by a continuous flow of reactant A and/or the inert gas. In another scenario, gas phase reactant B may be removed by evacuating the process station. Removal of gas phase reactant B may shift an adsorption/desorption process equilibrium, desorbing ligands, promoting surface rearrangement of adsorbed B to merge discontinuous islands of adsorbed B. At reactant B exposure phase 240B, reactant B is again exposed to the substrate surface. While the embodiment shown in FIG. 2 include one instance of a reactant B sweep and exposure cycle, it will be appreciated that any suitable number of iterations of alternating sweep and exposure cycles may be employed within the scope of the present disclosure.

Returning to the embodiment of FIG. 1, prior to activation by the plasma at 180A, gas phase reactant B may be removed from the process station in sweep phase 160A in some embodiments. A CFD cycle may include one or more sweep phases in addition to the above-described exposure phases. Sweeping the process station may avoid gas phase reactions where reactant B is susceptible to plasma activation. Further, sweeping the process station may remove surface adsorbed ligands that may otherwise remain and contaminate the film. Examples sweep gases include, but are not limited to, argon, helium, and nitrogen. In the embodiment shown in FIG. 1, sweep gas for sweep phase 160A is supplied by the inert gas stream. In some embodiments, sweep phase 160A may include one or more evacuation subphases for evacuating the process station. Alternatively, it will be appreciated that sweep phase 160 A may be omitted in some embodiments. Sweep phase 160A may have any suitable duration. In some embodiments, increasing a flow rate of a one or more sweep gases may decrease the duration of sweep phase 160A. For example, a sweep gas flow rate may be adjusted according to various reactant thermodynamic characteristics and/or geometric characteristics of the process station and/or process station plumbing for modifying the duration of sweep phase 160A. In one non-limiting example, the duration of a sweep phase may be optimized by adjustment of the sweep gas flow rate. This may reduce deposition cycle time, which may improve substrate throughput.

A CFD cycle, typically includes an "activation phase" in addition to the exposure and optional sweep phases described above. The activation phase serves to drive the reaction of the one or more reactants adsorbed on the substrate surface. At plasma activation phase 180A of the embodiment shown in FIG. 1, plasma energy is provided to activate surface reactions between surface adsorbed reactants A and B. For example, the plasma may directly or indirectly activate gas phase molecules of reactant A to form reactant A radicals. These radicals may then interact with surface adsorbed reactant B, resulting in film-forming surface reactions. Plasma activation phase 180A concludes deposition cycle 11 OA, which in the embodiment of FIG. 1 is followed by deposition cycle HOB, commencing with reactant A exposure phase 120B.

In some embodiments, the plasma ignited in plasma activation phase 180A may be formed directly above the substrate surface. This may provide a greater plasma density and enhanced surface reaction rate between reactants A and B. For example, plasmas for CFD processes may be generated by applying a radio frequency (RF) field to a low-pressure gas using two capacitively coupled plates. In alternative embodiments, a remotely generated plasma may be generated outside of the main reaction chamber. Any suitable gas may be used to form the plasma. In a first example, and inert gas such as argon or helium may be used to form the plasma. In a second example, a reactant gas such as oxygen or ammonia may be used to form the plasma. In a third example, a sweep gas such as nitrogen may be used to form the plasma. Of course, combinations of these categories of gases may be employed. Ionization of the gas between the plates by the RF field ignites the plasma, creating free electrons in the plasma discharge region. These electrons are accelerated by the RF field and may collide with gas phase reactant molecules. Collision of these electrons with reactant molecules may form radical species that participate in the deposition process. It will be appreciated that the RF field may be coupled via any suitable electrodes. Non- limiting examples of electrodes include process gas distribution showerheads and substrate support pedestals. It will be appreciated that plasmas for CFD processes may be formed by one or more suitable methods other than capacitive coupling of an RF field to a gas.

Plasma activation phase 180A may have any suitable duration. In some embodiments, plasma activation phase 180A may have a duration that exceeds a time for plasma-activated radicals to interact with all exposed substrate surfaces and adsorbates, forming a continuous film atop the substrate surface. For example, the embodiment shown in FIG. 1 includes a plasma post-saturation exposure time 190 in plasma activation phase 180A. As explained more fully below, and as suggested in the discussion of feature 4 above, extending a plasma exposure time and/or providing a plurality of plasma exposure phases may provide a post-reaction treatment of bulk and/or near-surface portions of the deposited film. In one scenario, decreasing surface contamination by plasma treatment may prepare the surface for adsorption of reactant A. For example, a silicon nitride film formed from reaction of a silicon-containing reactant and a nitrogen-containing reactant may have a surface that resists adsorption of subsequent reactants. Treating the silicon nitride surface with a plasma may create hydrogen bonds for facilitating subsequent adsorption and reaction events.

In some embodiments, film properties, such as film stress, dielectric constant, refractive index, etch rate may be adjusted by varying plasma parameters, which will be discussed in more detail below. Table 3 provides an example list of various film properties for three example CFD silicon dioxide films deposited at 400 degrees Celsius. For reference purposes, Table 3 also includes film information for an example PECVD silicon dioxide film deposited at 400 degrees Celsius.

Figure imgf000029_0001
Figure imgf000030_0001

For example, FIG. 3 schematically shows an embodiment of a CFD process timing diagram 300 including a deposition phase 310 followed by a plasma treatment phase 390. It will be appreciated that any suitable plasma may be used during a plasma treatment phase. In a first scenario, a first plasma gas may be used during activation in the deposition cycle and a second, different plasma gas may be used during a plasma treatment phase. In a second scenario, a second, different plasma gas may supplement a first plasma gas during the plasma treatment phase. Non-limiting parameter ranges for an example in-situ plasma treatment cycle are provided in Table 4.

Figure imgf000030_0002

At plasma activation phase 380 shown in FIG. 3, the substrate surface is exposed to a plasma to activate a film deposition reaction. As depicted in the embodiment shown in FIG. 3, the process station is provided with a continuous flow of reactant A, which may be, e.g., an auxiliary reactant such as oxygen, and an inert gas at plasma treatment sweep phase 390 A. Sweeping the process station may remove volatile contaminants from the process station. While a sweep gas is shown in FIG. 3, it will be appreciated that any suitable reactant removal method may be used within the scope of the present disclosure. At plasma treatment activation phase 390B, a plasma is ignited to treat the bulk and/or near-surface region of the newly deposited film.

While the embodiment of FIG. 3 includes one instance of a CFD cycle including a plasma treatment phase, it will be appreciated that any suitable number of iterations may be employed within the scope of the present disclosure. Further, it will be appreciated that one or more plasma treatment cycles may be inserted at intervals (regular or otherwise) between normal deposition cycles. For example, FIG. 4 shows an embodiment of a CFD process timing diagram 400 including a plasma treatment phase inserted between two deposition cycles. While the embodiment of FIG. 4 includes a plasma treatment cycle inserted between two deposition cycles, it will be appreciated that any suitable number of deposition cycles may precede or follow one or more plasma treatment cycles. For example, in a scenario where a plasma treatment is used to alter a film density, a plasma treatment cycle may be inserted after every tenth deposition cycle. In a scenario where a plasma treatment is used to prepare a surface for adsorption and reaction events, a plasma treatment phase may be incorporated in every CFD cycle, e.g., after each CFD deposition phase.

Plasma treatment of the deposited film may alter one or more physical characteristics of the film. In one scenario, a plasma treatment may densify a newly deposited film. Densified films may be more etch-resistant than non-densified films. For example, FIG. 5 shows an embodiment of a comparison 500 of etch rates for example CFD processed silicon dioxide films relative to thermally grown silicon dioxide films. The example film embodiments of FIG. 5 were deposited over a range of temperatures from 50 to 400 degrees Celsius by CFD processes 502 and 504. For reference, relative etch rates for undoped silicate glass (USG) and silicon dioxide spacer layers deposited by plasma-enhanced CVD processes are displayed in FIG. 5. Films produced by process 502, which included a one-second high-frequency oxygen plasma activation phase in each deposition cycle, were approximately one-half as resistant to a dilute hydrofluoric acid wet etch (100: 1 H20:HF) as film 504, which included a ten-second high-frequency oxygen plasma activation phase in each deposition cycle. Accordingly, it will be appreciated that varying one or more aspects of the plasma activation phase and/or including one or more plasma treatment cycles may vary an etch rate of a deposited film. In another scenario, plasma treatment of a film may vary the stress characteristics of the film. For example, FIG. 6 shows an embodiment of a correlation 600 between wet etch rate ratio and film stress for example CFD silicon dioxide films. In the embodiment shown in FIG. 6, decreases in the wet etch rate ratio by, for example, extending a plasma exposure time, may increase a compressive film stress.

In another scenario, plasma treatment of a deposited film may provide transient differential removal of trace film contaminants (e.g., hydrogen, nitrogen and/or carbon in an example silicon dioxide film) relative to other film constituents (e.g., silicon and/or oxygen in an example silicon dioxide film). For example, FIG. 7 shows an embodiment of a correlation 700 between deposition temperature, plasma exposure time, and film contaminant concentrations. In the embodiment shown in FIG. 7, a CFD silicon dioxide film 704 deposited at 50 degrees Celsius and having a ten-second oxygen plasma activation phase exhibits lower concentrations of hydrogen and carbon than a CFD silicon dioxide film 702 deposited at the same temperature but having a one-second oxygen plasma activation phase. Modifying contaminant concentrations in a film may modify electrical and/or physical properties of the film. For example, modulating carbon and/or hydrogen content may modulate a film dielectric constant and/or a film etch rate. Accordingly, it will be appreciated that varying one or more aspects of the plasma activation phase and/or including one or more plasma treatment cycles may provide an approach for varying film composition.

While the plasma treatment discussed above relates to an oxygen plasma treatment, it will be appreciated that any suitable plasma treatment may be employed without departing from the scope of the present embodiment. For example, in some embodiments a substituted amine may be employed as a nitrogen-containing reactant in a suitable CFD process in place of NH3. Although replacement of NH3 with a substituted amine (e.g., an alkyl amine like t-butyl amine) for conformal SiN deposition may provide a number of benefits, in some instances, the deposited film may include carbon residue originating from the alkyl amine reactant (e.g., carbon residue from the three methyl groups included each t-butyl amine molecule (NH2- (CH3)3)). This in-film carbon may result in electrical leakage and may render the film unusable for some dielectric barrier applications.

Thus, in some embodiments, igniting a hydrogen plasma during SiN film deposition may reduce carbon residue in the SiN film, which may comparatively improve the insulating character of the film. In some examples, the reduction in carbon residue may be readily observable in FTIR spectra. For example, the SiN:C-H levels may be reduced from approximately 10% atomic to approximately 1% atomic.

Therefore, in some embodiments, a silicon nitride film may be deposited with a CFD process using an alkyl amine or a mixture of alkyl amines included in the nitrogen-containing reactant and one or more instances of a hydrogen plasma treatment. It will be appreciated that any suitable hydrogen plasma may be employed without departing from the scope of the present disclosure. Thus, in some embodiments, an admixture of H2 with a gas such as He or Ar, or other H-containing gases, or active H atoms produced by a remote plasma source, may be used to treat the deposited film. Further, in some embodiments, the carbon content of the film may be tuned to any suitable concentration by varying one or more of the number of treatment pulses and their duration, the intensity of the treatment plasma, the substrate temperature, and the treatment gas composition.

While the hydrogen plasma treatment discussed above relates to a silicon nitride film, it will be appreciated that application of a suitable hydrogen plasma treatment may be used to adjust the carbon content of other CFD deposited films, including, but not limited to, SiOx, GeOx, and SiOxNy.

Certain embodiments disclosed herein pertain to ultraviolet treatment (with or without plasma treatment) of oxide CFD films. The treatment may mitigate defects in the oxide and improve electrical properties such as CV characteristics of a gate dielectric. Device and package applications employing CFD oxides that can benefit from such treatment include thru-silicon vias, logic technology employing gate oxides, shallow trench isolation (STI), thin thermal oxidation formed after STI- photoresist strip, sacrificial oxide (e.g., ~60A) before a P-well implant, post "well" thermal oxide growth, gate/channel oxide, DRAM PMD PECVD Oxide..

In some cases, untreated CFD oxide films have been observed to have relatively poor electrical performance due to, it is believed, fixed charge in the as deposited film. For example, some films have been found to have significant within- wafer Vfb variations. Such problems have been resolved by using a post-deposition treatment with UV-radiation and/or a thermal anneal in the presence of hydrogen. It is believed that this process passivates and/or alleviates defects related to fixed charge at the (1) oxide to silicon interface or (2) within the deposited dielectric film or (3) at the air to oxide surface (surface charge). Using such treatment, the Vfb spread for as deposited oxide has been tightened from 8.3V to about 1.5V after UV cure. While the these embodiments are primarily concerned with improving oxide films, the disclosed method may be applied generally to the growth of dielectrics, metals, metal to dielectric interface engineering. Specific dielectric materials include, for example, silicon oxides, including doped silicon oxides, silicon carbides, silicon oxycarbides, silicon nitrides, silicon oxynitrides, and ashable hard mask materials.

Examples of treatments that may be applied to improve dielectric properties include the following:

(A) Post deposition treatment of dielectric films synthesized by CFD with UV cure and then hydrogen-anneal. In the simplest embodiment, UV treatment may be used alone to reduce fixed charge.

(B) Pre-treatment of the substrate prior to CFD-dielectric film deposition with treatments including: H2-plasma, N2-plasma, N2/H2-plasma, NH3-plasma, Ar-plasma, He-plasma, He anneal, H2-anneal, NH3-anneal, and UV cure in the presence of He, H2, Ar, N2, H2/N2-forming gas, NH3. Plasma processing may be enabled with various plasma generators including, though not limited to, microwave, ICP-remote, direct and the like.

(C) Concurrent treatment (curing during deposition) with treatments including: H2-plasma, N2-plasma, N2/H2-plasma, NH3-plasma, Ar-plasma, He-plasma, He anneal, H2-anneal, NH3-anneal, and UV cure in the presence of He, H2, Ar, N2, H2/N2-forming gas, NH3. Plasma processing may be implemented with various plasma generators including, though not limited to, microwave, ICP-remote, direct and others known to those in the art. Isotropic and directional processing may be applied including, though not limited to, remote plasma, UV exposure, direct plasma, and microwave plasma. An example method includes intermittent treatment of the film between groups of CFD cycles. A group of CFD cycles may vary from about 1 to lOOOOcycles. A typical scenario includes: (1) 5 cycles of CFD oxide growth followed by (2) one or more film treatments with any of the methods described above (e.g., He-plasma, UV-treatment), followed by (3) 5cycles of CFD oxide growth. This method may be used to grow a film of any desired thickness. (D) UV treatment imparted as byproduct by any plasma listed above (e.g., a helium plasma emits UV radiation).

One example of a procedure for in situ "cure" during the CFD cycling involves the following operations:

UV treatment via He-plasma BTBAS dose

Purge

02/Ar-RF plasma activation

Purge

Repeat steps 1-5 to yield a film of desired thickness.

A range of UV cure conditions may be employed in any of the listed contexts. Generally, the pedestal temperature will be maintained between about 250 and 500C during the cure. For many device fabrication applications, the upper temperature will be limited to 450C or even 400C. The ambient employed during the cure may be inert or reactive. Examples of gases that may be present during the cure include helium, argon, nitrogen, forming gas, and ammonia. The flow rate of such gases may be about 2 to 20,000 seem, preferably about 4000 to 18,000 seem. The power of the UV lamp may, for example, about 2-10 kW, and preferably between about 3.5 and 7 kW. An appropriate duration of exposure to UV from such source is between about 20 and 200 seconds (e.g., about 90 seconds). Finally, the pressure may be held at a level between 0 Torr and about 40 Torr.

In a specific embodiment, an effective treatment of CFD oxide was obtained using the following conditions:

Pedestal temperature = 400C Ambient = He

Pressure 40 Torr He

Flow rate 10,000 seem

In some embodiments, a thermal anneal of the oxide is performed after the UV cure operation. In one example, the following conditions were used in the anneal:

Ped T = 400C Ambient = H2 + N2 Pressure = 2.5 Ton- Flow rates = 750 seem H2 ; 3000 seem N2 The physical and electrical characteristics of the deposited film may also be altered by adjusting other process parameters, such as deposition temperature. For example, correlation 700 of the embodiment depicted in FIG. 7 also shows an example relationship between CFD film deposition temperature and film contaminants concentration. As film deposition temperature increases, incorporation of film contaminants decreases. In another example, the embodiment shown in FIG. 5 illustrates that a wet etch rate ratio of example silicon dioxide CFD films decreases as deposition temperature increases, as described above. Other deposition parameters that may be adjusted to tune the film properties include RF power, RF frequency, pressure, and flow rates. Further, in some embodiments, film characteristics may be altered by altering a reactant selection. For example, a hydrogen content of a silicon dioxide film may be reduced by using tetra isocyanate silane (TICS) as a silicon- containing reactant and oxygen and/or nitrous oxide as an oxygen-containing reactant.

It will be appreciated that variation of physical and/or electrical film characteristics, like those discussed above, may provide opportunities to adjust device performance and yield, as well as opportunities to modify aspects of device manufacturing process integration. As one non-limiting example, the ability to tune etch rate characteristics of a CFD silicon dioxide film may make the film a candidate for etch stop, hard mask, and other process integration applications. Accordingly, various embodiments of CFD-produced films are provided herein for application throughout an integrated semiconductor device fabrication process.

In one scenario, a CFD process may deposit a conformal silicon dioxide film on a non-planar substrate. For example, a CFD silicon dioxide film may be used for gap fill of structures, such as a trench fill of shallow trench isolation (STI) structures. While the various embodiments described below relate to a gap fill application, it will be appreciated that this is merely a non-limiting, illustrative application, and that other suitable applications, utilizing other suitable film materials, may be within the scope of the present disclosure. Other applications for CFD silicon dioxide films include, but are not limited to, interlayer dielectric (ILD) applications, intermetal dielectric (IMD) applications, pre-metal dielectric (PMD) applications, dielectric liners for through-silicon via (TSV) applications, resistive RAM (ReRAM) applications, and/or stacked capacitor fabrication in DRAM applications.

Doped silicon oxide may be used as a diffusion source for boron, phosphorus, or even arsenic dopants. For example, a boron doped silicate glass (BSG), a phosphorus doped silicate glass (PSG), or even a boron phosphorus doped silicate glass (BPSG) could be used. Doped CFD layers can be employed to provide conformal doping in, for example, three-dimensional transistor structures such as multi-gate FinFET's and three-dimensional memory devices. Conventional ion implanters cannot easily dope sidewalls, especially in high aspect ratio structures. CFD doped oxides as diffusion sources have various advantages. First, they provide high conformality at low temperature. In comparison, low-pressure CVD produced doped TEOS (tetraethylorthosilicate) is known but requires deposition at high temperature, and sub-atmospheric CVD and PECVD doped oxide films are possible at lower temperature but have inadequate conformality. Conformality of doping is important, but so is conformality of the film itself, since the film typically is a sacrificial application and will then need to be removed. A non-conformal film typically faces more challenges in removal, i.e. some areas can be overetched. Additionally, CFD provides extremely well controlled doping concentration. As mentioned, a CFD process can provide from a few layers of undoped oxide followed by a single layer of doping. The level of doping can be tightly controlled by the frequency with which the doped layer is deposited and the conditions of the doping cycle. In certain embodiments, the doping cycle is controlled by for instance using a dopant source with significant steric hindrance. In addition to conventional silicon- based microelectronics, other applications of CFD doping include microelectronics and optoelectronics based on III-V semiconductors such as GaAs and II- VI semiconductors such as HgCdTe, photovoltaics, flat panel displays, and electrochromic technology.

Some gap fill processes involve two film deposition steps performed on different deposition tools, requiring a vacuum break and air exposure between deposition processes. FIG. 8 schematically shows an example non-planar substrate 800 including a plurality of gaps 802. As depicted in FIG. 8, gaps 802 may have varying aspect ratios, which may be defined as a ratio of gap depth (H) to gap width (W) for each gap 802. For example, a logic area of an integrated semiconductor device may have varying gap aspect ratios corresponding to different logic device structures. As depicted in FIG. 8, non-planar substrate 800 is covered by a thin, conformal film 804. While conformal film 804 has completely filled gap 802A, gaps 802B and 802C remain open. Closing gaps 802B and 802C with a conformal film may lead to extended process times. Thus, in some approaches, a thicker film may be deposited ex-situ by a higher deposition rate process, such as a CVD and/or PECVD method. However, ex-situ deposition of gap fill films may reduce wafer throughput in a production line. For example, substrate handling and transfer time between a deposition tools may reduce a number of substrate processing activities during a production period. This may diminish production line throughput and may require the installation and maintenance of additional process tools in the production line.

Further, while gap 802C may have an aspect ratio suitable for a gas-phase deposition process, 802B may have an aspect ratio that may lead to incomplete filling by a higher deposition rate process and may form a keyhole void. For example, FIG. 10 shows an example high aspect ratio structure 1000 formed in substrate 1002. As depicted in FIG. 10, bread loafing effects during the deposition of thicker film 1006 have produced keyhole void 1008. Keyhole voids may be re-opened and filled with conductive films in subsequent processes, which may lead to device shorting. Some approaches to addressing high aspect ratio gaps such as gap 802B include providing device design rules that avoid creation of such gaps. However, such design rules may require additional masking steps, may make device design difficult, and/or may lead to increased integrated semiconductor device area, which may increase manufacturing cost. Thus, in some embodiments, a CFD process may include an in-situ transition from a CFD process to a CVD and/or a PECVD process. For example, FIG. 9 shows an embodiment of a CFD process timing diagram 900 that has been divided into three phases. CFD process phase 902 depicts an example CFD process cycle. For clarity, a single CFD process cycle is shown in the embodiment depicted in FIG. 9, though it will be appreciated that any suitable number of CFD process cycles and plasma treatment cycles may be included in CFD process phase 902. A transition phase 904 follows CFD process phase 902. As depicted in the embodiment of FIG. 9, transition phase 904 includes aspects of both a CFD process and a PECVD process. Specifically, reactant B is provided to the process station past the end of reactant B exposure phase 904A so that reactants A and B are both present in the gas phase during plasma activation phase 904B. This may provide PECVD- type gas phase reactions concurrently with CFD-type surface reactions. While transition phase 904 includes only one iteration of reactant B exposure phase 904A and plasma activation phase 904B, it will be appreciated that any suitable number of iterations may be included within a transition phase. In some embodiments, a plasma generator may be controlled to provide intermittent pulses of plasma energy during plasma activation phase 904B. For example, the plasma may be pulsed at one or more frequencies including, but not limited to, frequencies between of 10 Hz and 150 Hz. This may enhance step coverage by reducing a directionality of ion bombardment in comparison to a continuous plasma. Further, this may reduce ion bombardment damage to the substrate. For example, photoresist substrates may be eroded by ion bombardment during a continuous plasma. Pulsing the plasma energy may reduce photoresist erosion.

In the embodiment shown in FIG. 9, the flow rate of reactant B during plasma activation phase 904B is less than the flow rate of reactant B during reactant B exposure phase 904A. Thus, reactant B may be "trickled" into the process station during plasma activation phase 904B. This may provide a gas-phase PECVD reaction supplementing the CFD-type surface reactions. However, it will be appreciated that, in some embodiments, flow rate of reactant B may be varied during a single plasma activation phase or over the course of a transition phase. For example, in a transition phase including two iterations of reactant B exposure and plasma activation, a flow rate of reactant B during a first plasma activation phase may be lower than a flow rate of reactant B during the second plasma activation phase. Varying a flow rate of reactant B during plasma activation phase 904B may provide a smooth transition from the step-coverage characteristics of CFD process phase 902 to the deposition rate characteristics of PECVD process phase 906.

In some embodiments, a CFD process may include an in-situ etch for selectively removing a re-entrant portion of deposited film. Non-limiting parameter ranges for an example silicon dioxide deposition process including an in-situ etch for

Figure imgf000039_0001
Figure imgf000040_0001

FIG. 11 shows an embodiment of a CFD process timing diagram 1100 including a deposition phase 1102, an etch phase 1104, and a subsequent deposition phase 1106. At deposition phase 1102 of the embodiment shown in FIG. 11, film is deposited onto the exposed surfaces of the substrate. For example, deposition phase 1102 may include one or more CFD process deposition cycles.

At etch phase 1104 of the embodiment of FIG. 11, reactants A and B are turned off and an etch gas is introduced to the process station. One non-limiting example of an etch gas is nitrogen trifluoride (NF3). In the embodiment depicted in FIG. 11, the etch gas is activated by a plasma ignited during etch phase 1104. Various process parameters, such as process station pressure, substrate temperature, etch gas flow rate, may be adjusted during etch phase 1104 for selectively removing a re-entrant portion of a deposited film on a non-planar substrate. Any suitable etch process may be employed within the scope of the present disclosure. Other example etch processes include, but are not limited to, reactive ion etching, non-plasma vapor phase etching, solid phase sublimation, and adsorption and directional activation (e.g., by ion bombardment) of the etch species.

In some embodiments, incompatible gas phase species may be removed from the process station before and after etching the film. For example, the embodiment of FIG. 11 includes a continuous flow of an inert gas after reactants A and B have been turned off and after the etch gas has been turned off during etch phase 1104.

At the conclusion of etch phase 1104, a deposition phase 1106 begins, further filling gaps on the non-planar substrate. Deposition phase 1106 may be any suitable deposition process. For example, deposition phase 1106 may include one or more of a CFD process, a CVD process, a PECVD process, etc. While the embodiment of FIG. 11 shows a single etch phase 1104, it will be appreciated that a plurality of in- situ etch processes may be inserted at intervals among multiple deposition phases of any suitable type during a gap fill process.

FIGS. 12A-C depict example cross-sections of a non-planar substrate at various phases of an embodiment of the in-situ deposition and etch processes described above. FIG. 12A shows a cross-section of an example non-planar substrate 1200, including a gap 1202. Gap 1202 is covered with a thin film 1204. Thin film 1204 is nearly conformal with gap 1202, but thin film 1204 includes a re-entrant portion 1206 near the top of gap 1202.

In the embodiment depicted in FIG. 12B, re-entrant portion 1206 of thin film 1204 has been selectively removed and that an upper region 1204 A of thin film 1204 is thinner than a lower region 1204B. Selective removal of the re-entrant portion and/or sidewall angle adjustment may be achieved by imposing mass transfer limitations and/or lifetime limitations on the active etch species. In some embodiments, selective etching at the top of gap 1202 may also adjust a sidewall angle of gap 1202, so that gap 1202 is wider at the top than at the bottom. This may further reduce bread loafing effects in subsequent deposition phases. In the embodiment shown in FIG. 12C, after a subsequent deposition phase, gap 1202 is nearly filled and exhibits no voids.

Another embodiment of an in-situ etch process is shown in FIG. 15, which depicts a through-silicon via (TSV) 2500 for a copper electrode. Some example TSVs have depths of approximately 105 microns and diameters of approximately 6 microns, giving an approximately 17.5:1 aspect ratio, and may have a thermal budget ceiling of approximately 200 degrees Celsius. As shown in the embodiment of FIG. 15, through-silicon via 2500 is covered by a dielectric isolation layer 2502 to electrically isolate a silicon substrate from a metal-filled via. Example dielectric isolation layer materials include, but are not limited to, silicon oxide, silicon nitride, a low-k dielectric material. In some embodiments, the example etch processes described above may be supplemented with physical sputtering of the re-entrant portion using a suitable sputter gas, such as argon.

Other example applications for CFD films include, but are not limited to conformal low-k films (e.g., k approximately 3.0 or lower in some non-limiting examples) for back-end-of-line interconnect isolation applications, conformal silicon nitride films for etch stop and spacer layer applications, conformal antireflective layers, and copper adhesion and barrier layers. Many different compositions of low-k dielectrics for BEOL processing can be fabricated using CFD. Examples include silicon oxides, oxygen doped carbides, carbon doped oxides, oxynitrides, and the like.

In another example, in one integrated process scenario, a silicon dioxide spacer layer may be deposited over a photoresist "core." Use of a photoresist core instead of an alternative core material (such as a silicon carbide layer) may eliminate a patterning step in the integrated process. The process may involve patterning photoresist using normal lithographic techniques and then depositing a thin layer of CFD oxide directly over that core. A directional dry etch process may be then used to remove the CFD oxide film at the top of the patterned photoresist and at the bottom leaving only material along the sidewall of the patterned photoresist (consider trenches). At this stage, simple ashing can be used to remove the exposed core leaving behind the CFD oxide. Where once there was a single photoresist line, now there are two CFD-oxide lines. In this manner the process doubles the pattern density; hence it is sometimes referred to as "double patterning". Unfortunately, use of a photoresist core may limit a spacer layer deposition temperature to less than 70 degrees Celsius, which may be less than deposition temperatures for conventional CVD, PECVD, and/or ALD processes. Thus, in some embodiments, a low temperature CFD silicon dioxide film may be deposited at temperatures below 70 degrees Celsius. It will be appreciated that other potential integrated process applications exist for suitable CFD-generated films within the scope of the present disclosure. Additionally, in various embodiments, a nitride such as a silicon nitride deposited as above may be employed as a conformal diffusion barrier layer and/or etch stop in various stages of semiconductor device manufacture. While the various CFD deposition processes described above have been directed at depositing, treating, and/or etching single film types, it will be appreciated that some CFD processes within the scope of the present disclosure may include in- situ deposition of a plurality of film types. For example, alternating layers of film types may be deposited in-situ. In a first scenario, a double spacer for a gate device may be fabricated by in-situ deposition of a silicon nitride/silicon oxide spacer stack. This may reduce cycle time and increase process station throughput, and may avoid interlay er defects formed by potential film layer incompatibility. In a second scenario, an antireflective layer for lithographic patterning applications may be deposited as a stack of SiON or amorphous silicon and SiOC with tunable optical properties. In certain embodiments, a dopant containing source layer is formed by a conformal film deposition process. The layer is termed a "source" layer because it provides a source of dopant species (e.g., dopant atoms such as boron, phosphorus, gallium, and/or arsenic). The doped CFD layer serves as a source of dopant for doping an underlying (or overlying) structure in a device. After the source layer is formed (or during its formation), the dopant species are driven or otherwise incorporated into adjacent structures in the device being fabricated. In certain embodiments, the dopant species are driven by an annealing operation during or after forming the conformal dopant source film. The highly conformal nature of CFD permits doping non-conventional device structures, including structures which require doping in three dimensions. The CFD dopant source layer is typically formed by one or more of the processes described herein, but includes the additional process operation of incorporating a dopant species. In some embodiments, a dielectric layer serves as the base source layer into which the dopant species is incorporated.

For example, doped silicon oxide may be used as a diffusion source for boron, phosphorus, arsenic, etc. For example, a boron doped silicate glass (BSG), a phosphorus doped silicate glass (PSG), or a boron phosphorus doped silicate glass (BPSG) can be used.

Doped CFD layers can be employed to provide conformal doping in, for example, three-dimensional transistor structures such as multi-gate FinFETs and three-dimensional memory devices. Examples of some three-dimensional structures can be found at "Tri-gate (Intel)": J.Kavalieros et al, Symp. VLSI Tech Pg 50, 2006 AND "FinFET: Yamashita et al. (IBM Alliance), VLSI 2011, both incorporated herein by reference in their entireties. Conventional ion implanters cannot easily dope sidewalls, especially in high aspect ratio structures. Additionally, in a dense array of i3D structures, there can be shadowing effects for the directional ion beam in an implanter, giving rise to serious dose retention problems for tilted implant angles. In addition to conventional silicon-based microelectronics, other applications of CFD doping include microelectronics and optoelectronics based on III-V semiconductors such as GaAs and II-VI semiconductors such as HgCdTe, photovoltaics, flat panel displays, and electrochromic technology. Figure 16 illustrates a transistor having a three-dimensional gate structure, in which the source and drain are formed in thin vertical structures that are difficult to dope by conventional ion implantation techniques. However, when a thin layer of n or p-doped CFD oxide is formed over the vertical structures conformal doping is accomplished. Conformal doping has been observed to increase current density in three-dimensional devices by 10-25% due to decreased series resistance. See

Yamashita et al, VLSI 2011. CFD doped oxides as diffusion sources have various advantages. First, they provide high conformality at low temperature. Because the doping film may be sacrificial, a non-conformal film typically faces more challenges in removal, i.e. some areas can be overetched. As explained, CFD provides highly conformal films.

Additionally, CFD provides extremely well controlled doping concentration. A CFD process can provide one or more layers of undoped oxide followed by a single layer of doping, as needed. The level of doping can be tightly controlled by the frequency with which the doped layer is deposited and the conditions of the doping cycle. In certain embodiments, the doping cycle is controlled by, for instance using a dopant source with significant steric hindrance.

Figure 17 presents a baseline CFD sequence of operations from left to right with advancing time along the x axis. Numerous variations are supported, and this figure is presented for purposes of illustration only. Initially in the sequence, during an operation A, a vapor phase oxidant is introduced into the reaction chamber that contains the substrate onto which the CFD films to be deposited. Examples of suitable oxidants include elemental oxygen (e.g., 02 or 03), nitrous oxide (N20), water, alkyl alcohols such as isopropanol, carbon monoxide, and carbon dioxide. The oxidant is typically provided together with an inert gas such as argon or nitrogen.

Next, in an operation B, a dielectric precursor is temporarily introduced into the reaction chamber. The duration of operation B is chosen to allow the precursor to adsorb onto the substrate surface in an amount sufficient to support one cycle of film growth. In some embodiments, the precursor saturates the substrate surface. The precursor will be chosen for its ability to produce a dielectric of the desired composition. Examples of dielectric compositions include silicon oxides (including silicate glasses), silicon nitrides, silicon oxynitrides, and silicon oxycarbides.

Examples of suitable precursors include alkylamino silanes (SiHx(NR2)4_x) where x = 1-3, and R includes alkyl groups such as methyl, ethyl, propyl, and butyl in various isomeric configurations) and halosilanes (SiHxY4_x) where x = 1-3, and Y includes CI, Br, and I). More specific examples include bis-alkylamino silanes and sterically hindered alkyl silanes. In one specific example, BTBAS is a precursor for producing silicon oxide.

During operation B, the oxidant which was introduced into the chamber during phase A continues to flow. In certain embodiments, it continues to flow at the same rate and in the same concentration as during operation A. At the conclusion of operation B, the flow of dielectric precursor into the chamber is terminated and an operation C begins as depicted. During operation C, the oxidant and inert gas continues to flow as during operations A and B to purge the remaining dielectric precursor in the reaction chamber.

After the purge is completed during operation C, the precursor is reacted on the substrate surface to form a portion of the dielectric film (see operation D). In various embodiments, a plasma is applied to drive the reaction of the adsorbed dielectric precursor. In some examples, this reaction is an oxidation reaction. Some of the oxidant previously flowing into the reaction chamber may be adsorbed onto the surface along with the dielectric precursor, thus providing an immediately available oxidizing agent for the plasma-mediated surface reaction. Operations A through D collectively provide a single cycle of the dielectric film deposition process. It should be understood that other CFD embodiments described herein may be used in place of the basic cycle depicted here. In the depicted embodiment, the deposition cycle (A through D) is performed without introduction of any dopant species. In various embodiments, the cycle represented by operations A through D is repeated one or more times in succession prior to introduction of a dopant species. This is illustrated in phase E of Figure 17. In some examples, operations A-D are repeated at least once, or at least twice, or at least five times, prior to introduction of a dopant.

As an example, the dielectric is deposited at a rate of about 0.5 to 1

Angstroms/cycle. Through each of the one or more cycles (repetitions of A-D), the oxidant continues to flow into the reaction chamber.

At some point in the process, the cycles of dielectric deposition are interrupted by introduction of a dopant precursor species such as, e.g., diborane. This is illustrated as an operation F in the figure. Examples of dopants that may be provided in the dielectric source film include valence III and IV elements such as boron, gallium, phosphorous, arsenic, and other dopants. Examples of dopant precursors, in addition to diborane, include phosphine and other hydride sources. Non-hydride dopants such as alkyl precursors (e.g. trimethylgallium), haloprecursors (e.g. gallium chloride) can also be used. In some versions, dopant is deposited at the interface with the underlying substrate, followed by CFD cycles interspersed with dopant pulses every x number of cycles (as described), and optionally topped with an undoped protective "capping" layer may be a CFD oxide film. See an example of the resulting stack in Figure 18. In a specific embodiment, the dopant precursor species is provided to the reaction chamber in mixture with a carrier gas such as an inert gas (e.g., argon), but not with an oxidant or other reactant. Thus, in this baseline example, flow of the oxidant ceases during operation F. In other embodiments, the precursor is introduced together with a reducing agent or an oxidizing agent. In certain embodiments, the concentration of dopant to carrier gas between about 1 :5 and 1 :20. In certain embodiments, the dopant deposition temperature is between about 300 and 400°C. The duration of the dopant exposure step varies according to the targeted dopant concentration. In certain embodiments, the exposure step is between about 2.5s and 7.5s. In a specific example, 1000 seem of diborane is flowed in 10000 seem of argon at 3 Torr pressure and about 400C.

In certain embodiments, the dopant precursor collects on the substrate surface by a non-surface limited mechanism. For example, the precursor may deposit by CVD-type process rather than an ALD (surface adsorption limited) process.

Optionally the dopant precursor is purged from the reaction chamber prior to further processing of the dielectric film. Additionally, as depicted in the Figure 17, delivery of the dopant precursor is followed by an optional activation operation G, which may be mediated by plasma, elevated temperature, etc. In the example of diborane as the dopant precursor, the activation operation converts diborane to elemental boron. After operation G is complete, the process continues with an optional purge (not shown).

In one example, involving CVD diborane dopant, the activation operation is solely temperature based decomposition to produce boron. This is a temperature sensitive process. At higher temperatures, one may employ relatively short exposure times to target the same boron concentration per unit thickness. Alternatively, in some processes (e.g., those employing trimethylborane (TMB)), the activation may involve a plasma or thermal oxidation step. For some other precursors, it may be appropriate to employ a "pinning" step to hold the free boron or other dopant in place. This may be accomplished using a "pinning" plasma.

In certain embodiments, plasma activation involves RF power of any frequency suitable for incorporating carbon into the film. In some embodiments, the RF power supply may be configured to control high- and low- frequency RF power sources independently of one another. Example low-frequency RF powers may include, but are not limited to, frequencies between about 200 kHz and 1000 kHz. Example high-frequency RF powers may include, but are not limited to, frequencies between about 10 MHz and 80 MHz (e.g., 13.56 MHz). Likewise, RF power supplies and matching networks may be operated at any suitable power to form plasma.

Examples of suitable powers include, but are not limited to, powers between about 100 W and 3000 W for a high-frequency plasma and powers between about 100 W and 10000 W for a low-frequency plasma (on a per wafer basis). The RF power supply may be operated at any suitable duty cycle. Examples of suitable duty cycles include, but are not limited to, duty cycles of between about 5 % and 90 %. Generally acceptable process pressures are between about 0.5-5 Torr and preferably about 2- 4Torr. For certain plasma pretreatments (of the underlying substrate) prior to exposure to dopant, pressures up to about 10 Torr (or up to about 9 Torr) have been found to work well.

The following table summarizes ranges of plasma parameters that may be used for various BSG processes:

Figure imgf000047_0001

In the depicted baseline process, the cycles of dielectric deposition and intermittent dopant delivery (operations A through G) may be performed multiple times as shown in a phase H of the figure. The actual number of times that the process sequence is repeated depends upon the desired total thickness of the film and the thickness of the dielectric deposited per cycle, as well as the amount of dopant incorporated into the film. In some embodiments, operations A-G are repeated at least twice, or at least three time, or at least five times, or at least about ten times.

After the dielectric film is completely deposited, it may be used as a source of dopant species for nearby semiconductor structures. This may be accomplished by driving the dopant from the deposited film into the device structure as depicted at an operation I of Figure 17. In various embodiments, the driving is accomplished by a thermally mediated diffusion process such as an anneal. In some cases, particularly those employing ultra-shallow junctions, laser spike annealing may be employed.

Numerous variations on this baseline process may be realized. Some of these variations have as their goal increasing the amount of dopant available for diffusion into an adjacent semiconductor structure. Other variations are designed to control the rate at which the dopant is delivered from the source film into the nearby

semiconductor structure. Still other variations control the direction that the dopant species diffuse. Frequently, it is desirable to favor the diffusion of the dopant toward the device structure and away from the opposite side of the film.

In certain embodiments, the frequency with which a dopant is introduced into a growing dielectric film is controlled. More frequent dopant precursor delivery cycles result in an overall greater concentration of dopant in the final dielectric film. They also result in a relatively even distribution of dopant throughout the film. When fewer dopant precursor delivery cycles are inserted into the deposition process, the regions of high dopant concentration in the film are more widely separated than is the case when the dopant delivery cycles are more frequent.

In one embodiment, the dopant precursor is delivered to the growing dielectric film one time for each cycle of dielectric deposition. In another embodiment, the dopant precursor is delivered once during every other cycle of dielectric deposition. In other embodiments, less frequent dopant precursor delivery cycles are incorporated in the process. For example, the dopant precursor may be delivered once during every third, fourth, or fifth cycle of dielectric deposition. In some cases, the dopant precursor is delivered at a frequency of about once during every 5-20 dielectric deposition cycles.

It should be understood that the frequency of the dopant precursor introduction into the growing film need not be consistent over the course of the dielectric film deposition. With this in mind, the resulting dielectric film may have a graded composition of dopant such that the average concentration of dopant over the thickness of the deposit dielectric film is non-uniform. In one embodiment, the concentration of dopant is greater on the side of the dielectric film that abuts the semiconductor device structure to be doped. Of course, the dopant concentration gradient in the dielectric film can be tailored as desired by carefully varying the frequency of dopant delivery cycles over the course of the entire dielectric deposition process.

Another variation on the baseline process involves adjusting the amount of dopant precursor delivered during any dopant precursor delivery cycle. The amount of dopant precursor delivered during any given dopant delivery cycle will be determined by the concentration of dopant precursor delivered to the reaction chamber as well as the duration of the exposure of the substrate to be delivered dopant precursor. As indicated above, some dopant precursors may be provided on to the growing film via a CVD-like process. In such cases, the amount of dopant precursor delivered to the growing film in any given cycle is not limited by adsorption or other surface-mediated phenomenon. Therefore, the amount of dopant precursor provided during any cycle of dopant delivery can be relatively large and controllable. To the extent that greater amounts of dopant precursor are delivered during any dopant delivery cycle, the overall concentration of dopant in the dielectric film increases. This may offset the effect of having relatively infrequent dopant precursor delivery cycles in the overall process. However, it should be understood that increasing the amount of dopant delivered during any given dopant precursor delivery cycle may result in a relatively high local concentration of dopant in the film. Of course, such dopant concentration spike can be softened by annealing or other operation by which the dopant diffuses to make its concentration more uniform in the dielectric film.

In the case of boron being the dopant, the flux of boron delivered during a typical boron precursor delivery cycle may vary from about 7.5 ML (Mega-

Langmuirs) to 30ML depending on target film concentration, ML being a unit of flux/exposure.

In some embodiments, the amount of dopant precursor delivered in each precursor delivery cycle is not constant throughout the growth of the full dielectric film. Thus, the amount of dopant precursor delivered per cycle can be tailored to produce a desired dopant concentration gradient in the dielectric film. For example, it may be desirable to provide greater amounts of dopant precursor in those dopant precursor delivery cycles that occur at locations in the dielectric film that are relatively close to the semiconductor device feature to be doped. The resulting concentration gradient has a greater concentration of dopant in regions of the film that abut device structures to be doped.

In some embodiments, the dopant precursor is incorporated onto the substrate surface in an adsorption-limited matter. With such precursors, the introduction of dopant into the film proceeds via an ALD-like process (as opposed to a CVD-like manner as described above). Examples of dopant precursors that attach to the substrate surface by an absorption-mediated process include trimethyl borane, and other alkyl precursors such as trimethylgallium. Examples of dopant precursors that accumulate on substrate surface by a CVD-like process include diborane, phosphine, and arsine. In general, the concentration profile of the dopant in the dielectric film can be tailored as appropriate. In one embodiment, the dopant concentration spikes to a high level at the edge of the film adjacent to the structure to be doped. In some

embodiments, the concentration increases and decreases intermittently throughout the film thickness. In one example, the dopant (e.g., boron) is provided only at the interface between the underlying substrate and the CFD dielectric layer. This dopant layer is sometimes referred to as a "spike layer." In some cases, pulsing the dopant exposure (using for example CVD exposure to a dopant precursor), rather than employing a single-step increases the within wafer uniformity of dopant

incorporation. In another example, the CFD oxide or other dielectric is interspersed with dopant (e.g., boron in doped BSG). See Figures 18 and 19. The interspersed doped dielectric may be provided with or without a spike layer. In yet another example, an undoped CFD oxide or other dielectric cap that acts as a protective layer. Again, see Figures 18 and 19.

The dielectric film in which the dopant species reside can itself be tailored to affect the diffusion of the dopant species through the film itself. For example, the film density and/or chemical composition may be controlled to produce a desired impact on dopant species diffusion. In some approaches, the entire dielectric thickness possesses the same density or composition such that the tailored dopant diffusion properties are invariant throughout the film thickness. In other approaches, the film properties are tailored such that the dopant diffusion varies across the film thickness. The inventors have found that plasma oxidation parameters can be changed to make a CFD oxide less dense to allow for greater dopant diffusion across it during an anneal, for example.

In certain embodiments, the composition of the dielectric film (or the process gas used to form the film) is tailored to influence the dopant diffusion therein. It has been found, for example, that the ratio of nitrogen to oxygen in the oxidant process gas delivered to the reaction chamber during the dielectric film deposition cycles influences the ability of dopant species to diffuse through the dielectric film. For example, a greater amount of nitrogen present in the oxidant gas used during formation of the dielectric film results in the dielectric film having a significant resistance to dopant diffusion. By contrast, a relatively greater amount of oxygen present in the gas results in the film having a much less resistance to dopant diffusion. The nitrogen present in the process gas may be provided by way of nitrogen containing compounds (e.g., N20) or elemental nitrogen, N2. In various

embodiments, the oxidant that flows continuously during the dielectric film

deposition cycles contains nitrous oxide. In certain embodiments, the dielectric film is fabricated by initially using an oxidant gas that is high in oxygen content and relatively low and nitrogen content during the initial growth phases of the dielectric film. Later, after the film is partially formed on the substrate structures to be doped, the oxidant gas is changed in composition so that it is relatively richer in nitrogen. For example, during initial deposition cycles, the oxidant gas used for the dielectric film may contain entirely molecular oxygen. In later dielectric deposition cycles, the oxidant gas is modified so that the oxygen is at least partially replaced with nitrous oxide. This assumes that the goal is to enhance diffusion in the direction toward the bottom of the film and block diffusion in the direction toward the top of the film - assuming the device structure to be doped is located underneath the dielectric film. The inventors have found that if nitrogen concentration levels are greater than about 1E20 atoms/cc (measured by, e.g., SIMS), then the blocking effect to boron diffusion is significant. By contrast, at nitrogen concentration levels of about 1E19 atoms/cc or lower, the blocking effect can be effectively eliminated.

From the perspective of the film composition itself, the nitrogen content in the film may vary from a relatively low level in the portion of the film near the substrate structure to be doped to a relatively higher level in the portion located opposite the structure to be doped. The deposition temperature employed during formation of the dielectric film also influences the ability of the dopant atoms to diffuse within the film. In general, it has been found that dielectric deposited at relatively low temperatures by CFD processing generally permits relatively high dopant diffusion rates. Examples of the relatively low temperatures associated with relatively high dopant diffusion rates are temperatures in the range of about 300 to 400 °C, or more specifically between about 350 to 400 °C. Of course, these temperature ranges depend upon the choice of dielectric precursor and other deposition parameters. While they may be employed with a number of precursors, they are particularly appropriate for the use of BTBAS as the dielectric precursor. By contrast, dielectric deposited at relatively higher temperatures tends to resist the diffusion of dopant species. Using BTBAS as the dielectric precursor, relatively high temperatures associated with relatively low dopant diffusion rates are in the range of about 350 to 400 °C, or more specifically between about 300 to 380 °C. Of course, these temperatures may be applied to other precursors. Further, while it is true that higher temperatures in general give denser films that resist dopant diffusion, one can also control diffusivity and/or density via other parameters such as RF exposure time and power during plasma oxidation. Examples of baseline parameters that may be employed during CFD oxide growth include (1) high frequency plasma at about 200 - 2500 Watts (for a 300 mm wafer), typically without low frequency plasma, and (2) plasma exposure times in the range of about 0.2 to 1.5 seconds.

In certain embodiments, a relatively low temperature is employed to deposit dielectric film adjacent to the device structure to be doped and a higher temperature is employed to deposit the portion of the dielectric film further away from the structure. In certain embodiments, the temperature employed during deposition of the full dielectric film is varied, and as well, the nitrogen to oxygen ratio in the oxidant gas is varied during the deposition process. In this manner, the dopant diffusion properties of the resulting dielectric film can be varied to an exaggerated degree across the thickness of the film.

In various embodiments, the deposition temperature is controlled by heating and/or cooling a pedestal or chuck that holds the substrate during CFD. Examples of suitable pedestals are described in US Patent Application No. 12/435,890 (published application no. US-2009-0277472), filed May 5, 2009, and US Patent Application No. 13/086,010, filed April 13, 2011, both of which are incorporated herein by reference in their entireties. In certain embodiments, the device structure on the substrate surface that is to be doped is pretreated prior to deposition of the dielectric film or the dopant precursor. In one example, the pretreatment involves exposure to a plasma such as a reducing plasma. Such treatment may be appropriate when, for example, the substrate features to be doped contains silicon. Typically silicon contains a small quantity of native oxide which could serve as a barrier to subsequent diffusion of the dopant. In a specific embodiment, the substrate surface is pretreated with a reducing plasma such as a hydrogen containing plasma, and then the surface is contacted with the dopant precursor, in the vapor phase, prior to the first cycle of dielectric film deposition. The precursor may be delivered to the reaction chamber immediately after the plasma pretreatment is completed. In some examples, the dopant precursor is diborane. In general, the process depicted in Figure 17 may be modified so that a dopant or dopant precursor is delivered to the substrate surface prior to the first dielectric deposition cycle.

In various embodiments, a partially formed dielectric film itself is pretreated with a plasma or other activating treatment prior to exposure to the dopant precursor. This serves to enhance the within- wafer uniformity by (a) providing thermal uniformity prior to dopant precursor exposure, (b) activate the dielectric surface (e.g., by chemical and/or physical roughening) to enhance dopant precursor sticking to dielectric surface.

In certain other embodiments, the chemical condition of the dopant species is controlled during the dopant precursor delivery and/or activation phases of the film deposition process. In some embodiments, the dopant precursor is treated in a manner that "fixes" the dopant in the dielectric film and thereby limits dopant diffusion until it is subsequently activated by an anneal other such operation. In one example, certain dopants are fixed by oxidizing them or their precursors during the dopant delivery phase of the dielectric film deposition process. In a specific example, diborane is delivered to the reaction chamber in an oxidizing environment to effectively fix the resulting boron-containing material in the dielectric film. Alternatively, the dopant is fixed by delivering precursor to the reaction chamber in an inert or reducing environment and thereafter exposed to oxidizing environment while located on the dielectric film. In contrast, treatment of certain dopant precursors with a reducing agent, without subsequent oxidation, may produce a more mobile dopant in the dielectric film.

After the source layer is formed (or during its formation), the dopant species are driven or otherwise incorporated into adjacent structures in the device being fabricated. In certain embodiments, the dopant species are driven by an anneal during or after the conformal dopant source film is formed. Besides conventional thermal annealing, flash annealing and laser spike annealing can be used, for example. The time and temperature of the anneal depends upon various parameters including the concentration, amount, and type of dopant in the source layer, the composition and morphology of the source layer matrix (e.g., an oxide glass), the distance that the dopant species must travel into adjacent device structures, the desired concentration of dopant in the device structure, and the composition and morphology of the device structure. In certain embodiments, the anneal is performed at a temperature of between about 900 and 1100 °C for about 2 to 30 seconds. Various apparatus may be designed to deposit the doped dielectric films as described here. Generally, the apparatus will contain a process chamber for holding a substrate during deposition of the doped film. The process chamber will include one or more inlets for admitting process gases, including dielectric precursors, oxidants, carrier gases or inert gases, dopant species and the like. In various embodiments, the apparatus will additionally include features for generating a plasma having properties suitable for creating the dielectric layer, incorporating dopant into the dielectric layer, treating the dielectric layer to modify the electrical, optical, mechanical, and/or chemical properties of the layer, and driving dopant from the film into the substrate. Typically, the apparatus will include a vacuum pump or provisions for connecting to such pump. Still further, the apparatus will have a controller or controllers configured or designed for controlling the apparatus to accomplish the sequence of doped dielectric deposition operations described here. The controller may include instructions for controlling various features of the apparatus including the valving to deliver of process gases and to control pressure, the power supply for generating plasmas, and the vacuum source. The instructions may control the timing and sequence of the various operations. In various embodiments, the apparatus may have features as provided in the Vector™ family of deposition tools available from Novellus Systems of San Jose, California. Other features of suitable apparatus for depositing doped dielectric films are described elsewhere herein.

DOPED CFD FILM PROPERTIES The dielectric film serving as a source of dopant species will have various characteristics. In various embodiments, the film thickness is between about 20 and 200 Angstroms. In some cases, such as for front end doping of source-drain extension regions of three-dimensional transistor structures, the film thickness is between about 50 and 100 Angstroms. The average concentration of dopant atoms (or other dopant species) in the dielectric film depends upon various factors including the total amount of dopant per unit surface area of the film as well as the diffusivity of the dopant atoms in the film and the doping application. In certain embodiments, the

concentration of dopant in the film is between about 0.01 and 10 percent by weight. In further embodiments, the concentration of dopant in the film is between about 0.1 to 1 percent by weight. In still further embodiments, the concentration of dopant in the film is between about 0.5 to 4 percent by weight. The techniques described herein permit tuning of dopant concentrations over a wide range, e.g., between about 0.01 and 10 weight percent. For example, it has been demonstrated that boron

concentration can be easily tuned between about 0.1 and 4.3 weight percent in CFD dielectric films. In certain embodiments, 5, 7, 10, and 12 nm CFD films are grown with between about 0.1 and 0.5wt% boron.

The CFD doped dielectric film may be characterized by other properties. For example, the sheet resistance (Rs) of CFD deposited films may vary from about 100 to 50000 ohms/square. In some cases, these values are attained after some or all dopant has been driven from the doped CFD layer. Further junction depths (measured by SIMS for example) produced by driving dopant from a CFD film can be modulated to a level of up to about 1000 Angstroms as appropriate. Of course, many front end devices require rather shallower junction depths, e.g., in the range of about 5 - 50 A, which are also attainable using CFD films. The actual junction depth can be controlled by many factors including, for example, interfacial dopant (e.g., boron) concentration, mobility of dopant into the substrate (e.g., silicon) from the bulk and interface, and the temperature and duration of the anneal used to drive in dopants.

CFD DOPING APPLICATIONS

The substrate surface on which the dielectric source layer is formed may require a highly conformal deposition. In certain examples, the dielectric source film conformably coats features having an aspect ratio of between about 1 :0.5 and 1 : 12 (more specifically between about 1 :1 and 1 :8), and have feature widths of no greater than about 60 nm (more specifically no greater than about 30 nm). Doping using dielectric source layers of the types described herein will find particular application in devices formed according to the 45 nm technology node and beyond, including the 22 nm technology node, the 16 nm technology node, etc.

Among the device structures that may be doped using a CFD source layer are conventional doped structures such as CMOS sources and drains, source-drain extension regions, capacitor electrodes in memory devices, gate structures, etc. Other structures that may be doped in this manner are non-planar or three-dimensional structures such as junctions at source/drain extension regions in gate structures such as those in some three-dimensional gate structures employed in some devices fabricated at the 22 nanometer technology node. Some three-dimensional structures can be found in "Tri-gate (Intel)": J.Kavalieros et al, Symp. VLSI Tech Pg 50, 2006 AND "FinFET: Yamashita et al. (IBM Alliance), VLSI 2011, and references therein, previously incorporated by reference.

Doped CFD films have various other applications such as providing etchable layers used at various stages in integrated circuit fabrication. In certain embodiments, the etchable layer is a glass layer having tunable wet etching rates, where the etch rate is tunable by the level of doping. In other words, the level of doping is chosen to provide a pre-defined etch rate. In specific embodiments, the etchable layer is a silicate glass layer containing a dopant such as phosphorus, boron, or combinations thereof. CFD DOPING EXAMPLES

CFD Boron-doped silicate glass (BSG) films were prepared and achieved nearly 100% step coverage on complex three-dimensional gate architectures. Similar results are expected with phosphorus-doped silicate glass (PSG). Boron or phosphorus can be driven from such films into the lateral and vertical regions of the source and drain junctions during a subsequent anneal step that provides

conformal/homogenous under diffusion of the dopant. Figure 20 shows a typical deposition block used to synthesize a CFD BSG/PSG film. The CFD oxide growth cycle includes (a) a saturating dose of the Si02 precursor (BTBAS), (b) an inert purge to flush out remnant precursor species, (c) an oxidative plasma step, and (d) an inert gas purge to remove reaction by-products. This mechanism ensures that the reaction is self- limiting and promotes the excellent conformality observed with these films. A boron or phosphorus exposure step is periodically inserted during the CFD oxide growth, followed by a pump and purge sequence, and an optional RF pinning/cure step (e.g., exposure to plasma) if needed. This deposition block is repeated as many times as required by the target BSG/PSG thickness. See Figure 20.

While the frequency of insertion of boron or phosphorus exposure modulates the dopant diffusion distance at a given temperature, the length of exposure controls the total dopant dose. These two powerful control parameters provide a versatile synthesis scheme to accurately tune the interface dopant concentration.

In experiments, CFD has demonstrated excellent growth characteristics in BSG films. The CFD BSG process used BTBAS as the silicon source, N20 plasma for oxidation and 5% diborane (B2H6) in argon for boron doping. A mixture of argon and N20 was used as the purging gas. A growth rate of ~1 A/cycle was obtained consistent with results on undoped CFD oxide, showing that the inclusion of a boron exposure step did not affect the CFD growth adversely. 250A-thick CFD BSG films exhibited near-perfect conformality on different test structures as shown by SEM photographs. Step coverage for these films was calculated to be—100% on dense and isolated structures (Figure 21). Step coverage is defined as the quotient of film thickness on the sidewall of a feature divided by film thickness on the top of the same feature. Table 3 shows the different splits from an initial study to partition out the effects of boron exposure time, frequency of the boron insertion and growth temperature on the final average boron concentration in the film. 25X CFD Ox means that there are 25 CFD undoped oxide cycles per boron insertion stage. This sample was grown to 500 Angstroms approximately, so the whole sequence was repeated around 20 times (given a growth rate of 1 A/cycle for th CFD oxide). SIMS data for these splits, as presented in Figure 22, show that the average boron

concentration can be tuned in a range of about 0.5 - 3.5wt% boron, which enables customized doping options.

Table 3

Figure imgf000057_0001

APPARATUS

It will be appreciated that any suitable process station may be employed with one or more of the embodiments described above. For example, FIG. 13 schematically shows an embodiment of a CFD process station 1300. For simplicity, CFD process station 1300 is depicted as a standalone process station having a process chamber body 1302 for maintaining a low-pressure environment. However, it will be appreciated that a plurality of CFD process stations 1300 may be included in a common low-pressure process tool environment. While the embodiment depicted in FIG. 13 shows one process station, it will be appreciated that, in some embodiments, a plurality of process stations may be included in a processing tool. For example, FIG. 14 depicts an embodiment of a multi- station processing tool 2400. Further, it will be appreciated that, in some embodiments, one or more hardware parameters of CFD process station 1300, including those discussed in detail below, may be adjusted programmatically by one or more computer controllers. CFD process station 1300 fluidly communicates with reactant delivery system

1301 for delivering process gases to a distribution showerhead 1306. Reactant delivery system 1301 includes a mixing vessel 1304 for blending and/or conditioning process gases for delivery to showerhead 1306. One or more mixing vessel inlet valves 1320 may control introduction of process gases to mixing vessel 1304.

Some reactants, like BTBAS, may be stored in liquid form prior to vaporization at and subsequent delivery to the process station. For example, the embodiment of FIG. 13 includes a vaporization point 1303 for vaporizing liquid reactant to be supplied to mixing vessel 1304. In some embodiments, vaporization point 1303 may be a heated vaporizer. The saturated reactant vapor produced from such vaporizers may condense in downstream delivery piping. Exposure of incompatible gases to the condensed reactant may create small particles. These small particles may clog piping, impede valve operation, contaminate substrates, etc. Some approaches to addressing these issues involve sweeping and/or evacuating the delivery piping to remove residual reactant. However, sweeping the delivery piping may increase process station cycle time, degrading process station throughput. Thus, in some embodiments, delivery piping downstream of vaporization point 1303 may be heat traced. In some examples, mixing vessel 1304 may also be heat traced. In one non-limiting example, piping downstream of vaporization point 1303 has an increasing temperature profile extending from approximately 100 degrees Celsius to approximately 150 degrees Celsius at mixing vessel 1304.

In some embodiments, reactant liquid may be vaporized at a liquid injector. For example, a liquid injector may inject pulses of a liquid reactant into a carrier gas stream upstream of the mixing vessel. In one scenario, a liquid injector may vaporize reactant by flashing the liquid from a higher pressure to a lower pressure. In another scenario, a liquid injector may atomize the liquid into dispersed microdroplets that are subsequently vaporized in a heated delivery pipe. It will be appreciated that smaller droplets may vaporize faster than larger droplets, reducing a delay between liquid injection and complete vaporization. Faster vaporization may reduce a length of piping downstream from vaporization point 1303. In one scenario, a liquid injector may be mounted directly to mixing vessel 1304. In another scenario, a liquid injector may be mounted directly to showerhead 1306. Showerhead 1306 and pedestal 1308 electrically communicate with RF power supply 1314 and matching network 1316 for powering a plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of a process station pressure, a gas concentration, an RF source power, an RF source frequency, and a plasma power pulse timing. For example, RF power supply 1314 and matching network 1316 may be operated at any suitable power to form a plasma having a desired composition of radical species. Examples of suitable powers include, but are not limited to, powers between 100W and 5000 W for a 300 mm wafer. Likewise, RF power supply 1314 may provide RF power of any suitable frequency. In some embodiments, RF power supply 1314 may be configured to control high- and low-frequency RF power sources independently of one another. Example low- frequency RF frequencies may include, but are not limited to, frequencies between 50 kHz and 500 kHz. Example high-frequency RF frequencies may include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz. It will be appreciated that any suitable parameters may be modulated discretely or continuously to provide plasma energy for the surface reactions. In one non- limiting example, the plasma power may be intermittently pulsed to reduce ion bombardment with the substrate surface relative to continuously powered plasmas.

In some embodiments, the plasma may be monitored in-situ by one or more plasma monitors. In one scenario, plasma power may be monitored by one or more voltage, current sensors (e.g., VI probes). In another scenario, plasma density and/or process gas concentration may be measured by one or more optical emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters may be programmatically adjusted based on measurements from such in-situ plasma monitors. For example, an OES sensor may be used in a feedback loop for providing programmatic control of plasma power. It will be appreciated that, in some embodiments, other monitors may be used to monitor the plasma and other process characteristics. Such monitors may include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure transducers.

In some embodiments, pedestal 1308 may be temperature controlled via heater 1310. Further, in some embodiments, pressure control for CFD process station 1300 may be provided by butterfly valve 1318. As shown in the embodiment of FIG. 13, butterfly valve 1318 throttles a vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of process station 1300 may also be adjusted by varying a flow rate of one or more gases introduced to CFD process station 1300. As described above, one or more process stations may be included in a multistation processing tool. FIG. 14 shows a schematic view of an embodiment of a multistation processing tool 2400 with an inbound load lock 2402 and an outbound load lock 2404, either or both of which may comprise a remote plasma source. A robot 2406, at atmospheric pressure, is configured to move wafers from a cassette loaded through a pod 2408 into inbound load lock 2402 via an atmospheric port 2410. A wafer is placed by the robot 2406 on a pedestal 2412 in the inbound load lock 2402, the atmospheric port 2410 is closed, and the load lock is pumped down. Where the inbound load lock 2402 comprises a remote plasma source, the wafer may be exposed to a remote plasma treatment in the load lock prior to being introduced into a processing chamber 2414. Further, the wafer also may be heated in the inbound load lock 2402 as well, for example, to remove moisture and adsorbed gases. Next, a chamber transport port 2416 to processing chamber 2414 is opened, and another robot (not shown) places the wafer into the reactor on a pedestal of a first station shown in the reactor for processing. While the embodiment depicted in FIG. 14 includes load locks, it will be appreciated that, in some embodiments, direct entry of a wafer into a process station may be provided.

The depicted processing chamber 2414 comprises four process stations, numbered from 1 to 4 in the embodiment shown in FIG. 14. Each station has a heated pedestal (shown at 2418 for station 1), and gas line inlets. It will be appreciated that in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, a process station may be switchable between a CFD and PECVD process mode. Additionally or alternatively, in some embodiments, processing chamber 2414 may include one or more matched pairs of CFD and PECVD process stations. While the depicted processing chamber 2414 comprises four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, a processing chamber may have five or more stations, while in other embodiments a processing chamber may have three or fewer stations.

FIG. 14 also depicts an embodiment of a wafer handling system 2490 for transferring wafers within processing chamber 2414. In some embodiments, wafer handling system 2490 may transfer wafers between various process stations and/or between a process station and a load lock. It will be appreciated that any suitable wafer handling system may be employed. Non-limiting examples include wafer carousels and wafer handling robots. FIG. 14 also depicts an embodiment of a system controller 2450 employed to control process conditions and hardware states of process tool 2400. System controller 2450 may include one or more memory devices 2456, one or more mass storage devices 2454, and one or more processors 2452. Processor 2452 may include a CPU or computer, analog and/or digital input/output connections, stepper motor controller boards, etc.

In some embodiments, system controller 2450 controls all of the activities of process tool 2400. System controller 2450 executes system control software 2458 stored in mass storage device 2454, loaded into memory device 2456, and executed on processor 2452. System control software 2458 may include instructions for controlling the timing, mixture of gases, chamber and/or station pressure, chamber and/or station temperature, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and/or susceptor position, and other parameters of a particular process performed by process tool 2400. System control software 2458 may be configured in any suitable way. For example, various process tool component subroutines or control objects may be written to control operation of the process tool components necessary to carry out various process tool processes. System control software 2458 may be coded in any suitable computer readable programming language.

In some embodiments, system control software 2458 may include input/output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each phase of a CFD process may include one or more instructions for execution by system controller 2450. The instructions for setting process conditions for a CFD process phase may be included in a corresponding CFD recipe phase. In some embodiments, the CFD recipe phases may be sequentially arranged, so that all instructions for a CFD process phase are executed concurrently with that process phase.

Other computer software and/or programs stored on mass storage device 2454 and/or memory device 2456 associated with system controller 2450 may be employed in some embodiments. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

A substrate positioning program may include program code for process tool components that are used to load the substrate onto pedestal 2418 and to control the spacing between the substrate and other parts of process tool 2400.

A process gas control program may include code for controlling gas composition and flow rates and optionally for flowing gas into one or more process stations prior to deposition in order to stabilize the pressure in the process station. A pressure control program may include code for controlling the pressure in the process station by regulating, for example, a throttle valve in the exhaust system of the process station, a gas flow into the process station, etc.

A heater control program may include code for controlling the current to a heating unit that is used to heat the substrate. Alternatively, the heater control program may control delivery of a heat transfer gas (such as helium) to the substrate. A plasma control program may include code for setting RF power levels applied to the process electrodes in one or more process stations.

In some embodiments, there may be a user interface associated with system controller 2450. The user interface may include a display screen, graphical software displays of the apparatus and/or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.

In some embodiments, parameters adjusted by system controller 2450 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF bias power levels), pressure, temperature, etc. These parameters may be provided to the user in the form of a recipe, which may be entered utilizing the user interface.

Signals for monitoring the process may be provided by analog and/or digital input connections of system controller 2450 from various process tool sensors. The signals for controlling the process may be output on the analog and digital output connections of process tool 2400. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

System controller 2450 may provide program instructions for implementing the above-described deposition processes. The program instructions may control a variety of process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control the parameters to operate in-situ deposition of film stacks according to various embodiments described herein.

The apparatus/process described hereinabove may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels and the like. Typically, though not necessarily, such tools/processes will be used or conducted together in a common fabrication facility. Lithographic patterning of a film typically includes some or all of the following operations, each operation enabled with a number of possible tools: (1) application of photoresist on a workpiece, i.e., substrate, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma- assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.

It is to be understood that the configurations and/or approaches described herein are exemplary in nature, and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. As such, various acts illustrated may be performed in the sequence illustrated, in other sequences, in parallel, or in some cases omitted. Likewise, the order of the above-described processes may be changed. The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems and configurations, and other features, functions, acts, and/or properties disclosed herein, as well as any and all equivalents thereof.

Claims

CLAIMS what is claimed is:
1. A method of depositing a film on a substrate surface in a reaction chamber, the method comprising:
(a) introducing a first reactant into the reaction chamber under conditions allowing the first reactant to adsorb onto the substrate surface;
(b) introducing a second reactant into the reaction chamber while the first reactant is adsorbed on the substrate surface;
(c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants on the substrate surface to form a portion of the film;
(d) repeating (a)-(c) at least once;
(e) introducing a dopant containing material, not introduced during (a)-(d), into the reaction chamber under conditions allowing the dopant containing material to contact an exposed surface of the film; and
(f) introducing a dopant into the film from the dopant containing material.
2. The method of claim 1, further comprising:
(g) repeating (a)-(c) after (e) or (f).
3. The method of claim 1, further comprising
(g) repeating (a)-(e).
4. The method of claim 1, wherein the amount of film deposited during (a)-(c) is between about 0.5 to 1 Angstroms.
5. The method of claim 1, further comprising driving the dopant from the film into features of the substrate surface on which the film resides.
6. The method of claim 5, wherein driving the dopant from the film comprises annealing the film.
7. The method of claim 5, wherein the film resides on a three-dimensional feature of the substrate surface and wherein driving the dopant from the film provides conformal diffusion of the dopant into the feature.
8. The method of claim 7, wherein the feature has a width of not greater than about 40 nanometers.
9. The method of claim 1, further comprising purging the second reactant from the reaction chamber prior to exposing the substrate surface to plasma.
10. The method of claim 9, wherein the purging comprises flowing a gas comprising an oxidant into the reaction chamber.
11. The method of claim 1, wherein the first and second reactants co-exist in vapor phase in the reaction chamber and wherein the first and second reactants do not appreciably react with one another in the reaction chamber until exposure to plasma in (c).
12. The method of claim 1, wherein introducing the dopant into the film comprises exposing the dopant containing material to a plasma.
13. The method of claim 1, wherein the first reactant is an oxidizing agent.
14. The method of claim 13, wherein the oxidizing agent is nitrous oxide.
15. The method of claim 1, wherein the second reactant is selected from the group consisting of
alkylamino silanes (SiHx(NR2)4_x), where x = 1-3, and R includes alkyl groups, and
halosilanes (SiHxY4_x), where x = 1-3, and Y includes CI, Br, and I).
16. The method of claim 1, wherein the second reactant is BTBAS.
17. The method of claim 1, wherein the dopant containing material is selected from the group consisting of phosphine, arsine, alkylboranes, alkyl gallanes, alkylphosphines, phosphorus halides, arsenic halides, gallium halides, boron halides, alkylboranes, and diborane.
18. The method of claim 1 , wherein in the film is a dielectric film.
19. The method of claim 1, wherein the total film thickness is between about 10 - 100 Angstroms.
20. The method of claim 1, wherein the concentration of dopant in the film is between about 0.01 and 10 percent by weight.
21. The method of claim 1 further comprising:
applying photoresist to the substrate surface;
exposing the photoresist to light;
patterning the resist and transferring the pattern to the substrate surface; and selectively removing the photoresist from the substrate surface.
22. A method of depositing a dielectric film on a substrate surface in a reaction chamber, the method comprising:
(a) flowing an oxidant into the reaction chamber under conditions allowing the first reactant to adsorb onto the substrate surface;
(b) introducing a dielectric precursor into the reaction chamber while the oxidant continues to flow into the reaction chamber;
(c) exposing the substrate surface to plasma to drive a reaction between the dielectric precursor and oxidant on the substrate surface to form a portion of the dielectric film;
(d) introducing a dopant containing material, not introduced during (a)-(c), into the reaction chamber under conditions allowing the dopant containing material to contact an exposed surface of the film; and
(e) causing a dopant from the containing material to integrate into the dielectric film.
23. The method of claim 22, wherein the dielectric precursor is BTB AS.
24. The method of claim 22, further comprising driving the dopant from the dielectric film into the substrate.
25. The method of claim 22, wherein operations (a)-(c) are repeated.
26. The method of claim 25, wherein the oxidant contains a first ratio of oxygen to nitrogen when (a) is initially performed and wherein the oxidant contains a second ratio of oxygen to nitrogen, which second ratio is smaller than the first ratio, when (a) is repeated.
27. The method of claim 26, wherein the oxidant comprises elemental oxygen when (a) is initially performed and wherein the oxidant comprises nitrous oxide when (a) is repeated.
28. The method of claim 25, wherein the substrate is at a first temperature when (c) is initially performed, and wherein the substrate is at a second temperature, which is higher than the first temperature, when (c) is repeated.
29. The method of claim 22, further comprising contacting the substrate surface with the dopant containing material prior to (a).
30. A method of depositing a dielectric film on a substrate surface in a reaction chamber, the method comprising:
(a) introducing a dielectric precursor into the reaction chamber under conditions allowing the precursor to adsorb onto the substrate surface;
(b) thereafter purging the dielectric precursor from the reaction chamber while the precursor remains adsorbed on the substrate surface;
(c) exposing the substrate surface to plasma to drive a reaction of the dielectric precursor on the substrate surface to form a portion of the dielectric film; and (d) introducing a dopant precursor, not introduced during (a)-(c), into the reaction chamber under conditions allowing the dopant precursor to contact the portion of the dielectric film.
31. The method of claim 30, further comprising flowing an oxidant into the reaction chamber prior to and during (a)-(c).
32. The method of claim 30, further comprising (e) reacting the dopant precursor to introduce a dopant to the film.
33. An apparatus for depositing a doped film on a substrate surface, the apparatus comprising:
a reaction chamber comprising a device for holding the substrate during deposition of the doped dielectric film;
one or more process gas inlets coupled to the reaction chamber; and
a controller designed or configured to cause the apparatus to perform the following operations:
(a) introducing a first reactant into the reaction chamber under conditions allowing the first reactant to adsorb onto the substrate surface; (b) introducing a second reactant into the reaction chamber while the first reactant is adsorbed on the substrate surface;
(c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants on the substrate surface to form a portion of the film;
(d) repeating (a)-(c) at least once;
(e) introducing a dopant containing material, not introduced during (a)-(d), into the reaction chamber under conditions allowing the dopant containing material to contact an exposed surface of the film; and
(f) introducing a dopant into the film from the dopant containing material.
34. The apparatus of claim 33, wherein the controller is further designed or configured to cause the apparatus to flow an oxidant into the reaction chamber prior to and during (a)-(d).
35. The apparatus of claim 33, wherein the controller is further designed or configured to cause (g) repeating (a)-(c) after (e) or (f).
36. The apparatus of claim 33, wherein the controller is further designed or configured to cause (g) driving the dopant from the film into features of the substrate surface on which the film resides.
37. The apparatus of claim 36, wherein driving the dopant from the film comprises annealing the film.
38. The apparatus of claim 33, wherein the controller is further designed or configured to cause purging the second reactant from the reaction chamber prior to exposing the substrate surface to plasma.
39. The apparatus of claim 38, wherein the purging comprises flowing a gas comprising an oxidant into the reaction chamber.
40. The apparatus of claim 33, wherein the controller is further designed or configured to cause (e) to be performed at intervals between one or more repetitions of (a)-(d) and wherein said intervals are varied over the course of depositing the film.
41. A system comprising the apparatus of claim 33 and a stepper.
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Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104103689A (en) * 2013-04-10 2014-10-15 三星电子株式会社 Semiconductor device and method for fabricating the same
JP2014229834A (en) * 2013-05-24 2014-12-08 株式会社日立国際電気 Method for manufacturing semiconductor device, substrate processing device, and program
US8956983B2 (en) 2010-04-15 2015-02-17 Novellus Systems, Inc. Conformal doping via plasma activated atomic layer deposition and conformal film deposition
US8999859B2 (en) 2010-04-15 2015-04-07 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9070555B2 (en) 2012-01-20 2015-06-30 Novellus Systems, Inc. Method for depositing a chlorine-free conformal sin film
US9076646B2 (en) 2010-04-15 2015-07-07 Lam Research Corporation Plasma enhanced atomic layer deposition with pulsed plasma exposure
US9214334B2 (en) 2014-02-18 2015-12-15 Lam Research Corporation High growth rate process for conformal aluminum nitride
US9230800B2 (en) 2010-04-15 2016-01-05 Novellus Systems, Inc. Plasma activated conformal film deposition
US9257274B2 (en) 2010-04-15 2016-02-09 Lam Research Corporation Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
JP2016507001A (en) * 2012-12-21 2016-03-07 プラサド ナーハー ガジル Low temperature deposition method for ceramic thin films
US9287113B2 (en) 2012-11-08 2016-03-15 Novellus Systems, Inc. Methods for depositing films on sensitive substrates
US9355886B2 (en) 2010-04-15 2016-05-31 Novellus Systems, Inc. Conformal film deposition for gapfill
US9355839B2 (en) 2012-10-23 2016-05-31 Lam Research Corporation Sub-saturated atomic layer deposition and conformal film deposition
US9373500B2 (en) 2014-02-21 2016-06-21 Lam Research Corporation Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications
US9390909B2 (en) 2013-11-07 2016-07-12 Novellus Systems, Inc. Soft landing nanolaminates for advanced patterning
US9478438B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method and apparatus to deposit pure titanium thin film at low temperature using titanium tetraiodide precursor
US9478411B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method to tune TiOx stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiOx/Ti based MIS contact scheme for CMOS
US9502238B2 (en) 2015-04-03 2016-11-22 Lam Research Corporation Deposition of conformal films by atomic layer deposition and atomic layer etch
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US9611544B2 (en) 2010-04-15 2017-04-04 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9685320B2 (en) 2010-09-23 2017-06-20 Lam Research Corporation Methods for depositing silicon oxide
US9773643B1 (en) 2016-06-30 2017-09-26 Lam Research Corporation Apparatus and method for deposition and etch in gap fill
US9865815B2 (en) 2015-09-24 2018-01-09 Lam Research Coporation Bromine containing silicon precursors for encapsulation layers
US9865455B1 (en) 2016-09-07 2018-01-09 Lam Research Corporation Nitride film formed by plasma-enhanced and thermal atomic layer deposition process
US9892917B2 (en) 2010-04-15 2018-02-13 Lam Research Corporation Plasma assisted atomic layer deposition of multi-layer films for patterning applications
US9997357B2 (en) 2010-04-15 2018-06-12 Lam Research Corporation Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors
US10037884B2 (en) 2016-08-31 2018-07-31 Lam Research Corporation Selective atomic layer deposition for gapfill using sacrificial underlayer
US10062563B2 (en) 2016-07-01 2018-08-28 Lam Research Corporation Selective atomic layer deposition with post-dose treatment
US10074543B2 (en) 2016-08-31 2018-09-11 Lam Research Corporation High dry etch rate materials for semiconductor patterning applications
US10134579B2 (en) 2016-11-14 2018-11-20 Lam Research Corporation Method for high modulus ALD SiO2 spacer
WO2018231522A1 (en) * 2017-06-12 2018-12-20 Headway Technologies, Inc. Silicon oxynitride based encapsulation layer for magnetic tunnel junctions
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9606519B2 (en) * 2013-10-14 2017-03-28 Applied Materials, Inc. Matching process controllers for improved matching of process
US10242848B2 (en) * 2014-12-12 2019-03-26 Lam Research Corporation Carrier ring structure and chamber systems including the same
FI126970B (en) * 2014-12-22 2017-08-31 Picosun Oy Atomic deposit where the first and second starting species are present at the same time
US9721887B2 (en) * 2015-08-19 2017-08-01 Taiwan Semiconductor Manufacturing Company, Ltd Method of forming metal interconnection
JP6509095B2 (en) * 2015-11-04 2019-05-08 東京エレクトロン株式会社 Method of forming nitride film
JP6540571B2 (en) * 2016-03-24 2019-07-10 豊田合成株式会社 Semiconductor device manufacturing method and semiconductor device
JP2018154874A (en) * 2017-03-17 2018-10-04 株式会社日本製鋼所 Film deposition method, method for manufacturing electronic device and mask support body

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050260347A1 (en) * 2004-05-21 2005-11-24 Narwankar Pravin K Formation of a silicon oxynitride layer on a high-k dielectric material
US20070232082A1 (en) * 2006-03-31 2007-10-04 Mihaela Balseanu Method to improve the step coverage and pattern loading for dielectric films
US20090065896A1 (en) * 2007-09-07 2009-03-12 Seoul National University Industry Foundation CAPACITOR HAVING Ru ELECTRODE AND TiO2 DIELECTRIC LAYER FOR SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
US20090148625A1 (en) * 2005-02-16 2009-06-11 Hynix Semiconductor Inc. Method for forming thin film
US20120009802A1 (en) * 2010-04-15 2012-01-12 Adrien Lavoie Plasma activated conformal dielectric film deposition

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4843472B1 (en) * 1968-05-09 1973-12-19
JPH0293071A (en) * 1988-09-29 1990-04-03 Toshiba Corp Thin film formation
JPH06177120A (en) * 1992-10-27 1994-06-24 Sony Corp Deposition of interlayer dielectric film
US5994209A (en) * 1996-11-13 1999-11-30 Applied Materials, Inc. Methods and apparatus for forming ultra-shallow doped regions using doped silicon oxide films
US6156149A (en) * 1997-05-07 2000-12-05 Applied Materials, Inc. In situ deposition of a dielectric oxide layer and anti-reflective coating
JP3437832B2 (en) * 2000-03-22 2003-08-18 東京エレクトロン株式会社 Film forming method and a film forming apparatus
KR100721503B1 (en) * 2000-06-08 2007-05-23 에이에스엠지니텍코리아 주식회사 Method for forming a thin film
JP2002134497A (en) * 2000-10-23 2002-05-10 Sony Corp Manufacturing method for semiconductor device
JP3437830B2 (en) * 2000-11-28 2003-08-18 東京エレクトロン株式会社 Film formation method
US7125815B2 (en) * 2003-07-07 2006-10-24 Micron Technology, Inc. Methods of forming a phosphorous doped silicon dioxide comprising layer
US7482247B1 (en) * 2004-12-30 2009-01-27 Novellus Systems, Inc. Conformal nanolaminate dielectric deposition and etch bag gap fill process
US7779785B2 (en) * 2005-02-17 2010-08-24 Hitachi Kokusai Electric Inc. Production method for semiconductor device and substrate processing apparatus
US7629267B2 (en) * 2005-03-07 2009-12-08 Asm International N.V. High stress nitride film and method for formation thereof
CN100554506C (en) * 2005-03-09 2009-10-28 东京毅力科创株式会社 Film formation method and apparatus for semiconductor process
US8034727B2 (en) * 2005-10-14 2011-10-11 Nec Corporation Method and apparatus for manufacturing semiconductor devices
US7897217B2 (en) * 2005-11-18 2011-03-01 Tokyo Electron Limited Method and system for performing plasma enhanced atomic layer deposition
JP2007180362A (en) * 2005-12-28 2007-07-12 Toshiba Corp Semiconductor device
JP4434149B2 (en) * 2006-01-16 2010-03-17 東京エレクトロン株式会社 Film forming method, the film forming apparatus and a storage medium
TW201415551A (en) * 2006-03-31 2014-04-16 Applied Materials Inc Method to improve the step coverage and pattern loading for dielectric films
JP2007287890A (en) * 2006-04-14 2007-11-01 Kochi Univ Of Technology Forming method of insulating film, manufacturing method of semiconductor device and plasma cvd apparatus
JP2007287889A (en) * 2006-04-14 2007-11-01 Kochi Univ Of Technology Forming method of insulating film and manufacturing method of semiconductor device
US7498273B2 (en) * 2006-05-30 2009-03-03 Applied Materials, Inc. Formation of high quality dielectric films of silicon dioxide for STI: usage of different siloxane-based precursors for harp II—remote plasma enhanced deposition processes
WO2007145513A1 (en) * 2006-06-16 2007-12-21 Fujifilm Manufacturing Europe B.V. Method and apparatus for atomic layer deposition using an atmospheric pressure glow discharge plasma
JP4929932B2 (en) * 2006-09-01 2012-05-09 東京エレクトロン株式会社 Film forming method, film forming apparatus, and storage medium
JP5258229B2 (en) * 2006-09-28 2013-08-07 東京エレクトロン株式会社 Film forming method and film forming apparatus
JP2008294260A (en) * 2007-05-25 2008-12-04 Sony Corp Semiconductor device and manufacturing method therefor, and laminate insulating film and forming method therefor
EP2193541A1 (en) 2007-09-18 2010-06-09 L'AIR LIQUIDE, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Method of forming silicon-containing films
JP4959733B2 (en) 2008-02-01 2012-06-27 東京エレクトロン株式会社 Thin film forming method, thin film forming apparatus, and program
KR101732187B1 (en) * 2009-09-03 2017-05-02 에이에스엠 저펜 가부시기가이샤 METHOD OF FORMING CONFORMAL DIELECTRIC FILM HAVING Si-N BONDS BY PECVD
US8197915B2 (en) * 2009-04-01 2012-06-12 Asm Japan K.K. Method of depositing silicon oxide film by plasma enhanced atomic layer deposition at low temperature
JP2010251654A (en) * 2009-04-20 2010-11-04 Elpida Memory Inc Deposition method and manufacturing method of semiconductor device
JP2011023576A (en) * 2009-07-16 2011-02-03 Hitachi Kokusai Electric Inc Method of manufacturing semiconductor device, and device for treating substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050260347A1 (en) * 2004-05-21 2005-11-24 Narwankar Pravin K Formation of a silicon oxynitride layer on a high-k dielectric material
US20090148625A1 (en) * 2005-02-16 2009-06-11 Hynix Semiconductor Inc. Method for forming thin film
US20070232082A1 (en) * 2006-03-31 2007-10-04 Mihaela Balseanu Method to improve the step coverage and pattern loading for dielectric films
US20090065896A1 (en) * 2007-09-07 2009-03-12 Seoul National University Industry Foundation CAPACITOR HAVING Ru ELECTRODE AND TiO2 DIELECTRIC LAYER FOR SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
US20120009802A1 (en) * 2010-04-15 2012-01-12 Adrien Lavoie Plasma activated conformal dielectric film deposition

Cited By (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9673041B2 (en) 2010-04-15 2017-06-06 Lam Research Corporation Plasma assisted atomic layer deposition titanium oxide for patterning applications
US9997357B2 (en) 2010-04-15 2018-06-12 Lam Research Corporation Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors
US8956983B2 (en) 2010-04-15 2015-02-17 Novellus Systems, Inc. Conformal doping via plasma activated atomic layer deposition and conformal film deposition
US8999859B2 (en) 2010-04-15 2015-04-07 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9892917B2 (en) 2010-04-15 2018-02-13 Lam Research Corporation Plasma assisted atomic layer deposition of multi-layer films for patterning applications
US9076646B2 (en) 2010-04-15 2015-07-07 Lam Research Corporation Plasma enhanced atomic layer deposition with pulsed plasma exposure
US9793110B2 (en) 2010-04-15 2017-10-17 Lam Research Corporation Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
US9230800B2 (en) 2010-04-15 2016-01-05 Novellus Systems, Inc. Plasma activated conformal film deposition
US9257274B2 (en) 2010-04-15 2016-02-09 Lam Research Corporation Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
US10361076B2 (en) 2010-04-15 2019-07-23 Lam Research Corporation Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
US9611544B2 (en) 2010-04-15 2017-04-04 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9355886B2 (en) 2010-04-15 2016-05-31 Novellus Systems, Inc. Conformal film deposition for gapfill
US9570274B2 (en) 2010-04-15 2017-02-14 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9570290B2 (en) 2010-04-15 2017-02-14 Lam Research Corporation Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications
US10043655B2 (en) 2010-04-15 2018-08-07 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US10043657B2 (en) 2010-04-15 2018-08-07 Lam Research Corporation Plasma assisted atomic layer deposition metal oxide for patterning applications
US9685320B2 (en) 2010-09-23 2017-06-20 Lam Research Corporation Methods for depositing silicon oxide
US9670579B2 (en) 2012-01-20 2017-06-06 Novellus Systems, Inc. Method for depositing a chlorine-free conformal SiN film
US9070555B2 (en) 2012-01-20 2015-06-30 Novellus Systems, Inc. Method for depositing a chlorine-free conformal sin film
US9355839B2 (en) 2012-10-23 2016-05-31 Lam Research Corporation Sub-saturated atomic layer deposition and conformal film deposition
US10008428B2 (en) 2012-11-08 2018-06-26 Novellus Systems, Inc. Methods for depositing films on sensitive substrates
US9287113B2 (en) 2012-11-08 2016-03-15 Novellus Systems, Inc. Methods for depositing films on sensitive substrates
US9786570B2 (en) 2012-11-08 2017-10-10 Novellus Systems, Inc. Methods for depositing films on sensitive substrates
JP2016507001A (en) * 2012-12-21 2016-03-07 プラサド ナーハー ガジル Low temperature deposition method for ceramic thin films
CN104103689A (en) * 2013-04-10 2014-10-15 三星电子株式会社 Semiconductor device and method for fabricating the same
JP2014229834A (en) * 2013-05-24 2014-12-08 株式会社日立国際電気 Method for manufacturing semiconductor device, substrate processing device, and program
US9472391B2 (en) 2013-05-24 2016-10-18 Hitachi Kokusai Electric Inc. Semiconductor device manufacturing method
US9905423B2 (en) 2013-11-07 2018-02-27 Novellus Systems, Inc. Soft landing nanolaminates for advanced patterning
US9390909B2 (en) 2013-11-07 2016-07-12 Novellus Systems, Inc. Soft landing nanolaminates for advanced patterning
US10192742B2 (en) 2013-11-07 2019-01-29 Novellus Systems, Inc. Soft landing nanolaminates for advanced patterning
US9214334B2 (en) 2014-02-18 2015-12-15 Lam Research Corporation High growth rate process for conformal aluminum nitride
US9373500B2 (en) 2014-02-21 2016-06-21 Lam Research Corporation Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications
US9478438B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method and apparatus to deposit pure titanium thin film at low temperature using titanium tetraiodide precursor
US9478411B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method to tune TiOx stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiOx/Ti based MIS contact scheme for CMOS
US9875891B2 (en) 2014-11-24 2018-01-23 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US9502238B2 (en) 2015-04-03 2016-11-22 Lam Research Corporation Deposition of conformal films by atomic layer deposition and atomic layer etch
US9865815B2 (en) 2015-09-24 2018-01-09 Lam Research Coporation Bromine containing silicon precursors for encapsulation layers
US10141505B2 (en) 2015-09-24 2018-11-27 Lam Research Corporation Bromine containing silicon precursors for encapsulation layers
US9773643B1 (en) 2016-06-30 2017-09-26 Lam Research Corporation Apparatus and method for deposition and etch in gap fill
US10373806B2 (en) 2016-06-30 2019-08-06 Lam Research Corporation Apparatus and method for deposition and etch in gap fill
US10062563B2 (en) 2016-07-01 2018-08-28 Lam Research Corporation Selective atomic layer deposition with post-dose treatment
US10037884B2 (en) 2016-08-31 2018-07-31 Lam Research Corporation Selective atomic layer deposition for gapfill using sacrificial underlayer
US10074543B2 (en) 2016-08-31 2018-09-11 Lam Research Corporation High dry etch rate materials for semiconductor patterning applications
US9865455B1 (en) 2016-09-07 2018-01-09 Lam Research Corporation Nitride film formed by plasma-enhanced and thermal atomic layer deposition process
US10134579B2 (en) 2016-11-14 2018-11-20 Lam Research Corporation Method for high modulus ALD SiO2 spacer
WO2018231522A1 (en) * 2017-06-12 2018-12-20 Headway Technologies, Inc. Silicon oxynitride based encapsulation layer for magnetic tunnel junctions
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer

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