US20070287301A1 - Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics - Google Patents
Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics Download PDFInfo
- Publication number
- US20070287301A1 US20070287301A1 US11/694,856 US69485607A US2007287301A1 US 20070287301 A1 US20070287301 A1 US 20070287301A1 US 69485607 A US69485607 A US 69485607A US 2007287301 A1 US2007287301 A1 US 2007287301A1
- Authority
- US
- United States
- Prior art keywords
- layer
- thin layer
- substrate
- deposited
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 title claims abstract description 61
- 238000007789 sealing Methods 0.000 title description 9
- 239000011148 porous material Substances 0.000 title description 3
- 239000003989 dielectric material Substances 0.000 title 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 50
- 239000002243 precursor Substances 0.000 claims abstract description 47
- 238000000151 deposition Methods 0.000 claims abstract description 41
- 239000001301 oxygen Substances 0.000 claims abstract description 41
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 41
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 36
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 31
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 230000008569 process Effects 0.000 claims abstract description 16
- 238000004140 cleaning Methods 0.000 claims abstract description 14
- 230000035515 penetration Effects 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 173
- HMMGMWAXVFQUOA-UHFFFAOYSA-N octamethylcyclotetrasiloxane Chemical compound C[Si]1(C)O[Si](C)(C)O[Si](C)(C)O[Si](C)(C)O1 HMMGMWAXVFQUOA-UHFFFAOYSA-N 0.000 claims description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 31
- 239000007789 gas Substances 0.000 claims description 25
- 230000004888 barrier function Effects 0.000 claims description 17
- 125000000217 alkyl group Chemical group 0.000 claims description 14
- WZJUBBHODHNQPW-UHFFFAOYSA-N 2,4,6,8-tetramethyl-1,3,5,7,2$l^{3},4$l^{3},6$l^{3},8$l^{3}-tetraoxatetrasilocane Chemical compound C[Si]1O[Si](C)O[Si](C)O[Si](C)O1 WZJUBBHODHNQPW-UHFFFAOYSA-N 0.000 claims description 8
- 239000001307 helium Substances 0.000 claims description 7
- 229910052734 helium Inorganic materials 0.000 claims description 7
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- UQEAIHBTYFGYIE-UHFFFAOYSA-N hexamethyldisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)C UQEAIHBTYFGYIE-UHFFFAOYSA-N 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- PUNGSQUVTIDKNU-UHFFFAOYSA-N 2,4,6,8,10-pentamethyl-1,3,5,7,9,2$l^{3},4$l^{3},6$l^{3},8$l^{3},10$l^{3}-pentaoxapentasilecane Chemical compound C[Si]1O[Si](C)O[Si](C)O[Si](C)O[Si](C)O1 PUNGSQUVTIDKNU-UHFFFAOYSA-N 0.000 claims description 4
- JJQZDUKDJDQPMQ-UHFFFAOYSA-N dimethoxy(dimethyl)silane Chemical compound CO[Si](C)(C)OC JJQZDUKDJDQPMQ-UHFFFAOYSA-N 0.000 claims description 4
- HTDJPCNNEPUOOQ-UHFFFAOYSA-N hexamethylcyclotrisiloxane Chemical compound C[Si]1(C)O[Si](C)(C)O[Si](C)(C)O1 HTDJPCNNEPUOOQ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- OFLMWACNYIOTNX-UHFFFAOYSA-N methyl(methylsilyloxy)silane Chemical compound C[SiH2]O[SiH2]C OFLMWACNYIOTNX-UHFFFAOYSA-N 0.000 claims description 4
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 4
- CZDYPVPMEAXLPK-UHFFFAOYSA-N tetramethylsilane Chemical compound C[Si](C)(C)C CZDYPVPMEAXLPK-UHFFFAOYSA-N 0.000 claims description 4
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 claims description 4
- KWEKXPWNFQBJAY-UHFFFAOYSA-N (dimethyl-$l^{3}-silanyl)oxy-dimethylsilicon Chemical compound C[Si](C)O[Si](C)C KWEKXPWNFQBJAY-UHFFFAOYSA-N 0.000 claims description 3
- 239000006117 anti-reflective coating Substances 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 230000002209 hydrophobic effect Effects 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 239000002344 surface layer Substances 0.000 claims description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims 3
- 229940094989 trimethylsilane Drugs 0.000 claims 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims 1
- 238000000231 atomic layer deposition Methods 0.000 claims 1
- 239000001257 hydrogen Substances 0.000 claims 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 claims 1
- 229920006395 saturated elastomer Polymers 0.000 claims 1
- 230000005661 hydrophobic surface Effects 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 106
- 238000004380 ashing Methods 0.000 description 31
- 230000008021 deposition Effects 0.000 description 21
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 21
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 10
- 238000009736 wetting Methods 0.000 description 10
- 239000000203 mixture Substances 0.000 description 9
- 150000003961 organosilicon compounds Chemical class 0.000 description 9
- 238000009832 plasma treatment Methods 0.000 description 9
- -1 and RY═H Chemical group 0.000 description 7
- 239000012159 carrier gas Substances 0.000 description 6
- 238000011282 treatment Methods 0.000 description 6
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- 125000004122 cyclic group Chemical group 0.000 description 5
- 238000009738 saturating Methods 0.000 description 5
- 238000004458 analytical method Methods 0.000 description 4
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 4
- 125000005375 organosiloxane group Chemical group 0.000 description 4
- 238000001179 sorption measurement Methods 0.000 description 4
- 239000002052 molecular layer Substances 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- 239000004215 Carbon black (E152) Substances 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 2
- 229910018557 Si O Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- NBBQQQJUOYRZCA-UHFFFAOYSA-N diethoxymethylsilane Chemical compound CCOC([SiH3])OCC NBBQQQJUOYRZCA-UHFFFAOYSA-N 0.000 description 2
- NEXSMEBSBIABKL-UHFFFAOYSA-N hexamethyldisilane Chemical compound C[Si](C)(C)[Si](C)(C)C NEXSMEBSBIABKL-UHFFFAOYSA-N 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 150000002430 hydrocarbons Chemical class 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- 125000004430 oxygen atom Chemical group O* 0.000 description 2
- 239000003361 porogen Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- JDYIHBJBOWFKFW-UHFFFAOYSA-N 1,2,3,4,5,6,7,8-octamethyl-1,3,5,7,2$l^{3},4$l^{3},6$l^{3},8$l^{3}-tetrazatetrasilocane Chemical compound CN1[Si](C)N(C)[Si](C)N(C)[Si](C)N(C)[Si]1C JDYIHBJBOWFKFW-UHFFFAOYSA-N 0.000 description 1
- ALFURVVDZFIESW-UHFFFAOYSA-N 1,2,3,4,5,6-hexamethyl-1,3,5,2$l^{3},4$l^{3},6$l^{3}-triazatrisilinane Chemical compound CN1[Si](C)N(C)[Si](C)N(C)[Si]1C ALFURVVDZFIESW-UHFFFAOYSA-N 0.000 description 1
- WGGNJZRNHUJNEM-UHFFFAOYSA-N 2,2,4,4,6,6-hexamethyl-1,3,5,2,4,6-triazatrisilinane Chemical compound C[Si]1(C)N[Si](C)(C)N[Si](C)(C)N1 WGGNJZRNHUJNEM-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 125000000962 organic group Chemical group 0.000 description 1
- 150000001282 organosilanes Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007704 wet chemistry method Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/308—Oxynitrides
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/312—Organic layers, e.g. photoresist
- H01L21/3121—Layers comprising organo-silicon compounds
- H01L21/3122—Layers comprising organo-silicon compounds layers comprising polysiloxane compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
- H01L21/31612—Deposition of SiO2 on a silicon body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31633—Deposition of carbon doped silicon oxide, e.g. SiOC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
Definitions
- Embodiments of the present invention generally relate to the fabrication of integrated circuits. More particularly, embodiments of the present invention relate to a process for depositing thin layers comprising silicon, carbon, and optionally oxygen and/or nitrogen on low dielectric constant layers.
- Integrated circuit geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years.
- Moore's Law the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years.
- Today's fabrication facilities are routinely producing devices having 0.13 ⁇ m and even 0.1 ⁇ m feature sizes, and tomorrow's facilities soon will be producing devices having even smaller feature sizes.
- insulators having low dielectric constants are desirable.
- low dielectric constant organosilicon films having dielectric constants less than about 3.0 have been developed.
- Extreme low k (ELK) films having dielectric constants less than 2.5 have also been developed.
- One method that has been used to develop low dielectric and extreme low dielectric constant organosilicon films has been to deposit the films from a gas mixture comprising an organosilicon compound and a compound, such as a hydrocarbon, comprising thermally labile species or volatile groups and then post-treat the deposited films to remove the thermally labile species or volatile groups, such as organic groups, from the deposited films.
- the removal of the thermally labile species or volatile groups from the deposited films creates nanometer-sized voids or pores in the films, which lowers the dielectric constant of the films, as air has a dielectric constant of approximately 1.
- Ashing processes to remove photoresists or bottom anti-reflective coatings (BARC) can deplete carbon from the low k films and oxidize the surface of the films.
- the oxidized surface of the low k films is removed during subsequent wet etch processes and contributes to undercuts and critical dimension (CD) loss.
- CD critical dimension
- the porosity of the low dielectric constant films can also result in the penetration of precursors used in the deposition of subsequent layers on the films, such as BARC layers or intermetallic barrier layers (TaN, etc.).
- precursors used in the deposition of subsequent layers on the films such as BARC layers or intermetallic barrier layers (TaN, etc.).
- the diffusion of barrier layer precursors into the porous low dielectric constant films results in current leakage in a device.
- the present invention generally provides a method of depositing a thin, conformal pore-sealing surface layer on a low dielectric constant film on a substrate in a chamber.
- the method comprises removing a photoresist from a patterned low dielectric constant film, and then treating the patterned low dielectric constant film having any aspect ratio or via dimension by depositing a thin, conformal layer having a controlled thickness of between about 4 ⁇ and about 100 ⁇ and comprising silicon and carbon and optionally oxygen and/or nitrogen on a surface of the patterned low dielectric constant film.
- depositing the layer comprises reacting octamethylcyclotetrasiloxane in the presence of a low level of RF power.
- the deposited layer recovers the surface carbon concentration of the low dielectric constant film after ashing and provides a hydrophobic surface for the patterned low dielectric constant film.
- the wet etch rate of a low dielectric constant film is minimized when its surface is hydrophobic.
- the layer protects the low dielectric constant film from subsequent wet cleaning processes that may be performed on the substrate and prevents undercuts and CD loss.
- the hydrophobic surface provided by the thin layer prevents moisture adsorption into the low dielectric constant films.
- a low dielectric constant film surface becomes oxidized and contains OH groups after photoresist ashing.
- the surface absorbs moisture and greatly increases the dielectric constant.
- Deposition of the thin layer after photoresist ashing drives out moisture absorbed in the surface and removes OH groups at the surface of the low dielectric constant film, and thus recovers the low dielectric constant.
- the deposition of the thin layer provides a hydrophobic sealing layer which prevents further moisture adsorption.
- Octamethylcyclotetrasiloxane is an example of a precursor that may be used to deposit the thin layers described herein.
- R x —Si—(OR′) y such as dimethyldimethoxysilane (CH 3 ) 2 —Si—(O—CH 3 ) 2 , wherein R ⁇ H, CH 3 , CH 2 CH 3 , or another alkyl group, R′ ⁇ CH 3 , CH 2 CH 3 ,
- linear organosiloxanes examples include linear organosiloxanes.
- the linear organosiloxanes may include the structure (R X —Si—O—Si—R Y ) z , such as 1,3-dimethyldisiloxane (CH 3 —SiH 2 —O—SiH 2 —CH 3 ), 1,1,3,3-tetramethyldisiloxane ((CH 3 ) 2 —SiH—O—SiH—(CH 3 ) 2 ), hexamethyldisiloxane ((CH 3 ) 3 —Si—O—Si—(CH 3 ) 3 ), etc.
- R X —Si—O—Si—R Y ) z such as 1,3-dimethyldisiloxane (CH 3 —SiH 2 —O—SiH 2 —CH 3 ), 1,1,3,3-tetramethyldisiloxane ((CH 3 )
- cyclic organosiloxanes R X —Si—O Y
- R X —Si—O cyclic organosiloxanes
- R X —Si—O cyclic organosiloxanes
- R X —Si—O cyclic organosiloxanes
- R Y ⁇ H, CH 3 , CH 2 CH 3 , or another alkyl group
- Cyclic organosilicon compounds that may be used may include a ring structure having three or more silicon atoms and the ring structure may further comprise one or more oxygen atoms.
- Commercially available cyclic organosilicon compounds include rings having alternating silicon and oxygen atoms with one or two alkyl groups bonded to the silicon atoms.
- the cyclic organosilicon compounds may include one or more of the following compounds:
- the thin layer comprises silicon, carbon, and optionally oxygen.
- the precursor may be a silicon and nitrogen-containing precursor that is used to deposit a thin conformal layer comprising silicon, nitrogen, and optionally carbon.
- the precursor may include linear silazanes and cyclic silazanes.
- the cyclic silazanes compounds may include a ring structure having three or more silicon atoms and the ring structure may further comprise one or more nitrogen atoms.
- Commercially available cyclic silazanes compounds include rings having alternating silicon and nitrogen atoms with one or two alkyl groups bonded to the silicon atoms.
- the cyclic silazanes compounds may include following:
- the thin, conformal layer can be deposited on any blanket or patterned film containing OH, NH, or NH 2 groups at the surface, including dielectric films and metallic films with oxide at the surface (such as Cu/CuO or Al/Al 2 O 3 ), as a protective layer to prevent moisture adsorption and wet chemistry etching, or a pore-sealing layer to prevent penetration of precursors or chemicals.
- the thin layer can also serve as a pore-sealing layer for porous dielectric films or metallic films with OH, NH, or NH 2 groups at the surface.
- FIGS. 1A-1E depict schematic cross-sectional views of a substrate structure at different stages of a process sequence according to an embodiment of the invention.
- FIG. 2 is a graph showing the dielectric constant (k) of low dielectric constant films before and after ashing and of low dielectric constant films having a thin OMCTS layer deposited thereon after ashing according to an embodiment of the invention.
- FIG. 3 is a graph showing the wetting angle of low dielectric constant films before and after ashing and of low dielectric constant films having a thin OMCTS layer deposited thereon after ashing according to an embodiment of the invention.
- FIG. 4A is a sketch of a trench profile (dense array) after ashing and before wet cleaning according to the prior art.
- FIG. 4B is a sketch of a trench profile (dense array) after ashing and wet cleaning according to the prior art.
- FIG. 4C is a sketch of a trench profile (dense array) after ashing and wet cleaning according to an embodiment of the invention.
- FIG. 5A is a sketch of a trench profile (iso structure/open area) after ashing and before wet cleaning according to the prior art.
- FIG. 5B is a sketch of a trench profile (iso structure/open area) after ashing and wet cleaning according to the prior art.
- FIG. 5C is a sketch of a trench profile (iso structure/open area) after ashing and wet cleaning according to an embodiment of the invention.
- FIG. 6 is a graph showing the wetting angle of a thin OMCTS layer according to an embodiment of the invention versus the length of time of a helium plasma post-treatment of the layer.
- Embodiments of the present invention provide a method of depositing a thin, conformal layer comprising silicon, carbon, and optionally oxygen and/or nitrogen on a patterned substrate.
- embodiments of the present invention provide a method of protecting a patterned low dielectric constant film after a photoresist that has been used to pattern the low dielectric constant film is removed from the film.
- embodiments of the present invention provide a method of controlling the critical dimension of a metal line in an interconnect and a method of controlling the thickness of a deposited layer to between about 4 ⁇ and about 100 ⁇ .
- a low dielectric constant film on a substrate is patterned using a photoresist and photolithography to form a vertical interconnect or a horizontal interconnect opening therein.
- the low dielectric constant film may be a film comprising silicon, carbon, and optionally oxygen and/or nitrogen.
- the low dielectric constant film may be deposited from a gas mixture comprising an organosilicon compound, such as an organosilane or organosiloxane.
- the gas mixture may also include an oxidizing gas.
- the gas mixture comprises an organosilicon compound and a porogen, such as a hydrocarbon, that is removed from the film after the film is deposited to create voids or pores in the film and lower the dielectric constant of the film.
- the porogen may be removed by a UV treatment, electron beam treatment, thermal treatment, or a combination thereof.
- Methods of forming porous low dielectric constant films are further described in commonly assigned U.S. Pat. No. 6,936,551 and in commonly assigned U.S. Pat. No. 7,060,330, which are herein incorporated by reference. It is noted that low dielectric constant films that have other compositions and/or are deposited from different gas mixtures can be used in embodiments of the invention.
- films other than low dielectric constant films can be used in embodiments, such as any films containing OH, NH, or NH 2 groups at the surface.
- the films that may be used have an oxygen-rich or nitrogen-rich surface that allows the selective deposition of a thin film comprising silicon, carbon, and optionally oxygen and/or nitrogen thereon.
- an oxygen-rich surface has a Si:O (silicon:oxygen) ratio of between about 1:1 to about 1:3.
- a nitrogen-rich surface has a Si:N (silicon:nitrogen) ratio of between about 1:1 to about 1:2.
- the films may be deposited on an oxygen-rich or nitrogen-rich surface, the films typically do not grow on carbon-rich surfaces, and thus, the deposition of the films on oxygen-rich or nitrogen-rich surfaces may be described as selective deposition processes.
- FIG. 1A shows an example of low dielectric constant film 102 on a substrate 100 .
- FIG. 1B shows a patterned photoresist 104 on the low dielectric constant film 102 .
- FIG. 1C shows the low dielectric constant film 102 after it has been patterned by the photoresist 104 to form an interconnect 106 and the photoresist has been removed.
- a thin, conformal layer 108 i.e., a layer having a thickness of about 4 ⁇ and about 100 ⁇ , comprising silicon, carbon, and optionally oxygen and/or nitrogen, is then deposited on a surface of the patterned low dielectric constant film, as shown in FIG. 1D .
- the layer may be deposited by reacting a gas mixture, such as a gas mixture comprising silicon, oxygen, and carbon, in the presence of RF power.
- the silicon, oxygen, and carbon may be provided by an organosilicon compound such as octamethylcyclotetrasiloxane.
- the organosilicon compound is typically introduced into a chamber with a carrier gas.
- the carrier gas is helium.
- other inert gases, such as argon or nitrogen, may be used.
- the substrate may be wet cleaned, such as with a 100:1 HF solution.
- a layer 110 such as a PVD barrier layer or an ALD barrier layer, e.g., an ALD tantalum nitride (TaN) layer, may be deposited on the layer.
- a layer, such as a barrier anti-reflective coating (BARC) layer 120 may be deposited on the layer 108 and fill the interconnect 106 .
- BARC barrier anti-reflective coating
- the layer comprising silicon, carbon, and optionally oxygen and/or nitrogen may be deposited in a chemical vapor deposition chamber or a plasma enhanced chemical vapor deposition chamber by reacting a gas mixture comprising an organosilicon compound in the presence of RF power.
- chambers that may be used to deposit the layer include a PRODUCER® chamber with two isolated processing regions and a DxZ® chamber, both of which are available from Applied Materials, Inc. of Santa Clara, Calif.
- the processing conditions provided herein are provided for a 300 mm PRODUCER® chamber with two isolated processing regions. Thus, the flow rates experienced per each substrate processing region and substrate are half of the flow rates into the chamber.
- the substrate is typically maintained at a temperature between about 150° C. and about 400° C.
- RF power is provided at a power level of about 100 W or less, such as between about 30 W and about 75 W, for a 300 mm substrate.
- the RF power may be provided at about 0.109 W/cm 2 or less, such as between about 0.033 W/cm 2 and about 0.082 W/cm 2 .
- the RF power may be provided to a showerhead, i.e., a gas distribution assembly, and/or a substrate support of the chamber.
- the RF power is provided at a high frequency between about 13 MHz and 14 MHz, preferably about 13.56 MHz.
- the RF power may be cycled or pulsed.
- the RF power may also be continuous or discontinuous.
- the spacing between the showerhead and the substrate support is greater than about 200 mils, such as between about 200 mils and about 1400 mils.
- the pressure in the chamber is about 1.5 Torr or greater, such as between about 1.5 Torr and about 8 Torr.
- the organosilicon compound may be introduced into the chamber at a flow rate of between about 100 sccm and about 1000 sccm.
- a carrier gas may be introduced into the chamber at a flow rate of between about 100 sccm and about 7,000 sccm.
- the ratio of the flow rate of the organosilicon compound, e.g., octamethylcyclotetrasiloxane (OMCTS, sccm), to the flow rate of the carrier gas, e.g., helium (sccm), into the chamber is about 0.1 or greater.
- the layer may be deposited for a period of time, such as between about 0.1 seconds and about 600 seconds depending on the aspect ratio of patterned structure, to deposit the layer to a thickness between about 4 ⁇ and about 100 ⁇ .
- the layer is deposited for a longer period of time when higher aspect ratios are used in order to provide a conformal surface.
- a thin, uniform, conformal layer having a thickness of only between about 4 ⁇ and about 100 ⁇ can be reliably deposited when a self-saturating organosilicon compound is used as a precursor to deposit the layer.
- a 1 ⁇ thickness range of the layer within a single 300 mm substrate has been obtained using the conditions provided herein.
- a “self-saturating precursor” is a precursor that deposits one thin layer, e.g., only one molecular layer of the precursor disregarding the length of deposition time, on a substrate.
- the thickness can be controlled by the choice of the precursor, as different precursors have different molecular sizes, resulting in different thicknesses for one molecular layer for different precursors.
- the presence of the thin layer hinders the further deposition of additional layers from the precursor under the processing conditions used to deposit the thin layer.
- the self-saturating precursor may comprise a methyl group that is selected to suppress continued growth of the thin layer.
- OMCTS is a preferred self-saturating precursor as it contains a large number of methyl groups that result in a self-saturating deposition of a layer, as the carbon in the methyl groups provides a carbon-rich film surface that substantially hinders further deposition thereon.
- a conformal first layer may be deposited from OMCTS because as soon as the surface of the underlying substrate is covered with OMCTS molecules, the presence of the Si—CH 3 bonds at the surface of the deposited layer provides a carbon-rich surface that hinders further deposition until some of the methyl groups are removed by some other treatment of the layer.
- the deposition of each molecular layer of OMCTS can be well controlled, which enhances the step coverage of the final layer.
- Other precursors that may be used include linear organosiloxanes and cyclic organosiloxane.
- the linear and cyclic organosiloxanes may include the structure (R X —Si—O—Si—R Y ) z , or the structure (R X —Si—O) Y , wherein R X ⁇ CH 3 , CH 2 CH 3 , or another alkyl group, and R Y ⁇ H, CH 3 , CH 2 CH 3 , or another alkyl group.
- precursors include diethoxymethylsilane (DEMS), hexamethyldisiloxane (HMDOS), and hexamethyldisilane (HMDS).
- DEMS diethoxymethylsilane
- HMDOS hexamethyldisiloxane
- HMDS hexamethyldisilane
- Other precursors containing Si, C, and H may be used in the process, such as trimethylsilane, tetramethylsilane, etc.
- X-ray photoelectron spectroscopy (XPS) analysis was performed on low dielectric constant films that had not been exposed to an ashing process and on low dielectric constant films that had been exposed to a photoresist ashing.
- XPS analysis was also performed on low dielectric constant films that were exposed to photoresist ashing and then treated by depositing a thin layer thereon, with the thin layer being deposited from OMCTS and comprising silicon, carbon, and oxygen according to embodiments of the invention.
- the XPS analysis showed that depositing the thin layer on the ashed low dielectric constant films provide a higher carbon content (atomic % carbon) at the surface of those films compared to the low dielectric constant films that were not treated by depositing the thin layer thereon.
- the ashed low dielectric constant films may have about 3 atomic % carbon, while the thin layer on the ashed low dielectric constant films provides about 15 atomic % carbon at the surface.
- the thin layer is a carbon-rich layer.
- the thin layer may have a carbon content of between about 5 atomic % and about 30 atomic %. Ashing depletes the carbon concentration at the surface of low dielectric constant film, while depositing the thin layer on the ashed low dielectric constant film recovers the surface carbon concentration.
- FIG. 2 shows that depositing a thin layer using OMCTS on the low dielectric constant films lowered the post-ashing dielectric constant of films subjected to one of three different ashing processes.
- the wetting angle for low dielectric constant films pre- and post-ashing (ELK ILD, i.e., extreme low k interlayer dielectric, and Ashed ELK ILD, respectively, in FIG. 3 ), and for low dielectric constant films post-ashing and having a thin OMCTS layer (Ashed ELK ILD with OMCTS deposition in FIG. 3 ) thereon was also measured. The results are shown in FIG. 3 .
- depositing the thin OMCTS layer on the low dielectric constant films post-ashing increased the wetting angle of the low dielectric constant films.
- the increased wetting angle shows that the thin OMCTS layer increased the hydrophobicity of the low dielectric constant films' surfaces.
- Such an increase in hydrophobicity is desirable, as a hydrophobic surface prevents moisture adsorption into the low dielectric constant films which can affect film performance or at least result in a need for time consuming steps to remove the moisture.
- the effect of the deposition of the thin, conformal OMCTS layer on the profile of interconnects after a post ash wet clean was also examined.
- the trench profiles of regions having high densities of trenches and low densities of trenches in low dielectric constant films with and without the thin OMCTS layer thereon were examined after the films were dipped in a 100:1 HF solution in a wet clean process.
- FIGS. 4A-4C show the trench profiles of regions having a high density of trenches.
- FIG. 4A shows the trench profile after ashing and before the wet clean.
- FIGS. 4B and 4C shows the trench profile after ashing and after the wet clean for low dielectric constant films without and with the thin OMCTS layer thereon, respectively.
- FIG. 4B shows that the wet clean causes a critical dimension loss of about 30 nm for trenches in a low dielectric constant film without the thin OMCTS layer thereon.
- FIG. 4C shows that such a CD loss was not observed when the low dielectric constant film had the thin OMCTS layer deposited thereon before the wet clean.
- FIGS. 5A-5C show the trench profiles of regions having a low density of trenches.
- FIG. 5A shows the trench profile after ashing and before the wet clean.
- FIGS. 5B and 5C shows the trench profile after ashing and after the wet clean for low dielectric constant films without and with the thin OMCTS layer thereon, respectively.
- FIG. 5B shows that the wet clean causes an undercut of greater than about 30 nm for trenches in a low dielectric constant film without the thin OMCTS layer thereon.
- FIG. 5C shows that such undercutting was not observed when the low dielectric constant film had the thin OMCTS layer deposited thereon before the wet clean.
- the thin OMCTS layer provides a carbon rich surface, which in turn provides a hydrophobic surface that prevents the critical dimension loss and undercutting of the low k films during wet etch processes.
- the thin layers provided according to embodiments of the invention act as dense, pore-sealing layers that can prevent the penetration of a material, such as a BARC material for a subsequently deposited BARC layer, or a PVD barrier precursor or an ALD barrier precursor, e.g., an ALD TaN precursor, for a subsequently deposited barrier layer, into porous low k films onto which the thin layers may be deposited.
- a material such as a BARC material for a subsequently deposited BARC layer, or a PVD barrier precursor or an ALD barrier precursor, e.g., an ALD TaN precursor, for a subsequently deposited barrier layer, into porous low k films onto which the thin layers may be deposited.
- the thin layer may be deposited on a low dielectric constant film after a via etch and photoresist ashing in a via first damascene process. Subsequent BARC filling may be performed on the thin layer.
- the thin layer provides a pore-sealing layer that prevents the penetration of the BARC material into the dielectric film.
- a dielectric barrier that is between the low dielectric constant film and an underlying conductive material, such as copper, may then be etched to expose the underlying conductive material after a trench etch and photoresist removal.
- a reducing chemistry may be used to clean the conductive surface exposed by the removal of the dielectric barrier and to remove an oxide from the surface, such as copper oxide (CuO).
- CuO copper oxide
- the thin layer is then deposited on the sidewalls of the via and trench.
- the thin layer provides a pore-sealing layer that prevents the penetration of subsequent barrier layer precursors into the low dielectric constant film.
- the thin layer may be helium (or other inert gas) plasma post-treated to adjust the carbon concentration at the surface of the thin layer and the wetting angle of the thin layer.
- the wetting angle may be decreased to about 70° C. or less to enhance the wetting and deposition of the BARC layer.
- FIG. 6 shows that the wetting angle decreases with increasing plasma treatment time. Mild processing conditions, i.e., an RF power of between about 30 W and about 100 W and a He flow rate of between about 100 sccm and about 10,000 sccm, are used such that the plasma treatment does not damage the pore-sealing nature of the thin layer.
- the thin layer may also be helium plasma post-treated before the deposition of layers other than BARC layers thereon, such as ALD barrier layers, if the surface wetting or contact angle needs to be adjusted.
- the thin layer may be plasma post-treated with different gases, such as O 2 , CO 2 , N 2 O, NH 3 , H 2 , helium, nitrogen, argon, or combinations thereof.
- the plasma post-treatment can modify the surface nature and characteristics of the layer, such as the surface tension and surface contact angle.
- a method of controlling the critical dimension of a metal line in an interconnect includes depositing a thin layer on a patterned low dielectric constant film, as described in embodiments above.
- the patterned low dielectric constant film may comprise an oxygen-rich or nitrogen-rich surface before the deposition of the thin layer thereon.
- the flow of the precursor used to deposit the layer such as OMCTS, is then terminated, and any remaining precursor is purged from the chamber by introducing carrier gas only, such as He carrier gas, into the chamber.
- carrier gas only such as He carrier gas
- an oxygen plasma treatment is performed in the chamber to treat the layer that is deposited on the substrate from the precursor and initiate next cycle of deposition, such as an OMCTS deposition.
- an NH 3 plasma treatment with or without the addition of H 2 can be used if a nitrogen-doped oxide or SiN layer is desired.
- the oxygen plasma may be provided by any oxygen-containing gas capable of generating oxygen radicals that oxidize the surface of the layer.
- the gas may include O 2 , CO 2 , N 2 O, or a combination thereof.
- the oxygen-containing gas may be introduced into the chamber at a flow rate.
- the oxygen-containing gas may be flowed into the chamber for a period of time such as between about 0.1 seconds and about 60 seconds depending on the via/trench pattern profile.
- the oxygen plasma may be provided by applying a RF power of between about 50 W and about 1000 W in the chamber at a frequency of 13.56 MHz. Mixed frequency RF power can be used.
- a low level of high frequency RF power is preferred, such as between about 30 W and about 100 W, which corresponds to between about 0.033 W/cm 2 and about 0.082 W/cm 2 .
- the plasma treatment may be terminated by terminating the flow of the oxygen-containing gas into the chamber.
- the thickness of the deposited layer is then measured.
- the flow of the precursor into the chamber is then resumed to deposit an additional amount of the thin layer.
- the chamber is purged and then an oxygen plasma treatment as described above is also done. Multiple cycles of deposition, purging, and plasma treatment may be performed until the desired thickness of layer is obtained.
- the thickness of a subsequently deposited metal line in the interconnect may be controlled.
- a method of controlling the thickness of a layer to between about 4 ⁇ and about 100 ⁇ on a substrate is provided.
- the substrate which may comprise an oxygen-rich or nitrogen-rich surface, is exposed to a silicon-containing precursor in the presence of a plasma to deposit a layer on the substrate, and then the layer is treated with a plasma from NH 3 with or without H 2 or with a plasma from an oxygen-containing gas selected from the group consisting of O 2 , CO 2 , and N 2 O.
- the exposure of the substrate to the silicon-containing precursor to deposit a layer and the treatment of the layer with a plasma are repeated until a desired thickness of the layer is obtained.
- a method of producing a dense dielectric spacer comprising either an oxide or a nitride comprises exposing a patterned substrate comprising a gate, which may comprise an oxygen-rich or nitrogen-rich surface, to a silicon-containing precursor in the presence of a plasma to deposit a layer on the gate and then treating the layer with a plasma from an oxygen-containing gas or nitrogen-containing gas selected from the group consisting of O 2 , CO 2 , N 2 O, a nitrogen-containing gas, and NH 3 with or without H 2 .
- the silicon-containing precursors and the plasma treatments provided above with respect to the method of controlling the critical dimension of a metal line in an interconnect may also be used for both the method of producing a dense dielectric spacer and the method of controlling the thickness of a layer to between about 4 ⁇ and about 100 ⁇ .
Abstract
Methods of processing films on substrates are provided. In one aspect, the methods comprise treating a patterned low dielectric constant film after a photoresist is removed form the film by depositing a thin layer comprising silicon, carbon, and optionally oxygen and/or nitrogen on the film. The thin layer provides a carbon-rich, hydrophobic surface for the patterned low dielectric constant film. The thin layer also protects the low dielectric constant film from subsequent wet cleaning processes and penetration by precursors for layers that are subsequently deposited on the low dielectric constant film.
Description
- This application claims benefit of U.S. provisional patent application Ser. No. 60/866,770, filed Nov. 21, 2006, which is herein incorporated by reference. This application is also a continuation-in-part of U.S. patent application Ser. No. 11/668,911, filed on Jan. 30, 2007, which claims benefit of U.S. provisional patent application Ser. No. 60/790,254, filed on Apr. 7, 2006, and of U.S. provisional patent application Ser. No. 60/788,279, filed Mar. 31, 2006, all of which are herein incorporated by reference.
- 1. Field of the Invention
- Embodiments of the present invention generally relate to the fabrication of integrated circuits. More particularly, embodiments of the present invention relate to a process for depositing thin layers comprising silicon, carbon, and optionally oxygen and/or nitrogen on low dielectric constant layers.
- 2. Description of the Related Art
- Integrated circuit geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication facilities are routinely producing devices having 0.13 μm and even 0.1 μm feature sizes, and tomorrow's facilities soon will be producing devices having even smaller feature sizes.
- The continued reduction in device geometries has generated a demand for inter layer dielectric films having lower dielectric constant (k) values because the capacitive coupling between adjacent metal lines must be reduced to further reduce the size of devices on integrated circuits. In particular, insulators having low dielectric constants, less than about 4.0, are desirable.
- More recently, low dielectric constant organosilicon films having dielectric constants less than about 3.0 have been developed. Extreme low k (ELK) films having dielectric constants less than 2.5 have also been developed. One method that has been used to develop low dielectric and extreme low dielectric constant organosilicon films has been to deposit the films from a gas mixture comprising an organosilicon compound and a compound, such as a hydrocarbon, comprising thermally labile species or volatile groups and then post-treat the deposited films to remove the thermally labile species or volatile groups, such as organic groups, from the deposited films. The removal of the thermally labile species or volatile groups from the deposited films creates nanometer-sized voids or pores in the films, which lowers the dielectric constant of the films, as air has a dielectric constant of approximately 1.
- Ashing processes to remove photoresists or bottom anti-reflective coatings (BARC) can deplete carbon from the low k films and oxidize the surface of the films. The oxidized surface of the low k films is removed during subsequent wet etch processes and contributes to undercuts and critical dimension (CD) loss.
- The porosity of the low dielectric constant films can also result in the penetration of precursors used in the deposition of subsequent layers on the films, such as BARC layers or intermetallic barrier layers (TaN, etc.). The diffusion of barrier layer precursors into the porous low dielectric constant films results in current leakage in a device.
- Therefore, there remains a need for a method of processing low dielectric constant films that minimizes damage to the films from subsequent processing steps, such as wet etch processes and the deposition of subsequent layers, such as BARC layers and barrier layers.
- The present invention generally provides a method of depositing a thin, conformal pore-sealing surface layer on a low dielectric constant film on a substrate in a chamber. The method comprises removing a photoresist from a patterned low dielectric constant film, and then treating the patterned low dielectric constant film having any aspect ratio or via dimension by depositing a thin, conformal layer having a controlled thickness of between about 4 Å and about 100 Å and comprising silicon and carbon and optionally oxygen and/or nitrogen on a surface of the patterned low dielectric constant film. In one embodiment, depositing the layer comprises reacting octamethylcyclotetrasiloxane in the presence of a low level of RF power. Ashing a photoresist depletes carbon from the surface of the low dielectric constant film, and the surface becomes hydrophilic. The deposited layer recovers the surface carbon concentration of the low dielectric constant film after ashing and provides a hydrophobic surface for the patterned low dielectric constant film. The wet etch rate of a low dielectric constant film is minimized when its surface is hydrophobic. The layer protects the low dielectric constant film from subsequent wet cleaning processes that may be performed on the substrate and prevents undercuts and CD loss. The hydrophobic surface provided by the thin layer prevents moisture adsorption into the low dielectric constant films.
- A low dielectric constant film surface becomes oxidized and contains OH groups after photoresist ashing. The surface absorbs moisture and greatly increases the dielectric constant. Deposition of the thin layer after photoresist ashing drives out moisture absorbed in the surface and removes OH groups at the surface of the low dielectric constant film, and thus recovers the low dielectric constant. The deposition of the thin layer provides a hydrophobic sealing layer which prevents further moisture adsorption.
- Octamethylcyclotetrasiloxane (OMCTS) is an example of a precursor that may be used to deposit the thin layers described herein. In addition to octamethylcyclotetrasiloxane, precursors having the general formula Rx—Si—(OR′)y, such as dimethyldimethoxysilane (CH3)2—Si—(O—CH3)2, wherein R═H, CH3, CH2CH3, or another alkyl group, R′═CH3, CH2CH3, or another alkyl group, x is from 0 to 4, y is 0 to 4, and x+y=4, may also be used to deposit a thin conformal layer with a suitable process window. Other precursors that may be used include linear organosiloxanes. The linear organosiloxanes may include the structure (RX—Si—O—Si—RY)z, such as 1,3-dimethyldisiloxane (CH3—SiH2—O—SiH2—CH3), 1,1,3,3-tetramethyldisiloxane ((CH3)2—SiH—O—SiH—(CH3)2), hexamethyldisiloxane ((CH3)3—Si—O—Si—(CH3)3), etc. Other precursors that may be used include cyclic organosiloxanes (RX—Si—O)Y, wherein RX═CH3, CH2CH3, or another alkyl group, and RY═H, CH3, CH2CH3, or another alkyl group. Cyclic organosilicon compounds that may be used may include a ring structure having three or more silicon atoms and the ring structure may further comprise one or more oxygen atoms. Commercially available cyclic organosilicon compounds include rings having alternating silicon and oxygen atoms with one or two alkyl groups bonded to the silicon atoms. For example, the cyclic organosilicon compounds may include one or more of the following compounds:
- hexamethylcyclotrisiloxane (—Si(CH3)2—O—)3— cyclic,
- 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS) (—SiH(CH3)—O—)4— cyclic,
- octamethylcyclotetrasiloxane (OMCTS) (—Si(CH3)2—O—)4— cyclic, and
- 1,3,5,7,9-pentamethylcyclopentasiloxane (—SiH(CH3)—O—)5— cyclic.
- The thin layer comprises silicon, carbon, and optionally oxygen. In another embodiment, the precursor may be a silicon and nitrogen-containing precursor that is used to deposit a thin conformal layer comprising silicon, nitrogen, and optionally carbon. The precursor may include linear silazanes and cyclic silazanes. The linear and cyclic silazanes may include the structure (RX—Si—NH—Si—RY)z, or the structure (RX—Si—NH)Y, wherein RX═CH3, CH2CH3, or another alkyl group, and RY═H, CH3, CH2CH3, or another alkyl group, x is from 0 to 4, y is 0 to 4, and x+y=4. The cyclic silazanes compounds may include a ring structure having three or more silicon atoms and the ring structure may further comprise one or more nitrogen atoms. Commercially available cyclic silazanes compounds include rings having alternating silicon and nitrogen atoms with one or two alkyl groups bonded to the silicon atoms. For example, the cyclic silazanes compounds may include following:
- 1,2,3,4,5,6,7,8-octamethylcyclotetrasilazane,
- 1,2,3,4,5,6-hexamethylcyclotrisilazane,
- 1,1,3,3,5,5-hexamethylcyclotrisilazane, and
- 1,1,3,3,5,5,7,7-octamethylcyclotetrasilazane.
- The thin, conformal layer can be deposited on any blanket or patterned film containing OH, NH, or NH2 groups at the surface, including dielectric films and metallic films with oxide at the surface (such as Cu/CuO or Al/Al2O3), as a protective layer to prevent moisture adsorption and wet chemistry etching, or a pore-sealing layer to prevent penetration of precursors or chemicals. The thin layer can also serve as a pore-sealing layer for porous dielectric films or metallic films with OH, NH, or NH2 groups at the surface.
- So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
-
FIGS. 1A-1E depict schematic cross-sectional views of a substrate structure at different stages of a process sequence according to an embodiment of the invention. -
FIG. 2 is a graph showing the dielectric constant (k) of low dielectric constant films before and after ashing and of low dielectric constant films having a thin OMCTS layer deposited thereon after ashing according to an embodiment of the invention. -
FIG. 3 is a graph showing the wetting angle of low dielectric constant films before and after ashing and of low dielectric constant films having a thin OMCTS layer deposited thereon after ashing according to an embodiment of the invention. -
FIG. 4A is a sketch of a trench profile (dense array) after ashing and before wet cleaning according to the prior art.FIG. 4B is a sketch of a trench profile (dense array) after ashing and wet cleaning according to the prior art.FIG. 4C is a sketch of a trench profile (dense array) after ashing and wet cleaning according to an embodiment of the invention. -
FIG. 5A is a sketch of a trench profile (iso structure/open area) after ashing and before wet cleaning according to the prior art.FIG. 5B is a sketch of a trench profile (iso structure/open area) after ashing and wet cleaning according to the prior art.FIG. 5C is a sketch of a trench profile (iso structure/open area) after ashing and wet cleaning according to an embodiment of the invention. -
FIG. 6 is a graph showing the wetting angle of a thin OMCTS layer according to an embodiment of the invention versus the length of time of a helium plasma post-treatment of the layer. - Embodiments of the present invention provide a method of depositing a thin, conformal layer comprising silicon, carbon, and optionally oxygen and/or nitrogen on a patterned substrate. In one aspect, embodiments of the present invention provide a method of protecting a patterned low dielectric constant film after a photoresist that has been used to pattern the low dielectric constant film is removed from the film. In other aspects, embodiments of the present invention provide a method of controlling the critical dimension of a metal line in an interconnect and a method of controlling the thickness of a deposited layer to between about 4 Å and about 100 Å.
- In one embodiment, a low dielectric constant film on a substrate is patterned using a photoresist and photolithography to form a vertical interconnect or a horizontal interconnect opening therein. The low dielectric constant film may be a film comprising silicon, carbon, and optionally oxygen and/or nitrogen. The low dielectric constant film may be deposited from a gas mixture comprising an organosilicon compound, such as an organosilane or organosiloxane. The gas mixture may also include an oxidizing gas. In one embodiment, the gas mixture comprises an organosilicon compound and a porogen, such as a hydrocarbon, that is removed from the film after the film is deposited to create voids or pores in the film and lower the dielectric constant of the film. The porogen may be removed by a UV treatment, electron beam treatment, thermal treatment, or a combination thereof. Methods of forming porous low dielectric constant films are further described in commonly assigned U.S. Pat. No. 6,936,551 and in commonly assigned U.S. Pat. No. 7,060,330, which are herein incorporated by reference. It is noted that low dielectric constant films that have other compositions and/or are deposited from different gas mixtures can be used in embodiments of the invention.
- It is also noted that films other than low dielectric constant films can be used in embodiments, such as any films containing OH, NH, or NH2 groups at the surface. Generally, the films that may be used have an oxygen-rich or nitrogen-rich surface that allows the selective deposition of a thin film comprising silicon, carbon, and optionally oxygen and/or nitrogen thereon. As defined herein, an oxygen-rich surface has a Si:O (silicon:oxygen) ratio of between about 1:1 to about 1:3. As defined herein, a nitrogen-rich surface has a Si:N (silicon:nitrogen) ratio of between about 1:1 to about 1:2.
- While the films may be deposited on an oxygen-rich or nitrogen-rich surface, the films typically do not grow on carbon-rich surfaces, and thus, the deposition of the films on oxygen-rich or nitrogen-rich surfaces may be described as selective deposition processes.
-
FIG. 1A shows an example of low dielectricconstant film 102 on asubstrate 100.FIG. 1B shows apatterned photoresist 104 on the low dielectricconstant film 102. - The photoresist is then removed from the low dielectric constant film by stripping or ashing, for example.
FIG. 1C shows the low dielectricconstant film 102 after it has been patterned by thephotoresist 104 to form aninterconnect 106 and the photoresist has been removed. A thin,conformal layer 108, i.e., a layer having a thickness of about 4 Å and about 100 Å, comprising silicon, carbon, and optionally oxygen and/or nitrogen, is then deposited on a surface of the patterned low dielectric constant film, as shown inFIG. 1D . The layer may be deposited by reacting a gas mixture, such as a gas mixture comprising silicon, oxygen, and carbon, in the presence of RF power. The silicon, oxygen, and carbon may be provided by an organosilicon compound such as octamethylcyclotetrasiloxane. The organosilicon compound is typically introduced into a chamber with a carrier gas. Preferably, the carrier gas is helium. However, other inert gases, such as argon or nitrogen, may be used. - After the layer is deposited, the substrate may be wet cleaned, such as with a 100:1 HF solution. Then, as shown in
FIG. 1E , alayer 110, such as a PVD barrier layer or an ALD barrier layer, e.g., an ALD tantalum nitride (TaN) layer, may be deposited on the layer. Alternatively, as shown inFIG. 1F , a layer, such as a barrier anti-reflective coating (BARC)layer 120, may be deposited on thelayer 108 and fill theinterconnect 106. - The layer comprising silicon, carbon, and optionally oxygen and/or nitrogen may be deposited in a chemical vapor deposition chamber or a plasma enhanced chemical vapor deposition chamber by reacting a gas mixture comprising an organosilicon compound in the presence of RF power. Examples of chambers that may be used to deposit the layer include a PRODUCER® chamber with two isolated processing regions and a DxZ® chamber, both of which are available from Applied Materials, Inc. of Santa Clara, Calif. The processing conditions provided herein are provided for a 300 mm PRODUCER® chamber with two isolated processing regions. Thus, the flow rates experienced per each substrate processing region and substrate are half of the flow rates into the chamber.
- During deposition of the layer on a substrate in the chamber, the substrate is typically maintained at a temperature between about 150° C. and about 400° C. RF power is provided at a power level of about 100 W or less, such as between about 30 W and about 75 W, for a 300 mm substrate. Generally, the RF power may be provided at about 0.109 W/cm2 or less, such as between about 0.033 W/cm2 and about 0.082 W/cm2. The RF power may be provided to a showerhead, i.e., a gas distribution assembly, and/or a substrate support of the chamber. The RF power is provided at a high frequency between about 13 MHz and 14 MHz, preferably about 13.56 MHz. The RF power may be cycled or pulsed. The RF power may also be continuous or discontinuous. The spacing between the showerhead and the substrate support is greater than about 200 mils, such as between about 200 mils and about 1400 mils. The pressure in the chamber is about 1.5 Torr or greater, such as between about 1.5 Torr and about 8 Torr.
- The organosilicon compound may be introduced into the chamber at a flow rate of between about 100 sccm and about 1000 sccm. A carrier gas may be introduced into the chamber at a flow rate of between about 100 sccm and about 7,000 sccm. The ratio of the flow rate of the organosilicon compound, e.g., octamethylcyclotetrasiloxane (OMCTS, sccm), to the flow rate of the carrier gas, e.g., helium (sccm), into the chamber is about 0.1 or greater. The layer may be deposited for a period of time, such as between about 0.1 seconds and about 600 seconds depending on the aspect ratio of patterned structure, to deposit the layer to a thickness between about 4 Å and about 100 Å. Typically, the layer is deposited for a longer period of time when higher aspect ratios are used in order to provide a conformal surface.
- It has been found that using the RF power levels, spacing, pressure, and flow rate ratios described above, a thin, uniform, conformal layer having a thickness of only between about 4 Å and about 100 Å can be reliably deposited when a self-saturating organosilicon compound is used as a precursor to deposit the layer. A 1 Å thickness range of the layer within a single 300 mm substrate has been obtained using the conditions provided herein. As defined herein, a “self-saturating precursor” is a precursor that deposits one thin layer, e.g., only one molecular layer of the precursor disregarding the length of deposition time, on a substrate. The thickness can be controlled by the choice of the precursor, as different precursors have different molecular sizes, resulting in different thicknesses for one molecular layer for different precursors. The presence of the thin layer hinders the further deposition of additional layers from the precursor under the processing conditions used to deposit the thin layer. Generally, the self-saturating precursor may comprise a methyl group that is selected to suppress continued growth of the thin layer. OMCTS is a preferred self-saturating precursor as it contains a large number of methyl groups that result in a self-saturating deposition of a layer, as the carbon in the methyl groups provides a carbon-rich film surface that substantially hinders further deposition thereon. In other words, a conformal first layer may be deposited from OMCTS because as soon as the surface of the underlying substrate is covered with OMCTS molecules, the presence of the Si—CH3 bonds at the surface of the deposited layer provides a carbon-rich surface that hinders further deposition until some of the methyl groups are removed by some other treatment of the layer. Thus, the deposition of each molecular layer of OMCTS can be well controlled, which enhances the step coverage of the final layer.
- Other than octamethylcyclotetrasiloxane, precursors having the general formula Rx—Si—(OR′)y, wherein R═H, CH3, CH2CH3, or another alkyl group, R′═CH3, CH2CH3, or another alkyl group, x is from 0 to 4, y is 0 to 4, and x+y=4, may also be used to deposit a thin conformal layer with a suitable process window. Other precursors that may be used include linear organosiloxanes and cyclic organosiloxane. The linear and cyclic organosiloxanes may include the structure (RX—Si—O—Si—RY)z, or the structure (RX—Si—O)Y, wherein RX═CH3, CH2CH3, or another alkyl group, and RY═H, CH3, CH2CH3, or another alkyl group. Examples of precursors that may be used include diethoxymethylsilane (DEMS), hexamethyldisiloxane (HMDOS), and hexamethyldisilane (HMDS). Other precursors containing Si, C, and H may be used in the process, such as trimethylsilane, tetramethylsilane, etc.
- X-ray photoelectron spectroscopy (XPS) analysis was performed on low dielectric constant films that had not been exposed to an ashing process and on low dielectric constant films that had been exposed to a photoresist ashing. XPS analysis was also performed on low dielectric constant films that were exposed to photoresist ashing and then treated by depositing a thin layer thereon, with the thin layer being deposited from OMCTS and comprising silicon, carbon, and oxygen according to embodiments of the invention. The XPS analysis showed that depositing the thin layer on the ashed low dielectric constant films provide a higher carbon content (atomic % carbon) at the surface of those films compared to the low dielectric constant films that were not treated by depositing the thin layer thereon. For example, the ashed low dielectric constant films may have about 3 atomic % carbon, while the thin layer on the ashed low dielectric constant films provides about 15 atomic % carbon at the surface. Thus, in one aspect, the thin layer is a carbon-rich layer. The thin layer may have a carbon content of between about 5 atomic % and about 30 atomic %. Ashing depletes the carbon concentration at the surface of low dielectric constant film, while depositing the thin layer on the ashed low dielectric constant film recovers the surface carbon concentration.
- The XPS analysis also showed that the oxygen content at the surface of the low dielectric constant films treated with the thin layer was lower than the oxygen content at the surface of the low dielectric constant films that were not treated with the thin layer after ashing, as OH groups at the surface of the ashed films was replaced by the thin layer that comprises carbon. The replacement of the OH groups at the surface of the ashed films with the thin layer that comprises carbon also lowers the dielectric constant of the ashed films.
FIG. 2 shows that depositing a thin layer using OMCTS on the low dielectric constant films lowered the post-ashing dielectric constant of films subjected to one of three different ashing processes. - The wetting angle for low dielectric constant films pre- and post-ashing (ELK ILD, i.e., extreme low k interlayer dielectric, and Ashed ELK ILD, respectively, in
FIG. 3 ), and for low dielectric constant films post-ashing and having a thin OMCTS layer (Ashed ELK ILD with OMCTS deposition inFIG. 3 ) thereon was also measured. The results are shown inFIG. 3 . As shown inFIG. 3 , depositing the thin OMCTS layer on the low dielectric constant films post-ashing increased the wetting angle of the low dielectric constant films. The increased wetting angle shows that the thin OMCTS layer increased the hydrophobicity of the low dielectric constant films' surfaces. Such an increase in hydrophobicity is desirable, as a hydrophobic surface prevents moisture adsorption into the low dielectric constant films which can affect film performance or at least result in a need for time consuming steps to remove the moisture. - The effect of the deposition of the thin, conformal OMCTS layer on the profile of interconnects after a post ash wet clean was also examined. The trench profiles of regions having high densities of trenches and low densities of trenches in low dielectric constant films with and without the thin OMCTS layer thereon were examined after the films were dipped in a 100:1 HF solution in a wet clean process.
-
FIGS. 4A-4C show the trench profiles of regions having a high density of trenches.FIG. 4A shows the trench profile after ashing and before the wet clean.FIGS. 4B and 4C shows the trench profile after ashing and after the wet clean for low dielectric constant films without and with the thin OMCTS layer thereon, respectively.FIG. 4B shows that the wet clean causes a critical dimension loss of about 30 nm for trenches in a low dielectric constant film without the thin OMCTS layer thereon.FIG. 4C shows that such a CD loss was not observed when the low dielectric constant film had the thin OMCTS layer deposited thereon before the wet clean. -
FIGS. 5A-5C show the trench profiles of regions having a low density of trenches.FIG. 5A shows the trench profile after ashing and before the wet clean.FIGS. 5B and 5C shows the trench profile after ashing and after the wet clean for low dielectric constant films without and with the thin OMCTS layer thereon, respectively.FIG. 5B shows that the wet clean causes an undercut of greater than about 30 nm for trenches in a low dielectric constant film without the thin OMCTS layer thereon.FIG. 5C shows that such undercutting was not observed when the low dielectric constant film had the thin OMCTS layer deposited thereon before the wet clean. - Thus, the thin OMCTS layer provides a carbon rich surface, which in turn provides a hydrophobic surface that prevents the critical dimension loss and undercutting of the low k films during wet etch processes.
- It was also found that the thin layers provided according to embodiments of the invention act as dense, pore-sealing layers that can prevent the penetration of a material, such as a BARC material for a subsequently deposited BARC layer, or a PVD barrier precursor or an ALD barrier precursor, e.g., an ALD TaN precursor, for a subsequently deposited barrier layer, into porous low k films onto which the thin layers may be deposited.
- For example, the thin layer may be deposited on a low dielectric constant film after a via etch and photoresist ashing in a via first damascene process. Subsequent BARC filling may be performed on the thin layer. The thin layer provides a pore-sealing layer that prevents the penetration of the BARC material into the dielectric film. A dielectric barrier that is between the low dielectric constant film and an underlying conductive material, such as copper, may then be etched to expose the underlying conductive material after a trench etch and photoresist removal. After the dielectric barrier etching, a reducing chemistry may be used to clean the conductive surface exposed by the removal of the dielectric barrier and to remove an oxide from the surface, such as copper oxide (CuO). The thin layer is then deposited on the sidewalls of the via and trench. The thin layer provides a pore-sealing layer that prevents the penetration of subsequent barrier layer precursors into the low dielectric constant film.
- In embodiments in which a BARC layer is deposited on the thin layer after wet cleaning the substrate, the thin layer may be helium (or other inert gas) plasma post-treated to adjust the carbon concentration at the surface of the thin layer and the wetting angle of the thin layer. The wetting angle may be decreased to about 70° C. or less to enhance the wetting and deposition of the BARC layer.
FIG. 6 shows that the wetting angle decreases with increasing plasma treatment time. Mild processing conditions, i.e., an RF power of between about 30 W and about 100 W and a He flow rate of between about 100 sccm and about 10,000 sccm, are used such that the plasma treatment does not damage the pore-sealing nature of the thin layer. - The thin layer may also be helium plasma post-treated before the deposition of layers other than BARC layers thereon, such as ALD barrier layers, if the surface wetting or contact angle needs to be adjusted. The thin layer may be plasma post-treated with different gases, such as O2, CO2, N2O, NH3, H2, helium, nitrogen, argon, or combinations thereof. The plasma post-treatment can modify the surface nature and characteristics of the layer, such as the surface tension and surface contact angle.
- In another embodiment, a method of controlling the critical dimension of a metal line in an interconnect is provided. The method includes depositing a thin layer on a patterned low dielectric constant film, as described in embodiments above. The patterned low dielectric constant film may comprise an oxygen-rich or nitrogen-rich surface before the deposition of the thin layer thereon. After the layer is deposited, the flow of the precursor used to deposit the layer, such as OMCTS, is then terminated, and any remaining precursor is purged from the chamber by introducing carrier gas only, such as He carrier gas, into the chamber. The chamber may be purged or pumped or purged and pumped.
- After the chamber is purged and/or pumped, in one embodiment, an oxygen plasma treatment is performed in the chamber to treat the layer that is deposited on the substrate from the precursor and initiate next cycle of deposition, such as an OMCTS deposition. In another embodiment, an NH3 plasma treatment with or without the addition of H2 can be used if a nitrogen-doped oxide or SiN layer is desired. The oxygen plasma may be provided by any oxygen-containing gas capable of generating oxygen radicals that oxidize the surface of the layer. For example, the gas may include O2, CO2, N2O, or a combination thereof. The oxygen-containing gas may be introduced into the chamber at a flow rate. The oxygen-containing gas may be flowed into the chamber for a period of time such as between about 0.1 seconds and about 60 seconds depending on the via/trench pattern profile. The oxygen plasma may be provided by applying a RF power of between about 50 W and about 1000 W in the chamber at a frequency of 13.56 MHz. Mixed frequency RF power can be used. To minimize the impact or damage of plasma treatment on the underlying layer (such as a low dielectric constant film), a low level of high frequency RF power is preferred, such as between about 30 W and about 100 W, which corresponds to between about 0.033 W/cm2 and about 0.082 W/cm2.
- The plasma treatment may be terminated by terminating the flow of the oxygen-containing gas into the chamber. Optionally, the thickness of the deposited layer is then measured. The flow of the precursor into the chamber is then resumed to deposit an additional amount of the thin layer. The chamber is purged and then an oxygen plasma treatment as described above is also done. Multiple cycles of deposition, purging, and plasma treatment may be performed until the desired thickness of layer is obtained. By controlling the thickness of the layer deposited in the interconnect, the thickness of a subsequently deposited metal line in the interconnect may be controlled.
- In another embodiment, a method of controlling the thickness of a layer to between about 4 Å and about 100 Å on a substrate is provided. The substrate, which may comprise an oxygen-rich or nitrogen-rich surface, is exposed to a silicon-containing precursor in the presence of a plasma to deposit a layer on the substrate, and then the layer is treated with a plasma from NH3 with or without H2 or with a plasma from an oxygen-containing gas selected from the group consisting of O2, CO2, and N2O. The exposure of the substrate to the silicon-containing precursor to deposit a layer and the treatment of the layer with a plasma are repeated until a desired thickness of the layer is obtained.
- In a further embodiment, a method of producing a dense dielectric spacer comprising either an oxide or a nitride is provided. The method comprises exposing a patterned substrate comprising a gate, which may comprise an oxygen-rich or nitrogen-rich surface, to a silicon-containing precursor in the presence of a plasma to deposit a layer on the gate and then treating the layer with a plasma from an oxygen-containing gas or nitrogen-containing gas selected from the group consisting of O2, CO2, N2O, a nitrogen-containing gas, and NH3 with or without H2. The silicon-containing precursors and the plasma treatments provided above with respect to the method of controlling the critical dimension of a metal line in an interconnect may also be used for both the method of producing a dense dielectric spacer and the method of controlling the thickness of a layer to between about 4 Å and about 100 Å.
- While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (26)
1. A method of processing a film on a substrate in a chamber, comprising:
treating the film by selectively depositing a thin layer having a thickness of between about 4 Å and about 100 Å and comprising silicon, carbon, and hydrogen on an oxygen-rich or nitrogen-rich surface of the film, wherein depositing the layer comprises reacting a precursor comprising Si, C, and H in the presence of RF power.
2. In the method of claim 1 , wherein the precursor is selected from the group trimethyl silane; tetramethyl silane; dimethyldimethoxysilane; 1,3-dimethyldisiloxane; 1,1,3,3-tetramethyldisiloxane; hexamethyldisiloxane; hexamethylcyclotrisiloxane; 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS); octamethylcyclotetrasiloxane (OMCTS); and 1,3,5,7,9-pentamethylcyclopentasiloxane.
3. The method of claim 1 , wherein the precursor comprises an alkyl group that is selected to suppress continued growth of the thin layer.
4. The method of claim 1 , wherein the thin layer has a higher carbon content than the oxygen-rich or nitrogen-rich surface of the film, and the thin layer provides a carbon-saturated surface layer on the film.
5. The method of claim 1 , further comprising wet cleaning the substrate after the thin layer is deposited.
6. The method of claim 1 , wherein the RF power is applied at a power level of about 0.109 W/cm2 or less.
7. The method of claim 1 , wherein the pressure in the chamber is about 1.5 Torr or greater.
8. The method of claim 1 , wherein the spacing between a showerhead in the chamber and a substrate support in the chamber is greater than about 200 mils.
9. The method of claim 1 , further comprising plasma post-treating the layer, using a gas selected from the group consisting of O2, CO2, N2O, NH3, H2, helium, argon, nitrogen, and combinations thereof.
10. The method of claim 1 , further comprising plasma post-treating the layer, wherein the plasma post-treating modifies the surface characteristics of the layer, and wherein the surface characteristics are selected from the group consisting of surface tension and surface contact angle.
11. The method of claim 1 , further comprising depositing a bottom anti-reflective coating (BARC) on the thin layer.
12. The method of claim 1 , further comprising depositing a barrier layer by atomic layer deposition or physical vapor deposition on the thin.
13. (canceled)
14. A method of controlling the thickness of a layer to between about 4 Å and about 100 Å on a substrate, comprising:
exposing a substrate to a silicon-containing precursor in the presence of a plasma to deposit a layer on the substrate;
treating the layer after it is deposited with a plasma from NH3 with or without H2, and an oxygen-containing gas selected from the group consisting of O2, CO2, and N2O; and
repeating the exposing and treating until a desired thickness of the layer is obtained.
15. The method of claim 14 , wherein the layer is deposited on an oxygen-rich or nitrogen-rich surface of the substrate.
16. The method of claim 14 , wherein the silicon-containing precursor is selected from the group consisting of precursors containing Si, C, and H; trimethyl silane; tetramethyl silane; dimethyldimethoxysilane; 1,3-dimethyldisiloxane; 1,1,3,3-tetramethyldisiloxane; hexamethyldisiloxane; hexamethylcyclotrisiloxane; 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS); octamethylcyclotetrasiloxane (OMCTS); and 1,3,5,7,9-pentamethylcyclopentasiloxane.
17. A method of controlling the thickness of a metal line in an interconnect, comprising:
exposing a patterned substrate comprising an interconnect to a silicon-containing precursor in the presence of a plasma to deposit a layer in the interconnect;
treating the layer after it is deposited with a plasma from an oxygen-containing gas selected from the group consisting of O2, CO2, and N2O, or NH3 with or without H2; and
repeating the exposing and treating until a desired thickness of the layer is obtained to provide a desired thickness of a subsequently deposited metal line in the interconnect.
18. The method of claim 17 , wherein the layer is deposited on an oxygen-rich or nitrogen-rich surface of the substrate.
19. The method of claim 18 , wherein the silicon-containing precursor is selected from the group consisting of trimethyl silane; tetramethyl silane; dimethyldimethoxysilane; 1,3-dimethyldisiloxane; 1,1,3,3-tetramethyidisiloxane; hexamethyldisiloxane; hexamethylcyclotrisiloxane; 1,3,5,7-tetramethylcyclotetrasiloxane (TMCTS); octamethylcyclotetrasiloxane (OMCTS); and 1,3,5,7,9-pentamethylcyclopentasiloxane.
20. A method of producing a dense dielectric spacer containing either oxide or nitride, comprising:
exposing a patterned substrate comprising a gate to a silicon-containing precursor in the presence of a plasma to deposit a layer on the gate;
treating the layer after it is deposited with a plasma from an oxygen or N-containing gas selected from the group consisting of O2, CO2, N2O, a nitrogen-containing gas, and NH3 with or without H2; and
repeating the exposing and treating until a desired thickness of the layer is obtained.
21. The method of claim 1 , wherein selectively depositing the thin layer is performed after the oxygen-rich or nitrogen rich surface of the film is formed during a photoresist removal process.
22. The method of claim 4 , wherein the surface of the thin layer is hydrophobic.
23. The method of claim 1 , further comprising wet cleaning the substrate after depositing the thin layer by exposing the thin layer to a wet cleaning chemistry comprising hydrofluoric acid (HF), wherein the thin layer is adapted to substantially prevent etching of the film during the wet cleaning.
24. The method of claim 23 , further comprising depositing a barrier layer or a BARO layer on the thin layer after wet cleaning the thin layer.
25. The method of claim 1 , wherein the thin layer is sufficiently dense to prevent the penetration of a material used to form a barrier layer or a BARC layer into the film.
26. The method of claim 17 , wherein the layer is a conformal layer that is deposited using a precursor containing an alkyl group.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/694,856 US20070287301A1 (en) | 2006-03-31 | 2007-03-30 | Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics |
KR1020070108170A KR100939593B1 (en) | 2006-11-21 | 2007-10-26 | Method to minimize wet etch undercuts and provide pore sealing of extreme low k less than 2.5 dielectrics |
TW096140628A TWI392024B (en) | 2006-11-21 | 2007-10-29 | Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics |
JP2007298307A JP5174435B2 (en) | 2006-11-21 | 2007-11-16 | Method for minimizing wet etch undercut and pore sealing ultra-low K (K <2.5) dielectrics |
US12/975,833 US8445075B2 (en) | 2006-03-31 | 2010-12-22 | Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US78827906P | 2006-03-31 | 2006-03-31 | |
US79025406P | 2006-04-07 | 2006-04-07 | |
US86677006P | 2006-11-21 | 2006-11-21 | |
US11/668,911 US7601651B2 (en) | 2006-03-31 | 2007-01-30 | Method to improve the step coverage and pattern loading for dielectric films |
US11/694,856 US20070287301A1 (en) | 2006-03-31 | 2007-03-30 | Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/668,911 Continuation-In-Part US7601651B2 (en) | 2006-03-31 | 2007-01-30 | Method to improve the step coverage and pattern loading for dielectric films |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/975,833 Continuation US8445075B2 (en) | 2006-03-31 | 2010-12-22 | Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics |
Publications (1)
Publication Number | Publication Date |
---|---|
US20070287301A1 true US20070287301A1 (en) | 2007-12-13 |
Family
ID=46206138
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/694,856 Abandoned US20070287301A1 (en) | 2006-03-31 | 2007-03-30 | Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics |
US12/975,833 Active US8445075B2 (en) | 2006-03-31 | 2010-12-22 | Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/975,833 Active US8445075B2 (en) | 2006-03-31 | 2010-12-22 | Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics |
Country Status (1)
Country | Link |
---|---|
US (2) | US20070287301A1 (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080261008A1 (en) * | 2007-04-18 | 2008-10-23 | Toppan Printing Co., Ltd. | Anti-reflection film |
WO2009158180A2 (en) * | 2008-06-27 | 2009-12-30 | Applied Materials, Inc. | Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer |
US20110097904A1 (en) * | 2009-10-22 | 2011-04-28 | Lam Research Corporation | Method for repairing low-k dielectric damage |
US20110244600A1 (en) * | 2009-10-22 | 2011-10-06 | Lam Research Corporation | Method for tunably repairing low-k dielectric damage |
US20120015517A1 (en) * | 2010-07-15 | 2012-01-19 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
US8445075B2 (en) | 2006-03-31 | 2013-05-21 | Applied Materials, Inc. | Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics |
CN104966694A (en) * | 2015-06-29 | 2015-10-07 | 上海集成电路研发中心有限公司 | Double Damascus integration technology method |
US20160176016A1 (en) * | 2014-12-19 | 2016-06-23 | Applied Materials, Inc. | Components for a chemical mechanical polishing tool |
US20220044929A1 (en) * | 2018-05-22 | 2022-02-10 | Versum Patents Us, Llc | Functionalized cyclosilazanes as precursors for high growth rate silicon-containing films |
Families Citing this family (324)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10378106B2 (en) | 2008-11-14 | 2019-08-13 | Asm Ip Holding B.V. | Method of forming insulation film by modified PEALD |
US9394608B2 (en) | 2009-04-06 | 2016-07-19 | Asm America, Inc. | Semiconductor processing reactor and components thereof |
US8802201B2 (en) | 2009-08-14 | 2014-08-12 | Asm America, Inc. | Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species |
JP5671253B2 (en) * | 2010-05-07 | 2015-02-18 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
KR20120030782A (en) * | 2010-09-20 | 2012-03-29 | 삼성전자주식회사 | Method of forming through silicon via using low-k material |
US9312155B2 (en) | 2011-06-06 | 2016-04-12 | Asm Japan K.K. | High-throughput semiconductor-processing apparatus equipped with multiple dual-chamber modules |
US9793148B2 (en) | 2011-06-22 | 2017-10-17 | Asm Japan K.K. | Method for positioning wafers in multiple wafer transport |
US10364496B2 (en) | 2011-06-27 | 2019-07-30 | Asm Ip Holding B.V. | Dual section module having shared and unshared mass flow controllers |
US10854498B2 (en) | 2011-07-15 | 2020-12-01 | Asm Ip Holding B.V. | Wafer-supporting device and method for producing same |
US20130023129A1 (en) | 2011-07-20 | 2013-01-24 | Asm America, Inc. | Pressure transmitter for a semiconductor processing environment |
US9017481B1 (en) | 2011-10-28 | 2015-04-28 | Asm America, Inc. | Process feed management for semiconductor substrate processing |
US8946830B2 (en) | 2012-04-04 | 2015-02-03 | Asm Ip Holdings B.V. | Metal oxide protective layer for a semiconductor device |
US9558931B2 (en) | 2012-07-27 | 2017-01-31 | Asm Ip Holding B.V. | System and method for gas-phase sulfur passivation of a semiconductor surface |
US9659799B2 (en) | 2012-08-28 | 2017-05-23 | Asm Ip Holding B.V. | Systems and methods for dynamic semiconductor process scheduling |
US9021985B2 (en) | 2012-09-12 | 2015-05-05 | Asm Ip Holdings B.V. | Process gas management for an inductively-coupled plasma deposition reactor |
US10714315B2 (en) | 2012-10-12 | 2020-07-14 | Asm Ip Holdings B.V. | Semiconductor reaction chamber showerhead |
US9640416B2 (en) | 2012-12-26 | 2017-05-02 | Asm Ip Holding B.V. | Single-and dual-chamber module-attachable wafer-handling chamber |
US9589770B2 (en) | 2013-03-08 | 2017-03-07 | Asm Ip Holding B.V. | Method and systems for in-situ formation of intermediate reactive species |
US9484191B2 (en) | 2013-03-08 | 2016-11-01 | Asm Ip Holding B.V. | Pulsed remote plasma method and system |
US20140273516A1 (en) * | 2013-03-13 | 2014-09-18 | Applied Materials, Inc. | Vbd and tddb improvement thru interface engineering |
US8993054B2 (en) | 2013-07-12 | 2015-03-31 | Asm Ip Holding B.V. | Method and system to reduce outgassing in a reaction chamber |
US9018111B2 (en) | 2013-07-22 | 2015-04-28 | Asm Ip Holding B.V. | Semiconductor reaction chamber with plasma capabilities |
US9793115B2 (en) | 2013-08-14 | 2017-10-17 | Asm Ip Holding B.V. | Structures and devices including germanium-tin films and methods of forming same |
US9240412B2 (en) | 2013-09-27 | 2016-01-19 | Asm Ip Holding B.V. | Semiconductor structure and device and methods of forming same using selective epitaxial process |
US9556516B2 (en) | 2013-10-09 | 2017-01-31 | ASM IP Holding B.V | Method for forming Ti-containing film by PEALD using TDMAT or TDEAT |
US9605343B2 (en) | 2013-11-13 | 2017-03-28 | Asm Ip Holding B.V. | Method for forming conformal carbon films, structures conformal carbon film, and system of forming same |
US10179947B2 (en) | 2013-11-26 | 2019-01-15 | Asm Ip Holding B.V. | Method for forming conformal nitrided, oxidized, or carbonized dielectric film by atomic layer deposition |
US10683571B2 (en) | 2014-02-25 | 2020-06-16 | Asm Ip Holding B.V. | Gas supply manifold and method of supplying gases to chamber using same |
US10167557B2 (en) | 2014-03-18 | 2019-01-01 | Asm Ip Holding B.V. | Gas distribution system, reactor including the system, and methods of using the same |
US9447498B2 (en) | 2014-03-18 | 2016-09-20 | Asm Ip Holding B.V. | Method for performing uniform processing in gas system-sharing multiple reaction chambers |
US11015245B2 (en) | 2014-03-19 | 2021-05-25 | Asm Ip Holding B.V. | Gas-phase reactor and system having exhaust plenum and components thereof |
US10858737B2 (en) | 2014-07-28 | 2020-12-08 | Asm Ip Holding B.V. | Showerhead assembly and components thereof |
US9543180B2 (en) | 2014-08-01 | 2017-01-10 | Asm Ip Holding B.V. | Apparatus and method for transporting wafers between wafer carrier and process tool under vacuum |
US9890456B2 (en) | 2014-08-21 | 2018-02-13 | Asm Ip Holding B.V. | Method and system for in situ formation of gas-phase compounds |
US9478414B2 (en) | 2014-09-26 | 2016-10-25 | Asm Ip Holding B.V. | Method for hydrophobization of surface of silicon-containing film by ALD |
US9657845B2 (en) | 2014-10-07 | 2017-05-23 | Asm Ip Holding B.V. | Variable conductance gas distribution apparatus and method |
US10941490B2 (en) | 2014-10-07 | 2021-03-09 | Asm Ip Holding B.V. | Multiple temperature range susceptor, assembly, reactor and system including the susceptor, and methods of using the same |
KR102300403B1 (en) | 2014-11-19 | 2021-09-09 | 에이에스엠 아이피 홀딩 비.브이. | Method of depositing thin film |
KR102263121B1 (en) | 2014-12-22 | 2021-06-09 | 에이에스엠 아이피 홀딩 비.브이. | Semiconductor device and manufacuring method thereof |
KR102272553B1 (en) | 2015-01-19 | 2021-07-02 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
US9478415B2 (en) | 2015-02-13 | 2016-10-25 | Asm Ip Holding B.V. | Method for forming film having low resistance and shallow junction depth |
US10529542B2 (en) | 2015-03-11 | 2020-01-07 | Asm Ip Holdings B.V. | Cross-flow reactor and method |
US10276355B2 (en) | 2015-03-12 | 2019-04-30 | Asm Ip Holding B.V. | Multi-zone reactor, system including the reactor, and method of using the same |
US10458018B2 (en) | 2015-06-26 | 2019-10-29 | Asm Ip Holding B.V. | Structures including metal carbide material, devices including the structures, and methods of forming same |
US10600673B2 (en) | 2015-07-07 | 2020-03-24 | Asm Ip Holding B.V. | Magnetic susceptor to baseplate seal |
US9899291B2 (en) | 2015-07-13 | 2018-02-20 | Asm Ip Holding B.V. | Method for protecting layer by forming hydrocarbon-based extremely thin film |
US10043661B2 (en) | 2015-07-13 | 2018-08-07 | Asm Ip Holding B.V. | Method for protecting layer by forming hydrocarbon-based extremely thin film |
US10083836B2 (en) | 2015-07-24 | 2018-09-25 | Asm Ip Holding B.V. | Formation of boron-doped titanium metal films with high work function |
US10087525B2 (en) | 2015-08-04 | 2018-10-02 | Asm Ip Holding B.V. | Variable gap hard stop design |
US9647114B2 (en) | 2015-08-14 | 2017-05-09 | Asm Ip Holding B.V. | Methods of forming highly p-type doped germanium tin films and structures and devices including the films |
US9711345B2 (en) | 2015-08-25 | 2017-07-18 | Asm Ip Holding B.V. | Method for forming aluminum nitride-based film by PEALD |
US9960072B2 (en) | 2015-09-29 | 2018-05-01 | Asm Ip Holding B.V. | Variable adjustment for precise matching of multiple chamber cavity housings |
US9909214B2 (en) | 2015-10-15 | 2018-03-06 | Asm Ip Holding B.V. | Method for depositing dielectric film in trenches by PEALD |
US10211308B2 (en) | 2015-10-21 | 2019-02-19 | Asm Ip Holding B.V. | NbMC layers |
US10322384B2 (en) | 2015-11-09 | 2019-06-18 | Asm Ip Holding B.V. | Counter flow mixer for process chamber |
US9455138B1 (en) | 2015-11-10 | 2016-09-27 | Asm Ip Holding B.V. | Method for forming dielectric film in trenches by PEALD using H-containing gas |
US9905420B2 (en) | 2015-12-01 | 2018-02-27 | Asm Ip Holding B.V. | Methods of forming silicon germanium tin films and structures and devices including the films |
US9607837B1 (en) | 2015-12-21 | 2017-03-28 | Asm Ip Holding B.V. | Method for forming silicon oxide cap layer for solid state diffusion process |
US9735024B2 (en) | 2015-12-28 | 2017-08-15 | Asm Ip Holding B.V. | Method of atomic layer etching using functional group-containing fluorocarbon |
US9627221B1 (en) | 2015-12-28 | 2017-04-18 | Asm Ip Holding B.V. | Continuous process incorporating atomic layer etching |
US11139308B2 (en) | 2015-12-29 | 2021-10-05 | Asm Ip Holding B.V. | Atomic layer deposition of III-V compounds to form V-NAND devices |
US9754779B1 (en) | 2016-02-19 | 2017-09-05 | Asm Ip Holding B.V. | Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches |
US10529554B2 (en) | 2016-02-19 | 2020-01-07 | Asm Ip Holding B.V. | Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches |
US10468251B2 (en) | 2016-02-19 | 2019-11-05 | Asm Ip Holding B.V. | Method for forming spacers using silicon nitride film for spacer-defined multiple patterning |
US10501866B2 (en) | 2016-03-09 | 2019-12-10 | Asm Ip Holding B.V. | Gas distribution apparatus for improved film uniformity in an epitaxial system |
US10343920B2 (en) | 2016-03-18 | 2019-07-09 | Asm Ip Holding B.V. | Aligned carbon nanotubes |
US9892913B2 (en) | 2016-03-24 | 2018-02-13 | Asm Ip Holding B.V. | Radial and thickness control via biased multi-port injection settings |
US10087522B2 (en) | 2016-04-21 | 2018-10-02 | Asm Ip Holding B.V. | Deposition of metal borides |
US10190213B2 (en) | 2016-04-21 | 2019-01-29 | Asm Ip Holding B.V. | Deposition of metal borides |
US10865475B2 (en) | 2016-04-21 | 2020-12-15 | Asm Ip Holding B.V. | Deposition of metal borides and silicides |
US10032628B2 (en) | 2016-05-02 | 2018-07-24 | Asm Ip Holding B.V. | Source/drain performance through conformal solid state doping |
US10367080B2 (en) | 2016-05-02 | 2019-07-30 | Asm Ip Holding B.V. | Method of forming a germanium oxynitride film |
KR102592471B1 (en) | 2016-05-17 | 2023-10-20 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming metal interconnection and method of fabricating semiconductor device using the same |
US11453943B2 (en) | 2016-05-25 | 2022-09-27 | Asm Ip Holding B.V. | Method for forming carbon-containing silicon/metal oxide or nitride film by ALD using silicon precursor and hydrocarbon precursor |
US10388509B2 (en) | 2016-06-28 | 2019-08-20 | Asm Ip Holding B.V. | Formation of epitaxial layers via dislocation filtering |
US10612137B2 (en) | 2016-07-08 | 2020-04-07 | Asm Ip Holdings B.V. | Organic reactants for atomic layer deposition |
US9859151B1 (en) | 2016-07-08 | 2018-01-02 | Asm Ip Holding B.V. | Selective film deposition method to form air gaps |
US9793135B1 (en) | 2016-07-14 | 2017-10-17 | ASM IP Holding B.V | Method of cyclic dry etching using etchant film |
US10714385B2 (en) | 2016-07-19 | 2020-07-14 | Asm Ip Holding B.V. | Selective deposition of tungsten |
US10381226B2 (en) | 2016-07-27 | 2019-08-13 | Asm Ip Holding B.V. | Method of processing substrate |
US10177025B2 (en) | 2016-07-28 | 2019-01-08 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
KR102532607B1 (en) | 2016-07-28 | 2023-05-15 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus and method of operating the same |
US10395919B2 (en) | 2016-07-28 | 2019-08-27 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
US9812320B1 (en) | 2016-07-28 | 2017-11-07 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
US9887082B1 (en) | 2016-07-28 | 2018-02-06 | Asm Ip Holding B.V. | Method and apparatus for filling a gap |
US10090316B2 (en) | 2016-09-01 | 2018-10-02 | Asm Ip Holding B.V. | 3D stacked multilayer semiconductor memory using doped select transistor channel |
US10410943B2 (en) | 2016-10-13 | 2019-09-10 | Asm Ip Holding B.V. | Method for passivating a surface of a semiconductor and related systems |
US10643826B2 (en) | 2016-10-26 | 2020-05-05 | Asm Ip Holdings B.V. | Methods for thermally calibrating reaction chambers |
US11532757B2 (en) | 2016-10-27 | 2022-12-20 | Asm Ip Holding B.V. | Deposition of charge trapping layers |
US10714350B2 (en) | 2016-11-01 | 2020-07-14 | ASM IP Holdings, B.V. | Methods for forming a transition metal niobium nitride film on a substrate by atomic layer deposition and related semiconductor device structures |
US10643904B2 (en) | 2016-11-01 | 2020-05-05 | Asm Ip Holdings B.V. | Methods for forming a semiconductor device and related semiconductor device structures |
US10435790B2 (en) | 2016-11-01 | 2019-10-08 | Asm Ip Holding B.V. | Method of subatmospheric plasma-enhanced ALD using capacitively coupled electrodes with narrow gap |
US10229833B2 (en) | 2016-11-01 | 2019-03-12 | Asm Ip Holding B.V. | Methods for forming a transition metal nitride film on a substrate by atomic layer deposition and related semiconductor device structures |
US10134757B2 (en) | 2016-11-07 | 2018-11-20 | Asm Ip Holding B.V. | Method of processing a substrate and a device manufactured by using the method |
KR102546317B1 (en) | 2016-11-15 | 2023-06-21 | 에이에스엠 아이피 홀딩 비.브이. | Gas supply unit and substrate processing apparatus including the same |
US10340135B2 (en) | 2016-11-28 | 2019-07-02 | Asm Ip Holding B.V. | Method of topologically restricted plasma-enhanced cyclic deposition of silicon or metal nitride |
KR20180068582A (en) | 2016-12-14 | 2018-06-22 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US9916980B1 (en) | 2016-12-15 | 2018-03-13 | Asm Ip Holding B.V. | Method of forming a structure on a substrate |
US11581186B2 (en) | 2016-12-15 | 2023-02-14 | Asm Ip Holding B.V. | Sequential infiltration synthesis apparatus |
US11447861B2 (en) | 2016-12-15 | 2022-09-20 | Asm Ip Holding B.V. | Sequential infiltration synthesis apparatus and a method of forming a patterned structure |
KR20180070971A (en) | 2016-12-19 | 2018-06-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US10269558B2 (en) | 2016-12-22 | 2019-04-23 | Asm Ip Holding B.V. | Method of forming a structure on a substrate |
US10867788B2 (en) | 2016-12-28 | 2020-12-15 | Asm Ip Holding B.V. | Method of forming a structure on a substrate |
US11390950B2 (en) | 2017-01-10 | 2022-07-19 | Asm Ip Holding B.V. | Reactor system and method to reduce residue buildup during a film deposition process |
US10655221B2 (en) | 2017-02-09 | 2020-05-19 | Asm Ip Holding B.V. | Method for depositing oxide film by thermal ALD and PEALD |
US10468261B2 (en) | 2017-02-15 | 2019-11-05 | Asm Ip Holding B.V. | Methods for forming a metallic film on a substrate by cyclical deposition and related semiconductor device structures |
US10283353B2 (en) | 2017-03-29 | 2019-05-07 | Asm Ip Holding B.V. | Method of reforming insulating film deposited on substrate with recess pattern |
US10529563B2 (en) | 2017-03-29 | 2020-01-07 | Asm Ip Holdings B.V. | Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures |
US10103040B1 (en) | 2017-03-31 | 2018-10-16 | Asm Ip Holding B.V. | Apparatus and method for manufacturing a semiconductor device |
USD876504S1 (en) | 2017-04-03 | 2020-02-25 | Asm Ip Holding B.V. | Exhaust flow control ring for semiconductor deposition apparatus |
USD830981S1 (en) | 2017-04-07 | 2018-10-16 | Asm Ip Holding B.V. | Susceptor for semiconductor substrate processing apparatus |
KR102457289B1 (en) | 2017-04-25 | 2022-10-21 | 에이에스엠 아이피 홀딩 비.브이. | Method for depositing a thin film and manufacturing a semiconductor device |
US10770286B2 (en) | 2017-05-08 | 2020-09-08 | Asm Ip Holdings B.V. | Methods for selectively forming a silicon nitride film on a substrate and related semiconductor device structures |
US10892156B2 (en) | 2017-05-08 | 2021-01-12 | Asm Ip Holding B.V. | Methods for forming a silicon nitride film on a substrate and related semiconductor device structures |
US10446393B2 (en) | 2017-05-08 | 2019-10-15 | Asm Ip Holding B.V. | Methods for forming silicon-containing epitaxial layers and related semiconductor device structures |
US10504742B2 (en) | 2017-05-31 | 2019-12-10 | Asm Ip Holding B.V. | Method of atomic layer etching using hydrogen plasma |
US10886123B2 (en) | 2017-06-02 | 2021-01-05 | Asm Ip Holding B.V. | Methods for forming low temperature semiconductor layers and related semiconductor device structures |
US11306395B2 (en) | 2017-06-28 | 2022-04-19 | Asm Ip Holding B.V. | Methods for depositing a transition metal nitride film on a substrate by atomic layer deposition and related deposition apparatus |
US10685834B2 (en) | 2017-07-05 | 2020-06-16 | Asm Ip Holdings B.V. | Methods for forming a silicon germanium tin layer and related semiconductor device structures |
KR20190009245A (en) | 2017-07-18 | 2019-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Methods for forming a semiconductor device structure and related semiconductor device structures |
US10541333B2 (en) | 2017-07-19 | 2020-01-21 | Asm Ip Holding B.V. | Method for depositing a group IV semiconductor and related semiconductor device structures |
US11374112B2 (en) | 2017-07-19 | 2022-06-28 | Asm Ip Holding B.V. | Method for depositing a group IV semiconductor and related semiconductor device structures |
US11018002B2 (en) | 2017-07-19 | 2021-05-25 | Asm Ip Holding B.V. | Method for selectively depositing a Group IV semiconductor and related semiconductor device structures |
US10590535B2 (en) | 2017-07-26 | 2020-03-17 | Asm Ip Holdings B.V. | Chemical treatment, deposition and/or infiltration apparatus and method for using the same |
US10605530B2 (en) | 2017-07-26 | 2020-03-31 | Asm Ip Holding B.V. | Assembly of a liner and a flange for a vertical furnace as well as the liner and the vertical furnace |
US10312055B2 (en) | 2017-07-26 | 2019-06-04 | Asm Ip Holding B.V. | Method of depositing film by PEALD using negative bias |
US10770336B2 (en) | 2017-08-08 | 2020-09-08 | Asm Ip Holding B.V. | Substrate lift mechanism and reactor including same |
US10692741B2 (en) | 2017-08-08 | 2020-06-23 | Asm Ip Holdings B.V. | Radiation shield |
US11139191B2 (en) | 2017-08-09 | 2021-10-05 | Asm Ip Holding B.V. | Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith |
US10249524B2 (en) | 2017-08-09 | 2019-04-02 | Asm Ip Holding B.V. | Cassette holder assembly for a substrate cassette and holding member for use in such assembly |
US11769682B2 (en) | 2017-08-09 | 2023-09-26 | Asm Ip Holding B.V. | Storage apparatus for storing cassettes for substrates and processing apparatus equipped therewith |
US10236177B1 (en) | 2017-08-22 | 2019-03-19 | ASM IP Holding B.V.. | Methods for depositing a doped germanium tin semiconductor and related semiconductor device structures |
USD900036S1 (en) | 2017-08-24 | 2020-10-27 | Asm Ip Holding B.V. | Heater electrical connector and adapter |
US11830730B2 (en) | 2017-08-29 | 2023-11-28 | Asm Ip Holding B.V. | Layer forming method and apparatus |
KR102491945B1 (en) | 2017-08-30 | 2023-01-26 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US11295980B2 (en) | 2017-08-30 | 2022-04-05 | Asm Ip Holding B.V. | Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process and related semiconductor device structures |
US11056344B2 (en) | 2017-08-30 | 2021-07-06 | Asm Ip Holding B.V. | Layer forming method |
US10607895B2 (en) | 2017-09-18 | 2020-03-31 | Asm Ip Holdings B.V. | Method for forming a semiconductor device structure comprising a gate fill metal |
KR102630301B1 (en) | 2017-09-21 | 2024-01-29 | 에이에스엠 아이피 홀딩 비.브이. | Method of sequential infiltration synthesis treatment of infiltrateable material and structures and devices formed using same |
US10844484B2 (en) | 2017-09-22 | 2020-11-24 | Asm Ip Holding B.V. | Apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods |
US10658205B2 (en) | 2017-09-28 | 2020-05-19 | Asm Ip Holdings B.V. | Chemical dispensing apparatus and methods for dispensing a chemical to a reaction chamber |
US10403504B2 (en) | 2017-10-05 | 2019-09-03 | Asm Ip Holding B.V. | Method for selectively depositing a metallic film on a substrate |
US10319588B2 (en) | 2017-10-10 | 2019-06-11 | Asm Ip Holding B.V. | Method for depositing a metal chalcogenide on a substrate by cyclical deposition |
US10923344B2 (en) | 2017-10-30 | 2021-02-16 | Asm Ip Holding B.V. | Methods for forming a semiconductor structure and related semiconductor structures |
US10910262B2 (en) | 2017-11-16 | 2021-02-02 | Asm Ip Holding B.V. | Method of selectively depositing a capping layer structure on a semiconductor device structure |
KR102443047B1 (en) | 2017-11-16 | 2022-09-14 | 에이에스엠 아이피 홀딩 비.브이. | Method of processing a substrate and a device manufactured by the same |
US11022879B2 (en) | 2017-11-24 | 2021-06-01 | Asm Ip Holding B.V. | Method of forming an enhanced unexposed photoresist layer |
CN111344522B (en) | 2017-11-27 | 2022-04-12 | 阿斯莫Ip控股公司 | Including clean mini-environment device |
KR102597978B1 (en) | 2017-11-27 | 2023-11-06 | 에이에스엠 아이피 홀딩 비.브이. | Storage device for storing wafer cassettes for use with batch furnaces |
US10290508B1 (en) | 2017-12-05 | 2019-05-14 | Asm Ip Holding B.V. | Method for forming vertical spacers for spacer-defined patterning |
US10872771B2 (en) | 2018-01-16 | 2020-12-22 | Asm Ip Holding B. V. | Method for depositing a material film on a substrate within a reaction chamber by a cyclical deposition process and related device structures |
KR20200108016A (en) | 2018-01-19 | 2020-09-16 | 에이에스엠 아이피 홀딩 비.브이. | Method of depositing a gap fill layer by plasma assisted deposition |
TWI799494B (en) | 2018-01-19 | 2023-04-21 | 荷蘭商Asm 智慧財產控股公司 | Deposition method |
USD903477S1 (en) | 2018-01-24 | 2020-12-01 | Asm Ip Holdings B.V. | Metal clamp |
US11018047B2 (en) | 2018-01-25 | 2021-05-25 | Asm Ip Holding B.V. | Hybrid lift pin |
USD880437S1 (en) | 2018-02-01 | 2020-04-07 | Asm Ip Holding B.V. | Gas supply plate for semiconductor manufacturing apparatus |
US10535516B2 (en) | 2018-02-01 | 2020-01-14 | Asm Ip Holdings B.V. | Method for depositing a semiconductor structure on a surface of a substrate and related semiconductor structures |
US11081345B2 (en) | 2018-02-06 | 2021-08-03 | Asm Ip Holding B.V. | Method of post-deposition treatment for silicon oxide film |
US11685991B2 (en) | 2018-02-14 | 2023-06-27 | Asm Ip Holding B.V. | Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process |
US10896820B2 (en) | 2018-02-14 | 2021-01-19 | Asm Ip Holding B.V. | Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process |
US10731249B2 (en) | 2018-02-15 | 2020-08-04 | Asm Ip Holding B.V. | Method of forming a transition metal containing film on a substrate by a cyclical deposition process, a method for supplying a transition metal halide compound to a reaction chamber, and related vapor deposition apparatus |
US10658181B2 (en) | 2018-02-20 | 2020-05-19 | Asm Ip Holding B.V. | Method of spacer-defined direct patterning in semiconductor fabrication |
KR102636427B1 (en) | 2018-02-20 | 2024-02-13 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing method and apparatus |
US10975470B2 (en) | 2018-02-23 | 2021-04-13 | Asm Ip Holding B.V. | Apparatus for detecting or monitoring for a chemical precursor in a high temperature environment |
US11473195B2 (en) | 2018-03-01 | 2022-10-18 | Asm Ip Holding B.V. | Semiconductor processing apparatus and a method for processing a substrate |
US11629406B2 (en) | 2018-03-09 | 2023-04-18 | Asm Ip Holding B.V. | Semiconductor processing apparatus comprising one or more pyrometers for measuring a temperature of a substrate during transfer of the substrate |
US11114283B2 (en) | 2018-03-16 | 2021-09-07 | Asm Ip Holding B.V. | Reactor, system including the reactor, and methods of manufacturing and using same |
KR102646467B1 (en) | 2018-03-27 | 2024-03-11 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming an electrode on a substrate and a semiconductor device structure including an electrode |
US10510536B2 (en) | 2018-03-29 | 2019-12-17 | Asm Ip Holding B.V. | Method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber |
US11230766B2 (en) | 2018-03-29 | 2022-01-25 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
US11088002B2 (en) | 2018-03-29 | 2021-08-10 | Asm Ip Holding B.V. | Substrate rack and a substrate processing system and method |
KR102501472B1 (en) | 2018-03-30 | 2023-02-20 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing method |
KR20190128558A (en) | 2018-05-08 | 2019-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Methods for depositing an oxide film on a substrate by a cyclical deposition process and related device structures |
TWI816783B (en) | 2018-05-11 | 2023-10-01 | 荷蘭商Asm 智慧財產控股公司 | Methods for forming a doped metal carbide film on a substrate and related semiconductor device structures |
KR102596988B1 (en) | 2018-05-28 | 2023-10-31 | 에이에스엠 아이피 홀딩 비.브이. | Method of processing a substrate and a device manufactured by the same |
US11718913B2 (en) | 2018-06-04 | 2023-08-08 | Asm Ip Holding B.V. | Gas distribution system and reactor system including same |
TW202013553A (en) | 2018-06-04 | 2020-04-01 | 荷蘭商Asm 智慧財產控股公司 | Wafer handling chamber with moisture reduction |
US11286562B2 (en) | 2018-06-08 | 2022-03-29 | Asm Ip Holding B.V. | Gas-phase chemical reactor and method of using same |
US10797133B2 (en) | 2018-06-21 | 2020-10-06 | Asm Ip Holding B.V. | Method for depositing a phosphorus doped silicon arsenide film and related semiconductor device structures |
KR102568797B1 (en) | 2018-06-21 | 2023-08-21 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing system |
WO2020003000A1 (en) | 2018-06-27 | 2020-01-02 | Asm Ip Holding B.V. | Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material |
TWI819010B (en) | 2018-06-27 | 2023-10-21 | 荷蘭商Asm Ip私人控股有限公司 | Cyclic deposition methods for forming metal-containing material and films and structures including the metal-containing material |
KR20200002519A (en) | 2018-06-29 | 2020-01-08 | 에이에스엠 아이피 홀딩 비.브이. | Method for depositing a thin film and manufacturing a semiconductor device |
US10612136B2 (en) | 2018-06-29 | 2020-04-07 | ASM IP Holding, B.V. | Temperature-controlled flange and reactor system including same |
US10388513B1 (en) | 2018-07-03 | 2019-08-20 | Asm Ip Holding B.V. | Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition |
US10755922B2 (en) | 2018-07-03 | 2020-08-25 | Asm Ip Holding B.V. | Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition |
US10767789B2 (en) | 2018-07-16 | 2020-09-08 | Asm Ip Holding B.V. | Diaphragm valves, valve components, and methods for forming valve components |
US10483099B1 (en) | 2018-07-26 | 2019-11-19 | Asm Ip Holding B.V. | Method for forming thermally stable organosilicon polymer film |
US11053591B2 (en) | 2018-08-06 | 2021-07-06 | Asm Ip Holding B.V. | Multi-port gas injection system and reactor system including same |
US10883175B2 (en) | 2018-08-09 | 2021-01-05 | Asm Ip Holding B.V. | Vertical furnace for processing substrates and a liner for use therein |
US10829852B2 (en) | 2018-08-16 | 2020-11-10 | Asm Ip Holding B.V. | Gas distribution device for a wafer processing apparatus |
US11430674B2 (en) | 2018-08-22 | 2022-08-30 | Asm Ip Holding B.V. | Sensor array, apparatus for dispensing a vapor phase reactant to a reaction chamber and related methods |
US11024523B2 (en) | 2018-09-11 | 2021-06-01 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
KR20200030162A (en) | 2018-09-11 | 2020-03-20 | 에이에스엠 아이피 홀딩 비.브이. | Method for deposition of a thin film |
US11049751B2 (en) | 2018-09-14 | 2021-06-29 | Asm Ip Holding B.V. | Cassette supply system to store and handle cassettes and processing apparatus equipped therewith |
CN110970344A (en) | 2018-10-01 | 2020-04-07 | Asm Ip控股有限公司 | Substrate holding apparatus, system including the same, and method of using the same |
US11232963B2 (en) | 2018-10-03 | 2022-01-25 | Asm Ip Holding B.V. | Substrate processing apparatus and method |
KR102592699B1 (en) | 2018-10-08 | 2023-10-23 | 에이에스엠 아이피 홀딩 비.브이. | Substrate support unit and apparatuses for depositing thin film and processing the substrate including the same |
US10847365B2 (en) | 2018-10-11 | 2020-11-24 | Asm Ip Holding B.V. | Method of forming conformal silicon carbide film by cyclic CVD |
US10811256B2 (en) | 2018-10-16 | 2020-10-20 | Asm Ip Holding B.V. | Method for etching a carbon-containing feature |
KR102605121B1 (en) | 2018-10-19 | 2023-11-23 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus and substrate processing method |
KR102546322B1 (en) | 2018-10-19 | 2023-06-21 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus and substrate processing method |
USD948463S1 (en) | 2018-10-24 | 2022-04-12 | Asm Ip Holding B.V. | Susceptor for semiconductor substrate supporting apparatus |
US10381219B1 (en) | 2018-10-25 | 2019-08-13 | Asm Ip Holding B.V. | Methods for forming a silicon nitride film |
US11087997B2 (en) | 2018-10-31 | 2021-08-10 | Asm Ip Holding B.V. | Substrate processing apparatus for processing substrates |
KR20200051105A (en) | 2018-11-02 | 2020-05-13 | 에이에스엠 아이피 홀딩 비.브이. | Substrate support unit and substrate processing apparatus including the same |
US11572620B2 (en) | 2018-11-06 | 2023-02-07 | Asm Ip Holding B.V. | Methods for selectively depositing an amorphous silicon film on a substrate |
US11031242B2 (en) | 2018-11-07 | 2021-06-08 | Asm Ip Holding B.V. | Methods for depositing a boron doped silicon germanium film |
US10818758B2 (en) | 2018-11-16 | 2020-10-27 | Asm Ip Holding B.V. | Methods for forming a metal silicate film on a substrate in a reaction chamber and related semiconductor device structures |
US10847366B2 (en) | 2018-11-16 | 2020-11-24 | Asm Ip Holding B.V. | Methods for depositing a transition metal chalcogenide film on a substrate by a cyclical deposition process |
US10559458B1 (en) | 2018-11-26 | 2020-02-11 | Asm Ip Holding B.V. | Method of forming oxynitride film |
US11217444B2 (en) | 2018-11-30 | 2022-01-04 | Asm Ip Holding B.V. | Method for forming an ultraviolet radiation responsive metal oxide-containing film |
KR102636428B1 (en) | 2018-12-04 | 2024-02-13 | 에이에스엠 아이피 홀딩 비.브이. | A method for cleaning a substrate processing apparatus |
US11158513B2 (en) | 2018-12-13 | 2021-10-26 | Asm Ip Holding B.V. | Methods for forming a rhenium-containing film on a substrate by a cyclical deposition process and related semiconductor device structures |
TW202037745A (en) | 2018-12-14 | 2020-10-16 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming device structure, structure formed by the method and system for performing the method |
TWI819180B (en) | 2019-01-17 | 2023-10-21 | 荷蘭商Asm 智慧財產控股公司 | Methods of forming a transition metal containing film on a substrate by a cyclical deposition process |
KR20200091543A (en) | 2019-01-22 | 2020-07-31 | 에이에스엠 아이피 홀딩 비.브이. | Semiconductor processing device |
CN111524788B (en) | 2019-02-01 | 2023-11-24 | Asm Ip私人控股有限公司 | Method for topologically selective film formation of silicon oxide |
US11482533B2 (en) | 2019-02-20 | 2022-10-25 | Asm Ip Holding B.V. | Apparatus and methods for plug fill deposition in 3-D NAND applications |
TW202104632A (en) | 2019-02-20 | 2021-02-01 | 荷蘭商Asm Ip私人控股有限公司 | Cyclical deposition method and apparatus for filling a recess formed within a substrate surface |
KR102626263B1 (en) | 2019-02-20 | 2024-01-16 | 에이에스엠 아이피 홀딩 비.브이. | Cyclical deposition method including treatment step and apparatus for same |
KR102638425B1 (en) | 2019-02-20 | 2024-02-21 | 에이에스엠 아이피 홀딩 비.브이. | Method and apparatus for filling a recess formed within a substrate surface |
TW202100794A (en) | 2019-02-22 | 2021-01-01 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing apparatus and method for processing substrate |
KR20200108243A (en) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | Structure Including SiOC Layer and Method of Forming Same |
KR20200108242A (en) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | Method for Selective Deposition of Silicon Nitride Layer and Structure Including Selectively-Deposited Silicon Nitride Layer |
KR20200108248A (en) | 2019-03-08 | 2020-09-17 | 에이에스엠 아이피 홀딩 비.브이. | STRUCTURE INCLUDING SiOCN LAYER AND METHOD OF FORMING SAME |
JP2020167398A (en) | 2019-03-28 | 2020-10-08 | エーエスエム・アイピー・ホールディング・ベー・フェー | Door opener and substrate processing apparatus provided therewith |
KR20200116855A (en) | 2019-04-01 | 2020-10-13 | 에이에스엠 아이피 홀딩 비.브이. | Method of manufacturing semiconductor device |
KR20200123380A (en) | 2019-04-19 | 2020-10-29 | 에이에스엠 아이피 홀딩 비.브이. | Layer forming method and apparatus |
KR20200125453A (en) | 2019-04-24 | 2020-11-04 | 에이에스엠 아이피 홀딩 비.브이. | Gas-phase reactor system and method of using same |
KR20200130118A (en) | 2019-05-07 | 2020-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Method for Reforming Amorphous Carbon Polymer Film |
KR20200130121A (en) | 2019-05-07 | 2020-11-18 | 에이에스엠 아이피 홀딩 비.브이. | Chemical source vessel with dip tube |
KR20200130652A (en) | 2019-05-10 | 2020-11-19 | 에이에스엠 아이피 홀딩 비.브이. | Method of depositing material onto a surface and structure formed according to the method |
JP2020188255A (en) | 2019-05-16 | 2020-11-19 | エーエスエム アイピー ホールディング ビー.ブイ. | Wafer boat handling device, vertical batch furnace, and method |
USD947913S1 (en) | 2019-05-17 | 2022-04-05 | Asm Ip Holding B.V. | Susceptor shaft |
USD975665S1 (en) | 2019-05-17 | 2023-01-17 | Asm Ip Holding B.V. | Susceptor shaft |
USD935572S1 (en) | 2019-05-24 | 2021-11-09 | Asm Ip Holding B.V. | Gas channel plate |
USD922229S1 (en) | 2019-06-05 | 2021-06-15 | Asm Ip Holding B.V. | Device for controlling a temperature of a gas supply unit |
KR20200141003A (en) | 2019-06-06 | 2020-12-17 | 에이에스엠 아이피 홀딩 비.브이. | Gas-phase reactor system including a gas detector |
KR20200143254A (en) | 2019-06-11 | 2020-12-23 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming an electronic structure using an reforming gas, system for performing the method, and structure formed using the method |
USD944946S1 (en) | 2019-06-14 | 2022-03-01 | Asm Ip Holding B.V. | Shower plate |
USD931978S1 (en) | 2019-06-27 | 2021-09-28 | Asm Ip Holding B.V. | Showerhead vacuum transport |
KR20210005515A (en) | 2019-07-03 | 2021-01-14 | 에이에스엠 아이피 홀딩 비.브이. | Temperature control assembly for substrate processing apparatus and method of using same |
JP2021015791A (en) | 2019-07-09 | 2021-02-12 | エーエスエム アイピー ホールディング ビー.ブイ. | Plasma device and substrate processing method using coaxial waveguide |
CN112216646A (en) | 2019-07-10 | 2021-01-12 | Asm Ip私人控股有限公司 | Substrate supporting assembly and substrate processing device comprising same |
KR20210010307A (en) | 2019-07-16 | 2021-01-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
KR20210010816A (en) | 2019-07-17 | 2021-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Radical assist ignition plasma system and method |
KR20210010820A (en) | 2019-07-17 | 2021-01-28 | 에이에스엠 아이피 홀딩 비.브이. | Methods of forming silicon germanium structures |
US11643724B2 (en) | 2019-07-18 | 2023-05-09 | Asm Ip Holding B.V. | Method of forming structures using a neutral beam |
CN112242296A (en) | 2019-07-19 | 2021-01-19 | Asm Ip私人控股有限公司 | Method of forming topologically controlled amorphous carbon polymer films |
CN112309843A (en) | 2019-07-29 | 2021-02-02 | Asm Ip私人控股有限公司 | Selective deposition method for achieving high dopant doping |
CN112309900A (en) | 2019-07-30 | 2021-02-02 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
CN112309899A (en) | 2019-07-30 | 2021-02-02 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
US11227782B2 (en) | 2019-07-31 | 2022-01-18 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
US11587814B2 (en) | 2019-07-31 | 2023-02-21 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
US11587815B2 (en) | 2019-07-31 | 2023-02-21 | Asm Ip Holding B.V. | Vertical batch furnace assembly |
CN112323048B (en) | 2019-08-05 | 2024-02-09 | Asm Ip私人控股有限公司 | Liquid level sensor for chemical source container |
USD965524S1 (en) | 2019-08-19 | 2022-10-04 | Asm Ip Holding B.V. | Susceptor support |
USD965044S1 (en) | 2019-08-19 | 2022-09-27 | Asm Ip Holding B.V. | Susceptor shaft |
JP2021031769A (en) | 2019-08-21 | 2021-03-01 | エーエスエム アイピー ホールディング ビー.ブイ. | Production apparatus of mixed gas of film deposition raw material and film deposition apparatus |
USD940837S1 (en) | 2019-08-22 | 2022-01-11 | Asm Ip Holding B.V. | Electrode |
USD930782S1 (en) | 2019-08-22 | 2021-09-14 | Asm Ip Holding B.V. | Gas distributor |
USD949319S1 (en) | 2019-08-22 | 2022-04-19 | Asm Ip Holding B.V. | Exhaust duct |
USD979506S1 (en) | 2019-08-22 | 2023-02-28 | Asm Ip Holding B.V. | Insulator |
KR20210024423A (en) | 2019-08-22 | 2021-03-05 | 에이에스엠 아이피 홀딩 비.브이. | Method for forming a structure with a hole |
KR20210024420A (en) | 2019-08-23 | 2021-03-05 | 에이에스엠 아이피 홀딩 비.브이. | Method for depositing silicon oxide film having improved quality by peald using bis(diethylamino)silane |
US11286558B2 (en) | 2019-08-23 | 2022-03-29 | Asm Ip Holding B.V. | Methods for depositing a molybdenum nitride film on a surface of a substrate by a cyclical deposition process and related semiconductor device structures including a molybdenum nitride film |
KR20210029090A (en) | 2019-09-04 | 2021-03-15 | 에이에스엠 아이피 홀딩 비.브이. | Methods for selective deposition using a sacrificial capping layer |
KR20210029663A (en) | 2019-09-05 | 2021-03-16 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
US11562901B2 (en) | 2019-09-25 | 2023-01-24 | Asm Ip Holding B.V. | Substrate processing method |
CN112593212B (en) | 2019-10-02 | 2023-12-22 | Asm Ip私人控股有限公司 | Method for forming topologically selective silicon oxide film by cyclic plasma enhanced deposition process |
TW202129060A (en) | 2019-10-08 | 2021-08-01 | 荷蘭商Asm Ip控股公司 | Substrate processing device, and substrate processing method |
KR20210043460A (en) | 2019-10-10 | 2021-04-21 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming a photoresist underlayer and structure including same |
KR20210045930A (en) | 2019-10-16 | 2021-04-27 | 에이에스엠 아이피 홀딩 비.브이. | Method of Topology-Selective Film Formation of Silicon Oxide |
US11637014B2 (en) | 2019-10-17 | 2023-04-25 | Asm Ip Holding B.V. | Methods for selective deposition of doped semiconductor material |
KR20210047808A (en) | 2019-10-21 | 2021-04-30 | 에이에스엠 아이피 홀딩 비.브이. | Apparatus and methods for selectively etching films |
US11646205B2 (en) | 2019-10-29 | 2023-05-09 | Asm Ip Holding B.V. | Methods of selectively forming n-type doped material on a surface, systems for selectively forming n-type doped material, and structures formed using same |
KR20210054983A (en) | 2019-11-05 | 2021-05-14 | 에이에스엠 아이피 홀딩 비.브이. | Structures with doped semiconductor layers and methods and systems for forming same |
US11501968B2 (en) | 2019-11-15 | 2022-11-15 | Asm Ip Holding B.V. | Method for providing a semiconductor device with silicon filled gaps |
KR20210062561A (en) | 2019-11-20 | 2021-05-31 | 에이에스엠 아이피 홀딩 비.브이. | Method of depositing carbon-containing material on a surface of a substrate, structure formed using the method, and system for forming the structure |
CN112951697A (en) | 2019-11-26 | 2021-06-11 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
KR20210065848A (en) | 2019-11-26 | 2021-06-04 | 에이에스엠 아이피 홀딩 비.브이. | Methods for selectivley forming a target film on a substrate comprising a first dielectric surface and a second metallic surface |
CN112885693A (en) | 2019-11-29 | 2021-06-01 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
CN112885692A (en) | 2019-11-29 | 2021-06-01 | Asm Ip私人控股有限公司 | Substrate processing apparatus |
JP2021090042A (en) | 2019-12-02 | 2021-06-10 | エーエスエム アイピー ホールディング ビー.ブイ. | Substrate processing apparatus and substrate processing method |
KR20210070898A (en) | 2019-12-04 | 2021-06-15 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
KR20210078405A (en) | 2019-12-17 | 2021-06-28 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming vanadium nitride layer and structure including the vanadium nitride layer |
KR20210080214A (en) | 2019-12-19 | 2021-06-30 | 에이에스엠 아이피 홀딩 비.브이. | Methods for filling a gap feature on a substrate and related semiconductor structures |
KR20210095050A (en) | 2020-01-20 | 2021-07-30 | 에이에스엠 아이피 홀딩 비.브이. | Method of forming thin film and method of modifying surface of thin film |
TW202130846A (en) | 2020-02-03 | 2021-08-16 | 荷蘭商Asm Ip私人控股有限公司 | Method of forming structures including a vanadium or indium layer |
KR20210100010A (en) | 2020-02-04 | 2021-08-13 | 에이에스엠 아이피 홀딩 비.브이. | Method and apparatus for transmittance measurements of large articles |
US11776846B2 (en) | 2020-02-07 | 2023-10-03 | Asm Ip Holding B.V. | Methods for depositing gap filling fluids and related systems and devices |
TW202146715A (en) | 2020-02-17 | 2021-12-16 | 荷蘭商Asm Ip私人控股有限公司 | Method for growing phosphorous-doped silicon layer and system of the same |
KR20210116240A (en) | 2020-03-11 | 2021-09-27 | 에이에스엠 아이피 홀딩 비.브이. | Substrate handling device with adjustable joints |
US11876356B2 (en) | 2020-03-11 | 2024-01-16 | Asm Ip Holding B.V. | Lockout tagout assembly and system and method of using same |
KR20210124042A (en) | 2020-04-02 | 2021-10-14 | 에이에스엠 아이피 홀딩 비.브이. | Thin film forming method |
TW202146689A (en) | 2020-04-03 | 2021-12-16 | 荷蘭商Asm Ip控股公司 | Method for forming barrier layer and method for manufacturing semiconductor device |
TW202145344A (en) | 2020-04-08 | 2021-12-01 | 荷蘭商Asm Ip私人控股有限公司 | Apparatus and methods for selectively etching silcon oxide films |
US11821078B2 (en) | 2020-04-15 | 2023-11-21 | Asm Ip Holding B.V. | Method for forming precoat film and method for forming silicon-containing film |
KR20210132600A (en) | 2020-04-24 | 2021-11-04 | 에이에스엠 아이피 홀딩 비.브이. | Methods and systems for depositing a layer comprising vanadium, nitrogen, and a further element |
TW202146831A (en) | 2020-04-24 | 2021-12-16 | 荷蘭商Asm Ip私人控股有限公司 | Vertical batch furnace assembly, and method for cooling vertical batch furnace |
JP2021172884A (en) | 2020-04-24 | 2021-11-01 | エーエスエム・アイピー・ホールディング・ベー・フェー | Method of forming vanadium nitride-containing layer and structure comprising vanadium nitride-containing layer |
KR20210134869A (en) | 2020-05-01 | 2021-11-11 | 에이에스엠 아이피 홀딩 비.브이. | Fast FOUP swapping with a FOUP handler |
KR20210141379A (en) | 2020-05-13 | 2021-11-23 | 에이에스엠 아이피 홀딩 비.브이. | Laser alignment fixture for a reactor system |
KR20210143653A (en) | 2020-05-19 | 2021-11-29 | 에이에스엠 아이피 홀딩 비.브이. | Substrate processing apparatus |
KR20210145078A (en) | 2020-05-21 | 2021-12-01 | 에이에스엠 아이피 홀딩 비.브이. | Structures including multiple carbon layers and methods of forming and using same |
TW202201602A (en) | 2020-05-29 | 2022-01-01 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing device |
TW202218133A (en) | 2020-06-24 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | Method for forming a layer provided with silicon |
TW202217953A (en) | 2020-06-30 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | Substrate processing method |
KR20220010438A (en) | 2020-07-17 | 2022-01-25 | 에이에스엠 아이피 홀딩 비.브이. | Structures and methods for use in photolithography |
TW202204662A (en) | 2020-07-20 | 2022-02-01 | 荷蘭商Asm Ip私人控股有限公司 | Method and system for depositing molybdenum layers |
KR20220027026A (en) | 2020-08-26 | 2022-03-07 | 에이에스엠 아이피 홀딩 비.브이. | Method and system for forming metal silicon oxide and metal silicon oxynitride |
USD990534S1 (en) | 2020-09-11 | 2023-06-27 | Asm Ip Holding B.V. | Weighted lift pin |
USD1012873S1 (en) | 2020-09-24 | 2024-01-30 | Asm Ip Holding B.V. | Electrode for semiconductor processing apparatus |
TW202229613A (en) | 2020-10-14 | 2022-08-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of depositing material on stepped structure |
TW202217037A (en) | 2020-10-22 | 2022-05-01 | 荷蘭商Asm Ip私人控股有限公司 | Method of depositing vanadium metal, structure, device and a deposition assembly |
TW202223136A (en) | 2020-10-28 | 2022-06-16 | 荷蘭商Asm Ip私人控股有限公司 | Method for forming layer on substrate, and semiconductor processing system |
KR20220076343A (en) | 2020-11-30 | 2022-06-08 | 에이에스엠 아이피 홀딩 비.브이. | an injector configured for arrangement within a reaction chamber of a substrate processing apparatus |
CN114639631A (en) | 2020-12-16 | 2022-06-17 | Asm Ip私人控股有限公司 | Fixing device for measuring jumping and swinging |
TW202231903A (en) | 2020-12-22 | 2022-08-16 | 荷蘭商Asm Ip私人控股有限公司 | Transition metal deposition method, transition metal layer, and deposition assembly for depositing transition metal on substrate |
USD980814S1 (en) | 2021-05-11 | 2023-03-14 | Asm Ip Holding B.V. | Gas distributor for substrate processing apparatus |
USD980813S1 (en) | 2021-05-11 | 2023-03-14 | Asm Ip Holding B.V. | Gas flow control plate for substrate processing apparatus |
USD981973S1 (en) | 2021-05-11 | 2023-03-28 | Asm Ip Holding B.V. | Reactor wall for substrate processing apparatus |
USD990441S1 (en) | 2021-09-07 | 2023-06-27 | Asm Ip Holding B.V. | Gas flow control plate |
Citations (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US606884A (en) * | 1898-07-05 | Half to john r | ||
US4980018A (en) * | 1989-11-14 | 1990-12-25 | Intel Corporation | Plasma etching process for refractory metal vias |
US5818071A (en) * | 1995-02-02 | 1998-10-06 | Dow Corning Corporation | Silicon carbide metal diffusion barrier layer |
US6068884A (en) * | 1998-04-28 | 2000-05-30 | Silcon Valley Group Thermal Systems, Llc | Method of making low κ dielectric inorganic/organic hybrid films |
US6147009A (en) * | 1998-06-29 | 2000-11-14 | International Business Machines Corporation | Hydrogenated oxidized silicon carbon material |
US6159871A (en) * | 1998-05-29 | 2000-12-12 | Dow Corning Corporation | Method for producing hydrogenated silicon oxycarbide films having low dielectric constant |
US6383907B1 (en) * | 1999-09-08 | 2002-05-07 | Sony Corporation | Process for fabricating a semiconductor device |
US6387608B2 (en) * | 2000-04-06 | 2002-05-14 | Konica Corporation | Photothermographic material |
US6451683B1 (en) * | 2000-08-28 | 2002-09-17 | Micron Technology, Inc. | Damascene structure and method of making |
US6465372B1 (en) * | 1999-08-17 | 2002-10-15 | Applied Materials, Inc. | Surface treatment of C-doped SiO2 film to enhance film stability during O2 ashing |
US6486061B1 (en) * | 1999-08-17 | 2002-11-26 | Applied Materials, Inc. | Post-deposition treatment to enhance properties of Si-O-C low K films |
US6514671B1 (en) * | 1998-08-12 | 2003-02-04 | Applied Materials, Inc. | Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics |
US6528432B1 (en) * | 2000-12-05 | 2003-03-04 | Advanced Micro Devices, Inc. | H2-or H2/N2-plasma treatment to prevent organic ILD degradation |
US6531407B1 (en) * | 2000-08-31 | 2003-03-11 | Micron Technology, Inc. | Method, structure and process flow to reduce line-line capacitance with low-K material |
US6547977B1 (en) * | 1998-04-02 | 2003-04-15 | Applied Materials Inc. | Method for etching low k dielectrics |
US6548899B2 (en) * | 1999-06-11 | 2003-04-15 | Electron Vision Corporation | Method of processing films prior to chemical vapor deposition using electron beam processing |
US20030073321A1 (en) * | 2001-08-23 | 2003-04-17 | Applied Material, Inc. | Etch process for dielectric materials comprising oxidized organo silane materials |
US6566283B1 (en) * | 2001-02-15 | 2003-05-20 | Advanced Micro Devices, Inc. | Silane treatment of low dielectric constant materials in semiconductor device manufacturing |
US6566278B1 (en) * | 2000-08-24 | 2003-05-20 | Applied Materials Inc. | Method for densification of CVD carbon-doped silicon oxide films through UV irradiation |
US20030109143A1 (en) * | 2001-12-12 | 2003-06-12 | Applied Materials, Inc. | Process for selectively etching dielectric layers |
US6583046B1 (en) * | 2001-07-13 | 2003-06-24 | Advanced Micro Devices, Inc. | Post-treatment of low-k dielectric for prevention of photoresist poisoning |
US6583070B1 (en) * | 1998-10-27 | 2003-06-24 | Advanced Micro Devices, Inc. | Semiconductor device having a low dielectric constant material |
US6582777B1 (en) * | 2000-02-17 | 2003-06-24 | Applied Materials Inc. | Electron beam modification of CVD deposited low dielectric constant materials |
US6583489B2 (en) * | 2001-04-24 | 2003-06-24 | United Microelectronics Corp. | Method for forming interconnect structure with low dielectric constant |
US6593247B1 (en) * | 1998-02-11 | 2003-07-15 | Applied Materials, Inc. | Method of depositing low k films using an oxidizing plasma |
US20030189208A1 (en) * | 2002-04-05 | 2003-10-09 | Kam Law | Deposition of silicon layers for active matrix liquid crystal display (AMLCD) applications |
US6632735B2 (en) * | 2001-08-07 | 2003-10-14 | Applied Materials, Inc. | Method of depositing low dielectric constant carbon doped silicon oxide |
US6717265B1 (en) * | 2002-11-08 | 2004-04-06 | Intel Corporation | Treatment of low-k dielectric material for CMP |
US20040069410A1 (en) * | 2002-05-08 | 2004-04-15 | Farhad Moghadam | Cluster tool for E-beam treated films |
US20040072436A1 (en) * | 2002-10-09 | 2004-04-15 | Ramachandrarao Vijayakumar S. | Replenishment of surface carbon and surface passivation of low-k porous silicon-based dielectric materials |
US20040077164A1 (en) * | 2002-03-08 | 2004-04-22 | Kevin Kornegay | Method for monolithically integrating silicon carbide microelectromechanical devices with electronic circuitry |
US20040102330A1 (en) * | 2001-02-13 | 2004-05-27 | Jian Zhou | Viscoelastic compositions |
US6743732B1 (en) * | 2001-01-26 | 2004-06-01 | Taiwan Semiconductor Manufacturing Company | Organic low K dielectric etch with NH3 chemistry |
US6759367B2 (en) * | 2001-03-29 | 2004-07-06 | Agfa-Gevaert | Thermographic recording material with improved print archivability without loss in printability |
US6800566B2 (en) * | 2002-02-21 | 2004-10-05 | Taiwan Semiconductor Manufacturing Company | Adjustment of N and K values in a DARC film |
US20040214446A1 (en) * | 2002-07-11 | 2004-10-28 | Applied Materials, Inc. | Nitrogen-free dielectric anti-reflective coating and hardmask |
US6825134B2 (en) * | 2002-03-26 | 2004-11-30 | Applied Materials, Inc. | Deposition of film layers by alternately pulsing a precursor and high frequency power in a continuous gas flow |
US20040266216A1 (en) * | 2003-05-08 | 2004-12-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for improving uniformity in deposited low k dielectric material |
US20050003676A1 (en) * | 2001-02-12 | 2005-01-06 | Ho Chok W. | Use of ammonia for etching organic low-k dielectrics |
US6846756B2 (en) * | 2002-07-30 | 2005-01-25 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for preventing low-k dielectric layer cracking in multi-layered dual damascene metallization layers |
US20050024630A1 (en) * | 2003-04-28 | 2005-02-03 | Renesas Technology Corp. | Device for examining end part |
US20050042889A1 (en) * | 2001-12-14 | 2005-02-24 | Albert Lee | Bi-layer approach for a hermetic low dielectric constant layer for barrier applications |
US20050065698A1 (en) * | 2002-02-08 | 2005-03-24 | David Bertrand | Direct determination of the maximum grip coefficient on the basis of measurement of the circumferential extension in a sidewall of a tire |
US20050100682A1 (en) * | 2003-11-06 | 2005-05-12 | Tokyo Electron Limited | Method for depositing materials on a substrate |
US6921727B2 (en) * | 2003-03-11 | 2005-07-26 | Applied Materials, Inc. | Method for modifying dielectric characteristics of dielectric layers |
US20050181623A1 (en) * | 1998-10-01 | 2005-08-18 | Applied Materials, Inc. | Silicon carbide deposition for use as a low dielectric constant anti-reflective coating |
US20050202685A1 (en) * | 2004-03-15 | 2005-09-15 | Applied Materials, Inc. | Adhesion improvement for low k dielectrics |
US20050230834A1 (en) * | 2004-03-31 | 2005-10-20 | Applied Materials, Inc. | Multi-stage curing of low K nano-porous films |
US20050255697A1 (en) * | 2001-07-23 | 2005-11-17 | Applied Materials, Inc. | Selective etching of organosilicate films over silicon oxide stop etch layers |
US20060046519A1 (en) * | 2004-08-31 | 2006-03-02 | Asm Japan K.K. | Method of forming fluorine-doped low-dielectric-constant insulating film |
US20060046427A1 (en) * | 2004-08-27 | 2006-03-02 | Applied Materials, Inc., A Delaware Corporation | Gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials |
US20060077916A1 (en) * | 2004-10-12 | 2006-04-13 | Seiko Epson Corporation | Transceiver, data transfer control device, and electronic instrument |
US20060154493A1 (en) * | 2005-01-10 | 2006-07-13 | Reza Arghavani | Method for producing gate stack sidewall spacers |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2812819B2 (en) | 1991-07-19 | 1998-10-22 | 中部電力株式会社 | Ultrasonic plate thickness measuring device |
DE4123924C2 (en) | 1991-07-19 | 1995-03-09 | Zeiss Carl Jena Gmbh | Methods for the analysis of substances, in particular liquids |
JP2899600B2 (en) * | 1994-01-25 | 1999-06-02 | キヤノン販売 株式会社 | Film formation method |
US5641710A (en) | 1996-06-10 | 1997-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post tungsten etch back anneal, to improve aluminum step coverage |
US6551665B1 (en) * | 1997-04-17 | 2003-04-22 | Micron Technology, Inc. | Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers |
US6303523B2 (en) | 1998-02-11 | 2001-10-16 | Applied Materials, Inc. | Plasma processes for depositing low dielectric constant films |
US6297163B1 (en) | 1998-09-30 | 2001-10-02 | Lam Research Corporation | Method of plasma etching dielectric materials |
TW497140B (en) | 2001-10-09 | 2002-08-01 | Taiwan Semiconductor Mfg | Process system for plasma etching and chemical vapor deposition |
US6656837B2 (en) | 2001-10-11 | 2003-12-02 | Applied Materials, Inc. | Method of eliminating photoresist poisoning in damascene applications |
KR100909175B1 (en) | 2002-12-27 | 2009-07-22 | 매그나칩 반도체 유한회사 | How to form a dual damascene pattern |
KR20050014231A (en) | 2003-07-30 | 2005-02-07 | 매그나칩 반도체 유한회사 | A method for forming a semiconductor device |
US20050037153A1 (en) | 2003-08-14 | 2005-02-17 | Applied Materials, Inc. | Stress reduction of sioc low k films |
US7345000B2 (en) * | 2003-10-10 | 2008-03-18 | Tokyo Electron Limited | Method and system for treating a dielectric film |
US6903004B1 (en) * | 2003-12-16 | 2005-06-07 | Freescale Semiconductor, Inc. | Method of making a semiconductor device having a low K dielectric |
US20070287301A1 (en) | 2006-03-31 | 2007-12-13 | Huiwen Xu | Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics |
-
2007
- 2007-03-30 US US11/694,856 patent/US20070287301A1/en not_active Abandoned
-
2010
- 2010-12-22 US US12/975,833 patent/US8445075B2/en active Active
Patent Citations (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US606884A (en) * | 1898-07-05 | Half to john r | ||
US4980018A (en) * | 1989-11-14 | 1990-12-25 | Intel Corporation | Plasma etching process for refractory metal vias |
US5818071A (en) * | 1995-02-02 | 1998-10-06 | Dow Corning Corporation | Silicon carbide metal diffusion barrier layer |
US6593247B1 (en) * | 1998-02-11 | 2003-07-15 | Applied Materials, Inc. | Method of depositing low k films using an oxidizing plasma |
US6547977B1 (en) * | 1998-04-02 | 2003-04-15 | Applied Materials Inc. | Method for etching low k dielectrics |
US6068884A (en) * | 1998-04-28 | 2000-05-30 | Silcon Valley Group Thermal Systems, Llc | Method of making low κ dielectric inorganic/organic hybrid films |
US6159871A (en) * | 1998-05-29 | 2000-12-12 | Dow Corning Corporation | Method for producing hydrogenated silicon oxycarbide films having low dielectric constant |
US6147009A (en) * | 1998-06-29 | 2000-11-14 | International Business Machines Corporation | Hydrogenated oxidized silicon carbon material |
US6514671B1 (en) * | 1998-08-12 | 2003-02-04 | Applied Materials, Inc. | Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics |
US20050181623A1 (en) * | 1998-10-01 | 2005-08-18 | Applied Materials, Inc. | Silicon carbide deposition for use as a low dielectric constant anti-reflective coating |
US6583070B1 (en) * | 1998-10-27 | 2003-06-24 | Advanced Micro Devices, Inc. | Semiconductor device having a low dielectric constant material |
US6548899B2 (en) * | 1999-06-11 | 2003-04-15 | Electron Vision Corporation | Method of processing films prior to chemical vapor deposition using electron beam processing |
US6486061B1 (en) * | 1999-08-17 | 2002-11-26 | Applied Materials, Inc. | Post-deposition treatment to enhance properties of Si-O-C low K films |
US6465372B1 (en) * | 1999-08-17 | 2002-10-15 | Applied Materials, Inc. | Surface treatment of C-doped SiO2 film to enhance film stability during O2 ashing |
US20050070128A1 (en) * | 1999-08-17 | 2005-03-31 | Applied Materials, Inc. | Post-deposition treatment to enhance properties of Si-O-C low K films |
US6858923B2 (en) * | 1999-08-17 | 2005-02-22 | Applied Materials Inc. | Post-deposition treatment to enhance properties of Si-O-C low films |
US20030077857A1 (en) * | 1999-08-17 | 2003-04-24 | Applied Materials, Inc. | Post-deposition treatment to enhance properties of SI-O-C low films |
US6383907B1 (en) * | 1999-09-08 | 2002-05-07 | Sony Corporation | Process for fabricating a semiconductor device |
US6582777B1 (en) * | 2000-02-17 | 2003-06-24 | Applied Materials Inc. | Electron beam modification of CVD deposited low dielectric constant materials |
US6387608B2 (en) * | 2000-04-06 | 2002-05-14 | Konica Corporation | Photothermographic material |
US6566278B1 (en) * | 2000-08-24 | 2003-05-20 | Applied Materials Inc. | Method for densification of CVD carbon-doped silicon oxide films through UV irradiation |
US6573572B2 (en) * | 2000-08-28 | 2003-06-03 | Micron Technology, Inc. | Damascene structure and method of making |
US6451683B1 (en) * | 2000-08-28 | 2002-09-17 | Micron Technology, Inc. | Damascene structure and method of making |
US6531407B1 (en) * | 2000-08-31 | 2003-03-11 | Micron Technology, Inc. | Method, structure and process flow to reduce line-line capacitance with low-K material |
US6528432B1 (en) * | 2000-12-05 | 2003-03-04 | Advanced Micro Devices, Inc. | H2-or H2/N2-plasma treatment to prevent organic ILD degradation |
US6743732B1 (en) * | 2001-01-26 | 2004-06-01 | Taiwan Semiconductor Manufacturing Company | Organic low K dielectric etch with NH3 chemistry |
US20050003676A1 (en) * | 2001-02-12 | 2005-01-06 | Ho Chok W. | Use of ammonia for etching organic low-k dielectrics |
US20040102330A1 (en) * | 2001-02-13 | 2004-05-27 | Jian Zhou | Viscoelastic compositions |
US6566283B1 (en) * | 2001-02-15 | 2003-05-20 | Advanced Micro Devices, Inc. | Silane treatment of low dielectric constant materials in semiconductor device manufacturing |
US6759367B2 (en) * | 2001-03-29 | 2004-07-06 | Agfa-Gevaert | Thermographic recording material with improved print archivability without loss in printability |
US6583489B2 (en) * | 2001-04-24 | 2003-06-24 | United Microelectronics Corp. | Method for forming interconnect structure with low dielectric constant |
US6583046B1 (en) * | 2001-07-13 | 2003-06-24 | Advanced Micro Devices, Inc. | Post-treatment of low-k dielectric for prevention of photoresist poisoning |
US20050255697A1 (en) * | 2001-07-23 | 2005-11-17 | Applied Materials, Inc. | Selective etching of organosilicate films over silicon oxide stop etch layers |
US6632735B2 (en) * | 2001-08-07 | 2003-10-14 | Applied Materials, Inc. | Method of depositing low dielectric constant carbon doped silicon oxide |
US20030073321A1 (en) * | 2001-08-23 | 2003-04-17 | Applied Material, Inc. | Etch process for dielectric materials comprising oxidized organo silane materials |
US6762127B2 (en) * | 2001-08-23 | 2004-07-13 | Yves Pierre Boiteux | Etch process for dielectric materials comprising oxidized organo silane materials |
US20030109143A1 (en) * | 2001-12-12 | 2003-06-12 | Applied Materials, Inc. | Process for selectively etching dielectric layers |
US20050042889A1 (en) * | 2001-12-14 | 2005-02-24 | Albert Lee | Bi-layer approach for a hermetic low dielectric constant layer for barrier applications |
US20050065698A1 (en) * | 2002-02-08 | 2005-03-24 | David Bertrand | Direct determination of the maximum grip coefficient on the basis of measurement of the circumferential extension in a sidewall of a tire |
US6800566B2 (en) * | 2002-02-21 | 2004-10-05 | Taiwan Semiconductor Manufacturing Company | Adjustment of N and K values in a DARC film |
US20040077164A1 (en) * | 2002-03-08 | 2004-04-22 | Kevin Kornegay | Method for monolithically integrating silicon carbide microelectromechanical devices with electronic circuitry |
US6825134B2 (en) * | 2002-03-26 | 2004-11-30 | Applied Materials, Inc. | Deposition of film layers by alternately pulsing a precursor and high frequency power in a continuous gas flow |
US20030189208A1 (en) * | 2002-04-05 | 2003-10-09 | Kam Law | Deposition of silicon layers for active matrix liquid crystal display (AMLCD) applications |
US20040069410A1 (en) * | 2002-05-08 | 2004-04-15 | Farhad Moghadam | Cluster tool for E-beam treated films |
US20040214446A1 (en) * | 2002-07-11 | 2004-10-28 | Applied Materials, Inc. | Nitrogen-free dielectric anti-reflective coating and hardmask |
US6846756B2 (en) * | 2002-07-30 | 2005-01-25 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for preventing low-k dielectric layer cracking in multi-layered dual damascene metallization layers |
US20040072436A1 (en) * | 2002-10-09 | 2004-04-15 | Ramachandrarao Vijayakumar S. | Replenishment of surface carbon and surface passivation of low-k porous silicon-based dielectric materials |
US6717265B1 (en) * | 2002-11-08 | 2004-04-06 | Intel Corporation | Treatment of low-k dielectric material for CMP |
US6921727B2 (en) * | 2003-03-11 | 2005-07-26 | Applied Materials, Inc. | Method for modifying dielectric characteristics of dielectric layers |
US20050024630A1 (en) * | 2003-04-28 | 2005-02-03 | Renesas Technology Corp. | Device for examining end part |
US20040266216A1 (en) * | 2003-05-08 | 2004-12-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for improving uniformity in deposited low k dielectric material |
US20050100682A1 (en) * | 2003-11-06 | 2005-05-12 | Tokyo Electron Limited | Method for depositing materials on a substrate |
US20050202685A1 (en) * | 2004-03-15 | 2005-09-15 | Applied Materials, Inc. | Adhesion improvement for low k dielectrics |
US20050230834A1 (en) * | 2004-03-31 | 2005-10-20 | Applied Materials, Inc. | Multi-stage curing of low K nano-porous films |
US20060046427A1 (en) * | 2004-08-27 | 2006-03-02 | Applied Materials, Inc., A Delaware Corporation | Gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials |
US20060046519A1 (en) * | 2004-08-31 | 2006-03-02 | Asm Japan K.K. | Method of forming fluorine-doped low-dielectric-constant insulating film |
US20060077916A1 (en) * | 2004-10-12 | 2006-04-13 | Seiko Epson Corporation | Transceiver, data transfer control device, and electronic instrument |
US20060154493A1 (en) * | 2005-01-10 | 2006-07-13 | Reza Arghavani | Method for producing gate stack sidewall spacers |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8445075B2 (en) | 2006-03-31 | 2013-05-21 | Applied Materials, Inc. | Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics |
US20080261008A1 (en) * | 2007-04-18 | 2008-10-23 | Toppan Printing Co., Ltd. | Anti-reflection film |
US8236684B2 (en) | 2008-06-27 | 2012-08-07 | Applied Materials, Inc. | Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer |
WO2009158180A2 (en) * | 2008-06-27 | 2009-12-30 | Applied Materials, Inc. | Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer |
US20090325381A1 (en) * | 2008-06-27 | 2009-12-31 | Applied Materials, Inc. | Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer |
WO2009158180A3 (en) * | 2008-06-27 | 2010-03-04 | Applied Materials, Inc. | Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer |
US8481422B2 (en) | 2008-06-27 | 2013-07-09 | Applied Materials, Inc. | Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer |
US20110097904A1 (en) * | 2009-10-22 | 2011-04-28 | Lam Research Corporation | Method for repairing low-k dielectric damage |
CN102549726A (en) * | 2009-10-22 | 2012-07-04 | 朗姆研究公司 | Method for tunably repairing low-K dielectric damage |
US20110244600A1 (en) * | 2009-10-22 | 2011-10-06 | Lam Research Corporation | Method for tunably repairing low-k dielectric damage |
US20120015517A1 (en) * | 2010-07-15 | 2012-01-19 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
US9337093B2 (en) * | 2010-07-15 | 2016-05-10 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
US20160176016A1 (en) * | 2014-12-19 | 2016-06-23 | Applied Materials, Inc. | Components for a chemical mechanical polishing tool |
US10434627B2 (en) * | 2014-12-19 | 2019-10-08 | Applied Materials, Inc. | Components for a chemical mechanical polishing tool |
US11376709B2 (en) | 2014-12-19 | 2022-07-05 | Applied Materials, Inc. | Components for a chemical mechanical polishing tool |
CN104966694A (en) * | 2015-06-29 | 2015-10-07 | 上海集成电路研发中心有限公司 | Double Damascus integration technology method |
US20220044929A1 (en) * | 2018-05-22 | 2022-02-10 | Versum Patents Us, Llc | Functionalized cyclosilazanes as precursors for high growth rate silicon-containing films |
Also Published As
Publication number | Publication date |
---|---|
US8445075B2 (en) | 2013-05-21 |
US20110092077A1 (en) | 2011-04-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8445075B2 (en) | Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics | |
JP5174435B2 (en) | Method for minimizing wet etch undercut and pore sealing ultra-low K (K <2.5) dielectrics | |
KR102376352B1 (en) | Method and composition for providing pore sealing layer on porous low dielectric constant films | |
US7851384B2 (en) | Method to mitigate impact of UV and E-beam exposure on semiconductor device film properties by use of a bilayer film | |
US6541397B1 (en) | Removable amorphous carbon CMP stop | |
US7091137B2 (en) | Bi-layer approach for a hermetic low dielectric constant layer for barrier applications | |
US7115534B2 (en) | Dielectric materials to prevent photoresist poisoning | |
US8492170B2 (en) | UV assisted silylation for recovery and pore sealing of damaged low K films | |
KR100743775B1 (en) | Method and apparatus for treating l0w k dielectric layers to reduce diffusion | |
JP5031987B2 (en) | Double-layer film for next-generation damascene barrier applications with good oxidation resistance | |
JP5268130B2 (en) | Method for forming an oxygen-containing silicon carbide film | |
US6632478B2 (en) | Process for forming a low dielectric constant carbon-containing film | |
US6927178B2 (en) | Nitrogen-free dielectric anti-reflective coating and hardmask | |
US8481422B2 (en) | Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer | |
US20050277302A1 (en) | Advanced low dielectric constant barrier layers | |
TWI673826B (en) | Flowable film curing penetration depth improvement and stress tuning | |
US7288205B2 (en) | Hermetic low dielectric constant layer for barrier applications | |
WO2007117320A2 (en) | A method to improve the ashing/wet etch damage resistance and integration stability of low dielectric constant films | |
US7105460B2 (en) | Nitrogen-free dielectric anti-reflective coating and hardmask | |
US20050124151A1 (en) | Novel method to deposit carbon doped SiO2 films with improved film quality | |
US20090107626A1 (en) | Adhesion improvement of dielectric barrier to copper by the addition of thin interface layer | |
KR101106425B1 (en) | Nitrogen-free dielectric anti-reflective coating and hardmask | |
TWI762761B (en) | Use of silicon structure former with organic substituted hardening additive compounds for dense osg films |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: APPLIED MATERIALS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:XU, HUIWEN;SHEK, MEI-YEE;XIA, LI-QUIN;AND OTHERS;REEL/FRAME:019095/0895;SIGNING DATES FROM 20070316 TO 20070330 |
|
AS | Assignment |
Owner name: APPLIED MATERIALS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:M/SAAD, HICHEM;REEL/FRAME:019268/0655 Effective date: 20070405 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |