WO2009020024A1 - サセプタ及びシリコンエピタキシャルウェーハの製造方法 - Google Patents

サセプタ及びシリコンエピタキシャルウェーハの製造方法 Download PDF

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Publication number
WO2009020024A1
WO2009020024A1 PCT/JP2008/063661 JP2008063661W WO2009020024A1 WO 2009020024 A1 WO2009020024 A1 WO 2009020024A1 JP 2008063661 W JP2008063661 W JP 2008063661W WO 2009020024 A1 WO2009020024 A1 WO 2009020024A1
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WO
WIPO (PCT)
Prior art keywords
susceptor
epitaxial wafer
silicon epitaxial
manufacturing silicon
film
Prior art date
Application number
PCT/JP2008/063661
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English (en)
French (fr)
Inventor
Tsuyoshi Nishizawa
Yoshio Hagiwara
Hideki Hariya
Original Assignee
Shin-Etsu Handotai Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin-Etsu Handotai Co., Ltd. filed Critical Shin-Etsu Handotai Co., Ltd.
Priority to US12/452,862 priority Critical patent/US8021968B2/en
Priority to JP2009526405A priority patent/JP5024382B2/ja
Publication of WO2009020024A1 publication Critical patent/WO2009020024A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/6875—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a plurality of individual support members, e.g. support posts or protrusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material

Abstract

　シリコン基板Ｗを載置する載置面にメッシュ状の溝１３ｂを備えたエピタキシャルウェーハ製造用のサセプタ１３であって、前記載置面には、炭化珪素の被膜Ｈが形成され、前記被膜Ｈは、表面粗さが中心線平均粗さＲａで１μｍ以上となり、当該被膜Ｈのコーティング時に発生する突起１３ｐの最大高さが５μｍ以下となるよう形成される。これにより、シリコン基板とサセプタとの貼り付きとともに、歪みやスリップといった欠陥の発生を防止することができる。
PCT/JP2008/063661 2007-08-03 2008-07-30 サセプタ及びシリコンエピタキシャルウェーハの製造方法 WO2009020024A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/452,862 US8021968B2 (en) 2007-08-03 2008-07-30 Susceptor and method for manufacturing silicon epitaxial wafer
JP2009526405A JP5024382B2 (ja) 2007-08-03 2008-07-30 サセプタ及びシリコンエピタキシャルウェーハの製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007203080 2007-08-03
JP2007-203080 2007-08-03

Publications (1)

Publication Number Publication Date
WO2009020024A1 true WO2009020024A1 (ja) 2009-02-12

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/063661 WO2009020024A1 (ja) 2007-08-03 2008-07-30 サセプタ及びシリコンエピタキシャルウェーハの製造方法

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Country Link
US (1) US8021968B2 (ja)
JP (1) JP5024382B2 (ja)
WO (1) WO2009020024A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018078284A (ja) * 2016-10-28 2018-05-17 ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ 開放空間均圧化通路および側方閉じ込めを備えた平坦な基板縁部接触部

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