TWI794275B - 通過迴圈沉積過程在基材的介電表面上沉積鉬金屬膜的方法和相關的半導體元件結構 - Google Patents

通過迴圈沉積過程在基材的介電表面上沉積鉬金屬膜的方法和相關的半導體元件結構 Download PDF

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TWI794275B
TWI794275B TW107129471A TW107129471A TWI794275B TW I794275 B TWI794275 B TW I794275B TW 107129471 A TW107129471 A TW 107129471A TW 107129471 A TW107129471 A TW 107129471A TW I794275 B TWI794275 B TW I794275B
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molybdenum
film
substrate
metal film
depositing
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TW201920736A (zh
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巴山 羅普
基蘭 什雷斯塔
山卡 施娃米納坦
朱馳宇
亨利 托瑪士 安特羅 傑席拉
琦 謝
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荷蘭商Ａｓｍ智慧財產控股公司
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Abstract

本發明公開了通過迴圈沉積過程在基材的介電表面上沉積鉬金屬膜的方法。所述方法可以包括：把包括介電表面的基材放到反應室中；在所述介電表面上直接沉積成核膜；然後在所述成核膜上直接沉積鉬金屬膜，其中沉積所述鉬金屬膜包括：使所述基材與包含鉬鹵化物前體的第一氣相反應物接觸；然後使所述基材與包含還原劑前體的第二氣相反應物接觸。還公開了包括利用中間的成核膜設置在介電材料的表面上的鉬金屬膜的半導體元件結構。

Description

通過迴圈沉積過程在基材的介電表面上沉積鉬金屬膜的方法和相關的半導體元件結構 〔相關申請的交叉引用〕
本申請案請求下列申請案的優先權：2017年8月30日提交的名稱為“Layer Forming Method”的美國非臨時專利申請案第15/691,241號；2017年12月18日提交的名稱為“Layer Forming Method”的美國臨時專利申請案第62/607,070號；以及2018年1月19日提交的名稱為“Deposition Method”的美國臨時專利申請案第62/619,579號。
本公開整體涉及用於在基材的介電表面上沉積鉬金屬膜的方法，尤其是用於在介電表面上直接沉積成核膜、然後在該成核膜上直接沉積鉬金屬膜的方法。本公開還整體涉及半導體元件結構，這些結構包括直接設置在成核膜上的鉬金屬膜，該成核膜直接設置在介電材料的表面上。
先進技術節點中的半導體元件製造過程通常需要目前最高水準 的用於形成金屬膜(例如鎢金屬膜和銅金屬膜)的沉積方法。
沉積金屬膜的一個常見要求是，沉積過程必須具有極高的保形性。例如，通常需要保形沉積，以便在包括高縱橫比特徵的三維結構上均勻地沉積金屬膜。沉積金屬膜的另一個常見要求是，沉積過程能夠沉積出在大的基材區域上連續的超薄膜。在金屬膜具有導電性的特定情況下，可能需要優化沉積過程來產生低電阻率膜。
在目前最高水準的半導體元件應用中普遍使用的低電阻率金屬膜可以包括鎢(W)金屬膜和/或銅(Cu)金屬膜。然而，鎢金屬膜和銅金屬膜常常需要在金屬膜與介電材料之間設置厚的阻擋層。這種厚的阻擋層可以用於防止金屬物質擴散到下面的介電材料中，從而提高元件可靠性和元件良率。但這種厚的阻擋層常常表現出高電阻率，因而造成半導體元件結構的總電阻率增大。
迴圈沉積過程(諸如原子層沉積(ALD)和迴圈化學氣相沉積(CCVD))將一種或多種前體(反應物)依序引入反應室，在反應室中，這些前體以依序的方式每次一個地與基材表面反應。現已證實，迴圈沉積過程採用原子級的厚度控制，產生了具有極佳保形性的金屬膜。
因此，期望開發出用來沉積和利用低電阻率金屬膜的方法和相關的元件結構，這些低電阻率金屬膜是通過保形迴圈沉積過程沉積在介電材料上的。
提供此概述是為了以簡化形式引入一系列概念。下文在本公開的實例實施例的詳細描述中進一步詳細描述這些概念。此概述並不意圖識別所要求的主題的關鍵特徵或基本特徵，也並非意圖用於限制所要求的主題的範圍。
在一些實施例中，提供了通過迴圈沉積過程在基材的介電表面上沉積鉬金屬膜的方法。這些方法可以包括：把包括介電表面的基材放到反應室中；在介電表面上直接沉積成核膜；然後在成核層上直接沉積鉬金屬膜，其中沉積該鉬金屬膜包括：使基材與包含鉬鹵化物前體的第一氣相反應物接觸；然後使基材與包含還原劑前體的第二氣相反應物接觸。
在一些實施例中，提供了半導體元件結構。這些半導體元件結構可以包括：包括介電表面的基材；直接設置在介電表面上的成核膜；以及直接設置在成核膜上的鉬金屬膜。
出於概述本發明和優於現有技術而實現的優勢的目的，上文中描述了本發明的某些目標和優勢。當然，應理解，未必所有此類目標或優勢都可根據本發明的任一特定實施例實現。因此，舉例來說，所屬領域的技術人員將認識到，本發明可以按實現或優化如本文中所教示或建議的一種優勢或一組優勢，但不一定實現如本文中可能教示或建議的其他目的或優勢的方式來實施或進行。
所有這些實施例意欲在本文中所公開的本發明的範圍內。對於所屬領域的技術人員來說，這些和其他實施例將從參考附圖的某些實施例的以下詳細描述變得顯而易見，本發明不限於所公開的任何特定實施例。
100:過程
110:把包括介電表面的基材放到反應室中
120:在介電表面上直接沉積成核膜
130:在成核膜上直接沉積鉬金屬膜
140:退出
205:迴圈沉積階段
210:將基材加熱到期望的沉積溫度
220:使基材與第一矽前體或鉬前體中的至少一種接觸
230:使基材與氮前體、氧前體、碳前體或第二矽前體中的至少一種接觸
240:將成核膜沉積到期望的厚度
250:退出
305:迴圈沉積階段
310:將基材加熱到期望的沉積溫度
320:使基材與鉬鹵化物前體接觸
330:使基材與還原劑前體接觸
340:將鉬膜沉積到期望的厚度
350:退出
400:半導體元件結構
402:基材
404:垂直間隙特徵
405:半導體元件結構
406:連續成核膜
406`:不連續成核膜
408:插圖
410:半導體元件結構
412:鉬金屬膜
500:半導體元件結構
502:基材
504:水平高縱橫比間隙特徵
505:半導體元件結構
506:連續成核膜
506`:不連續成核膜
510:半導體元件結構
512:鉬金屬膜
600:鉬金屬膜
602:鉬金屬膜
儘管本說明書結束於具體地指出被視為本發明多個實施例的內容並且明顯地要求這些內容的權利的權利要求，但是在結合附圖閱讀時，可以根據對本公開多個實施例的某些實例的描述更容易地確定本公開多個實施例的優點，在附圖中：圖1展示了根據本公開多個實施例的非限制性示例性工序流程，從而演示了 用於在介電表面上直接沉積成核膜、隨後在該成核膜上直接沉積鉬金屬膜的一種方法；圖2展示了根據本公開多個實施例的非限制性示例性工序流程，從而演示了用於在介電表面上直接沉積成核膜的一種迴圈沉積過程；圖3展示了根據本公開多個實施例的非限制性示例性工序流程，從而演示了用於在成核膜上直接沉積鉬金屬膜的一種迴圈沉積過程；圖4A、圖4B和圖4C展示了根據本公開多個實施例的在具有垂直間隙特徵的介電表面上直接沉積成核膜、隨後在該成核膜上直接沉積鉬金屬膜這樣的過程期間形成的半導體元件結構的橫截面示意圖；並且圖5A、圖5B和圖5C展示了根據本公開多個實施例的在具有水平間隙特徵的介電表面上直接沉積成核膜、隨後在該成核膜上直接沉積鉬金屬膜這樣的過程期間形成的半導體元件結構的橫截面示意圖；並且圖6展示了根據本公開多個實施例的直接沉積在介電表面上的鉬金屬膜和利用中間的成核膜沉積在介電表面上的鉬金屬膜這兩者的r.m.s.表面粗糙度(Ra)。
儘管下文公開某些實施例和實例，但所屬領域的技術人員將理解，本發明延伸超出了所具體公開的實施例和/或本發明的用途和顯而易見的修改以及其等效物。因此，希望本發明所公開的範圍不應受下文所描述特定公開實施例的限制。
本文中呈現的圖解並不意味著任何特定材料、結構或元件的實際視圖，而僅僅是用於描述本公開多個實施例的理想化圖示。
如本文所用，術語「基材」可以指代可以使用的，或者在其上可 以形成元件、電路或膜的任何一種或多種底層材料。
如本文所用，術語「迴圈沉積」可以指代將一種或多種前體(反應物)依序引入反應室以在基材上沉積膜，並且包括諸如原子層沉積和迴圈化學氣相沉積等沉積技術。
如本文所用，術語「迴圈化學氣相沉積」可以指代其中基材依序暴露於一種或多種揮發性前體的任何過程，該一種或多種揮發性前體在基材上反應和/或分解以產生期望的沉積。
如本文所用，術語「原子層沉積」(ALD)可以指代在反應室中實施沉積迴圈(優選地多個連續的沉積迴圈)的氣相沉積過程。通常，在每個迴圈期間，將前體用化學方法吸附沉積表面(例如，基材表面或先前沉積的底層表面，例如來自先前ALD迴圈的材料)，從而形成不易與額外前體反應的單層或亞單層(即，自限性反應)。此後，視需要，可以隨後將反應物(例如，另一種前體或反應氣體)引入到工藝腔室中以用於將用化學方法吸附的前體轉化成沉積表面上的所要材料。通常，此反應物能夠與前體進一步反應。此外，在每個迴圈期間還可利用沖洗步驟以在轉換用化學方法吸附的前體之後從工藝腔室去除過量前體和/或從工藝腔室去除過量反應物和/或反應副產物。另外，如本文所用的術語「原子層沉積」在使用一種或多種前體組合物、反應氣體和吹掃(例如，惰性載體)氣體這三者的交替脈衝執行時，還意在包括由諸如「化學氣相原子層沉積」、「原子層磊晶法」(ALE)、分子束磊晶法(MBE)、氣體源MBE或有機金屬MBE和化學束磊晶法等相關術語指定的那些過程。
如本文所用，術語「膜」和「薄膜」可以指代利用本文公開的方法形成的任何連續或非連續的結構和材料。例如，「膜」和「薄膜」可以包括2D材料、奈米層壓材料、奈米棒、奈米管或奈米粒子，或者甚至部分或完整的分子層，或者部分或完整的原子層或原子簇和/或分子簇。「膜」和「薄膜」可以包 含具有小孔、但仍然至少部分連續的材料或層。
如本文所用，術語「化合物材料」可以指代包含化學結合的兩種或更多種不同元素的材料。
如本文所用，術語「二元化合物材料」可以指代基本上由兩種不同元素組成的材料。儘管術語「二元化合物材料」可以指代基本上由兩種不同元素組成的材料，但是應當指出，二元化合物材料也可以包含痕量的雜質元素。
如本文所用，術語「矽二元化合物材料」可以指代基本上由矽原子和附加的不同元素組成的材料。儘管術語「矽二元化合物材料」可以指代基本上由矽原子和附加的不同元素組成的材料，但是應當指出，矽二元化合物材料也可以包含痕量的雜質元素。
如本文所用，術語「鉬二元化合物材料」可以指代基本上由鉬原子和附加的不同元素組成的材料。儘管術語「鉬二元化合物材料」可以指代基本上由鉬原子和附加的不同元素組成的材料，但是應當指出，鉬二元化合物材料也可以包含痕量的雜質元素。
如本文所用，術語「鉬鹵化物前體」可以指代至少包含鉬組分和鹵化物組分的反應物，其中鹵化物組分可以包括氯組分、碘組分或溴組分中的一種或多種。
如本文所用，術語「硫屬化物鹵化鉬」可以指代至少包含鉬組分、鹵化物組分和硫族元素組分的反應物，其中硫族元素是元素週期表第IV族的元素，包括氧(O)、硫(S)、硒(Se)和碲(Te)。
如本文所用，術語「鉬鹵氧化物」可以指代至少包含鉬組分、氧組分和鹵化物組分的反應物。
如本文所用，術語「還原劑前體」可以指代在氧化還原化學反應中將電子供給另一種物質的反應物。
如本文所用，術語「結晶膜」可以指代這樣的膜：它至少顯示短程有序的結晶結構、甚至顯示長程有序的結晶結構，不僅包括多晶膜、還包括單晶膜。
如本文所用，術語「間隙特徵」可以指代設置在不平坦表面的兩個表面之間的開口或空腔。術語「間隙特徵」可以指代設置在從基材表面垂直延伸的兩個突起的相對傾斜側壁之間或者垂直延伸到基材表面中的一個凹陷的相對傾斜側壁之間的開口或空腔，這樣的間隙特徵可以稱為「垂直間隙特徵」。術語「間隙特徵」還可以指代設置在兩個相對的基本上水平的表面之間的開口或空腔，這兩個水平表面界定水平開口或空腔；這樣的間隙特徵可以稱為「水平間隙特徵」。
如本文所用，術語「接縫」可以指代由於鄰接間隙填充金屬中所形成的邊緣而形成的一條線或者一個或多個空隙，並且「接縫」可以使用掃描穿透式電子顯微鏡(STEM)或穿透式電子顯微鏡(TEM)證實，其中，如果觀察結果揭示垂直間隙填充金屬中存在清晰的垂直線或者一個或多個垂直空隙，或者水平間隙填充金屬中存在清晰的水平線或者一個或多個水平空隙，則稱存在「接縫」。
儘管貫穿本公開的多個實施例給出了許多種示例材料，但是應當指出，針對這些示例材料中的每一種給出的化學式不應被理解為限制性的，而且給出的非限制性示例材料不應受到給出的示例化學計量的限制。
本公開包括利用中間的成核膜在介電材料的表面上沉積鉬金屬膜的方法，該中間的成核膜直接設置在介電材料的表面上。鉬金屬薄膜可以在許多應用中得到利用，諸如低電阻率間隙填充、用於3D-NAND的襯墊層、DRAM字線特徵，或者用作CMOS邏輯應用中的互連材料。由於能夠利用中間的成核膜(即，不使用高電阻率襯墊層)在介電表面上沉積鉬金屬膜，因而可以允許邏 輯應用(即CMOS結構)中的互連和記憶體應用(諸如3D-NAND結構和DRAM結構)中的字線/位線具有較低的有效電阻率。
因此，本公開的多個實施例可以包括利用中間的成核膜在基材的介電表面上沉積鉬金屬膜的方法。這些方法可以包括：把包括介電表面的基材放到反應室中；在介電表面上直接沉積成核膜；然後在成核膜上直接沉積鉬金屬膜，其中沉積該鉬金屬膜包括：使基材與包含鉬鹵化物前體的第一氣相反應物接觸；然後使基材與包含還原劑前體的第二氣相反應物接觸。
參照圖1展示了利用中間的成核膜在介電表面上沉積鉬金屬膜的示例性過程100。示例性過程100可以包括兩個沉積過程，分別是：用於在介電材料的表面上直接沉積成核膜的第一沉積過程，以及用於在成核膜上直接沉積鉬金屬膜的第二沉積過程。
更詳細地講並且參照圖1，示例性過程100可以藉助於程序方塊110開始，該程序方塊包括把包括介電表面的基材放到反應室中。
在本公開的一些實施例中，基材可以包括圖案化基材，該圖案化基材包括高縱橫比特徵，諸如溝槽結構、水平間隙和/或翅片結構。例如，基材可以包括一個或多個基本上垂直的間隙特徵以及/或者一個或多個基本上水平的間隙特徵。術語「間隙特徵」可以指代設置在從基材表面垂直延伸的兩個突起的相對傾斜側壁之間或者垂直延伸到基材表面中的一個凹陷的相對傾斜側壁之間的開口或空腔，這樣的間隙特徵可以稱為「垂直間隙特徵」。術語「間隙特徵」還可以指代設置在兩個相對的基本上水平的表面之間的開口或空腔，這兩個水平表面界定水平開口或空腔；這樣的間隙特徵可以稱為「水平間隙特徵」。應當指出，本公開的多個實施例並不限於填充垂直間隙特徵和/或水平間隙特徵，並且可以通過本文公開的過程，用鉬金屬填充設置在基材中和/或基材上且具有其他幾何形狀的間隙特徵。
在本公開的一些實施例中，基材可以包括一個或多個如圖4A所展示的基本上垂直的間隙特徵，該圖展示了包括基材402的半導體元件結構400，該基材402包括具有設置在該基材中的高縱橫比垂直間隙特徵404的介電材料。在一些實施例中，一個或多個垂直間隙特徵可以具有下述縱橫比(高度：寬度)，該縱橫比可以大於2：1、或大於5：1、或大於10：1、或大於25：1、或大於50：1、或甚至大於100：1，其中如該實例中所用的「大於」是指該間隙特徵的高度中的較大距離。
在本公開的一些實施例中，基材可以包括一個或多個如圖5A所展示的基本上水平的間隙特徵，該圖展示了包括基材502的半導體元件結構500，該基材502包括具有設置在該基材中的高縱橫比水平間隙特徵504的介電材料。在一些實施例中，一個或多個水平間隙特徵可以具有下述縱橫比(高度：寬度)，該縱橫比可以大於1：2、或大於1：5、或大於1：10、或大於1：25、或大於1：50、或甚至大於1：100，其中如該實例中所用的「大於」是指該間隙特徵的寬度中的較大距離。
基材可以包括一種或多種材料和材料表面，包括但不限於半導體材料、介電材料和金屬材料。
在一些實施例中，基材可以包括半導體材料，諸如但不限於矽(Si)、鍺(Ge)、鍺錫(GeSn)、矽鍺(SiGe)、矽鍺錫(SiGeSn)、碳化矽(SiC)或III-V族半導體材料。
在一些實施例中，基材可以包括金屬材料，諸如但不限於純金屬、金屬氮化物、金屬碳化物、金屬硼化物以及它們的混合物。
在一些實施例中，基材可以包括介電材料，諸如但不限於含矽的介電材料和金屬氧化物介電材料。在一些實施例中，基材可以包括一個或多個介電表面，該一個或多個介電表面包括含矽的介電材料，諸如但不限於二氧化 矽(SiO2)、矽低值氧化物、氮化矽(Si3N4)、氮氧化矽(SiON)、碳氧化矽(SiOC)、碳氧氮化矽(SiOCN)、碳氮化矽(SiCN)。在一些實施例中，基材可以包括一個或多個介電表面，該一個或多個介電表面包括金屬氧化物，諸如但不限於氧化鋁(Al2O3)、氧化鉿(HfO2)、氧化鉭(Ta2O5)、氧化鋯(ZrO2)、氧化鈦(TiO2)、矽酸鉿(HfSiOx)和氧化鑭(La2O3)。
在本公開的一些實施例中，基材可以包括工程化基材，其中表面半導體層設置在本體支撐件上，且這兩者之間設置有居間的隱埋氧化物(BOX)。
圖案化基材可以包括下述基材：這些基材可以包括形成到基材的表面中或基材的表面上的半導體元件結構，例如，圖案化基材可以包括製成和/或部分製成的半導體元件結構，諸如電晶體和/或記憶體元件。在一些實施例中，基材可以包含單晶表面以及/或者一個或多個次要表面，該一個或多個次要表面可以包括非單晶表面，諸如多晶表面和/或非晶表面。單晶表面可包括例如以下中的一種或多種：矽(Si)、矽鍺(SiGe)、鍺錫(GeSn)或鍺(Ge)。多晶表面或非晶表面可以包括介電材料，諸如氧化物、氮氧化物、碳氧化物、碳氧氮化物、氮化物或它們的混合物。
基材可以被設置到一個或多個反應室中，該一個或多個反應室被配置用於在介電材料的表面上直接沉積成核膜，並且用於在成核膜上直接沉積鉬金屬膜。在一些實施例中，可以通過化學氣相沉積(CVD)過程、浸泡過程、電漿增強化學氣相沉積(PECVD)過程或物理氣相沉積(PVD)過程中的一種或多種在介電表面上直接沉積成核膜。在本公開的多個特定實施例中，成核膜和鉬膜都可以利用迴圈沉積過程加以沉積，這是因為利用迴圈沉積過程可實現固有的保形性，並且迴圈沉積過程能夠在不平坦基材上形成包括一個或多個高縱橫比特徵(包括但不限於垂直間隙特徵和/或水平間隙特徵)的保形膜。
因此，能夠用於利用中間的成核膜在介電表面上沉積鉬金屬膜的 反應器或反應室可以被配置用於執行迴圈沉積過程，諸如原子層沉積過程或迴圈化學氣相沉積過程。因此，適用於執行本公開的多個實施例的反應器或反應室可以包括被配置為提供前體的ALD反應器以及CVD反應器。根據一些實施例，可使用噴淋頭反應器。根據一些實施例，可以使用錯流反應器、間歇式反應器、小批量反應器或空間ALD反應器。
在本公開的一些實施例中，可以使用間歇式反應器。在一些實施例中，可以使用垂直的間歇式反應器。在其他實施例中，間歇式反應器包括被配置為容納10個或更少晶片、8個或更少晶片、6個或更少晶片、4個或更少晶片、或者2個或更少晶片的小批量反應器。在使用間歇式反應器的一些實施例中，晶片到晶片的不均勻性小於3%(1σ)、小於2%、小於1%或甚至小於0.5%。
利用如本文所述的中間的成核膜沉積鉬金屬膜填充物的示例性過程可以任選地在連接到叢聚式設備的一個或多個反應器或者一個或多個反應室中進行。在叢聚式設備中，因為每個反應室都專用於一種類型的過程，所以每個模組中的反應室的溫度都可以保持恒定，與在每次運行前將基材加熱到高達過程溫度的反應器相比，這提高了生產量。此外，在叢聚式設備中，有可能縮短在任何兩個基材之間用泵將反應室增壓到期望的過程壓力程度的時間。在本公開的一些實施例中，本文公開的示例性過程可以在包括多個反應室的叢聚式設備中執行，其中每個單獨的反應室都可以用於將基材暴露於單獨的前體氣體，並且基材可以在不同的反應室之間轉移以便暴露於多種前體氣體，在受控的周圍環境下對基材執行轉移是為了防止基材氧化/污染。例如，沉積成核膜可以通過在與叢聚式設備相關聯的第一反應室中的迴圈沉積過程來執行，而沉積鉬膜可以通過在與同一個叢聚式設備相關聯的第二反應室中的迴圈沉積過程來執行，在第一反應室與第二反應室之間的轉移在受控的環境下發生，以便防止基材和相關聯的膜受到污染或出現降解。在本公開的一些實施例中，本公開的 過程可以在包括多個反應室的叢聚式設備中執行，其中每個單獨的反應室都可以被配置為將基材加熱到不同的溫度。
在一些實施例中，在介電表面上直接沉積成核膜並且在成核膜上直接沉積鉬金屬膜的示例性過程可以在單個獨立反應器中執行，該獨立反應器可以配備裝載腔。在該情況下，不必在每次運行之間將反應室冷卻下來。
一旦把基材放置在合適的反應室(例如，被配置用於迴圈沉積過程的反應室)內，圖1的示例性過程100就可以藉助於程序方塊120繼續進行，該程序方塊包括在介電表面上直接沉積成核膜。參照圖2更詳細地描述了程序方塊120及構成該程序方塊的子過程，該圖展示了用於在介電表面上直接沉積成核膜的示例性非限制性迴圈沉積過程。
更詳細地講，用於在介電表面上直接沉積成核膜的沉積過程可以藉助於子過程210繼續進行，該子過程包括將基材加熱到期望的沉積溫度。例如，可以將基材加熱到低於大約800℃、或低於大約700℃、或低於大約600℃、或低於大約500℃、或低於大約400℃、或低於大約300℃、或甚至低於大約200℃的基材溫度。在本公開的一些實施例中，程序方塊120的迴圈沉積過程期間的基材溫度可以介於250℃與800℃之間、或介於300℃與600℃之間、或介於550℃與600℃之間。
在一些實施例中，用於沉積成核膜的沉積溫度可以取決於正在沉積的材料的組成。例如，在本公開的一些實施例中，成核膜可以包含化合物材料，即，至少包含兩種不同元素的材料。在一些實施例中，該化合物材料可以包括二元化合物材料，即，基本上由兩種不同元素和痕量雜質元素組成的材料。在一些實施例中，該化合物可以包括三元化合物材料，即，基本上由三種不同元素和痕量雜質元素組成的材料。
在一些實施例中，二元化合物材料可以包括矽二元化合物材料， 其中矽化合物材料基本上由矽原子和不同元素與痕量雜質元素組成。例如，在一些實施例中，矽二元化合物材料可以包括氮化矽(例如，Si3N4)、碳化矽(例如，SiC)或氧化矽(例如，SiO2)中的至少一種。在此類示例實施例中，在沉積包含矽二元化合物材料的成核層期間基材的溫度可以低於大約500℃、或低於大約400℃、或低於大約300℃、或低於大約250℃、或甚至低於大約200℃。
在一些實施例中，二元化合物材料可以包括鉬二元化合物材料，其中鉬化合物材料基本上由鉬原子和不同元素與痕量雜質元素組成。例如，在一些實施例中，鉬二元化合物材料可以包括氮化鉬、碳化鉬、氧化鉬或矽化鉬中的至少一種。在此類示例實施例中，在沉積包含鉬二元化合物材料的成核膜期間基材的溫度可以低於大約700℃、或低於大約600℃、或低於大約500℃、或低於大約400℃、或甚至低於大約300℃。在一些實施例中，沉積包含鉬二元化合物材料的成核膜可以在介於300℃與600℃之間、或介於400℃與500℃之間的基材溫度下執行。
在本公開的一些實施例中，成核膜可以包含三元化合物，諸如矽三元化合物(例如，SiCN、SiON)或鉬三元化合物(例如，MoON、MoSiO)。在此類實施例中，在沉積三元化合物期間基材的溫度可以低於大約700℃、或低於大約600℃、或低於大約500℃、或低於大約400℃、或甚至低於大約300℃。
此外，為了實現期望的沉積溫度(即，期望的基材溫度)，用於在介電表面上直接沉積成核膜的示例性原子層沉積過程(即，程序方塊120)還可以在沉積期間調節反應室內的壓力，以便獲得直接位於介電表面上的成核膜的理想特性。例如，在本公開的一些實施例中，示例性迴圈沉積過程可以在被調節到反應室壓力小於300托、或小於200托、或小於100托、或小於50托、或小於25托、或小於15托、或甚至小於1托的反應室內執行。在一些實施例中，在沉積成核膜期間反應室內的壓力可以在介於1托與300托之間、或介於1托與50托之 間、或介於1托與15托之間、或者甚至等於或大於30托的壓力下調節。
一旦基材已被加熱到期望的溫度並且反應室內的壓力已被調節到期望的程度，用於在介電表面上直接沉積成核膜的示例性過程就可以藉助於迴圈沉積階段205繼續進行，該迴圈沉積階段可以包括原子層沉積(ALD)或迴圈化學氣相沉積(CCVD)。
迴圈沉積過程的一個非限制性示例實施例可以包括原子層沉積(ALD)，其中ALD典型地以自限性反應為基礎，由此，使用反應物的依序和交替的脈衝，在每個沉積迴圈內大約沉積材料的一個原子(或分子)單層。通常對沉積條件和前體進行選擇，以便提供自飽和反應，使得一種反應物的吸收層留下不與同一反應物的氣相反應物反應的表面終止狀態。基材隨後與不同反應物接觸，所述不同反應物與先前末端反應以實現繼續沉積。因此，交替脈衝的每個迴圈通常留下所要材料的不多於約一個單層。然而，如上文所提及，技術人員將認識到，在一個或多個ALD迴圈中，例如在一些氣相反應發生而不管過程的交替性質究竟如何的情況下，可以沉積材料的多於一個單層。
在用於在介電表面上直接形成成核膜的ALD類型過程中，一個沉積迴圈可以包括使基材暴露於第一氣相反應物、從反應室中移除任何未反應的第一反應物和反應副產物，然後使基材暴露於第二氣相反應物，之後進行第二次移除步驟。在本公開的一些實施例中，第一氣相反應物可以包括第一矽前體或鉬前體中的至少一種，第二氣相反應物可以包括氮前體、碳前體、氧前體或第二矽前體中的至少一種。
可以通過例如氬氣(Ar)或氮氣(N2)等惰性氣體來分離前體，以防止反應物之間的氣相反應並實現自飽和表面反應。但在一些實施例中，可以移動基材，以便單獨地接觸第一氣相反應物和第二氣相反應物。由於反應發生自飽和，因而可以不需要對基材進行嚴格的溫度控制，也不需要對前體進行 精確的劑量控制。然而，基材溫度優選地使得附帶的氣體物種既不冷凝成單層，也不在表面上分解。在使基材與下一反應化學品接觸之前，例如通過沖洗反應空間或通過移動基材來從基材表面去除剩餘的化學品和反應副產物(如果存在)。可以藉助於惰性沖洗氣體從反應空間中有效地排出不合期望的氣態分子。可以使用真空泵來輔助沖洗。
根據本公開的一些非限制性實施例，ALD過程可以用於在介電材料表面上直接沉積成核膜。在本公開的一些實施例中，每個ALD迴圈都可以包括兩個不同的沉積步驟或階段。在沉積迴圈的第一階段中，可以使期望在其上進行沉積的基材表面與化學吸附到基材表面上的第一氣相反應物接觸，該第一氣相反應物包括第一矽前體或鉬前體中的至少一種，從而在基材表面上形成反應物物質的不超過約一個單層。在沉積的第二階段中，可以使期望在其上進行沉積的基材表面與第二氣相反應物接觸，該第二氣相反應物包括氮前體、碳前體、氧前體或第二矽前體中的至少一種。
在將基材加熱到期望的沉積溫度並且調節反應室內的壓力之後，示例性原子層沉積過程120可以藉助於程序方塊220繼續進行迴圈沉積階段205，該程序方塊包括使基材與第一氣相反應物接觸，具體地講，在一些實施例中使基材與包括第一矽前體或鉬鹵化物前體中的至少一種的第一氣相反應物接觸。
在一些實施例中，成核膜可以包含矽二元化合物，並且在此類實施例中，第一氣相反應物可以包括第一矽前體。在一些實施例中，第一矽前體可以包括下列中的至少一種：N,N,N`,N-四乙基矽烷二胺(C8H22N2Si)、BTBAS(雙(叔丁基氨基)矽烷)、BDEAS(雙(二乙基氨基)矽烷)、TDMAS(三(二甲基氨基)矽烷)、六(乙基氨基)乙矽烷(Si2(NHC2H5)6)、四碘化矽(SiI4)、四氯化矽(SiCl4)、六氯乙矽烷(HCDS)或五氯乙矽烷(PCDS)。在一些實施例中，第 一矽前體可以包括矽烷，諸如矽烷(SiH4)、乙矽烷(Si2H6)、丙矽烷(Si3H8)、四矽烷(Si4H10)，或者具有一般經驗式SixH(2x+2)的更高級矽烷。
在一些實施例中，成核膜可以包含鉬二元化合物，並且在此類實施例中，第一氣相反應物可以包括鉬鹵化物前體。在一些實施例中，鉬鹵化物前體可以包括氯化鉬前體、碘化鉬前體或溴化鉬前體。例如，作為一個非限制性實例，第一氣相反應物可以包括氯化鉬，諸如五氯化鉬(MoCl5)。
在一些實施例中，鉬鹵化物前體可以包括鉬硫族化物，並且在多個具體實施例中，鉬鹵化物前體可以包括硫屬化物鹵化鉬。例如，硫屬化物鹵化鉬前體可以包括鉬鹵氧化物，該鉬鹵氧化物選自包括下列各項的組：氯氧化鉬、碘氧化鉬或溴氧化鉬。在本公開的多個具體實施例中，鉬前體可以包括氯氧化鉬，包括但不限於二氯二氧化鉬(IV)(MoO2Cl2)。
在本公開的一些實施例中，使基材與至少包含第一矽前體或鉬前體的第一氣相反應物接觸可以包括使第一氣相反應物與基材接觸介於約0.1秒與約60秒之間、介於約0.1秒與約10秒之間、或介於約0.5秒與約5.0秒之間的時間段。此外，在基材與第一氣相反應物接觸期間，前體的流量可以小於1000sccm、或小於500sccm、或小於100sccm、或小於10sccm、或甚至小於1sccm。此外，在基材與第一氣相反應物接觸期間，前體的流量可以在從約1sccm至2000sccm、從約5sccm至1000sccm、或從約10sccm至約500sccm的範圍內。
用於在介電表面上直接沉積成核膜的示例性原子層沉積過程如圖2的程序方塊120所展示，它可以通過吹掃反應室繼續進行。例如，可以從基材表面移除過量的第一氣相反應物和反應副產物(如果有的話)，例如通過用惰性氣體泵送。在本公開的一些實施例中，吹掃過程可以包括吹掃迴圈，其中吹掃基材表面的時間段小於大約5.0秒、或小於大約3.0秒、或甚至小於大約2.0秒。過量的第一氣相反應物(諸如過量的第一矽前體或鉬前體)和任何可能的反應 副產物可以藉助於由與反應室流體連通的泵送系統產生的真空移除。
在用吹掃迴圈吹掃反應室之後，示例性原子層沉積程序方塊120可以藉助於程序方塊230繼續進行迴圈沉積階段205的第二階段，該程序方塊包括使基材與第二氣相反應物接觸，具體地講，使基材與包括下列中的至少一種的第二氣相反應物接觸：氮前體、碳前體、氧前體或第二矽前體。
在本公開的一些實施例中，成核膜可以包含矽二元化合物材料，在多個具體實施例中包含氮化矽(例如，Si3N4)。在此類實施例中，第一氣相反應物可以包括第一矽前體，第二氣相反應物可以包括氮前體。
在本公開的一些實施例中，成核膜可以包含矽二元化合物材料，在多個具體實施例中包含氧化矽(例如，SiO2)。在此類實施例中，第一氣相反應物可以包括第一矽前體，第二氣相反應物可以包括氧前體。
在本公開的一些實施例中，成核膜可以包含矽二元化合物材料，在多個具體實施例中包含碳化矽(例如，SiC)。在此類實施例中，第一氣相反應物可以包括第一矽前體，第二氣相反應物可以包括碳前體。
在本公開的一些實施例中，成核膜可以包含鉬二元化合物材料，在多個具體實施例中包含氮化鉬。在此類實施例中，第一氣相反應物可以包括鉬前體，第二氣相反應物可以包括氮前體。
在本公開的一些實施例中，成核膜可以包含鉬二元化合物材料，在多個具體實施例中包含氧化鉬。在此類實施例中，第一氣相反應物可以包括鉬前體，第二氣相反應物可以包括氧前體。
在本公開的一些實施例中，成核膜可以包含鉬二元化合物材料，在多個具體實施例中包含矽化鉬。在此類實施例中，第一氣相反應物可以包括鉬前體，第二氣相反應物可以包括第二矽前體。
在本公開的一些實施例中，成核膜可以包含鉬二元化合物材料， 在多個具體實施例中包含碳化鉬。在此類實施例中，第一氣相反應物可以包括鉬前體，第二氣相反應物可以包括碳前體。
在其中成核膜包含氮化物(諸如氮化矽或氮化鉬)的多個實施例中，第二氣相反應物可以包括氮前體。在本公開的此類實施例中，氮前體可以包括下列中的至少一種：氨(NH3)、肼(N2H4)、三氮烷(N3H5)、叔丁基肼(C4H9N2H3)、甲基肼(CH3NHNH2)、二甲肼((CH3)2N2H2)或氮電漿，其中氮電漿包括原子氮、氮自由基和氫激發態物質。
在其中成核膜包含氧化物(諸如氧化矽或氧化鉬)的多個實施例中，第二氣相反應物可以包括氧前體。在本公開的此類實施例中，氧前體包括下列中的至少一種：水(H2O)、過氧化氫(H2O2)、臭氧(O3)或氮的氧化物，諸如一氧化氮(NO)、一氧化二氮(N2O)或二氧化氮(NO2)。在本公開的一些實施例中，氧前體可以包括有機醇，諸如異丙醇。在一些實施例中，氧前體可以包括氧電漿，其中氧電漿包括原子氧、氧自由基和氫激發態物質。
在其中成核膜包含碳化物(諸如碳化矽或碳化鉬)的多個實施例中，第二氣相反應物可以包括碳前體。在本公開的此類實施例中，碳前體可以包括烴，諸如直鏈或支鏈的烷烴。
在其中成核膜包含矽化物(諸如矽化鉬)的多個實施例中，第二氣相反應物可以包括第二矽前體。在本公開的此類實施例中，第二矽前體包括下列中的至少一種：N,N,N`,N-四乙基矽烷二胺(C8H22N2Si)、BTBAS(雙(叔丁基氨基)矽烷)、BDEAS(雙(二乙基氨基)矽烷)、TDMAS(三(二甲基氨基)矽烷)、六(乙基氨基)乙矽烷(Si2(NHC2H5)6)、四碘化矽(SiI4)、四氯化矽(SiCl4)、六氯乙矽烷(HCDS)或五氯乙矽烷(PCDS)。在一些實施例中，第二矽前體可以包括矽烷，諸如矽烷(SiH4)、乙矽烷(Si2H6)、丙矽烷(Si3H8)、四矽烷(Si4H10)，或者具有一般經驗式SixH(2x+2)的更高級矽烷。
在本公開的一些實施例中，使基材與第二氣相反應物接觸可以包括使基材與前體接觸介於約0.01秒與約120秒之間、介於約0.05秒與約60秒之間、或介於約0.1秒與約10秒之間的時間段。此外，在基材與第二氣相反應物接觸期間，第二氣相反應物的流量可以小於10000sccm、或小於5000X sccm、或甚至小於1000X。
在使基材與包括氮前體、碳前體、氧前體或第二矽前體中的至少一種的第二氣相反應物接觸之後，用於在介電表面上直接沉積成核膜的示例性程序方塊120可以通過吹掃反應室繼續進行。例如，可以從基材表面移除過量的第二氣相反應物和反應副產物(如果有的話)，例如通過在使惰性氣體流動的同時泵送。在本公開的一些實施例中，吹掃過程可以包括吹掃基材表面介於大約0.1秒與大約10秒之間、或介於大約0.5秒與大約3秒之間、或甚至介於大約1秒與2秒之間的時間段。
在將第二氣相反應物和任何反應副產物從反應室完全吹掃出去之後，程序方塊120的示例性原子層沉積的迴圈沉積階段205可以繼續進行決策閘240，其中決策閘240取決於所沉積的成核膜的厚度。例如，如果成核膜針對期望的元件應用沉積的厚度不足，則可以返回到程序方塊220並且繼續進行進一步的沉積迴圈，由此來重複迴圈沉積階段205，其中單位沉積迴圈可以包括：使基材至少與第一矽前體或鉬鹵化物前體接觸(程序方塊220)，吹掃反應室，使基材與氮前體、碳前體、氧前體或第二矽前體中的至少一種接觸(程序方塊230)，然後再次吹掃反應室。迴圈沉積階段205的單位沉積迴圈可以重複一次或多次，直到期望厚度的成核膜沉積在基材上，特別是直接沉積在介電表面上為止。一旦成核膜已經沉積到期望的厚度，示例性原子層沉積程序方塊120就可以經由程序方塊250退出，介電表面上沉積有成核膜的基材可以經受圖1的示例性過程100的進一步處理。
應當理解，在本公開的一些實施例中，基材與第一氣相反應物(例如，第一矽前體或鉬前體)和第二氣相反應物(例如，氮前體、碳前體、氧前體或第二矽前體)接觸的次序可以使得基材首先與第二氣相反應物接觸，之後再與第一氣相反應物接觸。此外，在一些實施例中，示例性程序方塊120的迴圈沉積階段205可以包括先使基材與第一氣相反應物接觸一次或多次，然後才使基材與第二氣相反應物接觸一次或多次。此外，在一些實施例中，示例性程序方塊120的迴圈沉積階段205可以包括先使基材與第二氣相反應物接觸一次或多次，然後才使基材與第一氣相反應物接觸一次或多次。
在一些實施例中，迴圈沉積過程可以是混合式ALD/CVD或迴圈CVD過程。例如，在一些實施例中，相比於CVD過程，ALD過程的生長速率可能較低。增大生長速率的一個方法可以是相比於通常在ALD過程中所採用的溫度在更高的基材溫度下操作，從而引起化學氣相沉積過程的一部分，但仍利用了對前體的依序引入，這樣的過程可以稱為迴圈CVD。在一些實施例中，迴圈CVD過程可以包括將兩種或更多種前體引入到反應室中，其中兩種或更多種前體可以在一個時間段內同時存在於反應室中，從而既引起沉積的ALD部分，又引起沉積的CVD部分。例如，迴圈CVD過程可以包括一種前體連續流入反應室，第二種前體週期性地脈衝進入反應室。
在本公開的一些實施例中，成核膜可以以從約0.05埃/週期至約5埃/週期、從約0.1埃/週期至約5埃/週期、或甚至從約0.5埃/週期至約1.5埃/週期的生長速率直接沉積在介電表面上。
在本公開的一些實施例中，成核膜被沉積為連續膜，參見例如半導體元件結構405，該結構包括直接設置在具有垂直間隙特徵404的介電基材402上的連續成核膜406，如圖4B所展示；或者參見例如半導體元件結構505，該結構包括直接設置在具有水平間隙特徵的介電基材502上的連續成核膜506，如圖 5B所展示。在一些實施例中，可以將連續成核膜406/506沉積至小於20埃、或小於10埃、或小於5埃、或甚至小於3埃的厚度。
在本公開的一些實施例中，成核膜被沉積為不連續膜，參見例如半導體元件結構405的插圖408，該結構包括直接設置在具有垂直間隙特徵404的介電基材402上的不連續成核膜406`的一個實例，如圖4B所展示；或者參見例如半導體元件結構505的插圖508，該結構包括直接設置在具有水平間隙特徵的介電基材502上的不連續成核膜506`的一個實例，如圖5B所展示。在一些實施例中，可以將不連續成核膜406`/506`沉積至小於20埃、或小於10埃、或小於5埃、或甚至小於3埃的厚度。
在一些實施例中，成核膜在一個或多個介電間隙特徵上的階梯覆蓋率可以等於或大於約50%、或大於約80%、或大於約90%、或大於約95%、或大於約98%、或為約99%或更大。
還應當指出，本公開的成核膜並不構成常用於半導體元件應用中以防止金屬物質擴散到下面的介電材料中的阻擋層或阻擋材料，該阻擋層是設置在金屬觸點與介電材料之間的。本公開的成核膜用於改善隨後沉積的鉬金屬膜的材料品質，並且不構成在普通的半導體元件製造過程中利用的厚膜、高電阻率阻擋層或阻擋材料。
當在介電表面上直接沉積成核膜之後，(圖1的)示例性過程100可以藉助於程序方塊130繼續進行，該程序方塊包括在成核膜上直接沉積鉬金屬膜，並且在一些特定實施例中通過迴圈沉積過程在成核膜上直接沉積鉬金屬膜。參照圖3更詳細地描述了程序方塊130和相關聯的構成該程序方塊的子程序方塊，該圖展示了用於沉積鉬金屬膜的示例性迴圈沉積過程。
更詳細地講，示例性迴圈沉積過程可以包括原子層沉積過程或迴圈化學氣相沉積過程。作為一個非限制性實例，程序方塊130可以包括原子層沉 積過程，並且可以藉助於子程序方塊310開始，該子程序方塊包括將基材加熱到期望的沉積溫度。例如，可以將基材加熱到低於大約800℃、或低於大約700℃、或低於大約600℃、或低於大約5500℃、或低於大約500℃、或低於大約400℃、或低於大約300℃、或甚至低於大約200℃的基材溫度。在本公開的一些實施例中，示例性原子層沉積程序方塊130期間的基材溫度可以介於200℃與800℃之間、或介於300℃與700℃之間、或介於400℃與600℃之間、或介於500℃與550℃之間。
此外，為了實現期望的沉積溫度(即，期望的基材溫度)，示例性原子層沉積過程130還可以在沉積期間調節反應室內的壓力，以便獲得所沉積的鉬金屬膜的理想特性。例如，在本公開的一些實施例中，示例性原子層沉積過程130可以在被調節到反應室壓力小於300托、或小於200托、或小於100托、或小於50托、或小於25托、或甚至小於10托的反應室內執行。在一些實施例中，沉積期間反應室內的壓力可以在介於10托與300托之間、或介於30托與80托之間、或者甚至等於或大於30托的壓力下調節。
在將基材加熱到期望的沉積溫度並且調節反應室內的壓力之後，示例性原子層沉積過程130可以藉助於程序方塊320繼續進行迴圈沉積階段305，該程序方塊包括使基材與第一氣相反應物接觸，具體地講，在一些實施例中使基材與包括鉬鹵化物前體(即，鉬前體)的第一氣相反應物接觸。
在本公開的一些實施例中，鉬鹵化物前體可以包括氯化鉬前體、碘化鉬前體或溴化鉬前體。例如，作為一個非限制性實例，第一氣相反應物可以包括氯化鉬，諸如五氯化鉬(MoCl5)。
在一些實施例中，鉬鹵化物前體可以包括鉬硫族化物，並且在多個特定實施例中，鉬鹵化物前體可以包括硫屬化物鹵化鉬。例如，硫屬化物鹵化鉬前體可以包括鉬鹵氧化物，該鉬鹵氧化物選自包括下列各項的組：氯氧化 鉬、碘氧化鉬或溴氧化鉬。在本公開的多個特定實施例中，鉬前體可以包括氯氧化鉬，包括但不限於二氯二氧化鉬(IV)(MoO2Cl2)。
在本公開的一些實施例中，使基材與包含鉬鹵化物前體的第一氣相反應物接觸可以包括使鉬鹵化物前體與基材接觸介於約0.1秒與約60秒之間、介於約0.1秒與約10秒之間、或介於約0.5秒與約5.0秒之間的時間段。此外，在基材與鉬鹵化物前體接觸期間，鉬鹵化物前體的流量可以小於1000sccm、或小於500sccm、或小於100sccm、或小於10sccm、或甚至小於1sccm。此外，在基材與鉬鹵化物前體接觸期間，鉬前體的流量可以在從約1sccm至2000sccm、從約5sccm至1000sccm、或從約10sccm至約500sccm的範圍內。
用於在成核膜上直接沉積鉬金屬膜的示例性原子層沉積過程130如圖3的程序方塊130所展示，它可以通過吹掃反應室繼續進行。例如，可以從基材表面移除過量的第一氣相反應物和反應副產物(如果有的話)，例如通過用惰性氣體泵送。在本公開的一些實施例中，吹掃過程可以包括吹掃迴圈，其中吹掃基材表面的時間段小於大約5.0秒、或小於大約3.0秒、或甚至小於大約2.0秒。過量的第一氣相反應物(諸如過量的鉬前體)和任何可能的反應副產物可以藉助於由與反應室流體連通的泵送系統產生的真空移除。
在用吹掃迴圈吹掃反應室之後，示例性原子層沉積程序方塊130可以藉助於程序方塊330繼續進行迴圈沉積階段305的第二階段，該程序方塊包括使基材與第二氣相反應物接觸，具體地講，使基材與包含還原劑前體(「還原前體」)的第二氣相反應物接觸。
在本公開的一些實施例中，還原劑前體可以包括下列中的至少一種：合成氣體(H2+N2)、氨(NH3)、肼(N2H4)、烷基肼(例如，叔丁基肼(C4H12N2))、分子氫(H2)、氫原子(H)、氫電漿、氫自由基、氫激發態物質、醇、醛、羧酸、硼烷或胺。在另外的實施例中，還原劑前體可以包括下列中的 至少一種：矽烷(SiH4)、乙矽烷(Si2H6)、丙矽烷(Si3H8)、鍺烷(GeH4)、乙鍺烷(Ge2H6)、硼烷(BH3)或乙硼烷(B2H6)。在本公開的多個特定實施例中，還原劑前體可以包括分子氫(H2)。
在本公開的一些實施例中，使基材與還原劑前體接觸可以包括使基材與還原劑前體接觸介於約0.01秒與約180秒之間、介於約0.05秒與約60秒之間、或介於約0.1秒與約10.0秒之間的時間段。此外，在基材與還原劑前體基材接觸期間，還原劑前體的流量可以小於30slm、或小於15slm、或小於10slm、或小於5slm、或小於1slm、或甚至小於0.1slm。此外，在基材與還原劑前體接觸期間，還原劑前體的流量可以在從約0.1slm至30slm、從約5slm至15slm、或者等於或大於10slm的範圍內。
在使基材與還原劑前體接觸之後，用於在成核膜上直接沉積鉬金屬膜的示例性程序方塊130可以通過吹掃反應室繼續進行。例如，可以從基材表面移除過量的還原劑前體和反應副產物(如果有的話)，例如通過在使惰性氣體流動的同時泵送。在本公開的一些實施例中，吹掃過程可以包括吹掃基材表面介於大約0.1秒與大約10秒之間、或介於大約0.5秒與大約3秒之間、或甚至介於大約1秒與2秒之間的時間段。
在將第二氣相反應物即還原劑前體(和任何反應副產物)從反應室完全吹掃出去之後，示例性原子層沉積程序方塊130的迴圈沉積階段305可以繼續進行決策閘340，其中決策閘340取決於所沉積的鉬金屬膜的厚度。例如，如果鉬金屬膜針對期望的元件應用沉積的厚度不足，則可以返回到程序方塊320並且繼續進行進一步的沉積迴圈，由此來重複迴圈沉積階段305，其中單位沉積迴圈可以包括：使基材與鉬鹵化物前體接觸(程序方塊320)，吹掃反應室，使基材與還原劑前體接觸(程序方塊330)，然後再次吹掃反應室。迴圈沉積階段305的單位沉積迴圈可以重複一次或多次，直到期望厚度的鉬金屬膜沉積在基材 上，特別是直接沉積在成核膜上為止。一旦鉬金屬膜已經沉積到期望的厚度，示例性原子層沉積程序方塊130就可以經由程序方塊350退出，介電表面上沉積有鉬金屬膜的基材可以經受進一步處理，以形成元件結構。例如，圖1的示例性過程100可以繼續進行到程序方塊140，其中該過程退出，並且其上設置有鉬金屬膜的基材可以經受進一步的半導體處理，以完成半導體元件結構。
應當理解，在本公開的一些實施例中，基材與第一氣相反應物(例如，鉬前體)和第二氣相反應物(例如，還原前體)接觸的次序可以使得基材首先與第二氣相反應物接觸，之後再與第一氣相反應物接觸。此外，在一些實施例中，示例性程序方塊130的迴圈沉積階段305可以包括先使基材與第一氣相反應物接觸一次或多次，然後才使基材與第二氣相反應物接觸一次或多次。此外，在一些實施例中，示例性程序方塊130的迴圈沉積階段305可以包括先使基材與第二氣相反應物接觸一次或多次，然後才使基材與第一氣相反應物接觸一次或多次。
在一些實施例中，用於在成核膜上直接沉積鉬金屬膜的迴圈沉積過程可以是如本文先前所述的混合式ALD/CVD或迴圈CVD過程。
通過本文公開的方法沉積的鉬金屬膜可以是連續膜。在一些實施例中，鉬金屬膜連續的厚度可以低於大約100埃、或低於大約60埃、或低於大約50埃、或低於大約40埃、或低於大約30埃、或低於大約20埃、或低於大約10埃、或甚至低於大約5埃。本文中提到的連續性可以是物理連續性或電氣連續性。在本公開的一些實施例中，材料膜可以物理連續的厚度可以與該膜電連續的厚度不同，反之亦然。
在本公開的一些實施例中，根據本公開的多個實施例形成的鉬金屬膜可以具有從約20埃至約250埃、或約50埃至約200埃、或甚至約100埃至約150埃的厚度。在一些實施例中，根據本文所述的一些實施例沉積的鉬金屬膜可以 具有大於約20埃、或大於約30埃、或大於約40埃、或大於約50埃、或大於約60埃、或大於約100埃、或大於約250埃、或大於約500埃、或者更大的厚度。在一些實施例中，根據本文所述的一些實施例沉積的鉬金屬膜可以具有小於約250埃、或小於約100埃、或小於約50埃、或小於約25埃、或小於約10埃、或甚至小於約5埃的厚度。在一些實施例中，利用中間的成核膜設置在介電表面上的鉬金屬膜可以具有介於大約100埃與250埃之間的厚度。
在本公開的一些實施例中，可以利用中間的成核膜在介電表面上沉積鉬金屬膜，使得該鉬金屬膜可以包括結晶膜。在一些實施例中，鉬金屬膜可以包括多晶膜，其中構成該多晶鉬金屬膜的多個晶粒可以具有大於100埃、或大於200埃、或甚至大於250埃的晶粒尺寸。在一些實施例中，該結晶鉬金屬膜的結晶結構可以包括體心的立方結構。
在本公開的一些實施例中，鉬金屬膜可以沉積在具有一個或多個高縱橫比特徵的介電表面上，該一個或多個高縱橫比特徵包括垂直高縱橫比特徵和/或水平高縱橫比特徵。
例如，圖4C展示了半導體元件結構410，該結構包括具有垂直高縱橫比特徵404的介電材料402，其中縱橫比(高度：寬度)可以大於2：1、或大於5：1、或大於10：1、或大於25：1、或大於50：1、或甚至大於100：1，其中在該具體實例中，「大於」是指間隙特徵的較大高度。本文公開的沉積方法可以用於在垂直高縱橫比間隙特徵404的表面上沉積鉬金屬膜，如鉬金屬膜412所展示。在一些實施例中，鉬金屬膜在垂直高縱橫比介電間隙特徵上的階梯覆蓋率可以等於或大於約50%、或大於約80%、或大於約90%、或大於約95%、或大於約98%、或為約99%或更大。
作為一個非限制性實例，半導體元件結構410可以表示部分製成的CMOS邏輯元件，其中介電材料402可以包括層間介電質，並且鉬金屬膜412 可以包括金屬間隙填充，用於提供與一個或多個電晶體結構(未示出)的電連接。如圖4A所展示，鉬金屬膜406與成核膜404直接接觸，該成核膜又直接設置在介電材料402上(即不需要中間的阻擋層材料)，從而降低了半導體元件結構410的整體有效電阻率。
在一些實施例中，鉬金屬膜412可以包括間隙填充金屬化，並且鉬金屬膜412可以在不形成接縫的情況下填充間隙特徵(即垂直高縱橫比間隙特徵404)，其中接縫可以指代由於鄰接間隙填充金屬中所形成的邊緣而形成的一條線或者一個或多個空隙，並且接縫可以使用掃描穿透式電子顯微鏡(STEM)或穿透式電子顯微鏡(TEM)證實，其中，如果觀察結果揭示間隙填充材料中存在清晰的垂直線或者一個或多個垂直空隙，則稱存在接縫。
作為一個另外的非限制性實例，圖5C展示了半導體元件結構510，該結構包括具有一個或多個水平高縱橫比間隙特徵504的介電材料502，其中縱橫比(高度：寬度)可以大於1：2、或大於1：5、或大於1：10、或大於1：25、或大於1：50、或甚至大於1：100，其中在該實例中，術語「大於」是指一個或多個間隙特徵的較大寬度。本文公開的沉積方法可以用於利用中間的成核膜506在水平高縱橫比間隙特徵504的表面上沉積鉬金屬膜512。在一些實施例中，設置在水平高縱橫比介電間隙特徵上的鉬金屬膜的階梯覆蓋率可以等於或大於約50%、或大於約80%、或大於約90%、或大於約95%、或大於約98%、或為約99%或更大。
作為一個非限制性示例實施例，半導體元件結構510可以表示部分製成的記憶體元件的一部分，其中介電材料502可以包括氧化鋁(Al2O3)，並且鉬金屬膜512可以構成金屬柵極結構的至少一部分。
與垂直間隙填充過程一樣，(圖5C的)鉬金屬膜512可以在不形成接縫的情況下用作水平高縱橫比特徵的間隙填充金屬化，如前所述。
在本公開的一些實施例中，在直接設置於介電表面上的成核膜上直接沉積的鉬金屬膜可以包括低電阻率的鉬金屬膜。在一些實施例中，利用中間的成核膜沉積在介電表面上的鉬金屬膜可以具有比直接沉積在介電表面上(即不使用任何中間的成核膜)的鉬膜更低的電阻率。例如，在一些實施例中，本公開的鉬金屬膜可以具有小於3000μΩ-cm、或小於1000μΩ-cm、或小於500μΩ-cm、或小於200μΩ-cm、或小於100μΩ-cm、或小於50μΩ-cm、或小於25μΩ-cm、或小於15μΩ-cm、或甚至小於10μΩ-cm的電阻率。作為一個非限制性實例，可以利用中間的成核膜在介電材料的表面上沉積鉬金屬膜，將其沉積到大約小於60埃的鉬金屬膜厚度，並且該鉬金屬膜可以表現出小於40μΩ-cm、或小於35μΩ-cm、或甚至小於30μΩ-cm的電阻率。
除了改善鉬金屬膜的電阻率之外，沉積中間的成核膜還可以改善所沉積的鉬金屬膜的表面粗糙度。例如，圖6展示了兩個示例性的60埃厚鉬金屬膜的r.m.s.表面粗糙度(Ra)(以埃為單位)。由標籤600表示的鉬金屬膜直接沉積在氧化鋁(Al2O3)介電表面上，並且具有大約7.3埃的對應r.m.s.表面粗糙度(Ra)。由標籤602表示的鉬金屬膜在直接設置於氧化鋁(Al2O3)介電表面上的4埃厚氮化矽成核膜上直接沉積，並且具有大約3.3埃的對應r.m.s.表面粗糙度(Ra)。應當指出，鉬金屬膜的r.m.s.表面粗糙度(Ra)可以利用原子力顯微鏡(例如，在1微米×1微米的表面積上)測定。
因此，使用中間的成核膜極大地改善了鉬金屬膜的表面粗糙度，例如，在一些實施例中，利用中間的成核膜沉積在介電表面上的鉬金屬膜的r.m.s.表面粗糙度可以具有小於5埃、或小於4埃、或小於3埃、或甚至小於2埃的r.m.s.表面粗糙度(Ra)。在一些實施例中，r.m.s.表面粗糙度(Ra)可以表示為粗糙度在總膜厚度中所占的百分比。例如，在一些實施例中，r.m.s.表面粗糙度(Ra)可以小於鉬金屬膜總厚度的10%、或5%、或3%、或甚至1%。
在本公開的一些實施例中，利用中間的成核膜在介電表面上沉積鉬金屬膜的方法還可以包括沉積雜質原子百分比(原子%)低的鉬金屬膜。例如，本公開的鉬金屬膜可以具有小於5原子%、或小於2原子%、或甚至小於1原子%的雜質濃度。在一些實施例中，設置在鉬金屬膜內的雜質可以至少包括氧和氯。
本公開的多個實施例還可以提供包括鉬金屬膜的半導體元件結構。在一些實施例中，這些半導體元件結構可以包括：包括介電表面的基材；直接設置在介電表面上的成核膜；以及直接設置在成核膜上的鉬金屬膜。作為非限制性實例，(圖4C的)半導體元件結構410和(圖5C的)半導體元件結構510包括介電基材402/502，該介電基材包括介電表面。成核膜406/506直接設置在介電基材402上，鉬金屬膜412/512又直接設置在成核膜406/506上。因此，在一些實施例中，成核膜406/506直接設置在鉬金屬膜412/512與介電材料402/502之間。
在一些實施例中，成核膜406/506可以包括連續膜，而在替代性實施例中，成核膜406`/506`可以包括不連續膜。在一些實施例中，連續成核膜406/506可以具有小於20埃、或小於10埃、或小於5埃、或甚至小於3埃的厚度。在一些實施例中，不連續成核膜406`/506`可以具有小於20埃、或小於10埃、或小於5埃、或甚至小於3埃的厚度。
在一些實施例中，成核膜406/506可以包含化合物材料，並且在多個特定實施例中，成核膜406/506可以包含二元化合物材料，諸如矽二元化合物材料或鉬二元化合物材料。在一些實施例中，成核膜406/506可以包含三元化合物材料，諸如矽三元材料或鉬三元材料。
作為非限制性實例，矽二元化合物材料可以包括氮化矽、碳化矽或氧化矽中的至少一種。作為另外的非限制性實例，鉬二元化合物材料可以包括氮化鉬、碳化鉬、氧化鉬或矽化鉬中的至少一種。
在一些實施例中，鉬金屬膜412/512可以是結晶的，並且具有小 於5原子%、或小於2原子%、或甚至小於1原子%的雜質濃度。此外，鉬金屬膜412/512在小於60埃的厚度下可以具有小於40μΩ-cm的電阻率。
在一些實施例中，鉬金屬膜412/512可以具有小於5埃、或小於4埃、或小於3埃、或甚至小於2埃的r.m.s.表面粗糙度(Ra)。在一些實施例中，r.m.s.表面粗糙度(Ra)可以表示為粗糙度在總膜厚度中所占的百分比。例如，在一些實施例中，r.m.s.表面粗糙度(Ra)可以小於鉬金屬膜總厚度的10%、或5%、或3%、或甚至1%。鉬金屬膜412/512的低表面粗糙度可以使鉬金屬膜能夠在不形成接縫的情況下填充設置在基材中和/或基材上的一個或多個間隙特徵，諸如垂直間隙特徵404和/或水平間隙特徵504，如鉬金屬膜412和512所展示。
上文所描述的本公開的示例實施例不限制本發明的範圍，這是因為這些實施例僅僅是本發明實施例的實例，本發明由所附權利要求書和其合法等效物界定。任何等效實施例都意欲在本發明的範圍內。實際上，除本文中所展示和描述的如所描述元件的替代適用組合的內容以外，對於所屬領域的技術人員來說，本公開的各種修改將從描述變得顯而易見。此類修改和實施例也意欲落在所附權利要求書的範圍內。
100‧‧‧過程
110‧‧‧把包括介電表面的基材放到反應室中
120‧‧‧在介電表面上直接沉積成核膜
130‧‧‧在成核膜上直接沉積鉬金屬膜
140‧‧‧退出

Claims (38)

  1. 一種通過迴圈沉積過程在基材的介電表面上沉積鉬金屬膜的方法，該方法包括：把包括介電表面的基材放到反應室中；在該介電表面上直接沉積成核膜；以及在該成核膜上直接沉積鉬金屬膜，其中沉積該鉬金屬膜包括：使該基材與包含鉬鹵化物前體的第一氣相反應物接觸；及使該基材與包含還原劑前體的第二氣相反應物接觸，其中該成核膜的厚度小於20埃。
  2. 如請求項1所述的方法，其中該成核膜是不連續膜。
  3. 如請求項1所述的方法，其中該成核膜是連續膜。
  4. 如請求項1所述的方法，其中該成核膜包含化合物材料。
  5. 如請求項4所述的方法，其中該化合物材料包括二元化合物材料。
  6. 如請求項5所述的方法，其中該二元化合物材料包括矽二元化合物材料。
  7. 如請求項5所述的方法，其中該二元化合物材料包括鉬二元化合物材料。
  8. 如請求項7所述的方法，其中該鉬二元化合物材料包括氮化鉬、碳化鉬、氧化鉬或矽化鉬中的至少一種。
  9. 如請求項1所述的方法，其中沉積該成核膜還包括將基材加熱到低於600℃的基材溫度。
  10. 如請求項1所述的方法，其中沉積該成核膜還包括執行迴圈沉積過程的至少一個單位迴圈，其中單位迴圈包括：使基材與第一氣相反應物接觸，該第一氣相反應物包括第一矽前體或鉬前 體中的至少一種；以及使基材與第二氣相反應物接觸，該第二氣相反應物包括氮前體、氧前體或第二矽前體中的至少一種。
  11. 如請求項1所述的方法，其中沉積該鉬金屬膜還包括將基材加熱到介於400℃與700℃之間的基材溫度。
  12. 如請求項1所述的方法，其中沉積該鉬金屬膜還包括在沉積期間將反應室內的壓力調節到大於30托。
  13. 如請求項1所述的方法，其中該鉬鹵化物包括硫屬化物鹵化鉬。
  14. 如請求項13所述的方法，其中該硫屬化物鹵化鉬包括鉬鹵氧化物，該鉬鹵氧化物選自包括下列各項的組：氯氧化鉬、碘氧化鉬或溴氧化鉬。
  15. 如請求項14所述的方法，其中該氯氧化鉬包括二氯二氧化鉬(IV)(MoO2Cl2)。
  16. 如請求項1所述的方法，其中該還原劑前體包括下列中的至少一種：分子氫(H2)、原子氫(H)、合成氣體(H2+N2)、氨(NH3)、肼(N2H4)、肼衍生物、氫基電漿、氫自由基、氫激發態物質、醇、醛、羧酸、硼烷、胺或矽烷。
  17. 如請求項1所述的方法，其中該鉬金屬膜是結晶膜。
  18. 如請求項1所述的方法，其中該鉬金屬膜具有小於2原子%的雜質濃度。
  19. 如請求項1所述的方法，其中該鉬金屬膜以大於90%的階梯覆蓋率沉積。
  20. 如請求項1所述的方法，其中該鉬金屬膜具有小於該鉬金屬膜的總厚度的5%的r.m.s.表面粗糙度(Ra)。
  21. 如請求項1所述的方法，其中該介電表面包括間隙特徵，並且該 鉬金屬膜在不形成接縫的情況下填充該間隙特徵。
  22. 一種通過迴圈沉積過程在基材的介電表面上沉積鉬金屬膜的方法，該方法包括：把包括介電表面的基材放到反應室中；在該介電表面上直接沉積成核膜；以及在該成核膜上直接沉積鉬金屬膜，其中沉積該鉬金屬膜包括：使該基材與包含鉬鹵化物前體的第一氣相反應物接觸；及使該基材與包含還原劑前體的第二氣相反應物接觸，其中該成核膜包含化合物材料，其中該化合物材料包括二元化合物材料，其中該二元化合物材料包括矽二元化合物材料，且其中該矽二元化合物材料包括氮化矽、碳化矽或氧化矽中的至少一種。
  23. 一種通過迴圈沉積過程在基材的介電表面上沉積鉬金屬膜的方法，該方法包括：把包括介電表面的基材放到反應室中；在該介電表面上直接沉積成核膜；以及在該成核膜上直接沉積鉬金屬膜，其中沉積該鉬金屬膜包括：使該基材與包含鉬鹵化物前體的第一氣相反應物接觸；及使該基材與包含還原劑前體的第二氣相反應物接觸，其中沉積該成核膜還包括將反應室內的壓力調節到大於15托的壓力。
  24. 一種通過迴圈沉積過程在基材的介電表面上沉積鉬金屬膜的方法，該方法包括：把包括介電表面的基材放到反應室中；在該介電表面上直接沉積成核膜；以及在該成核膜上直接沉積鉬金屬膜，其中沉積該鉬金屬膜包括： 使該基材與包含鉬鹵化物前體的第一氣相反應物接觸；及使該基材與包含還原劑前體的第二氣相反應物接觸，其中該鉬金屬膜在小於60埃的厚度下具有小於40μΩ-cm的電阻率。
  25. 一種半導體元件結構，包括：包括介電表面的基材；直接設置在該介電表面上的成核膜；以及直接設置在該成核膜上的鉬金屬膜，其中該成核膜的厚度小於20埃。
  26. 如請求項25所述的結構，其中該成核膜是不連續膜。
  27. 如請求項25所述的結構，其中該成核膜是連續膜。
  28. 如請求項25所述的結構，其中該成核膜包含化合物材料。
  29. 如請求項28所述的結構，其中該化合物材料包括二元化合物材料。
  30. 如請求項29所述的結構，其中該二元化合物材料包括矽二元化合物材料。
  31. 如請求項29所述的結構，其中該二元化合物材料包括鉬二元化合物材料。
  32. 如請求項31所述的結構，其中該鉬二元化合物材料包括氮化鉬、碳化鉬、氧化鉬或矽化鉬中的至少一種。
  33. 如請求項25所述的結構，其中該鉬金屬膜是結晶膜。
  34. 如請求項25所述的結構，其中該鉬金屬膜具有小於2原子%的雜質濃度。
  35. 如請求項25所述的結構，其中該鉬金屬膜具有小於該鉬金屬膜的總厚度的5%的r.m.s.表面粗糙度(Ra)。
  36. 如請求項25所述的結構，其中該介電表面包括間隙特徵，並且該鉬金屬膜在不形成接縫的情況下填充該間隙特徵。
  37. 一種半導體元件結構，包括：包括介電表面的基材；直接設置在該介電表面上的成核膜；以及直接設置在該成核膜上的鉬金屬膜，其中該成核膜包含化合物材料，其中該化合物材料包括二元化合物材料，其中該二元化合物材料包括矽二元化合物材料，且其中該矽二元化合物材料包括氮化矽、碳化矽或氧化矽中的至少一種。
  38. 一種半導體元件結構，包括：包括介電表面的基材；直接設置在該介電表面上的成核膜；以及直接設置在該成核膜上的鉬金屬膜，其中該鉬膜在小於60埃的厚度下具有小於40μΩ-cm的電阻率。
TW107129471A 2017-08-30 2018-08-23 通過迴圈沉積過程在基材的介電表面上沉積鉬金屬膜的方法和相關的半導體元件結構 TWI794275B (zh)

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