JP4589984B2 - 微細パターンの形成方法 - Google Patents
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- JP4589984B2 JP4589984B2 JP2008149271A JP2008149271A JP4589984B2 JP 4589984 B2 JP4589984 B2 JP 4589984B2 JP 2008149271 A JP2008149271 A JP 2008149271A JP 2008149271 A JP2008149271 A JP 2008149271A JP 4589984 B2 JP4589984 B2 JP 4589984B2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02219—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
Description
図1乃至図6は、この発明の第1の実施形態に係る微細パターンの形成方法を主要な製造工程毎に示す断面図である。
図12乃至図18は、この発明の第2の実施形態に係る微細パターンの形成方法を主要な製造工程毎に示す断面図である。
図19乃至図24は、この発明の第3の実施形態に係る微細パターンの形成方法を主要な製造工程毎に示す断面図である。
また、エトキシシランガス、及びアミノシランガスとしては、上記実施形態に示したものに限らない。また、活性化された酸素種として種々の酸素含有ガスプラズマを例示したが、これに限らず、ラジカル化している酸素を含むものであれば適用可能である。
102;薄膜
103;フォトレジスト膜
103´;レジストパターン
105;シリコン酸化膜
105´;側壁スペーサ
106;エッチングストッパ膜
107;ハードマスク膜
Claims (14)
- 基板上に、薄膜を形成する工程と、
前記薄膜上に、レジスト膜を最上層に設けた多層膜を形成する工程と、
前記多層膜を、フォトリソグラフィ技術を用いて、所定の間隔を持つパターンに加工する工程と、
有機シリコンを含むソースガスと活性化された酸素種とを交互に供給し、前記加工された多層膜、及び前記薄膜上に、前記薄膜及び前記多層膜とは異なったシリコン酸化膜を形成する工程と、
前記シリコン酸化膜を後退させ、前記加工された多層膜の側壁上に側壁スペーサを形成する工程と、
前記加工された多層膜を除去する工程と、
前記側壁スペーサをマスクに用いて、前記薄膜を加工する工程と、
を具備することを特徴とする微細パターンの形成方法。 - 基板上に、第1の薄膜を形成する工程と、
前記第1の薄膜上に、この第1の薄膜とは異なる膜からなる第2の薄膜を形成する工程と、
前記第2の薄膜上に、この第2の薄膜とは異なる膜からなるハードマスク膜を形成する工程と、
前記ハードマスク膜上に、レジスト膜を最上層に設けた多層膜を形成する工程と、
前記多層膜を、フォトリソグラフィ技術を用いて、所定の間隔を持つパターンに加工する工程と、
有機シリコンを含むソースガスと活性化された酸素種とを交互に供給し、前記加工された多層膜、及び前記ハードマスク膜上に、前記ハードマスク膜及び前記多層膜とは異なるシリコン酸化膜を形成する工程と、
前記シリコン酸化膜を後退させ、前記加工された多層膜の側壁上に側壁スペーサを形成する工程と、
前記加工された多層膜を除去する工程と、
前記側壁スペーサをマスクに用いて、前記ハードマスク膜を加工する工程と、
前記ハードマスク膜をマスクに用いて、前記第2の薄膜を加工する工程と、
を具備することを特徴とする微細パターンの形成方法。 - 前記第1の薄膜は、エッチングストッパ膜であることを特徴とする請求項2に記載の微細パターンの形成方法。
- 前記多層膜を、フォトリソグラフィ技術を用いて、所定の間隔を持つパターンに加工した後、前記加工された多層膜をトリミングし、前記加工された多層膜を微細化する工程を、さらに具備することを特徴とする請求項1乃至請求項3いずれか一項に記載の微細パターンの形成方法。
- 前記ソースガスとして、アミノシラン系プリカーサーを用いることを特徴とする請求項1乃至請求項4いずれか一項に記載の微細パターンの形成方法。
- 前記アミノシラン系プリカーサーは、1価または2価のアミノシラン系プリカーサーであることを特徴とする請求項5に記載の微細パターンの形成方法。
- 前記1価または2価のアミノシラン系プリカーサーは、
BTBAS(ビスターシャリブチルアミノシラン)、
BDMAS(ビスジメチルアミノシラン)、
BDEAS(ビスジエチルアミノシラン)、
DMAS(ジメチルアミノシラン)、
DEAS(ジエチルアミノシラン)、
DPAS(ジプロピルアミノシラン)、
BAS(ブチルアミノシラン)、
DIPAS(ジイソプロピルアミノシラン)、
BEMAS(ビスエチルメチルアミノシラン)、
から選択された少なくとも1種を用いることを特徴とする請求項6に記載の微細パターンの形成方法。 - 前記活性化された酸素種として、プラズマにより励起された酸素ラジカルを用いることを特徴とする請求項1乃至請求項7いずれか一項に記載の微細パターンの形成方法。
- 前記プラズマにより励起された酸素ラジカルは、O2ガス、NOガス、N2Oガス、H2Oガス、O3ガスのいずれかから選択される少なくとも1種をプラズマ化して得ることを特徴とする請求項8に記載の微細パターンの形成方法。
- 前記シリコン酸化膜は真空保持可能な処理容器内で形成され、前記ソースガスを前記処理容器内へ供給する工程と、前記活性化された酸素種を前記処理容器内へ供給する工程とを交互に実施して形成することを特徴とする請求項1乃至請求項9いずれか一項に記載の微細パターンの形成方法。
- 前記ソースガスを前記処理容器内へ供給する工程と、前記活性化された酸素種を前記処理容器内へ供給する工程との間に、前記処理容器内に残留しているガスを除去する工程を挿入することを特徴とする請求項10に記載の微細パターンの形成方法。
- 前記処理容器内に残留しているガスを除去する工程は、前記処理容器内を真空引きしながら前記処理容器内にパージガスを導入することを特徴とする請求項11に記載の微細パターンの形成方法。
- 前記シリコン酸化膜を形成する際の成膜温度が前記多層膜の耐熱温度以下であることを特徴とする請求項1乃至請求項12いずれか一項に記載の微細パターンの形成方法。
- 前記成膜温度は100℃以下であることを特徴とする請求項13に記載の微細パターンの形成方法。
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JP2008149271A JP4589984B2 (ja) | 2007-06-08 | 2008-06-06 | 微細パターンの形成方法 |
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JP2007153185 | 2007-06-08 | ||
JP2008149271A JP4589984B2 (ja) | 2007-06-08 | 2008-06-06 | 微細パターンの形成方法 |
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JP2009016814A JP2009016814A (ja) | 2009-01-22 |
JP4589984B2 true JP4589984B2 (ja) | 2010-12-01 |
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US (1) | US8168375B2 (ja) |
JP (1) | JP4589984B2 (ja) |
KR (1) | KR101011490B1 (ja) |
TW (1) | TW200913010A (ja) |
WO (1) | WO2008149989A1 (ja) |
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KR20090051186A (ko) | 2009-05-21 |
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US8168375B2 (en) | 2012-05-01 |
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US20100112496A1 (en) | 2010-05-06 |
KR101011490B1 (ko) | 2011-01-31 |
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