KR20210014580A - 고 도펀트 혼입을 달성하기 위해 n형 도펀트 및/또는 대안적인 도펀트를 활용하는 선택적 증착 방법 - Google Patents

고 도펀트 혼입을 달성하기 위해 n형 도펀트 및/또는 대안적인 도펀트를 활용하는 선택적 증착 방법 Download PDF

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KR20210014580A
KR20210014580A KR1020200090229A KR20200090229A KR20210014580A KR 20210014580 A KR20210014580 A KR 20210014580A KR 1020200090229 A KR1020200090229 A KR 1020200090229A KR 20200090229 A KR20200090229 A KR 20200090229A KR 20210014580 A KR20210014580 A KR 20210014580A
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reaction chamber
precursor
contact layer
semiconductor substrate
temperature
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KR1020200090229A
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존 톨레
조 마르게티스
다비드 코헨
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에이에스엠 아이피 홀딩 비.브이.
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Publication of KR20210014580A publication Critical patent/KR20210014580A/ko

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Abstract

도핑 층을 형성하기 위한 방법을 개시한다. 도핑 층은 NMOS 또는 실리콘 게르마늄 응용 분야에서 사용될 수 있다. 도핑 층은, 예를 들어 n형 도펀트 응용 분야에서 n형 할라이드 종을 사용하여 생성될 수 있다.

Description

고 도펀트 혼입을 달성하기 위해 N형 도펀트 및/또는 대안적인 도펀트를 활용하는 선택적 증착 방법{METHODS FOR SELECTIVE DEPOSITION UTILIZING N-TYPE DOPANTS AND/OR ALTERNATIVE DOPANTS TO ACHIEVE HIGH DOPANT INCORPORATION}
본 개시는 일반적으로 기판 상에 반도체 막의 선택적 증착에 관한 것이다. 보다 구체적으로, 본 개시는 도펀트를 활용한 선택적 증착에 관한 것이다. 도펀트 전구체는 하이드라이드 및 할로겐화 5족을 포함할 수 있다.
로직 응용 분야에서, FinFET 트랜지스터는 에피택셜 증착 공정에 의해 제조되었다. 도펀트는 특정 채널 유형, 예컨대 NMOS 응용 분야를 위한 n형 도핑 층을 매칭하기 위해 사용되어 왔다. 형성된 특정 n형 층은, 예를 들어 실리콘 카바이드(SiC), 실리콘 카보포스핀(SiCP), 및 실리콘 포스핀(SiP)을 포함할 수 있다.
층의 형성은, 치환 격자 부위에서 성장하는 경우에 어려울 수 있다. 성장 층의 선택도, 성장 속도, 도펀트 농도, 및 비저항 중 적어도 하나를 희생시킬 수 있는 문제점이 있을 수 있다. 예를 들어, 층에 대한 특정 선택도를 달성하기 위해, 이는 특정 화학물질의 흐름 또는 층 및/또는 도펀트 혼입의 성장 속도에 악영향을 끼칠 수 있는 공정 온도의 감소를 요구할 수 있다.
결과적으로, 도핑 층에 대해 원하는 선택도 및 기하학적 구조를 달성하면서 도핑 층의 최적의 성장 속도를 허용하는 공정을 개발하는 것이 바람직하다.
본 발명의 내용은 선정된 개념을 단순화된 형태로 소개하기 위해 제공된다. 이들 개념은 하기의 본 발명의 예시적 구현예의 상세한 설명에 더 상세하게 기재되어 있다. 본 발명의 내용은 청구된 요지의 주된 특징 또는 필수적인 특징을 구분하려는 의도가 아니며 청구된 요지의 범주를 제한하기 위해 사용하려는 의도 또한 아니다.
컨택 층을 형성하기 위한 방법을 개시한다. 상기 방법은, 임의의 옥사이드인 반도체 기판 상의 소자를 세정하는 단계(상기 반도체 기판은 반응 챔버 내의 서셉터 상에 배치됨); 상기 반응 챔버의 온도를 안정화시키는 단계; 할라이드 전구체(상기 할라이드 전구체는 불화수소(HF), 염화수소(HCl), 브롬화수소(HBr), 요오드화수소(HI), 염소(Cl2), 불소(F2), 브롬(Br2); 또는 요오드(I2) 중 적어도 하나를 포함함)를 상기 소자 상으로 흐르게 하는 단계; 실리콘 전구체(상기 실리콘 전구체는 실란(SiH4), 디클로로실란(DCS), 디실란, 또는 트리실란 중 적어도 하나를 포함함)를 소자 상으로 흐르게 하는 단계; 및 도펀트 전구체(상기 도펀트 전구체는 PCl3, PCl5, PBr3, PBr5, PI3, PI5, AsCl3, AsCl5, AsBr3, AsBr5, AsI3, AsI5, SbCl3, SbCl5, SbBr3, SbBr5, SbI3, SbI5, 아신(AsH3), 또는 포스핀(PH3) 중 적어도 하나를 포함함)를 상기 소자 상으로 흐르게 하는 단계를 포함하되, 상기 할라이드 전구체는 상기 반도체 기판 상에 배치된 유전체 층 상에 증착하는 것을 방지하고, 상기 실리콘 전구체 및 상기 도펀트 전구체는 반응하여 컨택 층을 형성하고, 상기 흐름 단계는 상기 컨택 층의 원하는 두께를 형성하도록 반복된다.
본원에 개시된 본 발명의 이러한 그리고 기타 특징, 양태 및 장점은 특정 구현예의 도면을 참조하여 아래에 설명될 것이고, 이는 본 발명을 예시하기 위함이고, 본 발명을 한정하기 위함은 아니다.
도 1은 본 발명 중 적어도 하나의 구현예에 따라 형성된 NMOS 소자의 단면도이다.
도 2는 본 발명 중 적어도 하나의 구현예에 따른 공정 흐름도이다.
도 3은 본 발명 중 적어도 하나의 구현예에 따른 장치를 나타낸다.
도면의 구성 요소들은 간략하고 명료하게 도시되어 있으며, 반드시 축적대로 도시되지 않았음을 이해할 것이다. 예를 들어, 본 개시에서 예시된 구현예의 이해를 돕기 위해 도면 중 일부 구성 요소의 치수는 다른 구성 요소에 비해 과장될 수 있다.
특정 구현예 및 실시예가 아래에 개시되었지만, 당업자는 본 발명이 구체적으로 개시된 구현예 및/또는 본 발명의 용도 및 이들의 명백한 변형물 및 균등물을 넘어 확장된다는 것을 이해할 것이다. 따라서, 개시된 발명의 범주는 후술되는 구체적인 개시된 구현예에 의해 제한되지 않도록 의도된다.
본원에 제시된 예시는 임의의 특정한 재료, 구조, 또는 소자의 실제 뷰를 의도하려 하는 것은 아니며, 단지 본 발명의 구현예를 설명하기 위해 사용되는 이상화된 표현이다.
FinFET 응용 분야에서, 컨택 층이 Fin의 상부에 필요할 수 있다. 컨택 층은 또한 실리콘 게르마늄(SiGe) 응용 분야에서도 성장될 수 있다. 특정 NMOS 응용 분야에서 컨택 층의 경우, n형 도펀트를 높은 레벨로 포함하는 것이 바람직할 수 있다. 이는 컨택 층의 전기적 활성 거동을 증가시킬 수 있다.
도 1은 본 발명 중 적어도 하나의 구현예에 따른 소자(100)를 나타낸다. 장치(100)는 핀(110), 얕은 트렌치 격리(STI) 층(120), 컨택 층(130), 및 게이트(140)를 포함할 수 있다. 핀(110)은 실리콘, 게르마늄, 실리콘 게르마늄 또는 이들의 조합 중 적어도 하나를 포함한 측방향 나노와이어의 적층체일 수 있다. STI 층(120)은, 예를 들어 실리콘 옥사이드, 실리콘 옥시나이트라이드, 실리콘 옥시카본, 및 이들의 조합과 같은 유전체 재료를 포함할 수 있다. 게이트(140)는, 예를 들어 하프늄 옥사이드 또는 알루미늄 옥사이드와 같은 옥사이드 재료를 포함할 수도 있다.
컨택 층(130)은, 예를 들어 실리콘 포스핀(SiP), 실리콘 아세나이드(SiAs), 실리콘 안티모나이드(SiSb), 또는 이들의 조합 중 적어도 하나를 포함할 수 있다. 컨택 층(130)은 밀러(Miller) 지수 표기에 따라 특정 결정학적 배향, 예컨대 (111) 방향으로 성장될 수 있다.
컨택 층(130) 성장에 있어서, 추가적인 문제가 선택도와 함께 발생할 수 있는데, 이는 STI 층(120)의 노출된 유전체 재료 상에 층을 증착하지 않고 컨택 층(130)을 성장하는 것이 어려울 수 있기 때문이다. 다른 응용 분야에서, 이러한 선택도를 달성하는 방법은, 염화수소(HCl)의 흐름을 증가시키거나 공정 온도를 감소시키는 것일 수 있다. 그러나, 이러한 것이 이 응용 분야에서 가능할 수 없는데, 그 이유는 HCl 흐름을 증가시키거나 공정 온도를 감소시키면 컨택 층(130)의 성장 속도를 억제할 수 있고/있거나 컨택 층(130)에 포함된 도핑 레벨에 악영향을 줄 수 있기 때문이다.
적절한 성장 속도 및 도핑 레벨을 달성하기 위해, 도 2는 컨택 층(130)을 성장시키기 위한 공정(200)을 나타낸다. 공정(200)은, 예비 세정 단계(210); 온도 안정화 단계(220); 할라이드 전구체 흐름 단계(230); 실리콘 전구체 흐름 단계(240); 도펀트 전구체 흐름 단계(250); 및 반복 사이클(260)을 포함할 수 있다. 공정(200)은 반응 챔버, 가열 요소, 서셉터 및 다수의 가스 공급원을 포함한 증착 장치에서 발생할 수 있다.
예비 세정 단계(210)는, 컨택 층(130)을 성장시키기 전에 소자 상의 임의의 옥사이드를 제거하는 공정을 포함할 수 있다. 예비 세정 단계(210)는 발명의 명칭이 "Reactor System for Sublimation of Pre-Cleaning Byproducts and Method Thereof"인 미국 특허 제10,053,774호에 설명된 바와 같은 화학물질의 흐름 및 승화를 포함할 수 있고, 이는 본원에 참고로 포함된다. 대안적으로, 예비 세정 단계(210)는 원격식 플라즈마를 이용해 NF3 및 암모니아(NH3) 화학 물질을 흐르게 할 수 있다. 예비 세정 단계(210)는 500oC 내지 800oC, 550oC 내지 700oC, 또는 600oC 내지 650oC 온도에서 일어날 수 있다.
온도 안정화 단계(220)는, 예비 세정 단계(210)가 컨택 층(130)을 형성하는 데 필요한 것과 다른 온도를 필요로 하는 경우에, 필요할 수 있다. 온도 안정화 단계(220)는, 반응 챔버의 온도가 300oC 내지 800oC, 400oC 내지 650 oC, 또는 450oC 내지 550oC이도록 할 수 있다.
할라이드 전구체 흐름 단계(230)는, 불화수소(HF), 염화수소(HCl), 브롬화수소(HBr), 요오드화수소(HI), 염소(Cl2), 불소(F2), 브롬(Br2), 요오드(I2), 또는 이들의 조합 중 적어도 하나의 흐름을 포함할 수 있다. 할라이드 전구체 흐름 단계(230)의 목적은, Fin(110) 상으로 그리고 STI 층(120) 상은 아니게 컨택 층(130)을 선택적으로 증착하는 것을 허용하는 것이다. 그러나, 할라이드 전구체 흐름 단계(230)는 컨택 층(130)의 성장 속도를 억제할 만큼 크지 않아야 한다.
실리콘 전구체 흐름 단계(240)는 실란(SiH4), 디클로로실란(DCS), 디실란, 트리실란, 트리클로로실란, 또는 이들의 조합 중 적어도 하나의 흐름을 포함할 수 있다. 실리콘 전구체는 핀(110) 상에 증착될 것이며, 여기서 컨택 층(130)을 형성하도록 반응한다.
도펀트 전구체 흐름 단계(250)는, 인 함유 할라이드, 예컨대 PCl3, PCl5, PBr3, PBr5, PI3, 또는 PI5; 비소 함유 할라이드, 예컨대 AsCl3, AsCl5, AsBr3, AsBr5, AsI3, 또는 AsI5; 안티몬 함유 할라이드, 예컨대 SbCl3, SbCl5, SbBr3, SbBr5, SbI3또는 SbI5; 또는 하이드라이드, 예컨대 아신(AsH3) 또는 포스핀(PH3) 중 적어도 하나의 흐름을 포함할 수 있다. 도펀트 전구체 흐름 단계(250)는 상기에서 나열된 것 중에서 선택된 다수의 도펀트 공급원을 공동으로 흐르게 하거나 교대로 흐르게 하는 단계를 포함할 수 있다.
이전의 접근법은, 도펀트 공급원으로서 포스핀 또는 아신을 사용하였을 수 있지만, 이러한 것은 높은 증기압이 포함되는 것으로 인해 취급 및 반응 챔버로의 전달 관점에서 안전 문제를 야기할 수 있다. 상기에서 나열된 도펀트 전구체 중 적어도 하나를 포함함으로써, 표면 화학 반응은, 안전한 방식으로 작동하면서, n형 도펀트의 대부분을 전기적 활성 격자 위치에 포함시키도록 개질될 수 있다.
방법(200)은 원하는 두께의 막을 형성하기 위해 반복 사이클 단계(260)를 또한 포함할 수 있다.
방법(200)의 단계 결과로서, 반응 챔버를 위한 더 낮은 온도 및 압력이 가능할 수 있다. 온도는 400oC 내지 800oC, 550oC 내지 700oC, 또는 600oC 내지 650oC 범위일 수 있다. 압력은 0.1 내지 760 토르, 10 내지 200 토르, 또는 30 내지 100 토르 범위일 수 있다.
또한, 공정(200)은, 예를 들어 결함 상태로 이어지지 않고서 높은 인 함량 및 전기적 활성 특성을 갖는, 실리콘 포스핀(SiP)으로 형성된 컨택 층을 생성할 수 있다. 또한, 공정(200)으로 인해 높은 레벨의 도펀트 혼입이 가능할 수 있다.
도 3은 본 개시의 적어도 하나의 구현예에 따른 소자 형성용 장치(300)를 나타낸다. 장치(300)는 반응 챔버(302), 제1 가스를 반응 챔버(302)에 제공하도록 구성된 제1 가스 공급원(304), 제2 가스를 반응 챔버(302)에 제공하도록 구성된 제2 가스 공급원(306); 및 소자가 위에 형성되는 반도체 기판을 유지하도록 구성된 서셉터(308)를 포함한다. 장치(300)는 하나 이상의 가스를 반응 챔버(302)에 제공하는 가스 분배 장치(310)를 추가로 포함할 수 있다. 추가적으로, 장치(300)는, 예를 들어 가스 유량, 반응 챔버 압력, 반응 챔버 온도를 제어하기 위한 제어기(312)를 포함할 수 있다. 장치(300)는 본원에서 설명하는 바와 같은 방법을 수행하도록 구성될 수 있다.
나타내고 설명된 구체적인 적용예는, 본 발명의 예시이자 최적 실시 모드이며, 어떤 방식으로도 양태와 적용예의 범주를 달리 제한하도록 의도되지 않는다. 실제로, 간결성을 위해서, 시스템의 종래의 제조, 연결, 준비 및 다른 기능적 양태는 상세히 기술되지 않을 수 있다. 또한, 다양한 도면들에서 도시된 연결선들은 다양한 요소들 사이의 예시적인 기능 관계 및/또는 물리적 결합을 표시하려는 의도이다. 많은 대안 또는 추가적인 기능적 관계 또는 물리적 연결은 실질적인 시스템에 존재할 수 있고/있거나 일부 구현예에서는 없을 수 있다.
본원에 기술된 구성 및/또는 접근법은 본질적으로 예시적인 것이며, 다양한 변형이 가능하기 때문에, 이들 특정 구현예 또는 실시예가 제한적인 의미로 고려되어서는 안 된다는 것을 이해해야 한다. 본원에 설명된 특정 루틴 또는 방법은 임의의 처리 전략 중 하나 이상을 나타낼 수 있다. 따라서, 도시된 다양한 동작은 도시된 시퀀스에서, 상이한 시퀀스에서 수행되거나, 경우에 따라 생략될 수 있다.
본 개시의 요지는, 본원에 개시된 다양한 공정, 시스템, 및 구성, 다른 특징, 기능, 행위 및/또는 성질의 모든 신규하고 비자명한 조합 및 하위 조합뿐만 아니라 임의의 그리고 모든 균등물을 포함한다.

Claims (6)

  1. 반도체 기판 상에 배치된 Fin 상에 컨택 층을 형성하는 방법으로서,
    임의의 옥사이드인 반도체 기판 상의 소자를 세정하는 단계(상기 반도체 기판은 반응 챔버 내 서셉터 상에 배치됨);
    상기 반응 챔버의 온도를 안정화시키는 단계;
    상기 소자 상으로 할라이드 전구체를 흐르게 하는 단계(상기 할라이드 전구체는 불화수소(HF), 염화수소(HCl), 브롬화수소(HBr), 요오드화수소(HI), 염소(Cl2), 불소(F2), 브롬(Br2), 또는 요오드(I2) 중 적어도 하나를 포함함);
    상기 소자 상으로 실리콘 전구체를 흐르게 하는 단계(상기 실리콘 전구체는 실란(SiH4); 디클로로실란(DCS); 디실란; 또는 트리실란 중 적어도 하나를 포함함); 및
    상기 소자 상으로 도펀트 전구체를 흐르게 하는 단계(상기 도펀트 전구체는, PCl3; PCl5; PBr3; PBr5; PI3; PI5; AsCl3; AsCl5; AsBr3; AsBr5; AsI3; AsI5; SbCl3; SbCl5; SbBr3; SbBr5; SbI3; SbI5; 아신(AsH3); 또는 포스핀(PH3) 중 적어도 하나를 포함함)를 포함하되,
    상기 할라이드 전구체는 상기 반도체 기판 상에 배치된 유전체 층 상으로 증착을 방지하고,
    상기 실리콘 전구체 및 상기 도펀트 전구체는 컨택 층을 형성하도록 반응하고,
    상기 흐름 단계 중 어느 하나를 반복해서 상기 컨택 층의 원하는 두께를 형성하는, 방법.
  2. 제1항에 있어서, 상기 세정 단계는 300oC 내지 800oC, 400oC 내지 650oC, 또는 450oC 내지 550oC의 온도에서 수행되는, 방법.
  3. 제1항에 있어서, 상기 안정화 단계는 상기 온도를 400oC 내지 800oC, 550oC 내지 700oC, 또는 600oC 내지 650oC 범위의 온도로 안정화하는 단계를 포함하는, 방법.
  4. 제1항에 있어서, 상기 반응 챔버의 압력은 0.1 내지 760 토르, 10 내지 200 토르, 또는 30 내지 100 토르의 범위인, 방법.
  5. 제1항에 있어서, 상기 형성된 컨택 층은 (111)의 결정학적 배향을 갖는, 방법.
  6. 소자를 형성하기 위한 장치로서,
    반응 챔버;
    상기 반응 챔버에 제1 가스를 제공하도록 구성된 제1 가스 공급원;
    상기 반응 챔버에 제2 가스를 제공하도록 구성된 제2 가스 공급원; 및
    소자가 위에 형성되는 반도체 기판을 유지하도록 구성된 서셉터를 포함하되,
    상기 장치는 제1항의 방법을 수행하도록 구성되는, 장치.
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