KR20240007889A - 순환 증착에 의해 기판 상에 금속막을 형성하는 방법 및 관련 반도체 디바이스 구조체 - Google Patents
순환 증착에 의해 기판 상에 금속막을 형성하는 방법 및 관련 반도체 디바이스 구조체 Download PDFInfo
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- KR20240007889A KR20240007889A KR1020230192258A KR20230192258A KR20240007889A KR 20240007889 A KR20240007889 A KR 20240007889A KR 1020230192258 A KR1020230192258 A KR 1020230192258A KR 20230192258 A KR20230192258 A KR 20230192258A KR 20240007889 A KR20240007889 A KR 20240007889A
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Classifications
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
- C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- C—CHEMISTRY; METALLURGY
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
- C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
- C23C16/18—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
- C23C16/45553—Atomic layer deposition [ALD] characterized by the use of precursors specially adapted for ALD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
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- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
순환 증착에 의해 기판 상에 금속막을 형성하는 방법이 제공된다. 일부 구현예에서, 상기 방법은 구리, 니켈 또는 코발트 중 적어도 하나를 포함하는 할로겐 비함유 금속 전구체를 포함하는 제1 반응물과 기판을 접촉시키는 단계 및 탄화수소 치환된 하이드라진을 포함하는 제2 반응물과 기판을 접촉시키는 단계를 포함할 수 있다. 일부 구현예에서, 관련 반도체 디바이스 구조체는 순환 증착 공정에 의해 형성된 금속성 배선부의 적어도 일부를 포함할 수 있다.
Description
공동 연구 협약의 당사자
본원에 청구된 발명은 헬싱키 대학교와 ASM Microchemistry Oy 간의 공동 연구 협약에 의해, 또는 이를 대신하여, 그리고/또는 이와 관련하여 작성되었다. 상기 협약은 청구된 발명이 작성된 날짜 이전에 효력이 있었으며, 청구된 발명은 협약 범위 내에서 수행된 활동의 결과로서 작성되었다.
본 발명은 일반적으로 순환 증착(cyclical deposition)에 의해 기판 상에 금속막을 형성하는 방법, 특히 구리, 코발트 및 니켈 중 적어도 하나를 포함하는 금속막을 형성하는 방법에 관한 것이다. 또한 본 발명은 순환 증착에 의해 형성된 금속막을 포함하는 반도체 디바이스 구조체에 관한 것이다.
금속막, 예를 들면 구리, 코발트 및 니켈을 포함하는 금속막은 반도체 디바이스 구조체의 제조에 이용될 수 있다. 예를 들면, 구리막이 나타내는 낮은 비저항(resistivity)과 일렉트로마이그레이션(electromigration)에 대한 및 높은 저항성(resistance)으로 인해, 구리는 마이크로전자 디바이스에서의 주요 배선 재료가 되었다. 구리 배선부는 구리 씨드층(seed layer)이 우선 물리적 증기 증착(PVD)에 의해 형성되고 이어서 후속 구리 충전 공정이 전기증착 공정에 의해 수행되는 2단계 공정으로 제조될 수 있다. 그러나, 차세대 마이크로전자 디바이스의 개발은 반도체 디바이스의 최소 배선폭(feature size)의 축소에 좌우된다. 따라서, 구리 씨드층은 낮은 비저항을 나타낼 뿐만 아니라 등각 방식(conformal manner)으로 형성될 수 있는 극도로 얇은 막일 필요가 있을 수 있다.
PVD 기술 고유의 제한된 등각성(conformality)으로 인해, 예를 들면 구리 씨드층의 형성을 위한 것과 같은, 반도체 디바이스 구조체의 제조에 이용하기 위한 금속막의 등각 증착(conformal deposition)을 위해서는 더욱 적합한 증착 공정이 요구될 수 있다. 순환 증착, 예를 들면, 원자층 증착 공정은, 기판 표면에서의 반응을 위한 2종 이상의 가스 전구체의 공급을 번갈아 수행함으로써 등각성의 금속막을 형성하는데 이용될 수 있다. 원자층 증착 공정을 구성하는 반응 단계는 자가 제한(self-limit)될 수 있으며, 이는 원자 수준의 정확도를 갖는 균일하고 등각성인 금속막의 증착을 가능하게 한다.
일례로서, 반도체 디바이스 구조체의 제조를 위한 구리의 순환 증착이 연구되었으며, 염화구리(CuCl), 아연(Zn) 및 수소(H2)를 포함하는 전구체를 이용할 수 있다 . 그러나, 저온에서 고품질 구리막을 증착하는 것은 도전적인 과제인 것으로 판명되었다. 원자층 증착 공정과 같은 순환 증착에서 응집을 억제하고 구리의 얇은 연속 막의 증착을 가능하게 하기 위해서는 낮은 증착 온도가 이용될 수 있다. 그러나, 대다수의 구리 ALD 공정은 고온 증착 기술을 요구하며, 저온 공정은 기판의 열화 및 불량한 등각 도포성(conformal coverage)을 초래할 수 있는 플라즈마 강화 공정(plasma enhanced process)에 의해 주로 달성된다.
따라서, 감소된 증착 온도에서 금속막을 증착할 수 있게 하는 방법 및 반도체 디바이스 구조체가 요망되며, 증착 공정은 고품질의 등각성의 금속막을 제공할 수 있다.
본 요약은 선정된 개념들을 단순화된 형태로 소개하기 위해 제공된다. 이들 개념은 하기에 개시된 예시적 구현예들의 상세한 설명에 더 상세하게 기재되어 있다. 이러한 요약은 청구된 요지의 주된 특징 또는 필수적인 특징을 구분하려는 의도가 아니며 청구된 요지의 범주를 제한하기 위해 사용하려는 의도 또한 아니다.
일부 구현예에서, 순환 증착에 의해 기판 상에 금속막을 형성하는 방법이 제공된다. 방법은 구리, 니켈 또는 코발트 중 적어도 하나를 포함하는 할로겐 비함유 금속 전구체를 포함하는 제1 반응물과 기판을 접촉시키는 단계 및 탄화수소 치환된 하이드라진 전구체를 포함하는 제2 반응물과 기판을 접촉시키는 단계를 포함할 수 있다.
본 명세서는 본 발명의 구현예로 여겨지는 것을 특별히 지적하고 명백하게 주장하는 청구범위로 결론을 내지만, 본 개시의 구현예들의 장점들은 첨부한 도면들과 관련하여 읽을 때 본 개시의 구현예들의 특정 예의 설명으로부터 더욱 쉽게 확인될 수 있고, 도면들 중:
도 1은 본 발명의 구현예에 따라 형성된 구리막의 X-선 회절(x-ray diffraction)(XRD) 스캔을 나타내는 그래프이고;
도 2는 본 발명의 구현예에 따라 형성된 반도체 디바이스 구조체의 단순화된 단면도이고;
도 3은 본 발명의 특정 구현예를 수행하도록 구성된 반응 시스템을 예시하고;
도 4는 본 발명의 구현예에 따라 형성된 구리막의 비행시간 탄성 반동 검파 분석(time-of-flight elastic recoil detection analysis)(TOF-ERDA)을 나타내는 그래프이다.
도 1은 본 발명의 구현예에 따라 형성된 구리막의 X-선 회절(x-ray diffraction)(XRD) 스캔을 나타내는 그래프이고;
도 2는 본 발명의 구현예에 따라 형성된 반도체 디바이스 구조체의 단순화된 단면도이고;
도 3은 본 발명의 특정 구현예를 수행하도록 구성된 반응 시스템을 예시하고;
도 4는 본 발명의 구현예에 따라 형성된 구리막의 비행시간 탄성 반동 검파 분석(time-of-flight elastic recoil detection analysis)(TOF-ERDA)을 나타내는 그래프이다.
본원에 제시된 예시는 임의의 특정한 물질, 구조, 또는 소자의 실제 뷰를 의도하려하는 것은 아니며, 단지 본 개시의 구현예를 설명하기 위해 사용되는 이상화된 묘사이다.
본원에서 사용되는 용어 "순환 증착"은 반응 챔버 내로 전구체(반응물)를 순차적으로 도입하여 기판 상에 층을 증착하는 것을 지칭할 수 있으며 원자층 증착 및 순환 화학적 증기 증착과 같은 가공 기술을 포함한다.
본원에서 사용되는 용어 "원자층 증착(atomic layer deposition)"(ALD)은 증착 주기(deposition cycle), 바람직하게는 복수의 연속 증착 주기가 공정 챔버에서 수행되는 증기 증착 공정을 지칭할 수 있다. 일반적으로, 각각의 사이클 동안, 전구체는 증착 표면(예들 들면, 기판 표면, 또는 이전 ALD 주기로부터의 물질과 같은 이전에 증착된 하부 표면)에 화학 흡착되고, 추가적인 전구체와 쉽게 반응하지 않는(즉, 자기 제한적 반응) 단층 또는 서브 단층을 형성한다. 따라서 필요하다면, 증착 표면에서 화학 흡착된 전구체를 원하는 물질로 전환시키는 용도로, 반응물(예들 들어, 다른 전구체 또는 반응 가스)이 후속해서 공정 챔버로 유입될 수 있다. 일반적으로, 이러한 반응물은 전구체와 더 반응할 수 있다. 또한, 각 사이클 동안 공정 챔버로부터 잉여 전구체를 제거하고(제거하거나) 화학 흡착된 전구체의 변환 후 공정 챔버로부터 잉여 반응물 및/또는 반응 부산물을 제거하기(제거하거나) 위해 퍼징(purging) 단계들이 사용될 수도 있다. 추가로, 본원에 사용된 용어 "원자층 증착"은 "화학적 증기 원자층 증착", "원자 층 에피택시(atomic layer epitaxy)"(ALE), 분자 빔 에피택시(molecular beam epitaxy)(MBE), 가스 공급원 MBE, 또는 유기금속 MBE, 및 전구체 조성물(들), 반응 가스, 및 퍼지(예를 들면, 불활성 캐리어) 가스의 교번 펄스(alternating pulses)로 수행되는 경우의 화학적 빔 에피택시와 같은 관련 용어들에 의해 지정된 공정을 포함하는 것을 또한 의미한다.
본원에서 사용되는 용어 "순환 화학적 증기 증착"은 목적하는 증착을 생성시키기 위해 기판 상에서 반응 및/또는 분해되는 두 개 이상의 휘발성 전구체에 기판이 순차적으로 노출되는 임의의 공정을 지칭할 수 있다.
본원에 사용되는 바와 같이, 용어 "기판"은, 사용될 수 있는, 또는 그 위에 소자, 회로, 또는 막이 형성될 수 있는, 임의의 하부 재료 또는 재료들을 지칭할 수 있다.
본원에서 사용되는 용어 "탄화수소 치환된 하이드라진"은 적어도 하나의 탄화수소 치환된 기를 포함할 수 있는 하이드라진 (N2H4) 의 유도체를 지칭할 수 있다.
본원에서 사용되는 용어 "할로겐 비함유 금속 전구체"는 할로겐 화학종이 실질적으로 없는 금속 전구체를 지칭할 수 있다.
본 발명은 순환 증착 공정에 의해 기판 상에 금속막을 형성하는 방법 및 순환 증착 공정에 의해 형성된 금속막을 포함하는 반도체 디바이스 구조체 자체를 포함한다. 본 발명의 방법은 예를 들면 구리, 코발트 및 니켈과 같은 금속막의 순환 증착 방법을 포함할 수 있다 본 발명은 구리와 같은 금속막을 금속성 배선부의 적어도 일부로서 이용할 수도 있다. 본 발명은 또한 감소된 전기 비저항 및 목적하는 결정학적 특성을 갖는 금속막을 형성하는 방법을 포함할 수 있다. 이러한 방법 및 반도체 디바이스의 예는 하기에 더 상세하게 기재되어 있다.
순환 증착 공정의 비제한적이고 예시적인 구현예는 ALD를 포함할 수 있으며, 이때 ALD는 통상적으로 자가 제한 반응에 기초하고, 이에 따라 반응물들의 순차적 및 교번 펄스를 사용하여 증착 주기당 약 하나의 원자(또는 분자) 물질의 단분자층을 증착한다. 증착 조건 및 전구체는 통상적으로 자가 포화 반응을 제공하도록 선택되어, 하나의 반응물의 흡착된 층이 동일한 반응물의 가스 상 반응물과 비반응성인 표면 종결부를 남긴다. 후속적으로 기판은 이전의 종결부와 반응하는 상이한 반응물과 접촉되어, 연속되는 증착을 가능하게 한다.. 따라서, 교번 펄스의 각각의 주기는 통상적으로 목적하는 재료의 대략 하나의 단분자층만을 남긴다. 그러나, 전술된 바와 같이, 당업자는 하나 이상의 ALD 주기에서, 예를 들면 공정의 교번 특성에도 불구하고 몇몇 기상 반응이 발생하는 경우, 하나 이상의 재료의 단분자층이 증착될 수 있음을 인식할 것이다.
금속막의 증착을 위한 ALD형 공정에서, 하나의 증착 주기는 기판을 제1 반응물에 노출시키고 임의의 미반응된 제1 반응물 및 반응 부산물을 반응 공간으로부터 제거하고 기판을 제2 반응물에 노출시키는 단계, 및 이어서 제2 제거 단계를 포함할 수 있다. 제1 반응물은 할로겐 비함유 금속 전구체를 포함할 수 있고 제2 반응물은 탄화수소 치환된 하이드라진 전구체를 포함할 수 있다.
반응물들간 가스상 반응을 방지하고 자기 포화적 표면 반응을 가능하게 하기 위하여 전구체들은 아르곤(Ar) 또는 질소(N2)와 같은 불활성 가스에 의해 분리될 수 있다. 그러나, 일부 구현예에서, 기판은 제1 증기 상 반응물 및 제2 증기 상 반응물을 개별적으로 접촉시키도록 이동될 수 있다. 반응은 자가 포화되기 때문에, 기판의 엄격한 온도 제어 및 전구체의 정확한 투여량 제어는 일반적으로는 요구되지 않는다. 그러나, 기판 온도는 바람직하게는 입사 가스 화학종이 단분자층으로 응축되지 않거나 표면 상에서 분해되지 않도록 한다. 과잉 화학 물질 및 반응 부산물이 있으면, 기판이 다음 반응 화학 물질과 접촉하기 전에 이들은, 예를 들어 반응 공간을 퍼징하거나 기판을 이동함으로써 기판 표면으로부터 제거된다. 원하지 않는 가스 분자들은 불활성 퍼지 가스의 도움으로 반응 공간으로부터 효과적으로 방출될 수 있다. 진공 펌프는 퍼징을 돕는 데 사용될 수 있다.
일부 구현예에 따라, ALD 공정은 집적 회로 피가공물과 같은 기판 상에 금속막을 형성하는데 사용된다. 본 발명의 일부 구현예에서, 각각의 ALD 주기는 두 개의 별개의 증착 단계(step 또는 phase)을 포함한다 증착 주기의 제1 단계("금속 단계")에서, 증착이 요구되는 기판 표면은 기판 표면 상에 화학흡착하는 금속 전구체를 포함하는 제1 증기 상 반응물과 접촉되어, 기판 표면 상에 반응물 화학종으로 이루어진 대략 하나의 단분자층만을 형성한다.
박막을 성장시키기 위해 사용될 수 있는 반응기들이 증착을 위해 사용될 수 있다. 이러한 반응기는 전구체들을 제공하기 위한 적절한 장비 및 수단을 장착하고 있는 CVD 반응기뿐만 아니라 ALD 반응기를 포함한다. 일부 구현예에 따르면, 샤워헤드 반응기가 사용될 수 있다.
사용될 수 있는 적합한 반응기의 예는 상업적으로 입수 가능한 단일 기판 (또는 단일 웨이퍼) 증착 설비, 예를 들면, 미국 애리조나주 피닉스 소재의 ASM America, Inc. 및 네덜란드 알메레 소재의 ASM Europe B.V)로부터 입수 가능한 Pulsar® 반응기(예를 들면 Pulsar® 2000 및 Pulsar® 3000 및 Pulsar® XP ALD), 및 EmerALD® XP 및 EmerALD® 반응기를 포함한다. 다른 상업적으로 입수 가능한 반응기는 Eagle® XP 및 XP8라는 상표명을 가진 ASM Japan K.K(일본, 동경)사의 제품들을 포함한다. 일부 구현예에서, 반응기는, 기판이 가공 과정에서 이동 또는 회전하는 공간 ALD 반응기이다
일부 구현예에서, 회분식 반응기가 사용될 수 있다. 적합한 회분식 반응기는, 이들에 한정되지는 않지만, A400 및 A412 PLUS라는 상표명으로 ASM Europe B.V(네덜란드, 알메르)사로부터 상업적으로 구매 가능한 Advance® 400 시리즈 반응기를 포함한다. 일부 구현예에서, 처리를 하는 동안 보트(boat)가 회전하는 수직 회분식 반응기, 예컨대 A412이 사용된다. 이처럼, 일부 구현예에서, 웨이퍼는 처리 중에 회전한다. 다른 구현예에서, 회분식 반응기는 10개 이하의 웨이퍼, 8개 이하의 웨이퍼, 6개 이하의 웨이퍼, 4개 이하의 웨이퍼 또는 2개의 웨이퍼를 수용하도록 구성된 소형 회분식 반응기를 포함한다. 회분식 반응기가 사용되는 일부 구현예에서, 웨이퍼 대 웨이퍼 균일도는 3%(1 시그마)미만, 2% 미만, 1% 미만 또는 심지어 0.5% 미만이다.
본원에 기재되어 있는 증착 공정은 클러스터 도구에 연결된 반응기 또는 반응 공간에서 선택적으로 수행될 수 있다. 클러스터 도구에서, 각각의 반응 공간은 하나의 유형의 공정에 전용되기 때문에, 각 모듈 내의 반응 공간의 온도는 일정하게 유지될 수 있으며, 이는 기판이 각각 실행되기 전에 공정 온도로 가열되는 반응기에 비해 처리량을 향상시킨다. 추가적으로, 클러스터 도구에서, 기판들 사이에서 목표한 공정 압력 레벨까지 반응 공간을 펌핑하는 시간을 줄일 수 있다.
독립형 반응기는 로드-록 (load-lock)이 장착되어 있을 수 있다. 이 경우, 각각의 구동 사이에 반응 공간을 냉각시킬 필요는 없다. 일부 구현예에서, 금속막을 포함하는 박막을 증착하기 위한 증착 공정은 복수의 증착 주기, 예를 들면 ALD 주기를 포함할 수 있다.
일부 구현예에서, 금속막을 포함하는 박막을 증착하기 위한 증착 공정은 복수의 증착 주기, 예를 들면 ALD 주기를 포함할 수 있다. 일부 구현예에서, 순환 증착은 하이브리드 ALD/CVD 또는 순환 CVD 공정일 수 있다. 예를 들면, 일부 구현예에서, ALD 공정의 성장 속도는 CVD 공정에 비해 낮을 수 있다. 성장 속도를 증가시키는 하나의 접근법은 ALD 공정에서 통상적으로 사용되는 것보다 높은 기판 온도에서 작동시켜, 화학적 증기 증착 공정을 유발할 수 있지만 전구체의 순차적 도입을 여전히 이용하는 방법일 수 있으며, 이러한 공정을 순환 CVD라고 한다.
일부 구현예에서, 본원에서 "금속 화합물"로도 지칭되는 금속 전구체는 할로겐 비함유 금속 전구체를 포함할 수 있고, 즉, 금속 전구체는 할로겐 화학종을 실질적으로 함유하지 않을 수 있다. 일부 구현예에서, 할로겐 비함유 금속 전구체는 구리, 코발트 및 니켈 중 하나를 포함할 수 있다. 따라서 할로겐 비함유 금속 전구체는 Cu(dmap)2(dmap = 디메틸아미노-2-프로폭사이드), Ni(dmap)2 또는 Co(dmap)2 중 적어도 하나를 포함할 수 있다. 따라서, 일부 구현예에서, 할로겐 비함유 금속 전구체는, 금속 중심 원자가 두자리 리간드에서 적어도 하나의 산소 및 적어도 하나의 질소 원자를 통해 결합되는 적어도 하나의 두자리 리간드를 포함할 수 있다. 따라서, 일부 구현예에서, 할로겐 비함유 금속 전구체는, 금속 중심 원자가 두자리 리간드에서 적어도 하나의 질소 원자를 통해 결합되는 적어도 하나의 두자리 리간드를 포함할 수 있다. 따라서, 일부 구현예에서, 할로겐 비함유 금속 전구체는, 금속 중심 원자가 두자리 리간드에서 적어도 하나의 질소 원자를 통해 결합되는 적어도 하나의 두자리 리간드를 포함할 수 있다. 따라서, 일부 구현예에서, 할로겐 비함유 금속 전구체는 적어도 하나의 두자리 리간드 및 적어도 두 개의 다른 리간드, 예를 들면 한자리 리간드를 포함할 수 있다. 따라서, 일부 구현예에서, 할로겐 비함유 금속 전구체는 적어도 하나의 두자리 리간드, 및 N 또는 O를 통해 금속 중심 원자에 결합되는 적어도 하나의 다른 리간드, 예를 들면 한자리 리간드를 포함할 수 있다. 따라서, 일부 구현예에서, 할로겐 비함유 금속 전구체는, 금속 중심 원자가가 적어도 하나의 질소 원자를 통해 결합되고 두자리 리간드에서 질소 이외의 적어도 하나의 다른 원자를 통해 결합되는 적어도 하나의 두자리 리간드를 포함할 수 있다. 따라서, 일부 구현예에서, 할로겐 비함유 금속 전구체는 금속 중심 원자가 두자리 리간드에서 두 개의 질소 원자를 통해 결합되는 적어도 하나의 두자리 리간드를 포함할 수 있다. 일부 구현예에서, 할로겐 비함유 금속 전구체는 적어도 두 개의 두자리 리간드를 포함한다. 일부 구현예에서, 할로겐 비함유 금속 전구체는 두 개의 두자리 리간드를 포함한다. 적합한 할로겐 비함유 베타디케트이미네이토(예를 들면, Ni(pda)2), (pda = 펜탄-2,4,-디케트이미네이토) 화합물의 일부 예가 미국 특허공보 제2009-0197411 A1호에 언급되어 있으며, 그 개시 내용은 전체가 본원에 포함되어 있다. 적합한 할로겐 비함유 아미디네이트 화합물(예를 들면, Ni(iPr-AMD)2)의 몇몇 예가 미국 특허공보 제2006-0141155 A1호에 언급되어 있으며, 그 개시 내용은 전체가 본원에 포함되어 있다. 적합한 할로겐 비함유 이미노알콕사이드 화합물의 몇몇 예가 미국 특허공보 제2014-0227444 A1호에 언급되어 있으며, 그 개시 내용은 전체가 본원에 포함되어 있다다. 일부 구현예에서, 할로겐 비함유 금속 전구체는 목적하는 금속(Co, Ni, Cu) 이외의 금속 원자를 포함하지 않는다. 일부 구현예에서, 할로겐 비함유 금속 전구체 내의 금속은 0의 산화 상태를 갖는다. 일부 구현예에서, 할로겐 비함유 금속 전구체 내의 금속은 +I의 산화 상태를 갖는다. 일부 구현예에서, 할로겐 비함유 금속 전구체 내의 금속은 +III의 산화 상태를 갖는다. 일부 구현예에서, 할로겐 비함유 금속 전구체 내의 금속은 +II의 산화 상태를 갖는다. 일부 구현예에서, 산화 상태는 실온에서 전구체 내의 금속의 산화 상태이다. 산화 상태는 상이한 조건에서, 예를 들면 상이한 압력, 온도 및/또는 분위기에서 뿐만 아니라 상기 상이한 조건에서 상이한 표면 재료와 접촉할 때 변할 수 있다. 일부 구현예에서, 할로겐 비함유 금속 전구체는 F, Cl, Br 또는 I와 같은 할로겐화물을 포함하지 않는다. 일부 구현예에서, 할로겐 비함유 금속 전구체는 탄소, 수소 및 질소 및 임의로 산소를 포함한다.
일부 구현예에서, 할로겐 비함유 구리 전구체는 예를 들면 Cu(dmap)2 또는 구리(I) N,N'-디이소프로필아세트아미디네이트를 포함할 수 있다. 일부 구현예에서, 구리 전구체는 구리 베타디케토네이트 화합물, 구리 베타디케트이미네이토 화합물, 구리 아미노알콕사이드 화합물, 예를 들면 Cu(dmae)2, Cu(deap)2 또는 Cu(dmamb)2, 구리 아미디네이트 화합물, 예를 들면 Cu(sBu-amd)]2, 구리 사이클로펜타디에닐 화합물, 구리 카보닐 화합물 및 이들의 조합으로 이루어진 그룹으로부터 선택될 수 있다. 일부 구현예에서, X(acac)y 또는 X(thd)y 화합물이 사용되며, 여기서 X는 구리이고, y는 일반적으로 2 또는 3이지만 꼭 그러하지만은 않고, thd는 2,2,6,6-테트라메틸-3,5-헵탄디오네이토이다. 일부 구현예에서, 할로겐 비함유 구리 전구체는 구리(II)아세테이트, [Cu(HMDS)]4 또는 Cu(nhc)HMDS(1,3-디-이소프로필-이미다졸린-2-일리덴 구리 헥사메틸 디실라지드) 또는 Cu-베타디케트이미네이트, 예를 들면 Cu(dki)VTMS(dki = 디케트이미네이트)이다.
일부 구현예에서, 할로겐 비함유 니켈 전구체는 예를 들면 비스(4-N-에틸아미노-3-펜텐-2-N-에틸이미네이토)니켈(II)일 수 있다. 일부 구현예에서, 니켈 전구체는 니켈 베타디케토네이트 화합물, 니켈 베타디케트이미네이토 화합물, 니켈 아미노알콕사이드 화합물, 니켈 아미디네이트 화합물, 니켈 사이클로펜타디에닐 화합물, 니켈 카보닐 화합물 및 이들의 조합으로 이루어진 그룹으로부터 선택될 수 있다. 일부 구현예에서, X(acac)y 또는 X(thd)y 화합물이 사용되며, 여기서 X는 니켈이고, y는 일반적으로 2 또는 3이지만 꼭 그러하지만은 않고, thd는 2,2,6,6-테트라메틸-3,5-헵탄디오네이토이다.
일부 구현예에서, Co 전구체는 Co 베타-디케토이미네이토 화합물이다. 일부 구현예에서, Co 전구체는 Co 케토이미네이트 화합물이다. 일부 구현예에서, Co 전구체는 Co 아미디네이트 화합물이다. 일부 구현예에서, Co 전구체는 Co 베타-디케토네이트 화합물이다. 일부 구현예에서, Co 전구체는 적어도 하나의 케토이민 리간드 또는 이들의 유도체를 함유한다. 일부 구현예에서, Co 전구체는 적어도 하나의 아미딘 리간드 또는 이들의 유도체를 함유한다. 일부 구현예에서, Co 전구체는 적어도 하나의 케토네이트 리간드 또는 이들의 유도체를 함유한다. 일부 구현예에서, Co 전구체는 Co2(CO)8, CCTBA, CoCp2, Co(Cp-amd), Co(Cp(CO)2), tBu-알릴Co(CO)3 또는 Co(HMDS)2이다.
일부 구현예에서, 기판을 할로겐 비함유 금속 전구체에 노출시키는 것은 금속 전구체(예를 들면, Cu(dmap)2)를 약 0.01 초와 약 60 초 사이, 약 0.05 초와 약 10.0 초 사이, 약 0.1 초와 약 5.0 초 사이의 기간 동안 기판 상으로 펄싱(pulsing)하는 단계를 포함할 수 있다. 또한, 금속 전구체를 기판 상으로 펄싱하는 동안 금속 전구체의 유량은 2000 sccm 미만, 또는 1000 sccm 미만, 또는 500 sccm 미만, 또는 200 sccm 미만 또는 심지어 100 sccm 미만일 수 있다.
과량의 금속 전구체 및 반응 부산물은 (존재하는 경우) 예를 들면 불활성 가스로 퍼징함으로써 기판 표면으로부터 제거될 수 있다. 예를 들면, 본 발명의 일부 구현예에서, 방법은, 기판 표면이 대략 1.0 초 미만의 기간 동안 퍼징되는 퍼지 주기를 포함할 수 있다. 과량의 금속 전구체 및 임의의 반응 부산물은 펌핑 시스템에 의해 생성된 진공의 도움으로 제거될 수 있다.
증착 주기의 제2 단계("치환된 하이드라진 단계")에서, 기판은 탄화수소 치환된 하이드라진 전구체를 포함하는 제2 증기 상 반응물과 접촉된다. 본 발명의 일부 구현예에서, 방법은, 적어도 네(4) 개의 탄소 원자를 갖는 알킬기를 포함하도록 치환된 하이드라진을 선택하는 단계를 추가로 포함하며, 이때 "알킬기"는 부틸, 펜틸, 헥실, 헵틸 및 옥틸 및 이들의 이성체, 예를 들면 이들의 n-, 이소-, 2급- 및 3급-이성체와 같지만 이에 한정되지 않는 적어도 네(4) 개의 탄소 원자 길이의 포화 또는 불포화 탄화수소 쇄를 지칭한다. 알킬기는 직쇄 또는 분지쇄일 수 있고 알킬기의 모든 구조 이성체 형태를 포괄할 수 있다. 일부 구현예에서, 알킬 쇄는 치환될 수 있다. 본 발명의 일부 구현예에서, 알킬-하이드라진은 질소에 결합된 적어도 하나의 수소를 포함할 수 있다. 본 발명의 일부 구현예에서, 알킬-하이드라진은 질소에 결합된 적어도 두 개의 수소를 포함할 수 있다. 본 발명의 일부 구현예에서, 알킬-하이드라진은 질소에 결합된 적어도 하나의 수소 및 질소에 결합된 적어도 하나의 알킬 쇄를 포함할 수 있다. 본 발명의 일부 구현예에서, 제2 반응물은 알킬-하이드라진을 포함할 수 있으며 3급부틸하이드라진 (C4H9N2H3), 디메틸하이드라진 또는 디에틸하이드라진 중 하나 이상을 추가로 포함할 수 있다. 본 발명의 일부 구현예에서, 치환된 하이드라진은 질소에 부착된 적어도 하나의 탄화수소기를 갖는다. 본 발명의 일부 구현예에서, 치환된 하이드라진은 질소에 부착된 적어도 두 개의 탄화수소기를 갖는다. 본 발명의 일부 구현예에서, 치환된 하이드라진은 질소에 부착된 적어도 세 개의 탄화수소기를 갖는다. 본 발명의 일부 구현예에서, 치환된 하이드라진은 질소에 부착된 적어도 하나의 C1-C3 탄화수소기를 갖는다. 본 발명의 일부 구현예에서, 치환된 하이드라진은 질소에 부착된 적어도 하나의 C4-C10 탄화수소기를 갖는다. 본 발명의 일부 구현예에서, 치환된 하이드라진은 질소에 부착된 선형, 분지형, 또는 환형 또는 방향족 탄화수소기를 갖는다. 본 발명의 일부 구현예에서, 치환된 하이드라진은 질소에 부착된 치환된 탄화수소기를 포함한다.
본 발명의 일부 구현예에서, 치환된 하이드라진은 다음의 화학식을 갖는다:
RIRII-N-NRIIIRIV ,
(1)
여기서 RI은 선형, 분지형, 환형, 방향족 또는 치환된 탄화수소기와 같은 탄화수소기로부터 선택될 수 있고, 각각의 RII, RIII, RIV 기는 수소, 또는 선형, 분지형, 환형, 방향족 또는 치환된 탄화수소기와 같은 탄화수소기로부터 독립적으로 선택될 수 있다.
일부 구현예에서, 화학식 (1)에서 각각의 RI, RII, RIII, RIV는 C1-C10 탄화수소, C1-C3 탄화수소, C4-C10 탄화수소 또는 수소, 예를 들면 선형, 분지형, 환형, 방향족 또는 치환된 탄화수소기일 수 있다. 일부 구현예에서, RI, RII, RIII, RIV 기 중 적어도 하나는 페닐기와 같은 방향족기를 포함한다. 일부 구현예에서, RI, RII, RIII, RIV 기 중 적어도 하나는 메틸, 에틸, n-프로필, i-프로필, n-부틸, i-부틸, s-부틸, 3급부틸기 또는 페닐기를 포함한다. 일부 구현예에서, 각각의 RI, RII, RIII, RIV 기 중 적어도 두 개는 메틸, 에틸, n-프로필, i-프로필, n-부틸, i-부틸, s-부틸, 3급부틸기 또는 페닐기를 포함하도록 독립적으로 선택될 수 있다 일부 구현예에서, RII, RIII 및 RIV 기는 수소이다. 일부 구현예에서, RII, RIII, RIV 기 중 적어도 두 개는 수소이다. 일부 구현예에서, RII, RIII, RIV 기 중 적어도 하나는 수소이다. 일부 구현예에서, RII, RIII, RIV 기는 모두 탄화수소이다.
일부 구현예에서, 치환된 하이드라진 전구체에 기판을 노출시키는 것은 치환된 하이드라진 전구체(예를 들면, 3급부틸하이드라진)를 0.1 초와 2.0 초 사이, 또는 약 0.01 초 내지 약 10 초, 또는 약 20 초 미만, 약 10 초 미만 또는 약 5 초 미만의 기간 동안 기판 상으로 펄싱하는 단계를 포함할 수 있다. 치환된 하이드라진 전구체를 기판 상으로 펄싱하는 동안 치환된 하이드라진 전구체의 유량은 2000 sccm 미만, 또는 1000 sccm 미만, 또는 500 sccm 미만, 또는 심지어 100 sccm 미만일 수 있다.
치환된 하이드라진 전구체를 포함하는 제2 증기 상 반응물은 기판 표면 상에 남아 있는 금속 함유 분자와 반응할 수 있다. 일부 구현예에서, 제2 상 치환된 하이드라진 전구체는 기판 표면 상에 남아 있는 금속 함유 분자를 환원시켜 금속막을 형성할 수 있는 환원제를 포함할 수 있다. 예를 들면, 제1 증기 상 반응물은 구리 전구체를 포함할 수 있고 제2 증기 상 반응물은 환원제를 포함할 수 있다. 구리 전구체가 반응 챔버로 도입되어 기판 표면 상으로 흡착된 후, 과량의 구리 전구체 증기는 챔버로부터 펌핑 또는 퍼징될 수 있다. 당해 공정에 이어, 구리 전구체와 반응하는 환원제를 기판 표면 상에 도입하여 구리 금속 및 자유 형태의 리간드를 형성한다. 필요한 경우 당해 증착 주기가 반복되어 목적하는 두께의 금속막을 얻을 수 있다.
과량의 제2 공급원 화학물질 및 반응 부산물은, 존재하는 경우, 예를 들면 가스 펄스(gas pulse) 및/또는 펌핑 시스템에 의해 생성된 진공을 퍼징함으로써 기판 표면으로부터 제거될 수 있다. 퍼지 가스는 제한 없이 임의의 불활성 가스, 예를 들어 아르곤(Ar), 질소(N2) 또는 헬륨(He)인 것이 바람직하다. 퍼지(즉, 퍼징 가스 펄스) 또는 다른 반응물 제가 단계가 개입하는 경우, 하나의 단계는 일반적으로 또 다른 단계를 곧바로 뒤따르는 것으로 간주된다.
기판이 제1 증기 상 반응물(즉, 할로겐 비함유 금속 전구체) 및 제2 증기 상 반응물(즉, 치환된 하이드라진 전구체)과 교대로 접촉되는 증착 주기는 목적하는 두께의 금속막이 증착될 때까지 2회 이상 반복될 수 있다. 본 발명의 일부 구현예에서, 기판과 제1 증기 상 반응물 및 제2 상 반응물과 접촉하는 순서는, 기판이 우선 제2 증기 상 반응물과 접촉하고 이어서 제1 증기 상 반응물과 접촉하는 순서일 수 있는 것으로 이해되어야 한다. 또한, 일부 구현예에서, 순환 증착 공정은 기판이 제1 증기 상 반응물과 1회 이상 접촉하고 이어서 기판이 제2 증기 상 반응물과 1회 이상 접촉하는 것을 포함할 수 있으며, 유사하게 대안적으로 기판이 제2 증기 상 반응물과 1회 이상 접촉하고 이어서 기판이 제1 증기 상 반응물과 1회 이상 접촉하는 것을 포함할 수 있다. 또한, 본 발명의 일부 구현예는 비-플라즈마 반응물을 포함하도록 제1 증기 상 반응물 및 제2 증기 상 반응물을 선택하는 단계를 포함할 수 있으며, 예를 들면, 제1 및 제2 증기 상 반응물은 이온화된 반응성 화학종을 실질적으로 함유하지 않는다. 일부 구현예에서, 제1 및 제2 증기 상 반응물은 이온화된 반응성 화학종, 여기된 화학종 또는 라디칼 화학종을 실질적으로 함유하지 않는다. 예를 들면, 하부 기판의 이온화 손상 및 관련 결함을 방지하기 위해, 제1 증기 상 반응물 및 제2 증기 상 반응물은 둘 다 비-플라즈마 반응물을 포함할 수 있다.
할로겐 비함유 금속 전구체 및 치환된 하이드라진 전구체를 이용하여 금속막을 형성하는 본원에 기재된 순환 증착 공정은 가열된 기판을 갖는 ALD 또는 CVD 증착 시스템에서 수행될 수 있다. 예를 들면, 일부 구현예에서, 방법은 기판을 대략 80°C와 대략 140°C 사이의 온도로 가열하는 단계, 또는 심지어 기판을 대략 80와 대략 120°C 사이의 온도로 가열하는 단계를 포함할 수 있다. 물론, 임의의 주어진 순환 증착 공정, 예를 들면 ALD 반응에 대한 적절한 온도 범위(window)는 관련된 표면 종결부 및 반응물 화학종에 좌우될 것이다. 본원에서, 온도는 사용되는 전구체에 따라 상이하며 일반적으로 약 700°C 또는 그 이하이고, 일부 구현예에서, 증착 온도는 증기 증착 공정에서 일반적으로 약 100°C 또는 그 이상이고, 일부 구현예에서, 증착 온도는 약 100°C와 약 250°C 사이이고, 일부 구현예에서, 증착 온도는 약 120°C와 약 200°C 사이이다. 일부 구현예에서, 증착 온도는 약 500°C 미만, 약 400°C 미만 또는 약 300°C 미만이다. 일부 예에서, 예를 들면 수소를 포함하는 반응물 또는 환원제와 같은 추가의 반응물 또는 환원제가 공정에 사용되는 경우 증착 온도는 약 200°C 미만, 약 150°C 미만 또는 약 100°C 미만일 수 있다. 일부 예에서 증착 온도는 약 20°C 초과, 약 50°C 초과 및 약 75°C 초과일 수 있다.
본원에 기재된 구현예들 중 일부에 따라 증착된 금속막을 포함하는 박막은 금속막을 포함하는 연속 박막일 수 있다. 일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 금속막을 포함하는 박막은 약 100 nm 미만, 약 60 nm 미만, 약 50 nm 미만, 약 40 nm 미만, 약 30 nm 미만, 약 25 nm 미만, 또는 약 20 nm 미만 또는 약 15 nm 미만 또는 약 10 nm 미만 또는 약 5 nm 미만 또는 그 이하의 두께에서 연속성일 수 있다. 본원에서 지칭하는 연속성(continuity)은 물리적으로 연속성이거나 전기적으로 연속성일 수 있다. 일부 구현예에서, 막이 물리적으로 연속성일 수 있는 두께는 막이 전기적으로 연속성인 두께와 동일하지 않을 수 있으며, 막이 전기적으로 연속성일 수 있는 두께는 막이 물리적으로 연속성인 두께와 동일하지 않을 수 있다.
일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 금속막을 포함하는 박막은 연속적일 수 있는 한편, 일부 구현예에서, 금속막을 포함하는 불연속 박막, 또는 금속막을 포함하는 개별 아일랜드(island) 또는 나노입자를 포함하는 박막을 형성하는 것이 요망될 수 있다. 일부 구현예에서, 금속막을 포함하는 증착된 박막은 실질적으로 또 다른 것과 물리적 또는 전기적으로 연속되지 않으며 구리, 니켈 또는 코발트를 포함하는 나노입자를 포함할 수 있다. 일부 구현예에서, 금속막을 포함하는 증착된 박막은 금속막을 포함하는 개별 나노입자, 또는 개별 아일랜드를 포함할 수 있다.
일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 금속막을 포함하는 박막은 약 100 nm 미만의 두께에서 약 20 μΩcm 미만의 전기 비저항을 가질 수 있다. 일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 금속막을 포함하는 박막은 약 60 nm 미만, 약 50 nm 미만, 약 40 nm 미만, 약 30 nm 미만, 약 25 nm 미만, 또는 약 20 nm 미만 또는 그 이하의 두께에서 약 20 μΩcm 미만의 전기 비저항을 가질 수 있다. 일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 금속막을 포함하는 박막은 약 60 nm 미만, 약 50 nm 미만, 약 40 nm 미만, 약 30 nm 미만, 약 25 nm 미만, 또는 약 20 nm 미만 또는 그 이하의 두께에서 약 15 μΩcm 미만의 전기 비저항을 가질 수 있다. 일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 금속막을 포함하는 박막은 약 60 nm 미만, 약 50 nm 미만, 약 40 nm 미만, 약 30 nm 미만, 약 25 nm 미만, 또는 약 20 nm 미만 또는 그 이하의 두께에서 약 10 μΩcm 미만의 전기 비저항을 가질 수 있다.
일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 금속막을 포함하는 박막은 약 30 nm 미만, 약 20 nm 미만, 약 15 nm 미만, 약 10 nm 미만, 약 8 nm 미만, 또는 약 5 nm 또는 그 이하의 두께에서 약 200 μΩcm 미만의 전기 비저항을 가질 수 있다.
일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 금속성 박막은 약 100 nm 미만의 두께에서 약 200 μΩcm 미만, 약 100 μΩcm 미만, 약 50 μΩcm 미만, 약 30 μΩcm 미만, 약 20 μΩcm 미만, 약 18 μΩcm 미만, 약 15 μΩcm 미만, 약 12 μΩcm 미만, 약 10 μΩcm 미만 또는 약 8 μΩcm 미만의 전기 비저항을 가질 수 있다.
일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 구리를 포함하는 박막은 약 100 nm 미만의 두께에서 약 200 μΩcm 미만, 약 100 μΩcm 미만, 약 50 μΩcm 미만, 약 30 μΩcm 미만, 약 20 μΩcm 미만, 약 18 μΩcm 미만, 약 15 μΩcm 미만, 약 12 μΩcm 미만, 약 10 μΩcm 미만, 약 8 μΩcm 미만, 또는 약 5 μΩcm 미만 또는 그 이하의 전기 비저항을 가질 수 있다. 일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 구리를 포함하는 박막은 약 50 nm 미만의 두께에서 약 20 μΩcm 미만, 약 18 μΩcm 미만, 약 15 μΩcm 미만, 약 12 μΩcm 미만, 약 10 μΩcm 미만, 약 8 μΩcm 미만, 또는 약 5 μΩcm 미만 또는 그 이하의 전기 비저항을 가질 수 있다. 본 발명의 일부 구현예에서, 금속막(예를 들면, 구리막)의 형성 단계는 대략 4 μΩ-cm 미만의 전기 비저항, 또는 3 μΩ-cm 미만의 전기 비저항, 또는 심지어 2 μΩ-cm 미만의 전기 비저항을 갖는 금속막을 형성하는 단계를 포함할 수 있다. 비제한적인 예로서, 구리막은 본 발명의 방법에 의해 대략 1.92 μΩ-cm의 전기 비저항을 갖도록 대략 50 나노미터의 두께로 형성될 수 있다.
일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 니켈 또는 코발트를 포함하는 박막은 약 100 nm 미만의 두께에서 약 200 μΩcm 미만, 약 100 μΩcm 미만, 약 50 μΩcm 미만, 약 30 μΩcm 미만, 약 20 μΩcm 미만, 약 18 μΩcm 미만, 약 15 μΩcm 미만, 약 12 μΩcm 미만, 약 10 μΩcm 미만 또는 약 8 μΩcm 미만의 전기 비저항을 가질 수 있다. 일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 니켈 또는 코발트를 포함하는 박막은 약 50 nm 미만의 두께에서 약 20 μΩcm 미만, 약 18 μΩcm 미만, 약 15 μΩcm 미만, 약 12 μΩcm 미만, 약 10 μΩcm 미만, 약 8 μΩcm 미만의 전기 비저항을 가질 수 있다.
일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 구리, 니켈 또는 코발트를 포함하는 박막은 결정질 또는 다결정질일 수 있다. 일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 구리, 니켈 또는 코발트를 포함하는 박막은 입방 결정 구조일 수 있다. 일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 구리, 니켈 또는 코발트를 포함하는 박막은 약 20 nm 내지 약 100 nm의 두께를 가질 수 있다. 일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 구리, 니켈 또는 코발트를 포함하는 박막은 약 20 nm 내지 약 60 nm의 두께를 가질 수 있다. 일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 구리, 니켈 또는 코발트를 포함하는 박막은 약 20 초과, 약 30 nm 초과, 약 40 nm 초과, 약 50 nm 초과, 약 60 nm 초과, 약 100 nm 초과, 약 250 nm 초과, 약 500 nm 초과, 또는 그 이상의 두께를 가질 수 있다. 일부 구현예에서, 본원에 기재된 구현예들 중 일부에 따라 증착된 구리, 니켈 또는 코발트를 포함하는 박막은 약 50 nm 미만, 약 30 nm 미만, 약 20 nm 미만, 약 15 nm 미만, 약 10 nm 미만, 약 5 nm 미만의 두께를 가질 수 있거나, 일부 예에서, 예를 들면 구리, 니켈 또는 코발트를 포함하는 불연속 막 또는 개별 입자 또는 아일랜드가 요망되는 경우 구리, 니켈 또는 코발트의 양은 약 5 nm 미만, 약 3 nm 미만, 약 2nm 미만 또는 약 1nm 미만의 두께에 해당한다.
일부 구현예에서, 금속막의 성장 속도는 약 0.005 Å/주기 내지 약 5 Å/주기, 약 0.01 Å/주기 내지 약 2.0 Å/주기이다. 일부 구현예에서, 금속막의 성장 속도는 약 0.05 Å/주기 초과, 약 0.1 Å/주기 초과, 약 0.15 Å/주기 초과, 약 0.20 Å/주기 초과, 약 0.25 Å/주기 초과 또는 약 0.3 Å/주기 초과이다. 일부 구현예에서, 금속막의 성장 속도는 약 2.0 Å/주기 미만, 약 1.0 Å/주기 미만, 약 0.75 Å/주기 미만, 약 0.5 Å/주기 미만 또는 약 0.3 Å/주기 미만이다.
일부 구현예에서, 구리, 니켈 또는 코발트를 포함하는 박막은 약 20 원자% 미만, 약 10 원자% 미만, 약 7 원자% 미만, 약 5 원자% 미만, 약 3 원자% 미만, 약 2 원자% 미만, 또는 약 1 원자% 미만의 불순물, 즉, Cu, Ni 또는 Co 이외의 원소 또는 목적하는 금속막의 금속을 포함할 수 있다. 일부 구현예에서, 구리, 니켈 또는 코발트를 포함하는 박막은 약 20 원자% 미만, 약 10 원자% 미만, 약 5 원자% 미만, 약 2 원자% 미만, 또는 약 1 원자% 미만의 수소를 포함한다. 일부 구현예에서, 구리, 니켈 또는 코발트를 포함하는 박막은 약 10 원자% 미만, 약 5 원자% 미만, 약 2 원자% 미만, 약 1 원자% 미만 또는 약 0.5 원자% 미만의 탄소를 포함할 수 있다. 일부 구현예에서, 구리, 니켈 또는 코발트를 포함하는 박막은 약 5 원자% 미만, 약 2 원자% 미만, 약 1 원자% 미만, 약 0.5 원자% 미만, 또는 약 0.2 원자% 미만의 질소를 포함할 수 있다. 일부 구현예에서, 구리, 니켈 또는 코발트를 포함하는 박막은 약 15 원자% 미만, 약 10 원자% 미만, 약 5 원자% 미만, 약 3 원자% 미만, 약 2 원자% 미만, 또는 약 1 원자% 미만의 산소를 포함할 수 있다. 일부 구현예에서, 구리, 니켈 또는 코발트를 포함하는 박막은 상기 구리, 니켈 또는 코발트의 표면에 평균 약 30 원자% 미만, 약 20 원자% 미만, 약 20 원자% 미만, 약 5 원자% 미만, 또는 약 3 원자% 미만의 산소를 포함할 수 있으며, 이때 표면은 최상부 표면으로부터 약 20 nm 미만의 두께인 것으로 이해될 수 있다. 일부 구현예에서, 구리, 니켈 또는 코발트를 포함하는 박막은 화학양론적 또는 비-화학양론적 산화구리, 산화니켈 또는 산화코발트를 재료의 최상부 표면 가까이에 포함할 수 있다. 일부 구현예에서, 구리, 니켈 또는 코발트를 포함하는 박막은 약 80 원자% 초과, 약 90 원자% 초과, 약 93 원자% 초과, 약 95 원자% 초과, 약 97 원자% 초과, 또는 약 99 원자% 초과의 구리, 니켈 또는 코발트를 포함할 수 있다. 비제한적인 예로서, 도 4는 본 발명의 구현예에 따라 형성된 구리막의 비행시간 탄성 반동 검파 분석(TOF-ERDA)을 나타내는 그래프를 예시한다.
본 발명의 구현예에 따라 형성된 금속막은 구리, 코발트 및 니켈 중 하나를 포함할 수 있다. 본 발명의 일부 구현예에서, 형성된 금속막은 구리, 코발트 및 니켈 중 하나로 필수적으로 이루어질 수 있다. 예를 들면, 비제한적이고 예시적인 구현예로서, 본 발명의 방법에 따라 형성된 금속막은 95.0 원자 % 초과, 또는 97.0 원자 % 초과, 또는 98.0 원자 % 초과, 또는 99.0 원자 % 초과, 또는 심지어 99.5 원자 % 초과의 구리 원소 조성을 갖는 구리를 포함할 수 있다. 일부 구현예에서, 구리 표면은 산화될 수 있으며 위의 값들은 표면 산화가 없는 벌크 막 값들을 나타낸다. 본원에 개요된 구현예에서, 원소의 원자 농도는 러더퍼드 후방산란(Rutherford backscattering)(RBS) 또는 비행시간 탄성 반동 검파 분석(TOF-ERDA)을 이용하여 결정될 수 있다. X-선 광전자 분광법(XPS)과 같은 다른 방법이 사용되는 경우 원자 농도가 변할 수 있다.
일부 구현예에서, 구리, 니켈 또는 코발트를 포함하는 박막은 3차원 구조로 증착될 수 있다. 일부 구현예에서, 구리, 니켈 또는 코발트를 포함하는 박막의 단차 도포성(step coverage)은, 약 2 초과, 약 5 초과, 약 10 초과, 약 25 초과, 약 50 초과 또는 약 100 초과의 종횡비(높이/너비)를 갖는 구조에서, 약 50% 이상, 약 80% 이상, 약 90% 이상, 약 95% 이상, 약 98% 이상 또는 약 99% 이상일 수 있다.
본 발명의 일부 구현예에서, 본원에 기재된 방법으로 형성된 금속막은 목적하는 결정학적 특성을 가질 수 있다. 예를 들면, 비제한적이고 예시적인 구현예로서, 금속막은 구리로 필수적으로 이루어질 수 있으며 구리막은 우세한 (111) 결정학적 배향을 갖는 입방 결정 구조를 포함할 수 있다. 보다 구체적으로, 도 1은 다양한 증착 온도에서 할로겐 비함유 금속 전구체 및 알킬-하이드라진 전구체를 이용하여 본 발명의 ALD 공정에 의해 형성된 비제한적 예인 금속성 구리막의 2 세타 X-선 회절(XRD) 스캔을 나타내는 그래프이다. 예를 들면, 라벨 100으로 표지된 XRD 스캔은 140의 기판 온도에서 Cu(dmap)2 및 3급부틸하이드라진을 이용하는 ALD에 의해 형성된 구리막으로부터 얻어진다. 라벨 100으로 표지된 XRD 스캔은, 본 발명의 방법에 의해 형성된 구리막이 (111) 및 (200)을 포함하고 (111) 결정학적 배향이 우세한 다수의 결정학적 배향을 포함할 수 있음을 나타낸다. 따라서, 본 발명의 일부 구현예에서, 본원에 기재된 ALD 공정에 의해 형성된 금속막은 (111) 결정학적 배향을 포함하고, 일부 구현예에서, 금속막은 우세한 (111) 결정학적 배향을 포함한다.
일부 구현예에서, 금속막을 포함하는 증착된 박막에는 증착 후 처리 공정이 수행될 수 있다. 일부 구현예에서, 당해 처리 공정은, 예를 들면, 금속막을 포함하는 증착된 박막의 전도도 또는 연속성을 향상시킬 수 있다. 일부 구현예에서, 처리 공정은 예를 들면 어닐링 공정을 포함할 수 있다. 일부 구현예에서, 금속막을 포함하는 박막은 진공 또는 하나 이상의 어닐링 가스, 예를 들면 수소를 포함하는 환원 가스와 같은 환원 가스를 포함하는 분위기에서 어닐링될 수 있다. 일부 구현예에서, 금속막은 진공 또는 어닐 가스에서의, 예를 들면 환원 가스에서의, 승온에서, 예를 들면 금속막 증착 반응 온도에서의 질소 및 어닐/처리를 포함할 수 있으며, 질소를 환원시킬 수 있거나 질소를 금속막으로부터 거의 완전히 제거할 수 있다. 일부 구현예에서, 환원 가스로의 처리는 매 주기마다, n번째 주기(이때 n은 1, 2, 3, 4, 9, 19, 49 또는 99 주기 이상일 수 있다)마다 적용되거나, 후처리로서 금속막 증착 후에 적용된다. 질소를 포함하는 금속막은 처리되기 전에는 약 60 원자% 미만, 약 50 원자% 미만, 약 40 원자% 미만, 약 30 원자% 미만, 약 20 원자% 미만, 약 10 원자% 미만, 또는 약 5 원자% 미만의 질소를 포함할 수 있다. 일부 구현예에서, 처리된 후의 금속막은 약 20 원자% 미만, 약 10 원자% 미만, 약 5 원자% 미만, 약 2 원자% 미만, 약 1 원자% 미만, 약 0.5 원자% 미만, 또는 약 0.2 원자% 미만의 질소를 포함할 수 있다.
본원에 기재된 순환 증착 공정에 의해 형성된 금속막은 반도체 디바이스 구조체의 형성과 같은 다양한 상황에 이용될 수 있다.
당업자는 본원에 기재된 공정이 FinFET와 같은 다중 게이트 트랜지스터 뿐만 아니라 평면 디바이스를 포함하는 트랜지스터 제조를 포함하는 다수의 상황에 적용 가능함을 이해할 것이다.
비제한적인 예로서, 도 2를 참조하여, 반도체 디바이스 구조체(200)는 기판(202), 장벽층(204), 유전층(206), 씨드층(208) 및 충전층(210)을 포함할 수 있는 배선 구조체를 포함할 수 있다. 본 발명의 교시에 따라, 씨드층(208)은 본원에 기재된 순환 증착 공정에 의해 형성된 금속성 구리막과 같은 금속막을 포함할 수 있다.
보다 구체적으로는, 반도체 디바이스 구조체(200)는 기판(202)을 포함할 수 있으며, 이때 기판(202)은 기판(202)에 형성된 디바이스 회로 부품(도시되어 있지 않음)을 포함하는 실리콘 재료를 포함할 수 있다. 장벽층(204)은 실리콘 카바이드, 실리콘 나이트라이드, 실리콘 옥시카바이드 및 실리콘 옥시나이트라이드와 같은 식각 저지층(etch stop layer)을 포함할 수 있다. 유전층(206)은 실리콘 다이옥사이드, 실리콘 나이트라이드, 중합체계 재료 및 탄소 풍부 유전체와 같은 중간층 유전체 재료를 포함할 수 있다.
본 발명의 일부 구현예에서, 반도체 디바이스 구조체(200)는 씨드층(208)을 포함할 수 있으며, 이때 씨드층은 본원에 기재된 순환 증착 공정에 의해 형성된 구리로 필수적으로 이루어진다. 씨드층은 대략 20 나노미터 미만, 또는 대략 10 나노미터 미만, 또는 심지어 대략 5 나노미터 미만의 두께로 형성될 수 있다. 또한 씨드층은 대략 50 μΩ-cm 미만, 대략 20 μΩ-cm 미만, 대략 10 μΩ-cm 미만, 대략 5 μΩ-cm 미만, 대략 4 μΩ-cm 미만의 전기 비저항, 또는 3 μΩ-cm 미만의 전기 비저항, 또는 심지어 2 μΩ-cm 미만의 전기 비저항을 갖도록 형성될 수 있다.
본 발명의 구현예는 본 발명의 금속막을 형성하도록 구성된 반응 시스템을 또한 포함할 수 있다. 보다 구체적으로는, 도 3은 소정의 압력, 온도, 및 주변 조건하에 기판(도시되지 않음)을 유지하기 위한, 그리고 다양한 가스에 기판을 선택적으로 노출시키기 위한 메커니즘을 추가로 포함하는 반응 챔버(302)를 포함하는 반응 시스템(300)을 도식적으로 예시한다. 전구체 반응물 공급원(304)은 도관 또는 다른 적절한 수단(304A)에 의해 반응 챔버(302)에 연결될 수 있고, 매니폴드, 밸브 제어 시스템, 질량 유량 제어 시스템, 또는 전구체 반응물 공급원(304)으로부터 유래되는 가스 전구체를 제어하기 위한 메커니즘에 추가로 연결될 수 있다. 전구체 반응물 공급원(304)에 의해 공급되는 전구체(도시되지 않음), 반응물(도시되지 않음)은 실온 및 표준 대기압 조건하에 액체 또는 고체일 수 있다. 이러한 전구체는, 전구체 공급원 챔버 내에서 증기화 온도 또는 그 이상으로 유지될 수 있는 반응물 공급원 진공 밸브 내에서 증기화될 수 있다. 이러한 구현예에서, 기화된 전구체는 캐리어 가스(예컨대, 비활성 또는 불활성 가스)와 함께 이동된 다음 도관(304A)을 통해 반응 챔버(302) 내로 공급될 수 있다. 다른 구현예에서, 전구체는 표준 조건 하의 증기일 수 있다. 이러한 구현예에서, 전구체는 증기화될 필요가 없으며, 캐리어 가스를 요구하지 않을 수 있다. 예를 들면, 일 구현예에서, 전구체는 가스 실린더 내에 저장될 수 있다. 반응 시스템(300)은 추가의 전구체 반응물 공급원을 또한 포함할 수 있으며, 이러한 전구체 반응물 공급원(306)은 또한 본원에 기재된 바와 같이 도관(306A)에 의해 반응 챔버로 연결될 수 있다.
퍼지 가스 공급원(308)은 도관(308A)을 통해 반응 챔버(302)로 연결될 수 있으며, 다양한 불활성 또는 비활성(noble) 가스를 반응 챔버(302)로 선택적으로 공급하여 반응 챔버로부터 전구체 가스 또는 폐가스를 제거하는 것을 돕는다. 공급될 수 있는 다양한 불활성 또는 비활성 가스는 고체, 액체 또는 저장된 기체 형태로부터 유래될 수 있다.
도 3의 반응 시스템(300)은 또한, 반응 시스템(300)에 포함된 밸브, 매니폴드, 펌프 및 기타 설비를 선택적으로 조작하기 위한 전자 회로 및 기계적 부품을 제공하는 시스템 조작 및 제어 메커니즘(310)을 포함할 수 있다. 이러한 회로 및 부품을 조작하여, 각각의 전구체 공급원(304, 306) 및 퍼지 가스 공급원(308)으로부터 전구체, 퍼지 가스를 도입한다. 시스템 조작 및 제어 메커니즘(310)은 가스 펄스 순서의 시점, 기판과 반응 챔버의 온도, 및 반응 챔버의 압력, 및 반응 시스템(300)의 적절한 조작을 제공하는데 필요한 다양한 기타 조작들을 또한 제어한다. 조작 및 제어 메커니즘(310)은 반응 챔버(302) 내외로의 전구체, 반응물 및 퍼지 가스의 유동을 제어하기 위한 제어 소프트웨어 및 전기적 또는 공기압 제어 밸브를 포함할 수 있다. 제어 시스템은 소프트웨어 또는 하드웨어 구성 요소, 예를 들어 특정 작업을 수행하는 FPGA 또는 ASIC와 같은 모듈을 포함할 수 있다. 유리하게는, 모듈은 제어 시스템의 어드레스 가능한 저장 매체에 탑재되어 하나 이상의 공정을 실행하도록 구성될 수 있다.
관련 기술분야의 당업자는 상이한 수 및 종류의 전구체 반응물 공급원 및 퍼지 가스 공급원을 포함하는 본 반응 시스템의 다른 구성이 가능함을 이해한다. 또한, 당업자는 가스를 반응 챔버(302) 내로 선택적으로 공급하는 목적을 달성하는데 사용될 수 있는 밸브, 도관, 전구체 공급원, 퍼지 가스 공급원의 다수의 배열이 존재함을 이해할 것이다. 또한, 반응 시스템의 도식적 표현으로서, 도면의 단순화를 위해 다수의 부품이 생략되어 있으며, 이러한 부품들은 예를 들면 다양한 밸브, 매니폴드, 정화기, 가열기, 용기, 벤트, 및/또는 우회로를 포함할 수 있다.
위에 기재된 본 개시의 구현예들은 본 발명의 구현예들의 예시일 뿐이기 문에 이들 구현예들은 첨부된 청구범위 및 그의 법적 등가물에 의해 정의되는 본 발명의 범주를 제한하지 않는다. 임의의 등가적인 구현예들은 본 발명의 범주 내에 있도록 의도된다. 확실하게, 본원에 도시되고 기재된 것 외에도, 기재된 요소들의 선택적인 유용한 조합과 같은 본 개시의 다양한 변경은 설명으로부터 당업자에게 분명할 수 있다. 이러한 변경 및 구현예들도 첨부된 청구범위의 범주 내에 있는 것으로 의도된다.
Claims (20)
- 순환 증착에 의해 기판 상에 금속막을 형성하는 방법으로서,
구리, 니켈 또는 코발트 중 적어도 하나를 포함하는 할로겐 비함유 금속 전구체를 포함하는 제1 반응물과 상기 기판을 접촉시키는 단계; 및
탄화수소 치환된 하이드라진 전구체를 포함하는 제2 반응물과 상기 기판을 접촉시키는 단계를 포함하며,
상기 제2 반응물과 상기 기판을 접촉시키는 단계는 상기 제1 반응물과 상기 기판을 접촉시키는 단계 직후에 수행되거나, 또는 상기 제1 반응물과 상기 기판을 접촉시키는 단계 후에 개입되는 퍼지 직후에 수행되며,
상기 탄화수소 치환된 하이드라진 전구체는 적어도 4 개의 탄소 원자의 분지쇄 알킬기 또는 적어도 4 개의 탄소 원자의 알킬기의 2급-(sec-) 또는 3급-(tert-) 이성체를 포함하는, 방법. - 제1항에 있어서, 상기 순환 증착이 원자층 증착을 포함하는, 방법.
- 제1항에 있어서, 상기 순환 증착이 순환 화학적 증기 증착을 포함하는, 방법.
- 제1항에 있어서, C4-C10 탄화수소기를 포함하도록 상기 치환된 탄화수소 하이드라진 전구체를 선택하는 단계를 추가로 포함하는, 방법.
- 제1항에 있어서, 방향족 탄화수소기를 포함하도록 상기 치환된 탄화수소 하이드라진 전구체를 선택하는 단계를 추가로 포함하는, 방법.
- 제1항에 있어서, 3급부틸 알킬기를 포함하도록 상기 치환된 탄화수소 하이드라진 전구체를 선택하는 단계를 추가로 포함하는, 방법.
- 제6항에 있어서, 메틸, 에틸 또는 3급부틸 알킬기 중 적어도 하나를 포함하도록 상기 알킬기를 선택하는 단계를 추가로 포함하는, 방법.
- 제1항에 있어서, 적어도 하나의 두자리 리간드를 포함하도록 상기 할로겐 비함유 금속 전구체를 선택하는 단계를 추가로 포함하는, 방법.
- 제1항에 있어서, 적어도 하나의 산소 원자와 적어도 하나의 질소 원자를 통해 금속 원자에 결합되는 적어도 하나의 리간드를 포함하도록 상기 할로겐 비함유 금속 전구체를 선택하는 단계를 추가로 포함하는, 방법.
- 제1항에 있어서, 적어도 두 개의 할로겐 비함유 리간드를 포함하도록 상기 할로겐 비함유 금속 전구체를 선택하는 단계를 추가로 포함하는, 방법.
- 제1항에 있어서, Cu(dmap)2, Ni(dmap)2 또는 Co(dmap)2 중 적어도 하나를 포함하도록 상기 할로겐 비함유 금속 전구체를 선택하는 단계를 추가로 포함하는, 방법.
- 제1항에 있어서, 상기 방법이, 상기 기판이 상기 제1 반응물 및 상기 제2 반응물과 교대로 순차적으로 접촉되는 적어도 1회의 증착 주기를 포함하는, 방법.
- 제12항에 있어서, 상기 증착 주기가 2회 이상 반복되는, 방법.
- 제1항에 있어서, 10 μΩ-cm 미만의 전기 비저항을 갖도록 상기 금속막을 형성하는 단계를 추가로 포함하는, 방법.
- 제1항에 있어서, 50 nm 미만의 막 두께에서 10 μΩ-cm 미만의 전기 비저항을 갖도록 상기 금속막을 형성하는 단계를 추가로 포함하는, 방법.
- 제1항에 있어서, 상기 기판을 500 ℃ 미만의 온도로 가열하는 단계를 추가로 포함하는, 방법.
- 제1항에 있어서, 상기 기판을 50 ℃ 초과의 온도로 가열하는 단계를 추가로 포함하는, 방법.
- 제1항에 있어서, 비-플라즈마 반응물을 포함하도록 상기 제1 반응물 및 상기 제2 반응물을 선택하는 단계를 추가로 포함하는, 방법.
- 제1항에 있어서, 구리, 코발트 또는 니켈 중 적어도 하나를 포함하도록 상기 금속막을 선택하는 단계를 추가로 포함하는, 방법.
- 제1항의 방법을 수행하도록 구성된 반응 시스템.
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JP2023022121A (ja) | 2023-02-14 |
US10468262B2 (en) | 2019-11-05 |
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