CN109285765A - 沉积iv族半导体的方法及相关的半导体器件结构 - Google Patents
沉积iv族半导体的方法及相关的半导体器件结构 Download PDFInfo
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- CN109285765A CN109285765A CN201810594778.8A CN201810594778A CN109285765A CN 109285765 A CN109285765 A CN 109285765A CN 201810594778 A CN201810594778 A CN 201810594778A CN 109285765 A CN109285765 A CN 109285765A
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Abstract
公开了一种在衬底的表面上沉积IV族半导体的方法。所述方法可包括:在反应室内提供衬底并加热衬底至沉积温度。所述方法可还包括:暴露衬底于至少一种IV族前体和暴露衬底于至少一种IIIA族掺杂剂前体;其中所述至少一种IIIA族掺杂剂前体包含硼氢化物、有机硼氢化物、卤化物或有机卤化物。还提供了包含通过本公开的方法沉积的IV族半导体的半导体器件结构。
Description
相关专利申请的交叉引用
本公开要求2017年7月19日提交并且标题为“沉积IV族半导体的方法及相关的半导体器件结构(A METHOD FOR DEPOSITING A GROU P IV SEMICONDUCTOR AND RELATEDSEMICONDUCTOR DEVIC E STRUCTURES)”的美国临时专利申请第62/534,618号的权益,该临时专利申请以引用方式并入本文。
技术领域
本公开一般涉及沉积IV族半导体的方法及相关的半导体器件结构。本公开还一般涉及掺杂IV族半导体的方法及可用于IV族半导体的p-型掺杂的掺杂前体。
背景技术
半导体器件结构如互补金属氧化物半导体(CMOS)器件的微缩化已带来集成电路速度和密度的显著改善。然而,常规的器件微缩化面临着未来技术节点的巨大挑战。
一种改善半导体器件性能的方法是利用应变诱导效应提高载流子迁移率,并因此提高晶体管驱动电流。例如,已经表明,在采用应力源区如晶体管结构的源极和漏极区中采用的应力源区的p-沟道硅(Si)晶体管中,空穴迁移率可大大提高。
与半导体器件结构的有源区的接触电阻可能是未来技术节点下不断进行的器件改进的一个关注点。例如,对于CMOS器件结构,接触电阻可包括接触结构与包含晶体管结构的源极和漏极区的一个或多个应力源区之间的电阻。就n-型MOS器件而言,应力源区可包含掺杂有磷或砷的高掺杂区,即具有大约5×1020cm-3 的载流子密度。在n-型MOS器件应力源区中可实现的高掺杂水平可能导致低至0.3mΩ-cm的接触电阻率。然而,对于p-型MOS器件,现有技术集中于利用硼掺杂剂前体如乙硼烷(B2H6)的硼p-型掺杂的使用上。p-型MOS器件中乙硼烷(B2H6)的使用可导致大约1×1020cm-3的载流子密度。通过添加另外的硼来增加p-型MOS器件中的p-型载流子密度的努力可能导致掺杂应力源区的结晶质量的下降并可能不会显著贡献于p-型应力源区中的有源载流子密度。因此,需要能够在半导体材料如IV族半导体材料中实现高p-型掺杂密度的替代方法和前体。
发明内容
根据本公开的至少一个实施方案,公开了一种在半导体的表面上沉积IV族半导体的方法。所述方法可包括:在反应室内提供衬底,加热衬底至沉积温度,暴露衬底于至少一种IV族前体,和暴露衬底于至少一种IIIA族掺杂剂前体,其中所述至少一种IIIA族掺杂剂前体包含硼氢化物、有机硼氢化物、卤化物或有机卤化物。本公开的实施方案还可包括半导体器件结构,其可包含通过本公开的方法沉积的IV族半导体。
为了概述本发明和所取得的优于现有技术的优点,本发明的某些目的和优点已在上文描述。当然,应理解,未必所有这些目的或优点都可根据本发明的任何特定实施方案取得。因此,举例来说,本领域技术人员应认识,本发明可以将取得或优化如本文所教导或建议的一个优点或一组优点的方式实施或进行而不一定取得如本文可能教导或建议的其他目的或优点。
所有这些实施方案均意在包括在所公开的本发明的范围内。通过下文结合附图对某些实施方案的详细描述,这些及其他实施方案对于本领域技术人员将是显而易见的,本发明不限于所公开的任何特定实施方案。
附图说明
尽管本说明书以具体地指出并且明显地要求被视为本发明实施例的部分的权利要求结束,但是当结合附图阅读时,可以从本公开实施例的某些实例的描述中更容易地确定本公开实施例的优势,在附图中:
图1示意了工艺流程图,该图示意了根据本公开的实施方案的一种示例性沉积方法;和
图2示意了包含根据本公开的实施方案沉积的p-型掺杂IV族半导体的半导体器件结构的示意图。
应理解,图中的元件仅为简单和清晰起见示意而不一定按比例绘制。举例来说,图中的一些元件的尺寸可能相对于其他元件被放大以帮助改善对所示意的本公开实施方案的理解。
具体实施方式
尽管下文公开了某些实施方案和实施例,但本领域技术人员应理解,本发明延伸到所具体公开的实施方案和/或本发明用途以及显而易见的修改和其等同物之外。因此,预期本发明所公开的范围不应受下文描述的具体公开实施方案的限制。
如本文所用,术语“衬底”可指可使用的或上面可形成器件、电路或膜的任何一种或多种下层材料。
如本文所用,术语“IV族半导体”可指包含碳(C)、硅(Si)、锗(Ge)、锡(Sn)中的至少之一或它们的合金的半导体材料。
如本文所用,术语“IIIA族掺杂剂前体”可指包含硼(B)、铝(Al)、镓(Ga)或铟(In)中的至少之一的掺杂剂前体。
本公开的实施方案可包括沉积IV族半导体的方法,特别是沉积包含I IIA族掺杂剂的IV族半导体的方法。作为本公开的实施方案的一个非限制性实例,所述方法可包括沉积包含IIIA族掺杂剂的IV族半导体层,所述掺杂剂例如为包含硼(B)、铝(Al)、镓(Ga)或铟(In)中的至少之一的掺杂剂。本公开的方法利用新型IIIA族掺杂剂前体,其可实现高的有源载流子浓度,例如高达高于大约1×1020cm-3 的有源载流子浓度。本公开的方法还可利用新型IIIA族掺杂剂前体来在IV族半导体中取得高的有源p-型载流子浓度,所述新型IIIA族掺杂剂前体包括IIIA族掺杂剂前体如硼氢化物、有机硼氢化物、卤化物或有机卤化物中的一种或多种。本文描述的用于在IV族半导体中取得高的有源p-型载流子浓度的新型IIIA族掺杂剂前体不仅可提供高的载流子浓度,而且可保持IV族半导体的结晶质量。例如,I V族半导体最常利用乙硼烷(B2H6)来掺杂硼。然而,向应力源区添加硼,例如向硅锗应力源区添加硼,可能减小由应力源区施加的总应变,导致载流子迁移率的减小并因此降低半导体器件性能。本文所述的新型IIIA族掺杂剂还允许与半导体器件结构如晶体管结构的电接触电阻的减小。
可结合图1理解本公开的方法,该图示意了用于形成IV族半导体的方法的一个非限制性实例实施方案。例如,图1可示意用于形成IV族半导体的方法100,其可包括工艺模块110,其中可向反应室中提供衬底并可在所述反应室内加热衬底至沉积温度。作为非限制性实例,反应室可以包含化学气相沉积系统的反应室。本公开的实施方案可在可以名称Intrepi dTMXP或得自ASM International N.V.的化学气相沉积系统中进行。然而,还预期可采用其他反应室如原子层沉积反应室和来自其他制造商的替代的化学气相沉积系统来执行本公开的实施方案。
在本公开的一些实施方案中,衬底可包括平面衬底或图案化衬底。图案化衬底可包括这样的衬底,其可包含形成于衬底中或衬底表面上的半导体器件结构,例如图案化衬底可包含部分制造的半导体器件结构如晶体管和存储元件。衬底可以含有单晶表面和/或一个或多个次表面,所述次表面可以包含非单晶表面,如多晶表面和非晶表面。单晶表面可包含例如以下中的一种或多种:硅(Si)、硅锗(SiGe)、锗锡(GeSn)或锗(Ge)。多晶或非晶表面可包含电介质材料,如氧化物、氮氧化物或氮化物,包括例如氧化硅和氮化硅。
继续参考图1,方法100可通过在反应室内加热衬底至所需沉积温度来继续。在本公开的一些实施方案中,方法100可包括加热衬底至低于大约700℃的温度、或至低于大约600℃的温度、或至低于大约500℃的温度、或至低于大约400℃的温度、或甚至至低于大约300℃的温度。例如,在本公开的一些实施方案中,加热衬底至沉积温度可包括加热衬底至大约280℃和大约700℃之间的温度。
在衬底被加热至所需沉积温度后,方法100可通过暴露衬底于一种或多种沉积前体来继续,所述沉积前体可包含一种或多种用于沉积IV族半导体的前体并还可包含一种或多种用于掺杂IV族半导体以一种或多种p-型掺杂剂的前体。
因此,本公开的方法可包括暴露衬底于至少一种IV族前体,如图1的工艺模块120所示意。在一些实施方案中,暴露衬底于至少一种IV族前体可还包括选择所述至少一种IV族前体为以下之一:甲硅烷(SiH4)、乙硅烷(Si2H6)、丙硅烷(Si3H8)、丁硅烷(Si4H10)、异戊硅烷(Si5H12)、新戊硅烷(Si5H12)、二氯硅烷(DCS)、甲锗烷(GeH4)、乙锗烷(Ge2H6)、丙锗烷(Ge3H8)、甲锗烷基硅烷(GeH6Si)、四氯化锡(SnCl4)或甲基硅烷(CH3-SiH3)。
在一些实施方案中,可在沉积工艺过程中采用单一IV族前体,例如,当待沉积的IV族半导体包含硅(Si)或锗(Ge)时可采用单一IV族前体。在一些实施方案中,可在沉积工艺过程中采用两种或更多种IV族前体,例如当待沉积的IV族半导体包含IV族半导体合金时可采用两种或更多种IV族前体,包括但不限于硅锗碳化物(Si1-x-yGexCy)、锗锡(Ge1-xSnx)、锗硅锡(Ge1-x-ySixSny)、锗硅锡碳化物(Ge1-x-ySixSnyCx)、硅锡(Si1-xSnx)、硅锡碳化物(Si1-x- ySnxCy)或硅碳化物(Si1-xCx)。
沉积IV族半导体的沉积工艺还可包括暴露衬底于至少一种IIIA族掺杂剂前体。例如,在本公开的一些实施方案中,如图1中所示意的沉积方法100可包括暴露衬底于至少一种IV族前体,同时还暴露衬底于至少一种IIIA族掺杂剂前体,即IV族前体和IIIA族掺杂剂前体共同流入反应室中并在设置于反应室内的衬底的表面上反应/分解。可利用所述一种或多种IV族前体和所述一种或多种IIIA族掺杂剂前体向反应室中的共同流入来使掺杂剂物质可随IV族半导体的沉积引入到IV族半导体中。
在一些实施方案中,暴露衬底于至少一种IIIA族掺杂剂前体可包括暴露衬底于硼氢化物、有机硼氢化物、卤化物或有机卤化物中的至少之一。
在本公开的一些实施方案中,暴露衬底于至少一种IIIA族掺杂剂前体可包括暴露衬底于至少一种或多种硼氢化物,包括硼氢化镓(Ga(BH4)3)、硼氢化铝(Al(BH4)3)或硼氢化铟(In(BH4)3)。在本公开的替代实施方案中,暴露衬底于至少一种IIIA族掺杂剂前体可包括选择硼氢化物以包含具有式YxM(BH4)3-x的硼氢化物,其中Y独立地选自氢、氘、氯、溴和碘;M为IIIA族金属,独立地选自镓、铝和铟;x为0-2的整数。
在本公开的一些实施方案中,暴露衬底于至少一种IIIA族掺杂剂前体可包括暴露衬底于一种或多种具有通式RxM(BH4)3-x的有机硼氢化物,其中R独立地选自CH3、C2H5、C6H5、CF3SO3和NH2;M为IIIA族金属,独立地选自镓、铝和铟;x为1-3的整数。
在本公开的一些实施方案中,暴露衬底于至少一种IIIA族掺杂剂前体可包括暴露衬底于一种或多种具有通式ZxMY3-x的卤化物,其中Z独立地选自氢、氘、氯、溴和碘;M为IIIA族金属,独立地选自镓、铝和铟;Y为卤化物,独立地选自氯、溴和碘;x为0-3的整数。在本公开的一些实施方案中,卤化物掺杂剂可包含二聚体结构,因此方法可包括选择卤化物以包含具有式(ZxMY3-x)2的卤化物,其中Z独立地选自氢、氘、氯、溴和碘;M为IIIA族金属,独立地选自镓、铝和铟;Y为卤化物,独立地选自氯、溴和碘;x为0-3的整数。
在本公开的一些实施方案中,暴露衬底于至少一种IIIA族掺杂剂前体可包括选择IIIA族掺杂剂以包含一种或多种有机卤化物并可还包括选择所述一种或多种有机卤化物以包含具有通式RxMY3-x的有机卤化物,其中R独立地选自CH3、C2H5、C6H5、CF3SO3和NH2;M为IIIA族金属,独立地选自镓、铝和铟;Y为卤化物,独立地选自氯、溴和碘;x为0-3的整数。
选择包含有机组分的IIIA族掺杂剂前体在IV族半导体的沉积中可能是进一步有益的。例如,向IV族半导体中引入碳可进一步增大正沉积的I V族半导体中的应变。因此,在本公开的一些实施方案中,暴露衬底于至少一种IIIA族前体还包括暴露衬底于有机硼氢化物或有机卤化物中的至少之一。在其他实施方案中,暴露衬底于有机硼氢化物或有机卤化物中的至少之一还包括向沉积的IV族半导体中引入碳,IV族半导体中碳的原子百分数(at-%)大于大约0.5%at-%。
在本公开的一些实施方案中,可向沉积的IV族半导体中引入两种或更多种掺杂剂物质。例如,在一些实施方案中,暴露衬底于至少一种IIIA族掺杂剂前体还包括暴露衬底于硼氢化物或有机硼氢化物中的至少之一。在采用硼氢化物或有机硼氢化物的实施方案中,除了另一种IIIA族掺杂剂(例如,镓、铝或铟)外,掺杂剂前体还含有硼(B)。因此,采用硼氢化物或有机硼氢化物包括向沉积的IV族半导体中引入硼掺杂剂和另一种III A族掺杂剂。可采用这样的方法来进一步增大IV族半导体中的掺杂剂浓度而不相应降低IV族半导体的结晶质量。
本公开的实施方案可以图1的工艺模块140继续,其中可在设置于反应室内的衬底的表面上沉积IV族半导体。在一些实施方案中,在衬底的表面上沉积IV族半导体包括沉积硅(Si)、锗(Ge)、硅锗(Si1-xGex)、硅锗碳化物(Si1-x-yGexCy)、锗锡(Ge1-xSnx)、锗硅锡(Ge1-x- ySixSny)、锗硅锡碳化物(Ge1-x-ySixSnyCx)、硅锡(Si1-xSnx)、硅锡碳化物(Si1-x-ySnxCy)或硅碳化物(Si1-xCx)中的至少之一。
本公开的方法允许以高的p-型掺杂剂浓度沉积IV族半导体而不降低IV族半导体的结晶质量。例如,在一些实施方案中,在衬底的表面上沉积IV族半导体还包括以大于大约1×1020个载流子每立方厘米、或大于大约2.5×1020个载流子每立方厘米、或甚至大于大约5×1020个载流子每立方厘米的掺杂浓度沉积IV族半导体。
本公开的实施方案还可提供包含通过本文所述方法沉积的IV族半导体的半导体器件结构。例如,图2示意了半导体器件结构200的一个非限制性实例,其中半导体器件结构200包含双栅MOSFET,通常称为FinFE T。半导体器件结构200可包含衬底202,其可包括体硅(Si)衬底。衬底202可被掺杂以p-型掺杂剂(对于NMOS型FinFET器件)或掺杂以n-型掺杂剂(对于PMOS型FinFET器件)。在图2的半导体器件结构的非限制性实例中,衬底200可包含n-型掺杂剂并且半导体器件结构200可包括P MOS FinFET。
半导体器件结构200还可包含隔离区204,其可包括浅沟槽隔离(ST I)区。半导体器件结构200还可包含在隔离区204的顶表面上方延伸的鳍结构206。可在鳍结构206的侧壁上方设置栅极电介质(未示出),并且栅极电介质可包含氧化硅或高-k电介质材料。可在栅极电介质上设置栅电极208以提供与鳍结构206内的沟道区的电接触。半导体器件结构200还可包含栅极间隔物210,其设置在栅电极208的侧壁上。
在本公开的一些实施方案中,半导体器件结构200可还包含沉积在Fi nFET器件的源极和漏极区上方的p-型IV族半导体应力源区212A和212B。应指出,p-型应力源区212A和212B可包含由于在鳍结构206的不同小平面上生长速率的差异而可能导致的多个小平面。在本公开的非限制性实例实施方案中,p-型应力源区212A和212B可采用本文描述的本公开的实施方案来沉积。例如,p-型应力源区212A和212B可包含硅锗(Si1-xGe x),其中硅锗应力源区中的锗成分可大于大约x>0.2、或大于大约x>0.50、或大于大约x>0.75、或甚至大约x=1.0。另外,p-型应力源区212A和212B可根据本公开的实施方案掺杂并因此p-型应力源区212A和212B可包含大于大约1×1020个载流子每立方厘米、或大于大约2.5×1020个载流子每立方厘米、或甚至大约大约5×1020个载流子每立方厘米的p-型掺杂浓度。
在本公开的一些实施方案中,可对沉积在图2中所示意的FinFET器件的源极和漏极区上方的p-型IV族半导体应力源区212A和212B作电接触。在一些实施方案中,电接触(未示出)可包含硅化物如硅化钛(TiSi2)。本公开的实施方案允许源极和漏极应力源区212A和212B中高的有源p-型载流子浓度,这又可导致对应力源区的电接触电阻的减小。例如,本公开的方法可包括形成与p-型应力源区212A和212B的电接触,其中所述电接触具有低于1×10-9Ohm.cm2、或低于5×10-9Ohm.cm2、或甚至低于1×10-8Ohm.cm2的电阻率。
应指出,本文给出的一个非限制性实例实施方案涉及形成在FinFET器件的源极和漏极区上方的p-型应力源区。然而,本公开的实施方案可用于其他目的,例如,可采用通过本公开的实施方案沉积的p-型IV族半导体来在器件结构的其他区域中诱导应力,例如通过在晶体管的沟道区上方沉积p-型应力源区来由此直接在晶体管器件结构的沟道区中诱导应变。
上文描述的本公开的实例实施方案不限制本发明的范围,因为这些实施方案仅是本发明的实施方案的实例,本发明由附随的权利要求书及其法定等同物限定。任何等同的实施方案均意在包括在本发明的范围内。实际上,除本文中展示和描述的那些外,本公开的各种修改,如所述元件的替代的可用组合,本领域技术人员可从说明书显而易见。此类修改和实施方案也意在落在附随的权利要求书的范围内。
Claims (18)
1.一种在衬底的表面上沉积IV族半导体的方法,所述方法包括:
在反应室内提供衬底;
加热所述衬底至沉积温度;
暴露所述衬底于至少一种IV族前体;和
暴露所述衬底于至少一种IIIA族掺杂剂前体,其中所述至少一种IIIA族掺杂剂前体包含:硼氢化物、有机硼氢化物、卤化物或有机卤化物中的至少之一。
2.根据权利要求1所述的方法,其中所述至少一种IIIA族掺杂剂前体包含选自以下的硼氢化物:硼氢化镓(Ga(BH4)3)、硼氢化铝(Al(BH4)3)或硼氢化铟(In(BH4)3)。
3.根据权利要求1所述的方法,其中所述至少一种IIIA族掺杂剂前体包含具有通式YxM(BH4)3-x的硼氢化物,其中Y独立地选自氢、氘、氯、溴和碘;M为IIIA族金属,独立地选自镓、铝和铟;x为0-2的整数。
4.根据权利要求1所述的方法,其中所述至少一种IIIA族掺杂剂前体包含具有式RxM(BH4)3-x的有机硼氢化物,其中R独立地选自CH3、C2H5、C6H5、CF3SO3和NH2;M为IIIA族金属,独立地选自镓、铝和铟;x为1-3的整数。
5.根据权利要求1所述的方法,其中所述IIIA族掺杂剂前体包含具有通式ZxMY3-x的卤化物,其中Z独立地选自氢、氘、氯、溴和碘;M为IIIA族金属,独立地选自镓、铝和铟;Y为卤化物,独立地选自氯、溴和碘;x为0-3的整数。
6.根据权利要求5所述的方法,其中所述IIIA族掺杂剂前体包含具有通式(ZxMY3-x)2的卤化物,其中Z独立地选自氢、氘、氯、溴和碘;M为IIIA族金属,独立地选自镓、铝和铟;Y为卤化物,独立地选自氯、溴和碘;x为0-3的整数。
7.根据权利要求1所述的方法,其中所述IIIA族掺杂剂前体包含具有通式RxMY3-x的有机卤化物,其中R独立地选自CH3、C2H5、C6H5、CF3SO3和NH2;M为IIIA族金属,独立地选自镓、铝和铟;Y为卤化物,独立地选自氯、溴和碘;x为0-3的整数。
8.根据权利要求1所述的方法,其中加热所述衬底至沉积温度还包括加热所述衬底至大约280℃和大约700℃之间的温度。
9.根据权利要求1所述的方法,其中暴露所述衬底于至少一种IV族前体还包括选择所述至少一种IV族前体以包含甲硅烷(SiH4)、乙硅烷(Si2H6)、丙硅烷(Si3H8)、丁硅烷(Si4H10)、异戊硅烷(Si5H12)、新戊硅烷(Si5H12)、二氯硅烷(DCS)、甲锗烷(GeH4)、乙锗烷(Ge2H6)、丙锗烷(Ge3H8)、甲锗烷基硅烷(GeH6Si)、四氯化锡(SnCl4)或甲基硅烷(CH3-SiH3)。
10.根据权利要求1所述的方法,其中在所述衬底的表面上沉积IV族半导体还包括沉积以下中的至少之一:硅(Si)、锗(Ge)、硅锗(Si1-xGex)、硅锗碳化物(Si1-x-yGexCy)、锗锡(Ge1- xSnx)、锗硅锡(Ge1-x-ySixSny)、锗硅锡碳化物(Ge1-x-ySixSnyCx)、硅锡(Si1-xSnx)、硅锡碳化物(Si1-x-ySnxCy)或硅碳化物(Si1-xCx)。
11.根据权利要求1所述的方法,其中在所述衬底的表面上沉积IV族半导体还包括以大于大约1×1020个载流子每立方厘米的掺杂浓度沉积所述IV族半导体。
12.根据权利要求1所述的方法,其中暴露所述衬底于至少一种IIIA族掺杂剂前体还包括暴露所述衬底于有机硼氢化物或有机卤化物中的至少之一。
13.根据权利要求12所述的方法,其中暴露所述衬底于有机硼氢化物或有机卤化物中的至少之一还包括向所述沉积的IV族半导体中引入碳,所述IV族半导体中碳的原子百分数大于大约0.5at-%。
14.根据权利要求1所述的方法,其中暴露所述衬底于至少一种IIIA族掺杂剂前体还包括暴露所述衬底于硼氢化物或有机硼氢化物中的至少之一。
15.根据权利要求14所述的方法,其中暴露所述衬底于硼氢化物或有机硼氢化物中的至少之一还包括向所述沉积的IV族半导体中引入硼掺杂剂和另外一种IIIA族掺杂剂。
16.一种半导体器件结构,所述半导体器件结构包含根据权利要求1所述的方法沉积的IV族半导体。
17.根据权利要求16所述的半导体器件结构,其中所述IV族半导体包含p-型应力源区。
18.根据权利要求17所述的半导体器件结构,所述半导体器件结构还包括形成与所述p-型应力源区的电接触,其中所述电接触具有低于1×10-8Ohm.cm2的电阻率。
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KR20200130652A (ko) | 2019-05-10 | 2020-11-19 | 에이에스엠 아이피 홀딩 비.브이. | 표면 상에 재료를 증착하는 방법 및 본 방법에 따라 형성된 구조 |
JP2020188255A (ja) | 2019-05-16 | 2020-11-19 | エーエスエム アイピー ホールディング ビー.ブイ. | ウェハボートハンドリング装置、縦型バッチ炉および方法 |
JP2020188254A (ja) | 2019-05-16 | 2020-11-19 | エーエスエム アイピー ホールディング ビー.ブイ. | ウェハボートハンドリング装置、縦型バッチ炉および方法 |
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US11004977B2 (en) | 2021-05-11 |
US20190027605A1 (en) | 2019-01-24 |
US20200083375A1 (en) | 2020-03-12 |
KR20190009697A (ko) | 2019-01-29 |
US10541333B2 (en) | 2020-01-21 |
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