CN101093804A - 半导体元件的形成方法 - Google Patents

半导体元件的形成方法 Download PDF

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CN101093804A
CN101093804A CNA2007101011855A CN200710101185A CN101093804A CN 101093804 A CN101093804 A CN 101093804A CN A2007101011855 A CNA2007101011855 A CN A2007101011855A CN 200710101185 A CN200710101185 A CN 200710101185A CN 101093804 A CN101093804 A CN 101093804A
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聂俊峰
陈建豪
顾克强
李资良
陈世昌
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体元件的形成方法。此方法包括提供半导体基板，形成栅极介电层于半导体基板上，形成栅极于栅极介电层之上，形成应力源于邻近栅极边缘的半导体基板中，且在形成应力源程序后布植杂质。此杂质较佳选自下列组成的组：IV族元素、惰性元素、氟、氮及上述的组合。

Description

半导体元件的形成方法
技术领域
本发明涉及半导体元件，特别涉及金-氧半导体元件的结构及其形成方法。
背景技术
近数十年来，半导体行业持续致力于缩小元件尺寸，增加半导体元件的速度、效能、密度以及降低单位成本。根据晶体管的设计及其内部特性，若调整栅极下方的源/漏极间的通道长度可改变通道区的电阻，由此影响晶体管的效能。特别是，缩短通道长度可降低晶体管中源极至漏极的电阻，因此当其他参数维持一定时，可增加源/漏极间的电流。
为了进一步增进MOS元件的效能，可对MOS元件中的通道施加应力，以增加载子的迁移效率。一般来说，最好对NMOS元件的通道区施加源极至漏极方向的张应力，且对PMOS元件的通道区施加源极至漏极方向的压应力。
目前半导体行业通常在源/漏极区成长SiGe应力源以对PMOS元件的通道区施加压应力。其方法包括形成栅极堆迭于半导体基板上，形成栅极间隙壁于栅极堆迭的侧壁，形成凹槽于硅基板中并对准栅极间隙壁，磊晶成长SiGe应力源于凹槽中。因为SiGe的晶格晶距比硅大，因此其可对源极SiGe应力源及漏极SiGe应力源间的通道区施加压应力。
发明内容
本发明提供一种半导体元件的形成方法，包括提供半导体基板，形成栅极介电层于半导体基板之上，形成栅极于该栅极介电层之上，形成间隙壁于邻接栅极的边缘的半导体基板中，以及在形成该应力源后布植杂质，其中该杂质选自下列组成的组：IV族元素、惰性元素、氟、氮及上述的组合。
本发明还提供一种半导体元件的形成方法，包括提供半导体基板，形成栅极介电层于该半导体基板之上，形成栅极于该栅极介电层之上，形成虚设间隙壁于该栅极及该栅极介层的边缘，沿着该虚设间隙壁的侧壁形成凹槽于该半导体基板中，磊晶成长SiGe于该凹槽中，以形成SiGe应力源，移除该虚设间隙壁，布植杂质于该SiGe应力源中，形成轻掺杂源/漏极区邻接该栅极；形成间隙壁于该栅极及该栅极介层的边缘，以及形成源/漏极区邻接该栅极。
本发明还提供一种半导体元件，包括半导体基板，栅极介电层，于该半导体基板之上，栅极，于该栅极介电层之上，以及SiGe应力源于邻接栅极的边缘的半导体基板中，此SiGe应力源包括p型杂质及含额外杂质的布植区，其中此额外杂质选自下列组成的组：氮、氟、IV族元素、惰性元素及上述组合。
本发明通过在形成应力源后形成布植区，可有效降低MOS元件的漏电流。
为了让本发明的上述和其他目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附图示作详细说明。
附图说明
图1显示栅极堆迭形于基板100之上。
图2显示毯覆形成虚设层。
图3显示图案化毯覆氧化层及氮化层以形成栅极间隙壁。
图4显示形成磊晶区。
图5显示移除间隙壁及硬式罩幕层。
图6显示形成轻掺杂源/漏极区。
图7显示形成间隙壁。
图8显示布植p型杂质及形成硅化区。
图9显示本发明可有效改善漏电流的情况。
附图主要符号说明
100～基板；4～栅极；2～栅极介电层；6～硬式罩幕；10～毯覆氧化层；12～氮化层；14～栅极间隙壁；16～凹槽；18～磊晶区；19～布植区；D1、D2～深度；20～界面；22～箭头；24～轻掺杂源/漏极区；25～口袋/晕状区；26～间隙壁；28～重源/漏极区；T2、T1～厚度；30～硅化区；40、42～线。
具体实施方式
本发明提供一种含SiGe应力源的PMOS元件的形成方法。参照图1，栅极堆迭形于基板100之上，其较佳为硅或其他公知材质，如硅上绝缘层(SOI)。在一实施例中，可使用低锗硅比的SiGe基板。形成浅沟槽隔离区以隔离各元件区。此栅极堆迭包括栅极4于栅极介电层2之上。此栅极堆迭较佳以硬式罩幕6作为罩幕，其材质可为氧化物、氮化硅、氮氧化硅及上述的组合。
参照图2，毯覆形成虚设层。在一较佳实施例中，虚设层包括毯覆氧化层10及氮化层12。在另一实施例中，虚设层包括单层或复合层，其较佳包括氧化物、氮化硅、氮氧化硅和/或其他介电材质。此虚设层可以公知的技术形成，例如，电浆蚀刻化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)、次大气压化学气相沉积(SACVD)等。
参照图3，图案化毯覆氧化层10及氮化层12以形成栅极间隙壁14，因此栅极间隙壁包括毯覆氧化部分及氮化部分。接着，沿着栅极间隙壁14形成凹槽16于基板100中，较佳为异向性蚀刻。在90nm工艺中，凹槽16的深度较佳介于约500至1000之间，更佳介于约700至900。
参照图4，以选择性磊晶成长半导体材料，较佳为SiGe，于凹槽16中以形成磊晶区18。半导体材料的晶格间距(lattice spacing)大于基板100。在磊晶成长时，可掺杂适合的杂质，但也可不掺杂。在一较佳实施例中，基板100为硅基板，SiGe成长于凹槽16中。在另一较佳实施例中，基板100包括SiGe，磊晶区18的锗含量较佳大于基板100，因此磊晶区18的晶格间隔大于基板的晶格间距。磊晶区18可对通道施加压应力。上述的磊晶区18以下亦称为SiGe应力源18。
参照图5，移除间隙壁14及硬式罩幕层6。在一实施例中，通过磷酸蚀刻来移除间隙壁14及硬式罩幕6的氮化硅区，且以稀释的氢氟酸来移除间隙壁14的毯覆氧化区。
以布植程序22形成布植区19。在一较佳实施例中，布植IV族元素，例如，碳、硅及锗。在另一实施例中，使用惰性气体，例如，氖、氩、氪、氙和/或氡。在另一实施例中，可布植氮和/或氟。应注意的是，不适当的布植会破坏SiGe应力源18产生的通道应力，且必须非常小心控制布植的能量及剂量。布植区的深度D1较佳小于SiGe应力源18的深度D2，且更佳小于SiGe应力源18深度的50％，因此不会破坏SiGe应力源18及下方基板100间的界面20接合。此外，深度D1较佳大于后续形成的轻源/漏极区及口袋/晕状区的深度，虽然D1深度亦可更深或更浅。此布植能量较佳小于约4keV，更佳介于约2keV至4keV之间，且布植剂量较佳介于约1E14/cm2至1E15/cm2之间，更佳介于5E14/cm2至7E14/cm2。因此，布植杂质的浓度小于约1E21/cm3，更佳介于1E20/cm3至5E20/cm3之间。
此外，上述所列的掺杂物，例如，碳，会降低晶格间距，而减少通道区的应力。因此，布植掺杂物的含量较佳小于锗含量。在一实施例中，布植区19中的布植掺杂物的浓度与锗浓度的比例小于约0.5％，较佳小于约0.1％。
一般而言，在布植NMOS区的源/漏极区时，较佳进行一预非晶化布植(以下简称PAI)以降低掺杂物通道效应(dopant channeling effect)，且可增加掺杂物活性。如果使用相同的掺杂物，则SiGe应力源的布植较佳与NOMS的PAI同时进行。
参照图6所示，形成轻掺杂源/漏极区24。较佳以p型杂质，如硼和/或铟布植于基板100及SiGe应力源18中，另以一n型杂质，如磷和/或砷形成口袋/晕状区25。由于形成轻掺杂源/漏极区24与口袋/晕状区25的方法为公知技术，在此不再赘述，且本领域技术人员知道，形成轻掺杂源/漏极区24与布植区19的次序可颠倒。此外，在移除虚设间隙壁14前可先形成布植区19，使布植区19实质上位于SiGe应力源18内。
参照图7，形成间隙壁26。毯覆形成毯覆氧化层及氮化层。图案化氧化层及氮化层以形成间隙壁26。间隙壁26较佳具有厚度T2，且厚度T2较佳大于虚设间隙壁14的厚度T1(参照图4)，但厚度T2也可相同或小于T1。
参照图8，较佳布植p型杂质，例如，硼和/或铟来形成深源/漏极区28。且深源/漏极区28实质上对准间隙壁26的边缘。图8也显示形成硅化区30，硅化区30较佳先沉积薄金属层，例如，钛、钴、镍、钨或其类似物于元件之上，包括SiGe应力源18及栅极4的曝露表面。接着，加热此基板使金属与硅接触的地方产生硅化反应。在硅化反应后，硅化物金属层形成于硅与金属之间，并选择性移除未反应的金属。
在形成SiGe应力源后形成布植区可有效地降低PMOS元件的漏电流。图9显示本发明可有效改善漏电流的情况。X轴表示以不同材质、结构、方位所形成的多个元件。Y轴表示漏电流。线40为未形成布植区于SiGe应力源的传统元件。线42为形成布植区于SiGe应力源上的元件，其中多个42表示以不同的布植种类、能量及剂量所形成的元件。结果显示，当于SiGe应力源形成布植区时，漏电流可改善约1倍以上，但其机制仍不明了，有可能与改善SiGe应力源表面有关。若SiGe应力源表面粗糙，具有凸出部分与凹陷部分，且若其粗糙的程度够大，则其后续形成的硅化物(或锗-硅化物)会趋向SiGe应力源的表面形态。形成于SiGe凹陷部分的硅化物接近于源/漏极的接合区，可能是造成漏电流的主因。通过布植程序，可减少凸出部分与凹陷部分的垂直距离，且凹陷部分可趋近于凸出部分(同时凸出部分也趋近于凹陷部分)。因此可降低漏电流的情况。
此外，于SiGe应力源上进行布植程序也可减少漏极引发能障下降效应(drain-induced barrier lowering，DIBL)。实验结果显示，当有布植碳于SiGe应力源的MOS元件时，能障下降效应比未布植的MOS元件小。在栅极尺寸约0.65μm时，可减少约10mV或6％的能障下降效应。
虽然本发明已以较佳实施例公开如上，但其并非用以限定本发明，本领域技术人员在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围应以所附的权利要求书所确定的范围为准。

Claims (16)

1.一种半导体元件的形成方法，包括
提供半导体基板；
形成栅极介电层于该半导体基板之上；
形成栅极于该栅极介电层之上；
形成应力源于邻近该栅极边缘的半导体基板中，以及
在形成该应力源后布植杂质，其中该杂质选自下列组成的组：IV族元素、惰性元素、氟、氮及上述的组合。
2.如权利要求1所述的半导体元件的形成方法，其中该半导体基板为PMOS元件，且该应力源包括SiGe。
3.如权利要求1所述的半导体元件的形成方法，其中杂质包括碳。
4.如权利要求1所述的半导体元件的形成方法，其中该布植程序的能量小于约4 keV。
5.如权利要求1所述的半导体元件的形成方法，其中该布植程序的剂量介于约1E14/cm2至1E14/cm2之间。
6.如权利要求1所述的半导体元件的形成方法，其中该杂质布植至一深度，且该深度小于应力源的深度。
7.如权利要求6所述的半导体元件的形成方法，其中该杂质的深度小于该应力源深度的50％。
8.如权利要求1所述的半导体元件的形成方法，还包括：
形成轻掺杂源/漏极区于该应力源的一部分中；
形成n型口袋/晕状区，以及
形成重掺杂源/漏极区于该应力源的至少一部分中。
9.如权利要求8所述的半导体元件的形成方法，其中该应力源形成之后，再形成该轻掺杂源/漏极区。
10.如权利要求8所述的半导体元件的形成方法，其中该应力源形成之前，先形成该轻掺杂源/漏极区。
11.一种半导体结构，包括
半导体基板；
栅极介电层，形成于该半导体基板上；
栅极，形成于该栅极介电层上，以及
应力源，形成于邻接栅极边缘的半导基板中，其中该应力源包括杂质布植区，其中该杂质选自下列组成的组：氮、氟、IV族元素、惰性元素及上述组合。
12.如权利要求11所述的半导体结构，还包括n型口袋/晕状区于该半导体基板中，以及轻掺杂源/漏极区与重掺杂源/漏极区于该应力源的至少一部分中。
13.如权利要求11所述的半导体结构，其中该杂质包括碳。
14.如权利要求11所述的半导体结构，该杂质的深度小于该应力源的深度。
15.如权利要求14所述的半导体结构，其中该杂质的深度小于该应力源深度的50％。
16.如权利要求14所述的半导体结构，其中该杂质选自下列组成的组：碳、硅、锗、氮、氟、氖、氩、氪、氙、氡及上述的组合。
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