JP2006332337A - 半導体装置及びその製造方法 - Google Patents
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- 239000012535 impurity Substances 0.000 claims abstract description 33
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- 229910052732 germanium Inorganic materials 0.000 claims abstract description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 78
- 238000000034 method Methods 0.000 claims description 14
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
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- 238000001459 lithography Methods 0.000 description 1
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- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
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- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Abstract
【解決手段】上記の課題を解決した半導体装置は、半導体基板の第1の導電型領域上に絶縁膜を介して形成されたゲート電極と、前記ゲート電極の側面に形成された第1の側壁と、前記第1の側壁の側面に形成された第2の側壁と、前記第2の側壁の下方に形成され、第2の導電型の第1の不純物層を含み、ゲルマニウムを含む半導体層と、前記第2の側壁の外側の領域に形成され、前記第1の不純物層より多量の第2の導電型不純物を含む第2の不純物層と、前記第2の不純物層上に形成されたシリサイド層とを具備する。
【選択図】図1
Description
本発明の第1の実施形態は、CMOS半導体装置のpMOSのソース/ドレイン・エクステンションにSiGeを使用し、さらにソース/ドレイン及びソース/ドレイン・エクステンションをチャネル領域よりも高くしたエレベーテッド構造の半導体装置及びその製造方法である。pMOSのソース/ドレイン・エクステンションにSiGeを使用することで、pMOSのチャネル領域に圧縮応力を与え、チャネルのキャリア(すなわち、ホール)の移動度を大きくすることができる。さらに、ソース/ドレイン及びソース/ドレイン・エクステンションをエレベーテッド構造とすることで、実効的なこれらの接合深さを浅くできる。その結果、pMOSの動作速度を早くすることができる。
第1の実施形態の変形例の一例を図5に示す。この変形例では、pMOSのソース/ドレイン・エクステンション34のドーピングを、SiGe層32の選択エピタキシャル成長時に、例えば、ホウ素(B)を同時にドープすることによって行う。このドープトSiGe層32を使用すると、ソース/ドレイン・エクステンション34の接合深さは、SiGe層32の厚さと等しくなる。この場合には、pMOSでは、第1の実施形態の工程(4)で行ったソース/ドレイン・エクステンション形成のためのイオン注入を省略することができる。
第1の実施形態の他の1つの変形例を図6に示す。第1の実施形態では、図1に示したように、pMOSのソース/ドレイン42上に形成したシリサイド層44−1が、ソース/ドレイン・エクステンション34と接触しない構造を説明した。しかし、図6に示したように、シリサイド層44−1を厚くする等により、シリサイド層44−1の一部とソース/ドレイン・エクステンション34とを接触させた構造とすることもできる。
本発明の第2の実施形態の半導体装置の断面構造の一例を図7に示す。本実施形態は、第1の実施形態と同様にpMOSのソース/ドレイン・エクステンション34にSiGe層32を使用したエレベーテッド構造であるが、pMOS、nMOSともにソース/ドレイン42、242は、凹みに形成したリセスト構造の半導体装置である。
本発明の第3の実施形態の半導体装置の断面構造の一例を図9に示す。本実施形態は、第1の実施形態とほぼ同様であるが、pMOSのソース/ドレイン・エクステンション34にSiGe層32を使用するがエレベーテッド構造とせずに、ソース/ドレイン42、242だけをエレベーテッド構造とした半導体装置である。
本発明の第4の実施形態の半導体装置の断面構造の一例を図10に示す。本実施形態は、第2の実施形態とほぼ同様であるが、pMOSのソース/ドレイン・エクステンション34にSiGe層32を使用するがエレベーテッド構造とせず、ソース/ドレイン42、242をリセスト構造とした半導体装置である。
Claims (5)
- 半導体基板の第1の導電型領域上に絶縁膜を介して形成されたゲート電極と、
前記ゲート電極の側面に形成された第1の側壁と、
前記第1の側壁の側面に形成された第2の側壁と、
前記第2の側壁の下方に形成され、第2の導電型の第1の不純物層を含み、ゲルマニウムを含む半導体層と、
前記第2の側壁の外側の領域に形成され、前記第1の不純物層より多量の第2の導電型不純物を含む第2の不純物層と、
前記第2の不純物層上に形成されたシリサイド層と
を具備することを特徴とする半導体装置。 - 前記半導体層は、シリコン・ゲルマニウムであることを特徴とする請求項1に記載の半導体装置。
- 前記半導体層の表面は、前記半導体基板の表面より上方に位置すること特徴とする請求項1若しくは2に記載の半導体装置。
- 前記第2の不純物層の表面は、前記半導体基板の表面と異なる高さに位置することを特徴とする請求項1ないし3のいずれか1に記載の半導体装置。
- 半導体基板の第1の導電型領域上に絶縁膜を介してゲート電極を形成する工程と、
前記ゲート電極の側面に第1の側壁を形成する工程と、
前記第1の側壁の外側の領域に第1の溝を形成する工程と、
前記第1の溝にゲルマニウムを含む半導体層を形成する工程と、
前記半導体層に第2の導電型不純物を添加して第1の不純物層を形成する工程と、
前記半導体層上で、前記第1の側壁の側面に第2の側壁を形成する工程と、
前記第2の側壁の外側の領域の前記半導体層を除去して第2の溝を形成する工程と、
前記第2の側壁の外側の領域に前記第1の不純物層より多量の前記第2の導電型不純物を添加して第2の不純物層を形成する工程と、
前記第2の不純物層上にシリサイド層を形成する工程と、
を具備することを特徴とする半導体装置の製造方法。
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JP2005153948A JP4630728B2 (ja) | 2005-05-26 | 2005-05-26 | 半導体装置及びその製造方法 |
US11/199,380 US7372099B2 (en) | 2005-05-26 | 2005-08-09 | Semiconductor device and its manufacturing method |
CNB2006100878420A CN100461456C (zh) | 2005-05-26 | 2006-05-26 | 半导体器件及其制造方法 |
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JP2007165817A (ja) * | 2005-11-18 | 2007-06-28 | Sony Corp | 半導体装置およびその製造方法 |
WO2008102448A1 (ja) * | 2007-02-22 | 2008-08-28 | Fujitsu Microelectronics Limited | 半導体装置と半導体装置の製造方法 |
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US10269961B2 (en) | 2009-06-12 | 2019-04-23 | Sony Corporation | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions |
US10535769B2 (en) | 2009-06-12 | 2020-01-14 | Sony Corporation | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions |
US10854751B2 (en) | 2009-06-12 | 2020-12-01 | Sony Corporation | Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions |
JP2012054587A (ja) * | 2011-10-24 | 2012-03-15 | Toshiba Corp | 半導体装置の製造方法 |
JP2015084440A (ja) * | 2014-12-17 | 2015-04-30 | ソニー株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
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US20060270133A1 (en) | 2006-11-30 |
CN100461456C (zh) | 2009-02-11 |
CN1870295A (zh) | 2006-11-29 |
US7372099B2 (en) | 2008-05-13 |
JP4630728B2 (ja) | 2011-02-09 |
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