JP2008251688A - 半導体装置及びその製造装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims description 23
- 238000002955 isolation Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 4
- 230000006835 compression Effects 0.000 abstract description 3
- 238000007906 compression Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 75
- 239000010409 thin film Substances 0.000 description 16
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 238000001039 wet etching Methods 0.000 description 9
- 238000001459 lithography Methods 0.000 description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L29/66409—Unipolar field-effect transistors
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Abstract
【解決手段】 Siチャネルを有する第1のpMISFET領域121、Siチャネルを有する第2のpMISFET領域122、及びSiチャネルを有するnMISFET領域123を備えた半導体装置であって、第1のpMISFET領域121に、Siチャネルを挟んで該Siチャネルに第1の圧縮歪みを与える第1のSiGe層321が埋め込み形成され、第2のpMISFET領域122に、Siチャネルを挟んで該Siチャネルに第1の圧縮歪みとは大きさの異なる第2の圧縮歪みを与える第2のSiGe層322が埋め込み形成されている。
【選択図】 図1
Description
米国特許公報6621131号
図1は、本発明の第1の実施形態に係わる半導体装置の概略構成を示す断面図である。
図6は、本発明の第2の実施形態に係わる半導体装置の概略構成を示す断面図である。なお、図1と同一部分には同一符号を付して、その詳しい説明は省略する。
Si開口率=Si開口領域面積/(Si開口領域+SiO2 領域面積)
と定義した。また、不純物としてBをドープした場合も同様の結果が得られた。
なお、本発明は上述した各実施形態に限定されるものではない。実施形態では、SiGe層の一例としてSiGeB膜を用いたが、SiGeB膜の代わりにSiGeC膜を用いても良い。つまり、SiGe層は勿論のこと、SiGeに不純物をドープしたものを用いることができる。
110…素子分離絶縁膜
121…第1のpMISFET領域
122…第2のpMISFET領域
123…nMISFET領域
130…ゲート絶縁膜
140…ポリシリコン膜
141…p+ ポリシリコン膜
142…n+ ポリシリコン膜
160…ハードマスク
170,190…薄膜
171,191…側壁膜
181,182,581,582…リセス
210,220,240,250,260…レジストパターン
231…第1のゲート電極パターン
232…第2のゲート電極パターン
233…第3のゲート電極パターン
301…第1のゲート電極
302…第2のゲート電極
303…第3のゲート電極
321…第1のSiGeB膜
322…第2のSiGeB膜
510…回路に寄与しない領域
Claims (5)
- Siチャネルを有する第1のpMISFET領域、Siチャネルを有する第2のpMISFET領域、及びSiチャネルを有するnMISFET領域を備えた半導体装置であって、
前記第1のpMISFET領域に、前記Siチャネルを挟んで該Siチャネルに第1の圧縮歪みを与える第1のSiGe層が埋め込み形成され、
前記第2のpMISFET領域に、前記Siチャネルを挟んで該Siチャネルに前記第1の圧縮歪みとは大きさの異なる第2の圧縮歪みを与える第2のSiGe層が埋め込み形成されていることを特徴とする半導体装置。 - 前記第1及び第2のSiGe層は、それぞれ不純物を含み、Ge濃度又は深さが異なることを特徴とする請求項1記載の半導体装置。
- Si基板上のウエルに素子分離領域を設けることによって、第1のpMISFET領域,第2のpMISFET領域,及びnMISFET領域を形成する工程と、
前記第2のpMISFET領域及びnMISFET領域を覆う第1のマスクを形成する工程と、
前記第1のマスクを用いて、前記第1のpMISFET領域中に、該領域のSiチャネルに対して第1の圧縮歪みを与える第1のSiGe層を選択的に埋め込み形成する工程と、
前記第1のマスクを除去した後に、前記第1のpMISFET領域及びnMISFET領域を覆う第2のマスクを形成する工程と、
前記第2のマスクを用いて、前記第2のpMISFET領域中に、該領域のSiチャネルに対して前記第1の圧縮歪みとは大きさの異なる第2の圧縮歪みを与える第2のSiGe層を選択的に埋め込み形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記第1及び第2のSiGe層を形成する各々の工程として、前記pMISFET領域を選択的にエッチングすることにより該領域のSiチャネルを挟む関係でリセスを形成した後、該リセス内にSiGe層を選択成長することを特徴とする請求項3記載の半導体装置の製造方法。
- Si基板上のウエルに素子分離領域を設けることによって、第1のpMISFET領域,第2のpMISFET領域,及びnMISFET領域を形成する工程と、
前記nMISFET領域を覆うマスクを形成する工程と、
1つのMISFET領域とそれを囲む素子分離絶縁膜を含む1セル領域内で、該セル領域の全体面積に対して基板Siが露出している面積の割合をSi開口率と定義し、前記nMISFET領域を前記マスクで覆った状態で、前記第1のpMISFET領域及び第2のpMISFET領域を各々のSi開口率が異なる条件で選択的にエッチングし、各々の領域のSiチャネルを挟む関係でリセスを形成する工程と、
前記第1のMISFET領域中のリセスに、該領域のSiチャネルに対して第1の圧縮歪みを与える第1のSiGe層を形成し、且つ前記第2のpMISFET領域中のリセスに、該領域のSiチャネルに対して前記第1の圧縮歪みとは大きさの異なる第2の圧縮歪みを与える第2のSiGe層を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。
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JP2007088836A JP4896789B2 (ja) | 2007-03-29 | 2007-03-29 | 半導体装置の製造方法 |
US12/056,909 US8013398B2 (en) | 2007-03-29 | 2008-03-27 | Semiconductor device |
US13/205,950 US8124472B2 (en) | 2007-03-29 | 2011-08-09 | Manufacturing method of a semiconductor device |
US13/569,604 USRE45462E1 (en) | 2007-03-29 | 2012-08-08 | Semiconductor device |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2009164267A (ja) * | 2007-12-28 | 2009-07-23 | Fujitsu Microelectronics Ltd | 半導体装置、半導体装置の製造方法及び半導体装置の設計方法 |
JP2014107546A (ja) * | 2012-11-22 | 2014-06-09 | Samsung Electronics Co Ltd | リセス内のストレッサを有する半導体素子形成方法及びその素子 |
US9768300B2 (en) | 2012-11-22 | 2017-09-19 | Samsung Electronics Co., Ltd. | Semiconductor devices including a stressor in a recess and methods of forming the same |
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JP4635062B2 (ja) | 2008-03-11 | 2011-02-16 | 株式会社東芝 | 半導体装置の製造方法 |
JP5329835B2 (ja) * | 2008-04-10 | 2013-10-30 | 株式会社東芝 | 半導体装置の製造方法 |
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JP2010103142A (ja) * | 2008-10-21 | 2010-05-06 | Toshiba Corp | 半導体装置の製造方法 |
JP2010157570A (ja) * | 2008-12-26 | 2010-07-15 | Toshiba Corp | 半導体装置の製造方法 |
US9041082B2 (en) * | 2010-10-07 | 2015-05-26 | International Business Machines Corporation | Engineering multiple threshold voltages in an integrated circuit |
US9214395B2 (en) * | 2013-03-13 | 2015-12-15 | United Microelectronics Corp. | Method of manufacturing semiconductor devices |
CN103346124B (zh) * | 2013-06-04 | 2015-08-26 | 上海华力微电子有限公司 | 改善半导体器件良率的方法 |
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US10037915B1 (en) | 2017-09-10 | 2018-07-31 | United Microelectronics Corp. | Fabricating method of a semiconductor structure with an epitaxial layer |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006121074A (ja) * | 2004-10-20 | 2006-05-11 | Samsung Electronics Co Ltd | 半導体素子及びその製造方法 |
JP2006253317A (ja) * | 2005-03-09 | 2006-09-21 | Fujitsu Ltd | 半導体集積回路装置およびpチャネルMOSトランジスタ |
JP2006332337A (ja) * | 2005-05-26 | 2006-12-07 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2007036205A (ja) * | 2005-06-22 | 2007-02-08 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2007048788A (ja) * | 2005-08-05 | 2007-02-22 | Toshiba Corp | 半導体装置 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001338988A (ja) * | 2000-05-25 | 2001-12-07 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2001358233A (ja) * | 2000-06-15 | 2001-12-26 | Hitachi Ltd | 半導体集積回路装置および半導体集積回路装置の製造方法 |
US6621131B2 (en) | 2001-11-01 | 2003-09-16 | Intel Corporation | Semiconductor transistor having a stressed channel |
JP2004214607A (ja) * | 2002-12-19 | 2004-07-29 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2005051148A (ja) * | 2003-07-31 | 2005-02-24 | Seiko Epson Corp | 半導体装置の製造方法 |
US7132338B2 (en) | 2003-10-10 | 2006-11-07 | Applied Materials, Inc. | Methods to fabricate MOSFET devices using selective deposition process |
KR100642747B1 (ko) | 2004-06-22 | 2006-11-10 | 삼성전자주식회사 | Cmos 트랜지스터의 제조방법 및 그에 의해 제조된cmos 트랜지스터 |
US7279406B2 (en) * | 2004-12-22 | 2007-10-09 | Texas Instruments Incorporated | Tailoring channel strain profile by recessed material composition control |
JP2006228958A (ja) | 2005-02-17 | 2006-08-31 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2006303451A (ja) | 2005-03-23 | 2006-11-02 | Renesas Technology Corp | 半導体装置及び半導体装置の製造方法 |
US7388278B2 (en) * | 2005-03-24 | 2008-06-17 | International Business Machines Corporation | High performance field effect transistors on SOI substrate with stress-inducing material as buried insulator and methods |
US7358551B2 (en) * | 2005-07-21 | 2008-04-15 | International Business Machines Corporation | Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions |
JP2007200961A (ja) | 2006-01-24 | 2007-08-09 | Sharp Corp | 半導体装置およびその製造方法 |
US7579248B2 (en) * | 2006-02-13 | 2009-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Resolving pattern-loading issues of SiGe stressor |
US7410875B2 (en) * | 2006-04-06 | 2008-08-12 | United Microelectronics Corp. | Semiconductor structure and fabrication thereof |
US7608489B2 (en) * | 2006-04-28 | 2009-10-27 | International Business Machines Corporation | High performance stress-enhance MOSFET and method of manufacture |
US7534689B2 (en) * | 2006-11-21 | 2009-05-19 | Advanced Micro Devices, Inc. | Stress enhanced MOS transistor and methods for its fabrication |
US7525161B2 (en) * | 2007-01-31 | 2009-04-28 | International Business Machines Corporation | Strained MOS devices using source/drain epitaxy |
KR100855977B1 (ko) * | 2007-02-12 | 2008-09-02 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
-
2007
- 2007-03-29 JP JP2007088836A patent/JP4896789B2/ja active Active
-
2008
- 2008-03-27 US US12/056,909 patent/US8013398B2/en not_active Ceased
-
2011
- 2011-08-09 US US13/205,950 patent/US8124472B2/en active Active
-
2012
- 2012-08-08 US US13/569,604 patent/USRE45462E1/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006121074A (ja) * | 2004-10-20 | 2006-05-11 | Samsung Electronics Co Ltd | 半導体素子及びその製造方法 |
JP2006253317A (ja) * | 2005-03-09 | 2006-09-21 | Fujitsu Ltd | 半導体集積回路装置およびpチャネルMOSトランジスタ |
JP2006332337A (ja) * | 2005-05-26 | 2006-12-07 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2007036205A (ja) * | 2005-06-22 | 2007-02-08 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2007048788A (ja) * | 2005-08-05 | 2007-02-22 | Toshiba Corp | 半導体装置 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009164267A (ja) * | 2007-12-28 | 2009-07-23 | Fujitsu Microelectronics Ltd | 半導体装置、半導体装置の製造方法及び半導体装置の設計方法 |
JP2014107546A (ja) * | 2012-11-22 | 2014-06-09 | Samsung Electronics Co Ltd | リセス内のストレッサを有する半導体素子形成方法及びその素子 |
US9741855B2 (en) | 2012-11-22 | 2017-08-22 | Samsung Electronics Co., Ltd. | Semiconductor devices including a stressor in a recess and methods of forming the same |
US9768300B2 (en) | 2012-11-22 | 2017-09-19 | Samsung Electronics Co., Ltd. | Semiconductor devices including a stressor in a recess and methods of forming the same |
Also Published As
Publication number | Publication date |
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JP4896789B2 (ja) | 2012-03-14 |
US20080237732A1 (en) | 2008-10-02 |
US8013398B2 (en) | 2011-09-06 |
US8124472B2 (en) | 2012-02-28 |
USRE45462E1 (en) | 2015-04-14 |
US20110294271A1 (en) | 2011-12-01 |
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