JP2005051148A - 半導体装置の製造方法 - Google Patents
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Abstract
【解決手段】 半導体装置の製造方法は,半導体層10内の高耐圧トランジスタ形成領域100に、第1ウェル20,22となる第1不純物層を形成する工程と、オフセット領域30,32となる第2不純物層を形成する工程と、半導体層に熱処理を施すことによって、第1および第2不純物層の不純物を拡散させ、第1ウェルおよびオフセット領域を形成する工程と、第1ウェルおよびオフセット領域を形成する工程の後に、半導体層内に、素子分離領域110,120,210をトレンチ素子分離法により形成する工程と、高耐圧トランジスタ形成領域100に、第1ゲート絶縁層60,62を形成する工程と、半導体層内の低電圧駆動形成領域200に、第2ウェル24,26を形成する工程と、第2ゲート絶縁層64,66を形成する工程と、高耐圧トランジスタ形成領域100および低電圧駆動形成領域200に、ゲート電極70,72,74,76を形成する工程と、を含む。
【選択図】 図1
Description
半導体層内の高耐圧トランジスタ形成領域に、第1ウェルとなる第1不純物層を形成する工程と、
前記高耐圧トランジスタ形成領域に、オフセット領域となる第2不純物層を形成する工程と、
前記半導体層に熱処理を施すことによって、前記第1および第2不純物層の不純物を拡散させ、前記第1ウェルおよび前記オフセット領域を形成する工程と、
前記第1ウェルおよび前記オフセット領域を形成する工程の後に、前記半導体層内に、素子分離領域をトレンチ素子分離法により形成する工程と、
前記高耐圧トランジスタ形成領域に、第1ゲート絶縁層を形成する工程と、
前記半導体層内の低電圧駆動トランジスタ形成領域に、第2ウェルを形成する工程と、
前記低電圧駆動トランジスタ形成領域に、第2ゲート絶縁層を形成する工程と、
前記高耐圧トランジスタ形成領域および前記低電圧駆動トランジスタ形成領域に、ゲート電極を形成する工程と、を含む。
前記低電圧駆動トランジスタ形成領域には、n型およびp型低電圧駆動トランジスタを形成することができる。
まず、本実施の形態における製造方法によって得られる半導体装置について説明する。図1は、本実施の形態における製造方法によって得られる半導体装置を模式的に示す断面図である。半導体装置は、半導体層10を有する。半導体装置には、高耐圧トランジスタ形成領域100と、低電圧駆動トランジスタ形成領域200とが設けられている。高耐圧トランジスタ形成領域100は、n型高耐圧トランジスタ形成領域100Nと、p型高耐圧トランジスタ形成領域100Pとを有する。低電圧駆動トランジスタ形成領域200は、n型低電圧駆動トランジスタ形成領域200Nと、p型低電圧駆動トランジスタ形成領域200Pとを有する。n型高耐圧トランジスタ形成領域100Nには、n型高耐圧トランジスタ100nが形成され、p型高耐圧トランジスタ形成領域100Pには、p型高耐圧トランジスタ100pが形成されている。同様に、n型低電圧駆動トランジスタ形成領域200Nには、n型低電圧駆動トランジスタ200nが形成され、p型低電圧駆動トランジスタ形成領域200Pには、p型低電圧駆動トランジスタ200pが形成されている。
まず、高耐圧トランジスタ形成領域100について説明する。高耐圧トランジスタ形成領域100と、低電圧駆動トランジスタ形成領域200との境界には、第1素子分離領域110が形成される。すなわち、第1素子分離領域110は、高耐圧トランジスタ形成領域100と、低電圧駆動トランジスタ形成領域200とを分離する。結果的に、高耐圧トランジスタ形成領域100は、第1素子分離領域110に囲まれる。
次に、低電圧駆動トランジスタ形成領域200について説明する。低電圧駆動トランジスタ形成領域200には、n型低電圧駆動トランジスタ200nと、p型低電圧駆動トランジスタ200pとが設けられている。隣り合うn型低電圧駆動トランジスタ200nと、p型低電圧駆動トランジスタ200pとの間には、第3素子分離領域210が設けられている。
次に、本実施の形態にかかる半導体装置の製造方法について、図1から図20を参照しながら説明する。図1から図20は、本実施の形態にかかる半導体装置の製造方法の工程を模式的に示す断面図である。
Claims (3)
- 半導体層内の高耐圧トランジスタ形成領域に、第1ウェルとなる第1不純物層を形成する工程と、
前記高耐圧トランジスタ形成領域に、オフセット領域となる第2不純物層を形成する工程と、
前記半導体層に熱処理を施すことによって、前記第1および第2不純物層の不純物を拡散させ、前記第1ウェルおよび前記オフセット領域を形成する工程と、
前記第1ウェルおよび前記オフセット領域を形成する工程の後に、前記半導体層内に、素子分離領域をトレンチ素子分離法により形成する工程と、
前記高耐圧トランジスタ形成領域に、第1ゲート絶縁層を形成する工程と、
前記半導体層内の低電圧駆動トランジスタ形成領域に、第2ウェルを形成する工程と、
前記低電圧駆動トランジスタ形成領域に、第2ゲート絶縁層を形成する工程と、
前記高耐圧トランジスタ形成領域および前記低電圧駆動トランジスタ形成領域に、ゲート電極を形成する工程と、を含む、半導体装置の製造方法。 - 請求項1において、
高耐圧トランジスタにおけるオフセットトレンチ絶縁層を形成する工程は、前記素子分離領域を形成する工程と同一の工程である、半導体装置の製造方法。 - 請求項1または2において、
前記高耐圧トランジスタ形成領域には、n型およびp型高耐圧トランジスタを形成し、
前記低電圧駆動トランジスタ形成領域には、n型およびp型低電圧駆動トランジスタを形成する、半導体装置の製造方法。
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Cited By (7)
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JP2006278633A (ja) * | 2005-03-29 | 2006-10-12 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2007115885A (ja) * | 2005-10-20 | 2007-05-10 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2007115967A (ja) * | 2005-10-21 | 2007-05-10 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2007115998A (ja) * | 2005-10-21 | 2007-05-10 | Seiko Epson Corp | 半導体装置 |
JP2007123339A (ja) * | 2005-10-25 | 2007-05-17 | Seiko Epson Corp | 半導体装置および半導体装置の製造方法 |
JP2007123338A (ja) * | 2005-10-25 | 2007-05-17 | Seiko Epson Corp | 半導体装置および半導体装置の製造方法 |
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JP4896789B2 (ja) * | 2007-03-29 | 2012-03-14 | 株式会社東芝 | 半導体装置の製造方法 |
TWI682502B (zh) * | 2017-12-29 | 2020-01-11 | 新唐科技股份有限公司 | 半導體裝置之形成方法 |
KR20210011783A (ko) | 2019-07-23 | 2021-02-02 | 삼성전자주식회사 | 트랜지스터를 구비하는 반도체 소자 |
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JP3272272B2 (ja) | 1997-06-30 | 2002-04-08 | 三洋電機株式会社 | 半導体集積回路の製造方法 |
US6548874B1 (en) | 1999-10-27 | 2003-04-15 | Texas Instruments Incorporated | Higher voltage transistors for sub micron CMOS processes |
JP2002170888A (ja) | 2000-11-30 | 2002-06-14 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
KR100396703B1 (ko) | 2001-04-28 | 2003-09-02 | 주식회사 하이닉스반도체 | 고전압 소자 및 그 제조방법 |
JP3719192B2 (ja) | 2001-10-26 | 2005-11-24 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
KR100481989B1 (ko) * | 2003-01-27 | 2005-04-14 | 매그나칩 반도체 유한회사 | 복합 로직 소자의 제조 방법 |
KR100493061B1 (ko) * | 2003-06-20 | 2005-06-02 | 삼성전자주식회사 | 비휘발성 메모리가 내장된 단일 칩 데이터 처리 장치 |
-
2003
- 2003-07-31 JP JP2003283664A patent/JP2005051148A/ja active Pending
-
2004
- 2004-07-29 US US10/902,699 patent/US7163855B2/en not_active Expired - Fee Related
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006278633A (ja) * | 2005-03-29 | 2006-10-12 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2007115885A (ja) * | 2005-10-20 | 2007-05-10 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2007115967A (ja) * | 2005-10-21 | 2007-05-10 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2007115998A (ja) * | 2005-10-21 | 2007-05-10 | Seiko Epson Corp | 半導体装置 |
JP2007123339A (ja) * | 2005-10-25 | 2007-05-17 | Seiko Epson Corp | 半導体装置および半導体装置の製造方法 |
JP2007123338A (ja) * | 2005-10-25 | 2007-05-17 | Seiko Epson Corp | 半導体装置および半導体装置の製造方法 |
JP2007129008A (ja) * | 2005-11-02 | 2007-05-24 | Seiko Epson Corp | 半導体装置およびその製造方法 |
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US20050059196A1 (en) | 2005-03-17 |
US7163855B2 (en) | 2007-01-16 |
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