TWI680502B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI680502B
TWI680502B TW105103612A TW105103612A TWI680502B TW I680502 B TWI680502 B TW I680502B TW 105103612 A TW105103612 A TW 105103612A TW 105103612 A TW105103612 A TW 105103612A TW I680502 B TWI680502 B TW I680502B
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Taiwan
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region
sidewall
gate
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TW105103612A
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TW201729262A (zh
Inventor
蔡佳真
Chia-Chen Tsai
張弘昌
Hung-Chang Chang
羅大剛
Ta-Kang Lo
陳再富
Tsai-Fu Chen
陳尚志
Shang-Jr Chen
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聯華電子股份有限公司
United Microelectronics Corp.
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Priority to TW105103612A priority Critical patent/TWI680502B/zh
Priority to US15/057,079 priority patent/US9634002B1/en
Priority to US15/450,037 priority patent/US9779998B2/en
Publication of TW201729262A publication Critical patent/TW201729262A/zh
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Publication of TWI680502B publication Critical patent/TWI680502B/zh

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    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials

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  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本發明提出了一種半導體元件及其製作方法，其利用多道的側壁子層來在不同的區域或元件上形成厚度不同的側壁子，藉此調整及控制所需的應變矽結構至閘極結構間距，以使各種的元件與電路佈局有一致的性能表現。

Description

半導體元件及其製作方法
本發明大體上與一種半導體元件暨其製造方法有關，更特定言之，其係關於一種製作具有不同側壁子厚度的半導體元件之方法，其側壁子厚度會視元件所需的應變矽結構至閘極結構間距來調整。
近年來，被應用在積體電路的半導體先進製程技術包含了「應變工程」(或稱為應力工程)，其廣泛用於半導體元件的製造中，研究發現調整金氧半導體(MOS)電晶體通道區域中晶格的應變可以增強該些區域的載子移動率。我們從金氧半導體元件的基礎知識技術中已經知道，金氧半導體元件的三極區與飽和區中的源/汲極電流(即驅動電流)都是與其通道區域中的載子移動率成正比。一般而言，壓應力會增強PMOS電晶體通道區域中的電洞移動率，而張應力則會增強NMOS電晶體通道區域中的電子移動率。就一般的積體電路而言，PMOS電晶體相較於NMOS電晶體會具有較低的驅動能力，故此，在現今的半導體製造上應變工程較常被應用在PMOS元件上。
目前已有多種習知的應變工程作法。根據我們所知的「嵌入式矽鍺」(eSiGe)作法，其PMOS電晶體的源/汲極區域是先對矽基底或井區域進行蝕刻，之後再以選擇性磊晶製程形成矽鍺合金來加以置換。如此，因為晶格裡含有鍺 原子(佔合金中25%-30%的原子數)，嵌入式矽鍺磊晶的晶格常數會較純矽晶來得大(也就是說，矽鍺磊晶單元之間的距離較矽晶單元之間的距離大)，因此嵌入式矽鍺源/汲極區域會施加壓應力在PMOS電晶體的通道區域上，這樣的壓應力會增加PMOS電晶體通道區域中的電洞移動率，進而增強其效能。
類似的作法也可以用來改善NMOS電晶體中的載子移動率。美國專利第7,023,018號(其併於文中做為參考)中說明了使用矽碳合金(SiC)作為NMOS電晶體中的源/汲極結構。如其文中所述，矽碳源/汲極結構會增加源/汲極電流方向上的張應力，這樣的張應力會增加PMOS電晶體通道區域中的電子移動率，進而增強其效能。
目前研究人員觀察到，應變矽鍺結構的形狀可能會因為鄰近結構的幾何形狀所導致的負載作用(loading effect)而會有不一致的情形，此問題主要是來自於積體電路在不同的圖形密度或佈局下會有不同的元件寬度或元件間距。應變矽鍺結構的形狀不一致會影響元件的效能，因為其矽鍺磊晶在基底中的填充程度以及其所產生施加在通道晶格上的應力會隨著元件的不同而改變。
目前有幾種習知作法被用來避免上述我們不想要的結果，其中之一是將積體電路中所有閘極結構都設計成具有相同的寬度與間距。然而，這種作法限制無疑大大地降低了電路設計者優化元件佈局與電路效能的能力。另一種作法是加入犧牲性質的虛置(dummy)閘極，由這類非功能性的假結構來吸收負載作用帶來的壞處。當然，這樣的作法會浪費掉可貴的晶片區域。故此，還需本領域的技術人員來找出此問題的較佳解法。
為了解決前述積體電路中負載作用會導致所形成的應變矽結構形狀不一的問題，本發明提出了具有不同側壁子厚度的元件概念，其可視元件的種 類或需求來調整側壁子的厚度，進而控制其應變矽結構至閘極結構(SiGe-to-Gate)之間距大小，達到不同圖形密度或電路佈局下諸元件性能一致的功效。
本發明的一目的在於提出一種半導體元件，其包含一基底，該基底上具有一第一區域與一第二區域、多個閘極結構位於該基底上，其中每一該閘極結構的兩側側壁上都具有側壁子、以及兩應變矽結構位於每一該側壁子外側的該基底上，該應變矽結構與該閘極結構之間的距離為應變矽至閘極間距，其中位於該第一區域上的該閘極結構與位於該第二區域上的該閘極結構的該應變矽至閘極間距不同，該第一區域上的該閘極結構的該側壁子僅由一第一側壁子層所構成，該第二區域上的該閘極結構的該側壁子是由該第一側壁子層以及其他不同的側壁子層所構成。
本發明的另一目的在於提出一種製造半導體元件的方法，其步驟包含提供一基底，該基底上具有一第一區域與一第二區域、在該基底上形成多個閘極結構、在該基底以及該多個閘極結構上形成一共形的第一側壁子層、形成一第一遮罩蓋住該第二區域、進行一第一蝕刻製程，使得未受該第一遮罩覆蓋的該第一區域上的該第一側壁子層在該第一區域上的每一該閘極結構的側壁上轉變成第一側壁子、去除該第一遮罩、在該基底、該些閘極結構、該些第一側壁子以及該第一側壁子層上形成一共形的第二側壁子層、形成一第二遮罩蓋住該第二區域、去除未受該第二遮罩覆蓋的該第一區域上的該第二側壁子層、去除該第二遮罩、形成一第三遮罩蓋住該第一區域、以及進行一第二蝕刻製程，使得未受該第三遮罩覆蓋的該第二區域上的該第一側壁子層與該第二側壁子層在該第二區域上的每一該閘極結構的側壁上一起轉變成第二側壁子。
無疑地，本發明的這類目的與其他目的在閱者讀過下文以多種圖示與繪圖來描述的較佳實施例細節說明後將變得更為顯見。
100‧‧‧基底
101‧‧‧第一區域
102‧‧‧第二區域
110‧‧‧淺溝渠隔離結構
111‧‧‧凹槽
112‧‧‧凹槽
120‧‧‧閘極結構
121‧‧‧閘極介電層
122‧‧‧閘極
123‧‧‧頂保護層
124‧‧‧襯層
125‧‧‧第一側壁子
130‧‧‧閘極結構
131‧‧‧閘極介電層
132‧‧‧閘極
133‧‧‧頂保護層
134‧‧‧襯層
135‧‧‧第二側壁子
140‧‧‧第一側壁子層
150‧‧‧第一遮罩
152‧‧‧緩衝層
160‧‧‧第二側壁子層
170‧‧‧第二遮罩
180‧‧‧第三遮罩
191‧‧‧應變矽結構
192‧‧‧應變矽結構
E1‧‧‧第一蝕刻製程
E2‧‧‧第二蝕刻製程
E3‧‧‧第三蝕刻製程
本說明書含有附圖併於文中構成了本說明書之一部分，俾使閱者對本發明實施例有進一步的瞭解。該些圖示係描繪了本發明一些實施例並連同本文描述一起說明了其原理。在該些圖示中：第1圖繪示出根據本發明一實施例中在基底的第一區域以及第二區域上形成閘極結構的示意圖；第2圖繪示出根據本發明一實施例中在基底與閘極結構上形成一共形的第一側壁子層的示意圖；第3圖繪示出根據本發明一實施例中在基底的第二區域上形成第一遮罩並進行蝕刻製程在基底的第一區域上形成第一側壁子的示意圖；第4A圖繪示出根據本發明一實施例中在第一側壁子形成後再形成一共形的第二側壁子層的示意圖；第4B圖繪示出根據本發明另一實施例中在第一側壁子形成後再形成一共形的緩衝層與第二側壁子層的示意圖；第5圖繪示出根據本發明一實施例中在基底的第二區域上形成第二遮罩並移除基底的第一區域上的第一側壁子層的示意圖；第6圖繪示出根據本發明一實施例中在基底的第一區域上形成第三遮罩並進行蝕刻製程在基底的第二區域上形成第二側壁子的示意圖；第7圖繪示出根據本發明一實施例中在各側壁子外側形成凹槽的示意圖；以及第8圖繪示出根據本發明一實施例中在各凹槽中形成應變矽磊晶結構的示意圖。
須注意本說明書中的所有圖示皆為圖例性質，為了清楚與方便圖示說明之 故，圖示中的各部件在尺寸與比例上可能會被誇大或縮小地呈現，一般而言，圖中相同的參考符號會用來標示修改後或不同實施例中對應或類似的元件特徵。
參照下述較佳實施例的詳細說明與隨附圖示能更了解本發明的特徵與優點，然而文中所舉之實施例實際上可能是以許多不同的形式來體現，其不應被理解成是僅侷限於文中所詳述者，所提供的這些實施例中有完善的揭露說明，能傳達完整的施作範例給此領域中的技藝人士。故此，這些實施例只會用附錄的申請專利範圍來界定。相同的元件符號在通篇說明書中都是用來指稱相同的元件。
文中所用的術語僅是用來說明特定的實施例，其並非意欲加以侷限。除非內文清楚地指出，不然文中所用的「一」、「一個」與「該」等詞也意欲要包含複數的形式。閱者將能進一步了解到，說明書中使用「包含」以及/或「含有」等詞是要具體說明所陳述之特徵、整體、步驟、運作、要素以及/或元件的存在，其並未排除其他的特徵、整體、步驟、運作、要素、元件以及/或其組合的存在或添加。
閱者將能了解到，當文中有元件或層結構被描述是與另一元件或層結構「連接」、「耦合」或是「位於其上」，其可能是直接地位於其上，或是有連接或耦合到其他的元件或層結構，或是兩者間有中介的元件或層結構存在。反之，當有元件被描述是「直接位於其上」、「直接連接至」或是「直接耦合至」另一元件或層結構時，它們之間就無任何中介的元件或層結構存在。如文中所用者，「以及/或」此詞是包含一或多個所列舉的相關物件或其組合。
文中的實施例係參照多張截面圖來說明，其中示意性地描繪出了各 實施例在製程演進時的結構以及其理想化的呈現。如此，可以預期到實作中所繪示之物件的形狀會因製程技術以及/或製造誤差而有所改變。故此，這些實施例不應被理解成是僅侷限於圖中所繪之特定形狀，其應包含因製造所導致的形狀差異。
此外，除非有另外加以界定，文中所用的所有術語(包含技術用語或科學用語等)會與本領域中一般技藝人士所普遍認知的意涵相同。閱者將能進一步瞭解到，這些術語會與本說明書以及相關先前技術的內文有一致的解釋。
現在下文將參照第1-8圖來說明根據本發明實施例之一種製造半導體元件的方法。須注意，本發明雖以平面型態的半導體元件製程來作為實施範例，其並不代表本發明之範疇僅侷限於此，其亦可應用在3D型態的半導體元件製程，如鰭式電晶體(FinFET)或是多閘道電晶體之製作。
請參照第1圖，首先提供一基底100，基底100例如是一矽基底、一含矽基底、一三/五族覆矽基底(例如GaN-on-silicon)、一石墨烯覆矽基底(graphene-on-silicon)或一矽覆絕緣(silicon-on-insulator，SOI)基底等半導體基底。在本發明實施例中，基底100包含一第一區域101以及一第二區域102，第一區域101與第二區域102可為兩個具有不同圖形密度的區域，或是其上係分別用來製作不同的半導體元件，例如其可分別為一P型金氧半導體元件(PMOS)區域與一N型金氧半導體元件(NMOS)區域，其可以各區域基底100中所摻雜的離子井類型來定義。各區域之間係以淺溝隔離結構(shallow trench isolation,STI)110來區隔。實作中基底上會劃分出兩個以上更多不同性質或具有不同類型元件的區域，後續的實施例中將僅以兩種區域來表示出區域上的差異。
在本發明實施例中，基底100的兩區域上分別形成有不同的閘極結構120與130，例如兩個具有不同厚度的PMOS閘極。或者，在其他實施例中，閘極結構120與130可分別是一NMOS閘極與一PMOS閘極。兩閘極結構120/130均包含 有一閘極介電層121/131、一位於閘極介電層上的閘極122/132、位於閘極頂部的頂保護層123/133。閘極介電層121/131可由矽氧化合物或氮氧化合物或高介電係數介電材料等單一絕緣材料或上述材料的任意組合所構成，其厚度可視元件的不同而不同。閘極122/132可由摻雜或未摻雜的單晶矽或多晶矽、矽鍺材料、金屬矽化物、金屬等導電材料所構成，頂保護層123/133則是由氮化矽或氧化矽等介電材料所構成。此外，閘極結構120/130的兩側亦可選擇性地形成襯層124/134，如一氧化層，來保護閘極結構或提供緩衝效果。兩閘極結構120/130可以具有相同或不同的寬度，如從第1圖中可以看出在本實施例中閘極結構130(如一PMOS)的寬度比閘極結構120大，這是為了在後文中說明本發明的側壁子的厚度與閘極寬度之間的關係。為簡明以及避免模糊本發明主題之故，後文與圖式中將省略輕摻雜汲極(lightly-doped drains)部位與其相關製作流程。
接著請參照第2圖，在基底100以及閘極結構120,130上共形地形成一第一側壁子層140。第一側壁子層140可使用習知的材料與製程來形成，其包含但不限定以氧化矽、氮化矽、碳氮化矽、以及/或氧碳氮化矽為原料使用化學氣相沉積(chemical vapor deposition)或原子層沉積法(atomic layer deposition)形成。在其他實施例中，第一側壁子層140也可是使用上述列舉之材質所構成的複層結構。第一側壁子層140的厚度會視所形成的MOS元件之設計需求來決定。舉例來說，第一側壁子層140的厚度會決定後續閘極結構與應變矽結構之間的間距(後文中將稱其為應變矽至閘極間距，SiGe-to-Gate)。此應變矽至閘極間距將會進一步影響應變矽結構的形狀及其在元件通道處的晶格所產生的應變效力。不同的元件或佈局具有不同的特徵尺寸或環境，如閘極間距(poly spacing)、閘極寬度、圖形密度、臨界電壓(Vts)、甚至是周遭結構的幾何形狀，視各種元件之不同來改變應變矽至閘極間距，其可有效地讓各元件的電性表現更為一致。本發明的要點係在於利用多道的側壁子層來在不同的區域或元件上形成厚度不同的側壁子， 藉此調整及控制所需的應變矽結構至閘極結構間距，以使各種的元件與電路佈局有一致的性能表現。
接下來的實施例中將詳細說明如何利用多道的層結構在基底的不同區域上形成不同厚度的側壁子。請參照第3圖，進行一微影製程在基底100的第二區域102上形成一第一遮罩150，如一光阻塗覆層(PR coating)。之後進行一第一蝕刻製程E1，如針對側壁子層材質的一非等向性的乾蝕刻製程，直至裸露出閘極的頂保護層123和基底100，如此使得未受第一遮罩150覆蓋的第一區域101上的第一側壁子層140在第一區域的閘極結構120側壁上轉變成第一側壁子125。第二區域102上的第一側壁子層140則在第一遮罩150的保護下維持不變。可以從第3圖中看出，由於非等向性蝕刻的因素，第一區域101上所形成的第一側壁子125的底部厚度會約略等於原先第一側壁子層140的厚度，此厚度即決定了第一區域101上半導體元件的應變矽至閘極間隔。
請參照第4A圖，在形成第一側壁子125後，接下來移除第二區域上的第一遮罩150，如進行一光阻灰化步驟，使得剩餘的第一側壁子層140裸露出來，之後即可在基底100、閘極結構120、以及裸露的第一側壁子層140上共形地形成一第二側壁子層160，從圖中可以看到第一側壁子層140與第二側壁子層160在第二區域102上形成了複層結構。第二側壁子層160可使用習知的材料來形成，其包含但不限定以氧化矽、氮化矽、碳氮化矽、以及/或氧碳氮化矽等為原料使用化學氣相沉積或原子層沉積法來形成。在本發明實施例中，第二側壁子層160的材料最好與第一側壁子層140不同，以達成較佳的蝕刻選擇比，如此將可在後續的製程中使用蝕刻方式選擇性地移除第二側壁子層160。再者，第二側壁子層160的厚度會視所形成的MOS元件之設計需求來決定，特別係第二側壁子層160與先前沉積的第一側壁子層140的底部總厚度會決定了第二區域102上半導體元件的應變矽至閘極間隔。
或者，在其他實施例中，如第4B圖所示，第一側壁子層140與第二側壁子層160之間還可以額外形成一緩衝層152，如一氧化層。在第一側壁子層140與第二側壁子層160材質相同的情況下，緩衝層152可以在後續移除第二側壁子層160的製程中作為一蝕刻停止層，如此兩者不具備較佳的蝕刻選擇比的情況下也可以順利地移除第二側壁子層160而不損及內側的第一側壁子層140。
請參照第5圖，在形成第二側壁子層160後，接下來使用微影製程在基底100的第二區域102上形成一第二遮罩170，如一光阻塗覆層。之後移除未受第二遮罩170覆蓋的第一區域101上的第二側壁子層160，第二區域102上的第二側壁子層160則在第二遮罩170的保護下維持不變。在第二側壁子層160與第一側壁子層140的材質不同的情況下，第二側壁子層160之移除可使用一選擇性的蝕刻製程，其僅會移除第二側壁子層160之材質而不會影響其下的第一側壁子125。或者，在第一側壁子125與第二側壁子層160的材質相同的情況下，亦可使用一等向性的蝕刻製程來去除第一區域101上一定厚度的側壁子層，如此亦可以保留下來先前所形成的第一側壁子125。
請參照第6圖，在去除第一區域上的第二側壁子層160後，接著去除第二區域上的第二遮罩170，如進行一光阻灰化步驟，使得第二區域102上的第二側壁子層160裸露出來。接著，再於第一區域101上形成一第三遮罩180，如一光阻塗覆層，來蓋住第一區域101上的閘極結構120。之後進行一第二蝕刻製程E2，如一針對側壁子材質的非等向性的乾蝕刻製程，直至裸露出閘極結構130的頂保護層133和基底100，如此使得未受第三遮罩180覆蓋的第二區域102上的第一側壁子層140與第二側壁子層160在第二區域的閘極結構130側壁上轉變成第二側壁子135。第一區域101上的第一側壁子125則在第三遮罩180的保護下維持不變。從第6圖中可以看出，第二區域102上所形成的第二側壁子135是由第一側壁子層140與第二側壁子層160構成的複層結構，其厚度會約略等於原先第一側壁子層140 與第二側壁子層160的底部總厚度，此厚度即決定了第二區域102上半導體元件的應變矽至閘極間隔。由於內層的第一側壁子層140與外層的第二側壁子層160是在同一道蝕刻製程中形成側壁子，可以看到第二側壁子135內部的第一側壁子層140是呈L形。
在實作中，寬度較大的閘極結構(如130)會需要較大的臨界電壓(Vts)來驅動，增加應變矽至閘極間距將可有效地增大臨界電壓。故就本發明而言，使用如第2圖~第6圖所述般在基底的特定區域上形成複層的側壁子層之作法，這樣的作法將可有效地在具有不同寬度或性質的各種閘極結構兩側形成具有不同對應厚度的側壁子，以此達到控制與調整各元件應變矽至閘極間距的目的。重複第2圖~第6圖的製程步驟將可形成兩層以上更多的複層側壁子結構並增加所需的側壁子厚度。
請參照第7圖，在形成第二側壁子135後，接著去除第一區域101上的第三遮罩180，如進行一光阻灰化製程，使得第一區域101上的閘極結構120與第一側壁子125裸露出來。之後以閘極結構120,130、第一側壁子125與第二側壁子135、以及淺溝槽隔離結構110為遮罩對基底100進行一第三蝕刻製程E3，例如以乾蝕刻、濕蝕刻或兩者都施行之方式，以在各第一側壁子125與第二側壁子135外側的基底100上形成多個凹槽111,112，作為後續成長應變矽結構的空間。蝕刻會沿著矽基底100的結晶面〈110〉和〈111〉進行蝕刻，故凹槽111,112會具有特定的蝕刻特徵面，如圖中所示的鑽石形刻面。
由於第三蝕刻製程是以閘極結構120/130、第一側壁子125與第二側壁子135、以及淺溝槽隔離結構110作為蝕刻遮罩，從圖中清楚的看到，凹槽111,112的寬度會是由側壁子125/135的寬度以及閘極結構120/130到淺溝槽隔離結構110的間距來界定的。
在實作中，當閘極結構之間的間距越大，亦即在圖形密度較小的佈 局中，後續凹槽111/112中所成長出的應變矽結構會因為過充(overfill)而體積變大，進而因為應力過高而導致疊層缺陷(stack fault)的問題。本發明可以透過調整應變矽至閘極間距來控制應變矽結構的體積。舉例言之，在相同的閘極間距的設定下，減少側壁子的厚度可以使得後續所形成的凹槽111/112寬度變大，如此後續的磊晶生長製程會因為凹槽的容積變大的關係而不會有過充、體積過大的情形發生。
請參照第8圖，在形成凹槽111,112後，進行一預清洗(pre-clean)步驟，去除凹槽111,112表面的原生氧化物或其他不純物質，俾使後續形成於凹槽中之應變矽結構具有更佳之形狀及截面結構。之後，進行一磊晶製程來形成應變矽結構。在此階段，由於基底100上僅凹槽111,112的表面是純矽晶面，故磊晶製程僅會在凹槽111,112中生長應變矽結構191/192，如矽鍺合金(SiGe)。在本較佳實施例中，可結合選擇性應力系統(selective strain scheme,SSS)等製程，例如利用選擇性磊晶成長(selective epitaxial growth,SEG)方法來製作應變矽結構。其中應變矽結構191/192的材質可視電晶體的性質來選擇，例如PMOS區域(如102)中使用可鍺化矽(SiGe)材質之應變矽結構192，NMOS區域(如101)中則使用碳化矽(SiC)、磷化矽(SiP)或碳磷化矽(SiCP)材質之應變矽結構191。如第8圖所示，應變矽結構191/192會填滿凹槽111/112，其有可能突出於基底100之上。
在其他實施例中，如閘極結構120與130分別為NMOS和PMOS的情況下，第一區域101上的凹槽111與第二區域102上的凹槽112可分別在不同的蝕刻步驟中形成，其對應之應變矽結構191與192亦可能在不同的磊晶製程中形成。
須注意，閘極結構120/130的源/汲極區是可以在應變矽結構191/192的生長前、生長後、或是生長同時(in-situ)來加以製作或形成。為簡明以及避免模糊本發明主題之故，內文與圖式中省略了源/汲極區部位與其相關製作流程。為簡明以及避免模糊本發明主題之故，內文與圖式中省略了其相關的製作流程與 說明。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。

Claims (11)

  1. 一種半導體元件，包含：一基底，該基底上具有一第一區域與一第二區域；多個閘極結構，位於該基底上，其中每一該閘極結構的兩側側壁上都具有側壁子，該第一區域上的該閘極結構的該側壁子僅由一第一側壁子層所構成，該第二區域上的該閘極結構的該側壁子是由該第一側壁子層以及其他不同的側壁子層所構成，其中該閘極結構與該閘極結構之間的間距越大，該側壁子的寬度越大；以及兩應變矽結構，位於每一該側壁子外側的該基底上，該應變矽結構與該閘極結構之間的距離為應變矽至閘極間距，其中位於該第一區域上的該閘極結構與位於該第二區域上的該閘極結構的該應變矽至閘極間距不同。
  2. 如申請專利範圍第1項所述之半導體元件，其中該閘極結構的寬度越大，該閘極結構的該應變矽至閘極間距越大。
  3. 如申請專利範圍第1項所述之半導體元件，其中該閘極結構的該應變矽至閘極間距越大，構成該閘極結構的該側壁子層的側壁子層層數越多。
  4. 如申請專利範圍第1項所述之半導體元件，其中該閘極結構與該閘極結構之間的間距越大，該閘極結構兩側的該應變矽結構的寬度越大。
  5. 如申請專利範圍第1項所述之半導體元件，其中該第二區域上的該閘極結構的該側壁子中的第一側壁子層呈L形。
  6. 如申請專利範圍第1項所述之半導體元件，其中該第一側壁子層的材質與該其他不同的側壁子層的材質不同。
  7. 如申請專利範圍第1項所述之半導體元件，更包含一緩衝層設置在該第一側壁子層與該第二側壁子層之間。
  8. 一種製造半導體元件的方法，包含：提供一基底，該基底上具有一第一區域與一第二區域；在該基底上形成多個閘極結構；在該基底以及該多個閘極結構上形成一共形的第一側壁子層；形成一第一遮罩蓋住該第二區域；進行一第一蝕刻製程，使得未受該第一遮罩覆蓋的該第一區域上的該第一側壁子層在該第一區域上的每一該閘極結構的側壁上轉變成第一側壁子；去除該第一遮罩；在該基底、該些閘極結構、該些第一側壁子以及該第一側壁子層上形成一共形的第二側壁子層；形成一第二遮罩蓋住該第二區域；去除未受該第二遮罩覆蓋的該第一區域上的該第二側壁子層；去除該第二遮罩；形成一第三遮罩蓋住該第一區域；以及進行一第二蝕刻製程，使得未受該第三遮罩覆蓋的該第二區域上的該第一側壁子層與該第二側壁子層在該第二區域上的每一該閘極結構的側壁上一起轉變成第二側壁子。
  9. 如申請專利範圍第8項所述之製造半導體元件的方法，更包含在該第二蝕刻製程後去除該第三遮罩。
  10. 如申請專利範圍第9項所述之製造半導體元件的方法，更包含在去除該第三遮罩後進行一第三蝕刻製程，以在每一該閘極結構的該第一側壁子或該第二側壁子外側的該基底上形成凹槽。
  11. 如申請專利範圍第10項所述之製造半導體元件的方法，更包含進行一磊晶製程在該些凹槽中形成應變矽結構。
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