CN104051506B - 氟掺杂信道硅锗层 - Google Patents
氟掺杂信道硅锗层 Download PDFInfo
- Publication number
- CN104051506B CN104051506B CN201410097863.5A CN201410097863A CN104051506B CN 104051506 B CN104051506 B CN 104051506B CN 201410097863 A CN201410097863 A CN 201410097863A CN 104051506 B CN104051506 B CN 104051506B
- Authority
- CN
- China
- Prior art keywords
- silicon layer
- channel
- germanium
- fluorine
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title claims abstract description 86
- 108091006146 Channels Proteins 0.000 claims abstract description 112
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 49
- 239000011737 fluorine Substances 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims abstract 15
- 238000002513 implantation Methods 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 abstract description 9
- 230000005669 field effect Effects 0.000 abstract description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 33
- 238000005516 engineering process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 230000012010 growth Effects 0.000 description 4
- 125000004429 atom Chemical group 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910020750 SixGey Inorganic materials 0.000 description 1
- VDRSDNINOSAWIV-UHFFFAOYSA-N [F].[Si] Chemical compound [F].[Si] VDRSDNINOSAWIV-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明涉及一种氟掺杂信道硅锗层，其中，所揭示的是用于在信道硅锗(cSiGe)层具有改良型接口粗糙度的P型信道金属氧化物半导体场效晶体管(PMOSFET)的形成方法以及所产生的装置。具体实施例可包括在衬底中指定作为信道区的区域，在所指定信道区之上形成信道硅锗层，以及将氟直接植入到信道硅锗层内。具体实施例或可包括将氟植入到硅衬底中被指定为信道区的区域内，在所指定信道区之上形成信道硅锗层，以及加热硅衬底和信道硅锗层以将氟扩散到信道硅锗层内。
Description
技术领域
本揭示涉及半导体装置中的信道硅锗(channel silicon-germanium，简称cSiGe)层。本揭示尤其适用于形成具有改良型接口粗糙度的信道硅锗层，同时维持p信道金属氧化物半导体场效晶体管(PMOSFET)中的临界电压效率。
背景技术
针对高k介电金属栅极技术在PMOSFET中使用信道硅锗层可降低临界电压(threshold voltage)。然而，降低临界电压所需的例如等于或大于100埃()的厚度提高信道硅锗层与其它层（例如硅衬底及/或栅极介电层）之间的粗糙度。接口粗糙度的增加使晶体管的可靠度及效能降低。
因此，存在令具有改良型接口粗糙度的信道硅锗层较厚又同时维持有效临界电压的方法、及所产生的装置的需求。
发明内容
本揭示的一个态样是用于在PMOSFET中形成氟掺杂信道硅锗层的有效方法。
本揭示的另一个态样是具有氟掺杂信道硅锗层的PMOSFET。
本揭示的另外态样及其它特征将在下文的说明中提出，并且在审阅下文后对于所属领域的技术人员将是显而易知或可学习自本揭示的实践。可如所附权利要求书特别指出而实现并且取得本揭示的优点。
根据本揭示，某些技术功效可藉由包括如下所述的方法而部分达成：在衬底(substrate)中指定作为信道区的区域，在所指定信道区之上形成信道硅锗层，以及将氟直接植入到信道硅锗层内。
本揭示的一个态样包括以8×1014至2×1015原子/平方公分(cm2)的剂量在信道硅锗层中植入氟。本揭示的一个态样是以5至10仟电子伏特(keV)的能量在信道硅锗层中植入氟。本揭示的又一个态样是在植入氟之后以400至650℃对信道硅锗进行退火。本揭示另外的态样是形成信道硅锗层至40到80埃的厚度。本揭示的另一个态样是在信道硅锗层上方形成栅极介电层。本揭示另外的态样是在栅极介电层上形成栅极。
进一步技术功效也可藉由包括如下所述的方法而部分达成：将氟植入到硅衬底中被指定为信道区的区域，在所指定信道区之上形成信道硅锗层，以及加热硅衬底和信道硅锗层以使氟扩散到信道硅锗层内。
另一个态样包括以1×1015至3×1015原子/平方公分的剂量在所指定信道区中植入氟。另外的态样包括以5至10仟电子伏特的能量在所指定信道区中植入氟。又一个态样包括在植入氟之后以及形成信道硅锗层之前以650至1050℃对硅衬底进行退火。进一步态样包括形成信道硅锗层至40到80埃的厚度。其它态样包括在信道硅锗层之上形成栅极介电层，其中，硅衬底和信道硅锗层的加热发生在形成栅极介电层期间及/或之后。进一步态样包括在栅极介电层上形成栅极，其中，硅衬底和信道硅锗层的加热发生在形成栅极期间及/或之后。
本揭示的另一个态样是装置，其包括：衬底，衬底中的P型信道区，以及衬底上的P型信道区之上的氟掺杂信道硅锗层，信道硅锗层形成至40到80埃的厚度。
态样包括以5至10keV的能量植入的氟。另外的态样包括以1×1015至3×1015原子/平方公分的剂量植入并且以650至1050℃进行退火的氟。进一步态样包括以8×1014至2×1015原子/平方公分的剂量植入并且以400至650℃进行退火的氟。又一个态样包括信道硅锗层之上的栅极介电层。另一个态样包括栅极介电层之上的高k介电质金属栅极。
本揭示另外的态样及技术功效经由下文所述实施方式对所属领域的技术人员而言将显而易见，其中，本揭示的具体实施例单纯地藉由描述经考虑用以实施本揭示的最佳模式予以说明。将了解的是，本揭示能有其它及不同的具体实施例，并且其细节能以各种明显方式改进，全部都不脱离本揭示内容。因此，图式及说明本质上视为描述性而非限制性。
附图说明
本揭示藉由实施例而非经由限制予以在所附图式的图标中描述，并且相同的组件符号意指类似组件，以及其中：
图1至图4为根据一个示例性具体实施例示意性描述用于在PMOSFET中形成氟掺杂信道硅锗层的方法；以及
图5至图7为根据替代的示例性具体实施例示意性描述用于在PMOSFET中形成氟掺杂信道硅锗层的方法。
主要组件符号说明
101 衬底
103 区域
201 信道硅锗层
301 氟掺杂信道硅锗层
401 栅极介电层
403 栅极
405 间隔件
407 源极/漏极区
409 信道
411 氟掺杂信道硅锗层
501 氟掺杂层
701 氟掺杂信道硅锗层。
具体实施方式
在下文的说明中，为了解释，提出许多特定细节以便透彻理解示例性具体实施例。然而，应该显而易知的是，可无需这些特定细节或利用等效配置来实践示例性具体实施例。在其它实例中，方块图中显示众所周知的结构和装置以防示例性具体实施例受到不必要的混淆。另外，除非另有所指，说明书及权利要求书中用来表达数量、比率、以及成分的数值特性、反应条件等等的所有数字在所有实例中都应理解为藉由术语「大约」修饰。
本揭示处理并且解决了目前为了降低PMOSFET中的临界电压将信道硅锗层形成至足够厚度所伴随而来的效能及可靠度不良的问题。根据本揭示的具体实施例，氟掺杂信道硅锗层在PMOSFET内缩减厚度形成，以改良装置可靠度及效能同时维持足够的临界电压。
根据本揭示一个具体实施例的方法包括在衬底中指定区域作为信道区。其次，在所指定信道区之上形成信道硅锗层。可将信道硅锗层形成至40到80埃的厚度。接着，将氟直接植入到信道硅锗层内。后续步骤可包括在信道硅锗层上方形成栅极介电层与栅极。
根据本揭示另一个具体实施例的方法包括将氟植入到硅衬底中被指定为信道区的区域内。其次，在所指定信道区之上形成信道硅锗层。可将信道硅锗层形成至40到80埃的厚度。随后，加热硅衬底及信道硅锗层以使氟扩散到信道硅锗层内。
请参阅图1，根据一个示例性具体实施例，用于在PMOSFET中形成氟掺杂信道硅锗层的方法始于衬底101。如图所示，衬底101可为块体硅(Si)晶圆。或者，衬底101可为绝缘体上覆硅(SOI)晶圆。在下文所述后续处理后，衬底可包括将变成信道区的区域103。
其次，如图2所示，在衬底101上方形成信道硅锗层201。信道硅锗层201可形成至40到80埃的厚度并且可根据诸如藉由外延生长等习知处理技术形成。
随后，将氟直接植入到信道硅锗层201内以形成氟掺杂信道硅锗层301，如图3所示。可以8×1014至2×1015原子/平方公分(atoms/cm2)的剂量及5至10仟电子伏特(keV)的能量植入氟。所植入的氟使产生的PMOSFET的临界电压降低并且使信道硅锗层更薄。植入氟之后，信道硅锗层301于400至650℃进行退火4分钟以修复将氟直接植入到信道硅锗层201内所造成的任何植入损坏。
随后，如图5所示，在氟掺杂信道硅锗层301上方形成栅极介电层401、栅极403、以及间隔件405。接着形成源极/漏极区407，信道409则在先前置于栅极403下面并且介于源极/漏极区407之间的区域103处形成，从而形成PMOSFET。可将氟掺杂信道硅锗层301蚀刻至与栅极403的宽度一样，如所蚀刻的氟掺杂信道硅锗层411所示。栅极介电层401可为诸如氮化硅酸铪(HfSiON)的高k介电质，并且栅极403可为金属栅极。
较薄的氟掺杂信道硅锗层301/411导致比提供等效临界电压的习知、较厚(例如，等于或大于100埃)、非氟掺杂信道硅锗层更小的接口粗糙度。较薄的氟掺杂信道硅锗层301/411也使接口电荷捕捉(trapping)与去陷(de-trapping)更少以及装置迁移率更高。而且，在衬底101的表面上控制氟植入比控制SiGe生长更容易。信道硅锗层的厚度缩减再加上诸如SiGe(例如SixGeyOz)顶部上所形成的氧化层中或后续所形成的高k介电层中的氟消耗型带电氧空位(fluorine consuming charged oxygen vacancies)的特性改良了所产生的PMOSFET的可靠度及效能。例如，氟掺杂信道硅锗层301/411比习知、非氟掺杂信道硅锗层改良了25至70毫伏(mV)的最大电压供给(VDDMAX)以及20至40mV的时变性介电质崩溃电压(TDDB)。
请参阅图5，根据另一个示例性具体实施例用于在PMOSFET层中形成氟掺杂信道硅锗层的方法始于图1中具有区域103的衬底101。其次，将氟植入到形成氟掺杂层501的区域103内的衬底101的顶部表面内，如图5所示。可将氟以1×1015至3×1015/cm2的剂量及5至10keV的能量植入到衬底101内。氟以此剂量使产生的PMOSFET的临界电压降低并且使信道硅锗层更薄。在植入氟之后，视温度而定，以650至1050℃退火衬底5至240秒以修复任何由氟植入造成的损坏。
其次，如图6所示，在衬底101之上形成信道硅锗层201。信道硅锗层201可形成至40到80埃的厚度并且可根据诸如藉由外延生长的习知处理技术形成。衬底101内植入的氟也降低SiGe生长率，使得信道硅锗层201更薄。
随后，如图7所示，可进行诸如在信道硅锗层201之上形成栅极介电层401、栅极403、以及间隔件405等额外处理步骤。可进行其它处理步骤以形成源极/漏极区407，其中，在区域103先前置于栅极403下面并且介于源极/漏极区407之间处形成信道区409，从而形成PMOSFET。任何含括加热衬底101的后续处理步骤将造成氟掺杂层501中的氟扩散到信道硅锗层201内以产生氟掺杂信道硅锗层，其可进一步予以屏蔽并且蚀刻以形成宽度更窄的氟掺杂信道硅锗层701，如图7所示。任何后续加热也将进一步修复氟植入所造成的衬底101的接口损坏。
本揭示的具体实施例达到许多技术功效，包括维持有效临界电压同时降低PMOSFET中信道硅锗层与附加层(例如，Si衬底和栅极介电层)之间的接口粗糙度，从而改良晶体管的效能和可靠度。本揭示的具体实施例享有各种工业应用的用途，举例如微处理器、智能型手机、行动电话、蜂巢式手机、机上盒、DVD记录器与播放器、汽车导航、打印机与周边装置、网络与电信设备、游戏系统、以及数字相机。本揭示因而在各类高整合度半导体装置中享有产业利用性。
在前述说明中，本揭示参照其特定示例性具体实施例予以说明。然而，显而易见的是，可对其进行各种改进及变更而不脱离本揭示更广泛的精神与范畴，如权利要求书所述者。说明书及图式因而视为描述性而非限制性。要理解的是，本揭示能够使用各种其它组合与具体实施例并且能够在如本文所表达发明概念的范畴内进行任何变更或改进。
Claims (18)
1.一种形成半导体装置的方法，包含：
在衬底中指定作为P型信道区的区域；
在指定的该P型信道区之上形成厚度40到80埃的信道硅锗层；以及
将氟直接植入到该信道硅锗层中。
2.根据权利要求1所述形成半导体装置的方法，包含以8×1014至2×1015原子/平方公分的剂量植入该氟到该信道硅锗层中。
3.根据权利要求1所述形成半导体装置的方法，包含以5至10仟电子伏特的能量植入该氟到该信道硅锗层中。
4.根据权利要求1所述形成半导体装置的方法，进一步包含在植入该氟之后，以400至650℃对该信道硅锗层进行退火。
5.根据权利要求1所述形成半导体装置的方法，进一步包含在该信道硅锗层上方形成栅极介电层。
6.根据权利要求5所述形成半导体装置的方法，进一步包含在该栅极介电层上形成栅极。
7.一种形成半导体装置的方法，包含：
将氟植入到硅衬底中被指定为P型信道区的区域；
在指定的该P型信道区之上形成厚度40到80埃的信道硅锗层；以及
加热该硅衬底和该信道硅锗层，以使该氟扩散到该信道硅锗层中。
8.根据权利要求7所述形成半导体装置的方法，包含以1×1015至3×1015原子/平方公分的剂量在指定的该P型信道区中植入该氟。
9.根据权利要求7所述形成半导体装置的方法，包含以5至10仟电子伏特的能量在指定的该P型信道区中植入该氟。
10.根据权利要求7所述形成半导体装置的方法，进一步包含在植入该氟之后以及形成该信道硅锗层之前，以650至1050℃对该硅衬底进行退火。
11.根据权利要求7所述形成半导体装置的方法，进一步包含：
在该信道硅锗层上方形成栅极介电层，
其中，该硅衬底和该信道硅锗层的该加热发生在形成该栅极介电层期间及/或之后。
12.根据权利要求11所述形成半导体装置的方法，进一步包含：
在该栅极介电层上形成栅极，
其中，该硅衬底和该信道硅锗层的该加热发生在形成该栅极期间及/或之后。
13.一种半导体装置，包含：
衬底；
该衬底中的P型信道区；以及
该衬底上的该P型信道区之上的氟掺杂信道硅锗层，该信道硅锗层形成至40到80埃的厚度。
14.根据权利要求13所述的半导体装置，其中，该氟以5至10仟电子伏特的能量植入。
15.根据权利要求14所述的半导体装置，其中，该氟以1×1015至3×1015原子/平方公分的剂量植入，并且以650至1050℃进行退火。
16.根据权利要求14所述的半导体装置，其中，该氟以8×1014至2×1015原子/平方公分的剂量植入，并且以400至650℃进行退火。
17.根据权利要求13所述的半导体装置，进一步包含该信道硅锗层之上的栅极介电层。
18.根据权利要求17所述的半导体装置，进一步包含该栅极介电层之上的金属栅极。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/832,495 | 2013-03-15 | ||
| US13/832,495 US20140264484A1 (en) | 2013-03-15 | 2013-03-15 | Fluorine-doped channel silicon-germanium layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104051506A CN104051506A (zh) | 2014-09-17 |
| CN104051506B true CN104051506B (zh) | 2017-08-08 |
Family
ID=51419203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410097863.5A Expired - Fee Related CN104051506B (zh) | 2013-03-15 | 2014-03-17 | 氟掺杂信道硅锗层 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US20140264484A1 (zh) |
| KR (1) | KR20140113311A (zh) |
| CN (1) | CN104051506B (zh) |
| DE (1) | DE102014202684B4 (zh) |
| SG (1) | SG2014001598A (zh) |
| TW (1) | TWI627664B (zh) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101536174B1 (ko) * | 2014-02-11 | 2015-07-14 | 연세대학교 산학협력단 | 산소 확산을 억제할 수 있는 반도체 소자 제조 방법 |
| KR102391512B1 (ko) | 2017-08-17 | 2022-04-27 | 삼성전자주식회사 | 반도체 소자 |
| KR20200121941A (ko) | 2019-04-16 | 2020-10-27 | 삼성디스플레이 주식회사 | 표시 패널 및 표시 패널의 제조 방법 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093804A (zh) * | 2006-06-22 | 2007-12-26 | 台湾积体电路制造股份有限公司 | 半导体元件的形成方法 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6797555B1 (en) * | 2003-09-10 | 2004-09-28 | National Semiconductor Corporation | Direct implantation of fluorine into the channel region of a PMOS device |
| DE102009047304B4 (de) * | 2009-11-30 | 2012-04-26 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Leistungssteigerung in PFET-Transistoren mit einem Metallgatestapel mit großem ε durch Verbessern des Dotierstoffeinschlusses |
| US20120153350A1 (en) * | 2010-12-17 | 2012-06-21 | Globalfoundries Inc. | Semiconductor devices and methods for fabricating the same |
| US8507989B2 (en) * | 2011-05-16 | 2013-08-13 | International Business Machine Corporation | Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance |
| KR20120133652A (ko) * | 2011-05-31 | 2012-12-11 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
| US8828834B2 (en) * | 2012-06-12 | 2014-09-09 | Globalfoundries Inc. | Methods of tailoring work function of semiconductor devices with high-k/metal layer gate structures by performing a fluorine implant process |
-
2013
- 2013-03-15 US US13/832,495 patent/US20140264484A1/en not_active Abandoned
- 2013-11-27 TW TW102143198A patent/TWI627664B/zh not_active IP Right Cessation
- 2013-12-31 KR KR1020130169068A patent/KR20140113311A/ko not_active Application Discontinuation
-
2014
- 2014-01-09 SG SG2014001598A patent/SG2014001598A/en unknown
- 2014-02-14 DE DE201410202684 patent/DE102014202684B4/de not_active Expired - Fee Related
- 2014-03-17 CN CN201410097863.5A patent/CN104051506B/zh not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093804A (zh) * | 2006-06-22 | 2007-12-26 | 台湾积体电路制造股份有限公司 | 半导体元件的形成方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201436000A (zh) | 2014-09-16 |
| DE102014202684A1 (de) | 2014-09-18 |
| DE102014202684B4 (de) | 2015-05-13 |
| SG2014001598A (en) | 2014-10-30 |
| US20140264484A1 (en) | 2014-09-18 |
| KR20140113311A (ko) | 2014-09-24 |
| TWI627664B (zh) | 2018-06-21 |
| CN104051506A (zh) | 2014-09-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101432859B (zh) | 具有埋置应变层和减少的浮体效应的soi晶体管及其形成方法 | |
| JP4597531B2 (ja) | チャネル領域のドーパント分布がレトログレードな半導体デバイスおよびそのような半導体デバイスの製造方法 | |
| US6849516B2 (en) | Methods of forming drain/source extension structures of a field effect transistor using a doped high-k dielectric layer | |
| CN101517741B (zh) | 具有包含性能增进材料成分的受应变沟道区的晶体管 | |
| JP2005203770A (ja) | 半導体素子のトランジスタ及びその製造方法 | |
| CN104241110B (zh) | 利用氟掺杂形成半导体设备结构的方法及半导体设备结构 | |
| JP2008283182A (ja) | Ｐｍｏｓトランジスタ製造方法及びｃｍｏｓトランジスタ製造方法 | |
| CN104051506B (zh) | 氟掺杂信道硅锗层 | |
| CN110491944A (zh) | P型mosfet及其制造方法 | |
| TWI556320B (zh) | 半導體設備製造中低的熱預算方案 | |
| US7510923B2 (en) | Slim spacer implementation to improve drive current | |
| US10049917B2 (en) | FDSOI channel control by implanted high-K buried oxide | |
| US20050098818A1 (en) | Drain/source extension structure of a field effect transistor including doped high-k sidewall spacers | |
| CN104916540B (zh) | 一种应变沟道晶体管及其制备方法 | |
| KR101213723B1 (ko) | 반도체 소자 및 그 제조 방법 | |
| CN110364436B (zh) | 半导体器件及其形成方法 | |
| US20040053473A1 (en) | Method for fabricating semiconductor device | |
| CN105226095B (zh) | 一种半导体器件及其制备方法 | |
| TW490747B (en) | Method of forming a MOS transistor on a semiconductor wafer | |
| CN104637815B (zh) | Mos晶体管及其制备方法 | |
| CN112652663A (zh) | Mos晶体管及利用离子注入提高源漏掺杂浓度的方法 | |
| CN101814456A (zh) | 集成电路装置及其形成方法 | |
| CN108666269A (zh) | 一种整合虚拟侧墙工艺的方法 | |
| Claeys et al. | Influence of γ-Radiation on Short Channel SOI-MOSFETs with Thin SiO 2 Films | |
| JPS6126263A (ja) | 半導体装置の製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170808 Termination date: 20180317 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |