CN101432859B - 具有埋置应变层和减少的浮体效应的soi晶体管及其形成方法 - Google Patents

具有埋置应变层和减少的浮体效应的soi晶体管及其形成方法 Download PDF

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CN101432859B
CN101432859B CN200780014957XA CN200780014957A CN101432859B CN 101432859 B CN101432859 B CN 101432859B CN 200780014957X A CN200780014957X A CN 200780014957XA CN 200780014957 A CN200780014957 A CN 200780014957A CN 101432859 B CN101432859 B CN 101432859B
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germanium
silicon
strained silicon
junction
insulator
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CN101432859A (zh
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A·魏
T·卡姆勒
J·亨奇尔
M·霍斯特曼
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Advanced Micro Devices Inc
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Abstract

通过在有浮体架构的SOI晶体管(200，300，400)中之应变硅/锗材料(207，307，407)内形成一部分(209A，309A，409A)的PN结(209，309，409)，可明显增加结漏电，从而减少浮体效应。可基于注入及退火技术来实现定位PN结(209，309，409)之一部分(209A，309A，409A)于应变硅/锗材料(207，307，407)内，这与外延生长于原位掺杂之硅/锗来形成深漏极和源极区的习知方法相反。结果，可将高驱动电流能力与减少之浮体效应结合。

Description

具有埋置应变层和减少的浮体效应的SOI晶体管及其形成方法
技术领域
本发明大体有关于集成电路的形成，且更特别的是有关于通过使用漏极和源极区内的埋置应变层来形成具有应变信道区(strainedchannel region)的晶体管以增进MOS晶体管之信道区内的电荷载子移动率(charge carrier mobility)。
背景技术
集成电路的制造需要根据指定的电路布局在给定的芯片面积上形成大量的电路组件。一般而言，目前已实施复数个工艺技术，其中，对于复杂的电路，例如微处理器、储存芯片、及其类似物，由于从操作速度及/或耗电量及/或成本效率的角度看来有优异的特性，CMOS技术为目前最有前景的方法之一。在使用CMOS技术制造复杂的集成电路期间，有数百万个晶体管，亦即，N型信道晶体管与P型信道晶体管，形成于包含结晶半导体层的基板上。不论所考量的是N型信道晶体管还是P型信道晶体管，MOS晶体管都含有所谓的PN结，其系由以下两者的界面形成：高度掺杂的漏极/源极区、配置于该漏极区及该源极区之间的反向掺杂信道区。
用形成于信道区附近且通过薄绝缘层与该信道区隔离的栅极电极来控制信道区的导电率(亦即，导电信道的驱动电流能力)。在施加适当的控制电压于栅极电极来形成导电信道后，信道区的导电率则取决于掺质浓度、多数电荷载子的移动率，且对于信道区在晶体管宽度方向的给定延伸部分而言，其系取决于源极区与漏极区之间的距离，该距离也被称作信道长度。所以，结合在施加控制电压于栅极电极后即可在绝缘层下方快速产生导电信道的能力，信道区的整体导电率实质上决定了MOS晶体管的效能。因此，为了实现提高集成电路的操作速度，减少信道长度，以及减少与信道长度有关的信道电阻率，使得信道长度成为主要的设计准则。
持续缩减晶体管尺寸会产生复数个与此相关联的问题而必须加以处理以免过度地抵消掉逐步减少MOS晶体管信道长度所得到的优点。由于持续减少关键尺寸(亦即，晶体管的栅极长度)需要调适而且可能的话还要开发新的高度复杂的工艺技术，为了使晶体管组件的信道导电率也增强，有人已提出可通过增加信道区对于给定信道长度的电荷载子移动率，从而提供实现改善效能的潜力，而能与未来技术节点的进展匹敌，同时避免或至少延迟许多与器件缩放尺寸(device scaling)相关联的工艺调适所遭遇的许多问题。用来增加电荷载子移动率的一个有效机构是修改信道区中的晶格结构，例如通过在信道区附近产生拉伸(tensile)或压缩(compressive)应力以在信道区中产生对应的应变(strain)分别用来修改电洞移动率与电子移动率。例如，在信道区中产生压缩应变(compressive strain)可增加电洞的移动率，从而提供提高P型晶体管之效能的潜力。集成电路的制造导入应力或应变工程技术为极有前景而可用于下一个器件世代(device generation)的方法，因为，例如，应变硅(strained silicon)可视为是“新型”的半导体材料，这使得制造快速有力的半导体器件成为有可能而不需要昂贵的半导体材料，同时仍可使用许多广为接受的制造技术。
因此，有一个方法是，通过在晶体管之漏极/源极区中形成应变硅/锗层来增强PMOS晶体管的电洞移动率，其中压缩应变的漏极和源极区会在邻近的硅信道区中产生应变。为此目的，基于离子注入来形成PMOS晶体管的漏极和源极延伸区。之后，为了在随后的制造阶段中界定深漏极和源极结与金属硅化物(silicide)，按需要形成各个侧壁间隔物于栅极电极处。在形成深漏极和源极结之前，基于所述侧壁间隔物而选择性地使这些区域凹陷，同时屏蔽(mask)所述NMOS晶体管。随后，用外延生长(epitaxial growth)技术在PMOS晶体管中选择性地形成高度掺杂的硅/锗层。通常，在外延生长期间提供有某一程度之“溢出”的应变硅/锗以减少所欲应变硅/锗材料在硅化工艺(silicidation process)期间的消耗量，该硅化工艺系用来在漏极和源极区内形成金属硅化物以便得到减少之接触电阻。基于习知注入技术，在N型信道晶体管中选择性成长工艺及形成各个漏极和源极区后，可进行退火工艺以活化掺杂物，且使注入引发的损伤(implantation-induced damage)再结晶。此外，在退火工艺期间，也使应变硅/锗层内的掺杂物扩散，从而在应变硅/锗层外和在毗邻的硅材料内形成各自的PN结。
图1示意地图标于各个退火工艺108期间在基体(bulk)基板101上形成的对应之P型信道晶体管100。在此制造阶段中，晶体管100可包含栅极电极104，该栅极电极104系包含侧壁间隔物结构106且形成于使栅极电极104与本体区102隔开的栅极绝缘层105上，在施加适当的控制电压于栅极电极104时，可在本体区102中建立导电信道。在本体区102附近，延伸区103可位于包含有适当高之浓度之P型掺杂物的地方。紧邻在延伸区103旁形成高度P型掺杂的应变硅/锗区107。
如前述，可基于广为接受的技术形成晶体管100。在退火工艺108期间，如箭头所示，在延伸区103及应变区107内的掺杂物可扩散以最终得到完全位于硅基区(silicon-based region)102内的各个PN结109。之后，基于广为接受之硅化技术，可在应变硅/锗区107的过剩部分(excess portion)107A内和栅极电极104内形成金属硅化物(未图标)。
这种工艺技术可为基体器件提供显著的优点，在此可深蚀刻用于容纳应变硅/锗材料的各个凹洞(cavity)而且可在硅材料内配置PN结，藉此提供低漏电结(low leakage junction)。不过，结果证明，对于绝缘层上覆硅(SOI)器件，由于硅层的厚度有限而且在晶体管架构没有额外的本体接触(body contact)时浮体效应会增加，这种策略的效率可能会较差。
鉴于上述情形，亟须一种改良技术可利用应变半导体材料来提高SOI晶体管的效能，同时实质避免或至少减少一个或多个上述问题。
发明内容
以下提出本发明的概要以提供基本了解本发明的某些态样。此概要并非述尽本发明的概观。也不是旨在识别本发明的关键或重要组件或者是描绘本发明的范畴。唯一的目的是要以简要的形式提出一些概念作为以下更详细之说明的前言。
一般而言，本发明是针对一种提供有增强效能之SOI晶体管的技术，该SOI晶体管在各自漏极和源极区中包含用来在信道区中产生所需之应变的应变硅/锗材料，其中，在一个态样中，对应的应变硅/锗材料的位置与栅极电极靠得很近。此外，浮体效应，如没有额外本体接触件的部分空乏SOI晶体管常会遭遇者，可通过定位各自PN结之一部分于应变硅/锗材料内而显著减少，藉此增加各自结漏电(junctionleakage)，因为与硅相比，硅/锗具有大约100毫伏特(millivolt)的价带偏移(valence band offset)，因此增加各自本体/漏极/源极二极管电流和结漏电。结果，通常累积于浮体中的少数电荷载子可更有效地被放电(discharge)，从而使任何临界电压变化显著减少。根据一个态样，与习知技术相反，基于注入技术，可在应变硅/锗材料中有效地形成PN结，其中由于关于缺陷产生之预期到的困难，因此在选择性外延生长工艺期间，使漏极和源极区有高掺杂物浓度。
根据本发明之一个例示实施例，一种半导体器件包含形成于埋藏绝缘层(buried insulating layer)上的含硅半导体层与形成于该含硅半导体层上方的栅极电极，其中通过栅极绝缘层来隔开该栅极电极与该含硅半导体层。该半导体器件更包含形成于栅极电极之侧壁的侧壁间隔物(sidewall spacer)以及在与该侧壁间隔物毗邻之半导体层中形成的应变硅/锗材料。此外，漏极区及源极区系部分地形成于该应变硅/锗材料内，其中该漏极区与该源极区于其之间界定浮体区。所述漏极和源极区形成为以该浮体区界定各自PN结，其中所述PN结之一部分位于该应变硅/锗材料内。
根据本发明之另一例示实施例，一种方法包含：形成与栅极电极结构毗邻的凹处，该栅极电极结构包含在半导体层内的侧壁间隔物，该半导体层形成于埋藏绝缘层上。该方法更包含：在该凹处中形成应变硅/锗材料。此外，通过离子注入工艺与退火工艺形成与该栅极电极结构毗邻的漏极和源极区，其中所述漏极和源极区以浮体区界定各自PN结，以及其中所述漏极和源极区形成使得所述PN结之一部分是位在该应变硅/锗材料内。
根据本发明之又一例示实施例，一种方法包含：形成与栅极电极结构毗邻的凹处，该栅极电极结构包含在半导体层内的侧壁间隔物，该半导体层形成于埋藏绝缘层上。此外，在该凹处中形成第一应变硅/锗材料，且之后在该第一应变硅/锗材料上形成包含P型掺杂物材料的第二应变硅/锗材料。此外，通过离子注入工艺形成与该栅极电极结构毗邻的漏极和源极延伸区，以及进行退火工艺用于以浮体区界定各自PN结，其中所述PN结之一部分是位在应变硅/锗材料内。
附图说明
参考以下结合附图的说明可了解本发明，图中类似的组件用相同的组件符号表示，且其中：
图1系根据习知技术示意地图标呈基体配置之P型信道晶体管的剖面图，其中提供应变硅/锗材料且通过外扩散(out-diffusing)P型掺杂物来形成各个PN结，藉此配置完全在硅材料里面的各个PN结；
图2a至图2f系根据本发明的例示实施例示意地图标有浮体区之SOI晶体管处于各种制造阶段的剖面图，其中系以离子注入形成深漏极和源极区；
图3a至图3f系根据本发明的另一例示实施例示意地图标有浮体区之SOI晶体管处于各种制造阶段的剖面图，其中系基于可抛弃(disposable)间隔物使应变硅/锗材料与信道区靠得很近；以及
图4a至图4e根据本发明的另一例示实施例示意地图标有浮体区之SOI晶体管的剖面图，其中系基于原位掺杂和适当的退火工艺使部分PN结位于应变硅/锗材料内。
尽管本发明容许各种修改和替代形式，本文仍以附图为例图标本发明的特定实施例且详述于本文。然而，应了解本文所描述的特定实施例不是想要把本发明限制成为所揭示的特定形式，相反地，本发明是要涵盖落入由附上申请专利范围所界定之本发明精神及范畴内的所有修改、等效及替代者。
具体实施方式
以下描述本发明的例示实施例。为了清楚说明，本专利说明书没有描述实际实作的所有特征。当然，应了解，在开发任何此种实际实施例时，必需做许多实作特定的决策以达成开发人员的特定目标，例如符合与系统相关及商务有关的限制，这些都会随着每一个具体实作而有所不同。此外，应了解，此类开发既复杂又花时间，但对本技术领域中具有通常知识者而言，在阅读本揭示内容后将会像是例行工作一般。
现在根据附图来描述本发明。示意地图标于附图的各种结构、系统及器件均仅作解释目的且藉此使本发明不被熟习该技艺者所习知的细节混淆。然而，仍纳入附图用来描述及解释本发明的例示范例。应理解及解释本文所用的字汇及词组的意思都与相关技艺技术人员所理解的一致。没有特别定义的术语或词组(亦即，不同于熟习该技艺者所理解之一般及业界惯用意义的定义)想要用一贯使用的本文术语或词组来暗示。在想要术语或词组有特定的意思的程度上，亦即，不同于熟习该技艺者所理解的意思，此特定的定义会在本专利说明书中以直接明白地提供该术语或词组之定义的方式清楚地陈述。
本发明大体有关于带有浮体区的绝缘层上覆硅(SOI)晶体管架构，其中在部分漏极和源极区中以及在部分浮体区中以埋置硅/锗材料的形式提供有高度效率的应变引发机构(strain-inducing mechanism)。形成所述漏极和源极区以致于各个PN结有一部分(亦即，浮体区与高度P型掺杂的漏极/源极区之间的边界)是在应变硅/锗材料内。与硅材料相比，由于硅/锗材料的能带隙(band gap)减少而导致结漏电流增加(这被认为不宜用于基体器件)，对于浮体区内的累积电荷载子可提供有效的泄漏路径(leakage path)，从而可显著减少对应的操作取决(operation-dependent)的电位变化，这也被称作滞后效应(hysteresiseffect)。
通过适当地设计制造过程，亦即，通过控制用来形成对应凹洞或凹处的各个蚀刻工艺，适当地选择用于后续用以形成深漏极和源极区之注入工艺的注入参数以及适当的退火技术，可有效调整设于应变硅/锗材料内之各个PN结的面积，藉此也可提供能用来调适结漏电流的所需程度的控制机构。与习知在可容忍之缺陷率(defect rate)下提供高掺杂浓度必须基于原位掺杂应变硅/锗材料的教导相反，以注入方式形成的PN结能够导致结漏电流显著增加，从而可显著减少浮体效应同时仍能保持通过提供应变硅/锗材料所得到的改良驱动电流能力。在其它的实施例中，通过使用可抛弃间隔物来配置靠近信道区的应变半导体材料仍可增加有浮体区之SOI晶体管的效能，其中可调整应变硅/锗材料的偏移而与其它的器件要求无关，例如在漏极/源极区中形成金属硅化物的器件要求。结果，甚至可进一步增加位于应变硅/锗材料内之PN结的各个部分，从而提供进一步减少浮体效应的可能性。此外，应变硅/锗材料不一定要有用来容纳金属硅化物的过剩高度以免使信道区附近的应变材料过度松弛，这在习知技术通常会这样，因为在实质上呈平坦配置的漏极和源极区中形成金属硅化物仍会在信道区与金属硅化物之间留下有高度应变的硅/锗材料。结果，若于各个金属硅化物区上方可提供应力被覆层(stressed overlayer)时，可进一步增强由应力被覆层转移应力至各个信道区。
此外，在本发明之一些实施例中，各个PN结有一部分可在应变硅/锗材料内，且通过适当地组合注入顺序和应变硅/锗材料的掺杂及无掺杂之外延生长技术而使应变硅/锗材料内产生的注入引发损伤减少。
现在根据附图更详细地描述本发明进一步的例示实施例。图2a示意地图标半导体器件200的剖面图，该器件为带有浮体区的SOI晶体管。该晶体管200在此制造阶段可包含含有基材(base material)210和形成于其上之埋藏绝缘层211的基板201。例如，基板201可代表硅基板，其中有基材210，而再于其上形成二氧化硅层或任何其它合适的绝缘材料作为埋藏绝缘层211。形成于埋藏绝缘层211上的是含硅结晶层202，其中与层202的任何其它成份相比，硅含量有50原子百分比的硅或更多。半导体层202具有用来形成部分或完全空乏之SOI晶体管所需要的厚度，其中，在一些例示实施例中，半导体层202的厚度大约是在10至100奈米的范围内。此外，在半导体层202上方形成栅极电极204且通过栅极绝缘层205来与它隔开。例如，在一个例示实施例中，在此制造阶段，栅极电极204可由掺杂或未掺杂的多晶硅(polysilicon)构成，其中栅极电极204的长度(亦即，图2a中栅极电极的水平延伸部分)大约为100奈米及明显更短，例如约50奈米及以下。栅极绝缘层205可代表任何合适的电介质材料，例如二氧化硅、氮化硅、高K的电介质材料、彼等之组合、及其类似物。栅极电极204可在其上表面上形成由例如氮化硅或任何其它合适材料构成的覆盖层212。此外，在栅极电极204之侧壁可设置包含间隔物213与衬里(liner)214(如有必要)的侧壁间隔物结构。可形成有适当高之浓度之P型掺杂物的各个注入区203于包含间隔物结构213的栅极电极204附近，而可为仍待形成的深漏极和源极区的漏极和源极延伸区。
如图2a所示，用于形成晶体管200的典型工艺流程可包含以下工艺。在提供其上可能已形成含硅层202的基板201后，可进行广为接受的工艺(如有必要)，包括形成隔离结构(未图标)以及在层202中建立特定的垂直掺质分布(dopant profile)。之后，可由基于氧化及/或沉积技术所形成的各个材料层来图案化栅极电极204、覆盖层202与门极绝缘层205，接着实施精密的微影及蚀刻技术。之后，如有必要，可用例如氧化法形成衬里214，随后通过沉积介电层和非等向性蚀刻该介电层来形成间隔物213。接下来，可进行注入工艺215以产生漏极和源极延伸区203，其中根据仿真、实验及其类似方法可轻易建立各个注入参数。
图2b示意地图标处于下一个制造阶段的晶体管200。根据器件要求，在栅极电极204之侧壁上形成另一侧壁间隔物结构206，其中间隔物结构206的宽度的选择与在形成深漏极和源极区用之后续注入工艺期间的屏蔽效应(masking effect)有关，也与金属硅化物形成工艺期间的屏蔽效应有关。此外，在邻近间隔物结构206的半导体层202中形成各个凹处或凹洞216。基于广为接受的技术可形成间隔物结构206，如有必要，包括共形(conformal)沉积衬里材料，例如二氧化硅及其类似物，以及随后沉积间隔物材料，例如氮化硅及其类似物，接着进行非等向性蚀刻工艺以移除先前所沉积之间隔物层的水平部分，其中各个衬里(若有的话)可用作有效的蚀刻中止层。应了解，在用于形成凹处216的蚀刻工艺217之前，可屏蔽其它的器件面积，这包括例如N型信道晶体管。基于广为接受的配方，可进行蚀刻工艺217，其中可适当地调整工艺参数(例如，高分子产生剂(polymer generator)的浓度、离子轰击的方向、离子的辐射流密度(flux density)及其类似者)，以便使间隔物结构206有某一程度的蚀刻不足(under-etching)。此外，由于层202的厚度有限，停止蚀刻工艺217以便留下某一数量的结晶体材料给后续的选择性外延生长工艺用。
图2c示意地图标选择性外延生长工艺218期间在凹处216中成长应变硅/锗材料207时的半导体器件200。在外延生长工艺218期间，用覆盖层212与间隔物结构206可靠地覆盖栅极电极204。在一个例示实施例中，如同习知技术，以不添加P型掺杂物材料的方式实质地执行选择性外延生长工艺218，藉此可提供应变硅/锗材料207作为实质上无掺杂的材料。结果，可显著降低外延生长工艺218的工艺复杂度，因为以适当高之掺杂程度来原位掺杂硅/锗材料可能需要精密稳定地控制各个工艺参数，例如各个沉积大气中之前驱物(precursor)与载体气体(carrier gas)的浓度、各自压力、基板的温度及其类似者。此外，可在应变硅/锗材料207上方提供过剩部分207A，亦即，在一些实施例中，应变半导体材料207可延伸高于由栅极绝缘层205的上表面205S所界定的高度。在一些例示实施例中，由于后面的制造阶段会消耗过剩部分207A从而将它转变成金属硅化物，过剩部分207A的数量可实质上对应于半导体材料的数量。在其它的例示实施例中，可以硅材料的形式来提供过剩部分207A，因此可提高在部分207A中形成金属硅化物的弹性。就此情形而言，可使用复数个广为接受的硅化技术，而硅/锗材料207的存在对此实质上不会有影响。
图2d示意地图标注入工艺219期间的晶体管200，以形成向下延伸至埋藏绝缘层211的高度P型掺杂深漏极和源极区220。应了解，可基于数种工艺参数进行注入工艺219以便保持应变硅/锗材料207中至少有一部分(如207B所示)实质上未被掺杂，或进行分开的注入步骤(例如，环状注入(halo implantation)及其类似者)以便在部分207B中产生各个想要的N型掺杂面积。如先前所述，通过在蚀刻工艺217期间产生某一程度的非等向性(图2b)，可保证在注入工艺219期间部分207仍被屏蔽着，其中在想要减少部分207B的大小时，通过在注入219期间选定适当的倾斜角度也可调整部分207B的大小。另一方面，如果想要部分207B有更显著的PN结，可用相对于用来形成深漏极和源极区220之P型掺杂物为相反的掺杂物(counter dopant)来进行各个倾斜式环状注入工艺。
图2e示意地图标退火工艺208期间用于活化延伸区203及深漏极和源极区220中之掺杂物的晶体管200。如箭头225所示，区域203及220的P型掺杂物正在扩散，同时可实质上使结晶体被注入215(图2a)及219(图2d)损伤的地方再结晶。可适当选定退火工艺208的参数以便得到有想要形状的PN结209，其中在应变硅/锗材料内形成彼之一部分(以209A表示)。例如，可选定退火工艺208的温度与持续时间使得P型掺杂物的平均扩散长度小于在注入工艺219所沉积的各个PN结与应变硅/锗材料207的边界之间的距离。就此情形而言，能使PN结209的部分209A可靠地保持在应变硅/锗材料207内。例如，如先前所述，于形成凹处216期间与工艺219之注入参数结合的非等向程度可产生充分的偏移以允许有效的掺杂物活化和再结晶，同时仍保持部分209A于材料207内。由于可轻易调查及/或计算应变硅/锗材料中之P型掺杂物的扩散行为，基于各个结果可建立一组合适的工艺参数。结果，基于上述程序，能可靠地控制部分209A的面积(亦即，图2e剖面的长度)，从而也能调整结漏电流量以及由浮体区(实质上由最终得到的PN结209界定)移除累积电荷载子的效率。结果，基于注入技术，在部分应变硅/锗材料内可有效地形成各个漏极和源极区220，同时可控制结漏电流的程度以便显著地减少浮体效应。
图2f示意地图标处于下一个制造阶段的晶体管200，其中在过剩部分207A与栅极电极204中都形成金属硅化物区222。如前述，取决于过剩部分207A内含之材料的类型，可使用合适的硅化技术。例如，如果以硅的形式来提供过剩部分207A，任何合适的材料(例如，铂、镍、钴、或彼等的组合)都可用来形成各个金属硅化物。由于金属硅化物222实质上局限于过剩部分207A，因此实质上不会造成区域207的应变松弛，从而在本体区221内可提供有效的应变产生机构(strain generatingmechanism)。
此时，参考图3a至图3f，更详细地描述本发明的其它例示实施例，与用图2a至图2f所图标及描述的实施例相比，在此应变硅/锗材料的位置更为靠近栅极电极。
图3a中，晶体管300包含基板301，该基板301包含基材310与于其上已形成半导体层302的埋藏绝缘层311。关于所述组件的性质，适用与先前描述图2a所用的标准。此外，处于此制造阶段时，晶体管300包含栅极电极304，该栅极电极304形成于半导体层302上方且通过栅极绝缘层305而与该半导体层302隔开。覆盖栅极电极304的上表面的覆盖层312和各个有特定宽度313W的间隔物结构313结合衬里314一起用来囊封栅极电极304。在一个例示实施例中，包含衬里314之间隔物313的宽度可约为10奈米或明显更小，而且在一些例示实施例中，甚至约为2奈米及以下。基于实质上与先前根据图2a所描述的相同的工艺技术，可形成如图3a所示之晶体管300。应了解，基于共形沉积技术和接着进行广为接受的非等向性蚀刻工艺，可形成间隔物结构313。基于氧化工艺，可形成衬里314。
图3b示意地图标蚀刻工艺317期间的晶体管300，该工艺系用来在邻近间隔物结构313的半导体层302中形成各个凹处或凹洞316。取决于间隔物宽度313W和想要的蚀刻不足程度，可适当控制蚀刻工艺317的非等向性程度。亦即，对于低间隔物宽度313W，可将蚀刻工艺317设计成实质上呈非等向的蚀刻工艺以实质上避免在栅极绝缘层305附近造成不适当的蚀刻破坏(etch attack)。以高度非等向方式用来蚀刻硅材料的对应蚀刻配方在本技术领域中是广为接受的，这些配方可选择例如氮化硅、二氧化硅、及其类似物。
图3c示意地图标选择性外延生长工艺318期间的晶体管300，该工艺318用来在凹处316中形成应变硅/锗材料307。在外延生长工艺318期间，可成长无掺杂的硅/锗材料，从而如先前所解释的，与包含原位掺杂的习知策略相比，可放宽工艺控制的限制。此外，在一个例示实施例中，可形成应变硅/锗材料307到达栅极绝缘层305所界定的高度，因为可能不需要有容纳金属硅化物的过剩高度，对此随后会加以说明。之后，例如当覆盖层312与间隔物313大体由氮化硅组成时，基于以热磷酸为基础之高度选择性的湿式化学蚀刻配方，可选择性移除间隔物313与覆盖层312。
图3d示意地图标注入工艺315期间的晶体管300，该注入工艺315系用来在层302与部分应变硅/锗材料307中形成各个延伸区303。取决于延伸区303相对于栅极电极304的必要偏移，可在栅极电极304的侧壁上形成额外的偏移间隔物(未图标)。
图3e示意地图标处于下一个制造阶段的晶体管300。在此，栅极电极304上已形成另一个间隔物结构306，如有必要，它可包含任何合适数目的个别间隔物组件与各个衬里材料，以使深漏极和源极区320有想要的侧向及垂直轮廓(profiling)。为此目的，使器件300暴露于注入工艺而用于以必要的高掺杂浓度导入P型掺杂物。应了解，如果需要更加复杂的深漏极和源极区320之侧向轮廓，可以间歇方式进行间隔物结构306的形成和注入工艺的个别步骤。在图标的范例中，间隔物结构306中可提供单一间隔物组件，它可基于广为接受的间隔物技术来形成，之后可进行注入以得到如图标的深漏极和源极区320。接下来，基于适当选定的工艺参数(例如，持续时间、温度、以热传递的类型)，以便适当地使注入引发的损伤再结晶并且活化由注入工艺导入的掺杂物。应了解，在其它的例示实施例中，取决于工艺策略，在注入315后以及在形成深漏极和源极区320之前，可分开退火所述延伸区303。此外，如先前参照器件200所解释的，在注入315之前或之后以及在用于形成漏极和源极区320的注入工艺之前，可进行其它的注入工艺，例如环状注入及其类似者。
如先前所解释的，可事前决定各个P型掺杂物材料的扩散率以便适当地选定各个退火参数，其中，就此情形而言，由于在靠近栅极电极304的地方形成各个凹洞316，可使实质上无掺杂或被反掺杂之应变硅/锗材料的部分307B显著增加。因此，在退火工艺308期间，起动P型掺杂物的扩散以便最终形成各个PN结309，而PN结309而它有明显的部分309A是在应变硅/锗材料307内。结果，器件300包含浮体区321，而有一部分(亦即，部分307B)是由靠近本体区321之区域的应变硅/锗材料构成，其中信道可在器件300操作后形成。结果，由于应变硅/锗材料与本体区321的各个信道部分靠得很近，而各自可以高度有效的方式得到其中的应变。此外，如上述的工艺策略可导致部分307B明显增加，从而使位于应变硅/锗材料内之PN结309的部分309A增加。结果，可使结漏电流增加，从而进一步减少任何浮体效应。因此，器件300可提供增加的驱动电流能力和减少的浮体效应。
基于蚀刻工艺317以及基于宽度313W与深漏极和源极区320有另一侧向轮廓(可用一个或多个间隔物组件结合各个注入工艺来实现)，可轻易控制部分309A的大小。此外，适当的退火工艺参数也可用来控制P型掺杂物的外扩散程度以使部分309A有想要的大小。例如，在一些例示实施例中，可使用精密的退火技术，其中可使用基于雷射或基于快闪(flash-based)的工艺，其中可对器件300照射短脉冲(shortduration pulse)辐射以便以极为局部的方式加热半导体层302。因此，可实现高度的掺杂物活化，同时由于活化过程的持续时间短而使掺杂物的扩散显著减少。另一方面，如有必要，以大约600至800℃范围内的降低后的温度进行热处理，可使注入引发的损伤再结晶。以此方式，可显著减少掺杂物材料的扩散同时仍可达成高度的晶格再结晶。应注意，结合根据图2a至图2e所描述的实施例，也可有效使用对应的先进退火技术。
图3f示意地图标处于下一个制造阶段的晶体管300。在此阶段，晶体管300更包含形成于应变硅/锗材料307之上半部和栅极电极304内的金属硅化物区322。如先前所述，可形成金属硅化物322于材料307内而不提供过剩部分，由于部分307C中仍有应变硅/锗材料，因此在位于栅极绝缘层305下方的信道区321C中可提供有效的应变引发机构。在一些例示实施例中，晶体管300可进一步包含压缩应力被覆层323，它可由例如氮化硅组成，基于电浆增强化学气相沉积(PECVD)技术可使它具有高压缩应力，从而进一步提高信道区321C内的应变。此外，由于金属硅化物区322相对于栅极绝缘层305实质上有平坦的配置，与图1及图2f的设计相比，可实现由被覆层323到信道区321C的更有效的应力转移，其中实质上松弛的金属硅化物部分会减少应力通过对应的侧壁间隔物结构转移的有效性。结果，由于基于应变部分307C而有极有效的应变产生机构以及通过被覆层323而得到增强的应力转移机构，如图3f所示的配置可提供高驱动电流能力，另外，同时PN结309A有良好可控性及增加的大小因而可提供高结漏电流，从而可使浮体区321的电位变化显著减少。
此时，参考图4a至图4e，更详细地描述本发明的其它例示实施例，其中可结合注入技术和原位掺杂的外延生长技术用来减少应变硅/锗材料的注入引发的损伤。
图4a中，SOI晶体管400可包含基板401，该基板401系包含基材410与埋藏绝缘层411，其中有半导体层402形成于该埋藏绝缘层411上。此外，栅极电极404可形成于栅极绝缘层405上且可包含侧壁间隔物结构406与覆盖层412。此外，处于此制造阶段时，在半导体层402中可形成延伸区403。关于各种组件和用于形成所述组件的任何工艺技术，可参考于先前依据图2a至图2f所描述的实施例。此外，在一个例示实施例中，可使晶体管400暴露于用来形成深漏极和源极区420的注入工艺419。藉此，选定注入参数使得对应的深漏极和源极区420可在想要的蚀刻深度下方延伸，如图中虚线所示，用来形成后续填满应变硅/锗材料的各个凹处或凹洞。
图4b示意地图标处于下一个制造阶段的晶体管400，其中系进行选择性外延生长工艺418，其中在工艺418A的第一期时，成长实质上无掺杂的应变硅/锗材料407A，随后添加合适的掺杂物前驱物材料于沉积大气以便提供含有高浓度之P型掺杂物材料的第二应变硅/锗材料407B。如先前所述，特别是由于硅/锗材料的固有性质，可高度精准地控制用于形成实质上未掺杂之应变材料407A的第一期。结果，可提供有高的P型掺杂浓度的部分407C，同时在毗邻面积中，无掺杂的材料407A就在具有实质上无P型掺杂物材料的邻近硅材料旁边。因此，在深漏极和源极区420附近，以及延伸区403附近，对应之无掺杂材料407A的两侧被高度P型掺杂的半导体材料包围，同时在深漏极和源极区420与延伸区403之间的面积中，固有部分407A中只有一个“邻居”包含高的P型掺杂浓度。结果，在后续的退火工艺期间，可达成至对应于延伸区403与深漏极和源极区420之无掺杂材料407A的增加的扩散作用，同时可使部分407C附近的扩散作用明显减少。结果，在延伸区403与深漏极和源极区420附近，增加的掺杂物扩散可“跨过(bridge)”实质上未掺杂的部分407A，同时在部分407A附近可建立各自的PN结于实质上无掺杂部分407A内。应了解，适当选定用于工艺418的参数(亦即，实质上无掺杂部分407A的厚度)，结合适当选定的退火参数，可使得PN结有一部分能可靠地在应变硅/锗材料内形成。
图4c示意地图标上述退火工艺完成后的晶体管400。因此，这时对应的深漏极和源极区420可继续向下延伸到埋藏绝缘层411而且延伸区403也可与深漏极和源极区420相连，从而形成各个PN结409，同时其仍有一部分(以409A表示)位于应变硅/锗材料407A/407B内。应了解，在其它的例示实施例中，当增加之结电容较不要紧时，注入419可省略而且在各自之退火工艺后可得到实质上完全是在实质上无掺杂区407A内的结409。
图4d示意地图标根据另一例示实施例的晶体管400，其中基于适当设计过的间隔物413，在栅极电极404附近已形成各个凹处416以便得到凹处416相对于栅极电极404有减少的偏移。此外，在较早的制造阶段，可能已形成延伸区403，当对应之注入工艺是在后面阶段时，亦即在形成外延生长的硅/锗材料之后，这被认为是不适宜的。此外，在此阶段可进行注入419，藉此在半导体层402的其余部分中导入P型掺杂物，其中减少的掺杂浓度与减少的注入能量在其余的硅部分中可导致程度明显减少的晶体损伤。在其它的例示实施例中，在对应之蚀刻工艺之前可进行注入419，如同先前在说明图4a时所描述的。之后，如同先前在说明工艺418时所描述的，可进行对应的外延生长工艺。
图4e示意地图标各个外延生长工艺完成后的晶体管400。因此，形成实质上未掺杂的硅/锗材料407A于深漏极和源极区420上方，接着是高度原位掺杂的材料407B。之后，如先前所解释的，可进行对应的退火工艺以形成各个漏极和源极区和各个PN结409，其中各个PN结有一部分也都仍在应变硅/锗材料407A、407B内。之后，可继续其它的处理用来移除各个间隔物413与覆盖层412而且形成额外的侧壁间隔物供后续的硅化工艺用。结果，以上用图4a至图4e描述的实施例可提供应变硅/锗材料，其中各个PN结有一部分系在硅/锗材料内，同时由于结合用于形成实质上本质及高度掺杂之应变半导体材料的外延生长工艺而可显著减少应变硅/锗材料中的注入引发的损伤。
结果，本发明提供一种改良技术可用来形成有浮体区的SOI晶体管，其中系结合高度有效率的应变引发机构和增加之结漏电流以显著减少浮体效应。为此目的，在一些态样中，注入工艺可用来取代应变硅/锗材料的原位掺杂，因此对于各个PN结的设计可提供高度弹性，其中能可靠地保证各个PN结有一部分是在应变半导体材料内，从而提供想要增加之结漏电流。例如，在如图3a至图3f所述的实施例中，在相同的晶体管参数下，与如图1所示的习知整合方案相比，结漏电流的增加可达6个数量级。与习知整合方案相比，如图2a至图2f所述的实施例也可提供约有2个数量级的结漏电流之显著增加。另外，可使应变半导体材料接近栅极电极，其中可达成大约2奈米及甚至更少的偏移，从而也能提高各个信道区内的应变而可各自对应地转换成驱动电流能力的增加。在其它态样中，可结合应变硅/锗材料的注入、原位掺杂、以及本质外延生长(intrinsic epitaxial growth)以降低应变半导体材料的整体缺陷率。
显然熟习该技艺者在藉助于本文的教导后可以不同但为等效的方式来修改及实施本发明，故以上所揭示的特定实施例都仅供例示用。例如，可用不同的顺序进行以上所提及的工艺步骤。此外，不希望限制本文所示之构造或设计的细节，除了以下的申请专利范围所述者。因此，显然可改变或修改以上所揭示的特定实施例而应将所有此类变体视为仍在本发明的范畴与精神内。因此，在此寻求的保护范围系如以下提出的申请专利范围。

Claims (7)

1.一种形成绝缘层上覆硅晶体管的方法，包括下列步骤：
形成与栅极电极结构毗邻的凹处，该栅极电极结构包含在半导体层内的侧壁间隔物，该半导体层形成于埋藏绝缘层上；
通过选择性外延生长工艺在该凹处中形成第一应变硅/锗材料；
在该第一应变硅/锗材料上形成第二应变硅/锗材料，该第二应变硅/锗材料包括P型掺杂物；以及
通过离子注入工艺与退火工艺形成与该栅极电极结构毗邻的漏极与源极区，所述漏极与源极区以浮体区界定各自的PN结，所述PN结的一部分位于该第一应变硅/锗材料内。
2.如权利要求1所述的形成绝缘层上覆硅晶体管的方法，进一步包括在该第一应变硅/锗材料上形成过剩半导体材料以得到高度延伸超过由栅极绝缘层界定的高度，该栅极绝缘层形成于该栅极电极与该半导体层之间。
3.如权利要求2所述的形成绝缘层上覆硅晶体管的方法，其中，该过剩半导体材料形成为第二应变硅/锗材料。
4.如权利要求2所述的形成绝缘层上覆硅晶体管的方法，其中，该过剩半导体材料形成为硅材料。
5.如权利要求1所述的形成绝缘层上覆硅晶体管的方法，进一步包括在形成该凹处之前，通过离子注入法形成漏极与源极延伸区。
6.如权利要求1所述的形成绝缘层上覆硅晶体管的方法，进一步包括：
在形成该凹处之后以及在形成该第一应变硅/锗材料之后，移除该侧壁间隔物；以及
在该栅极电极的侧壁形成器件间隔物结构，其中，基于该器件间隔物结构来形成所述漏极与源极区。
7.如权利要求1所述的形成绝缘层上覆硅晶体管的方法，进一步包括在形成该第一应变硅/锗材料之前，在该半导体层的底面导入P型掺杂物于该半导体层中。
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