JP2007525813A - 犠牲注入層を用いて非晶質ではない超薄膜半導体デバイスを形成させるための方法 - Google Patents
犠牲注入層を用いて非晶質ではない超薄膜半導体デバイスを形成させるための方法 Download PDFInfo
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- JP2007525813A JP2007525813A JP2005513128A JP2005513128A JP2007525813A JP 2007525813 A JP2007525813 A JP 2007525813A JP 2005513128 A JP2005513128 A JP 2005513128A JP 2005513128 A JP2005513128 A JP 2005513128A JP 2007525813 A JP2007525813 A JP 2007525813A
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- 239000007943 implant Substances 0.000 title claims description 40
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- 239000013078 crystal Substances 0.000 claims abstract description 20
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- 229910052710 silicon Inorganic materials 0.000 claims description 45
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
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- 229910052787 antimony Inorganic materials 0.000 claims description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 3
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Abstract
Description
Claims (20)
- 半導体デバイスを形成させるための方法であって、
単結晶基板(106)の上に犠牲層(108)を定める工程、
前記単結晶基板(106)が実質的に非晶質化されないように、ドーパント化学種を前記犠牲層(108)に注入する工程、および
前記ドーパント化学種を前記犠牲層(108)から前記単結晶基板(106)中に移動させるように、前記犠牲層(108)をアニールする工程
を含む方法。 - 前記犠牲層(108)は、酸化物層、窒化物層およびオキシ窒化物層の少なくとも一つをさらに含む誘電体層である、請求項1に記載の方法。
- ハロ注入部を形成させる工程をさらに含み、前記犠牲層(108)のアニーリングの前に、前記ドーパント化学種に加えて、さらに損傷発生化学種を前記犠牲層(108)に注入する、請求項1に記載の方法。
- 前記損傷発生化学種は、シリコン、ゲルマニウム、インジウム、フッ素および貴ガスの少なくとも一つをさらに含む、請求項3に記載の方法。
- 前記犠牲層(108)を用いて拡張注入部を形成させる工程をさらに含む、請求項3に記載の方法。
- 前記ハロ注入部のためのアニーリングは、前記拡張注入部の場合より高い温度および長い時間実施される、請求項5に記載の方法。
- 前記犠牲層(108)は、シリコン基板の上に形成される酸化物層をさらに含み、前記酸化物層は、約15から約100オングストロームの厚さで形成される、請求項1に記載の方法。
- 前記ドーパント化学種の注入エネルギーは、前記ドーパント化学種のピーク濃度を前記酸化物層の中間付近に位置させるように選ばれる、請求項7に記載の方法。
- 前記単結晶基板は、約100オングストローム未満のシリコン厚さを有するシリコン・オン・インシュレータ(SOI)デバイスのシリコン領域をさらに含む、請求項1に記載の方法。
- 前記単結晶基板は、約200オングストローム未満の厚さを有する電界効果トランジスタ(FET)デバイスのシリコン領域をさらに含む、請求項1に記載の方法。
- 前記単結晶基板(106)の上に形成されたパターン化されたゲートスタック(100)の上に前記犠牲層(108)を定める工程、
前記犠牲層(108)に前記注入する工程と、前記犠牲層(108)を前記アニールする工程とによって、ハロ注入部を形成させる工程、および
前記犠牲層(108)の別の注入工程およびアニーリング工程によって、拡張注入部を形成させる工程
をさらに含む、請求項1に記載の方法。 - 前記犠牲層(108)は、酸化物層、窒化物層およびオキシ窒化物層の少なくとも一つをさらに含む誘電体層である、請求項11に記載の方法。
- 前記ハロ注入部の形成の間に、前記犠牲層(108)のアニーリングの前に、前記ドーパント化学種に加えて、さらに損傷発生化学種を前記犠牲層(108)に注入する、請求項12に記載の方法。
- 前記損傷発生化学種は、シリコン、ゲルマニウム、インジウム、フッ素および貴ガスの少なくとも一つをさらに含む、請求項13に記載の方法。
- 前記ハロ注入部のためのアニーリングは、前記拡張注入部の場合より高い温度および長い時間実施される、請求項13に記載の方法。
- 前記犠牲層(108)は、シリコン基板の上に形成される酸化物層をさらに含み、前記酸化物層は、約15から約100オングストロームの厚さで形成される、請求項12に記載の方法。
- 前記ドーパント化学種の注入エネルギーは、前記ドーパント化学種のピーク濃度を前記酸化物層の中間付近に位置させるように選ばれる、請求項16に記載の方法。
- 前記単結晶基板は、約100オングストローム未満のシリコン厚さを有するシリコン・オン・インシュレータ(SOI)デバイスのシリコン領域をさらに含む、請求項11に記載の方法。
- 前記単結晶基板は、約200オングストローム未満の厚さを有する電界効果トランジスタ(FET)デバイスのシリコン領域をさらに含む、請求項11に記載の方法。
- 前記ドーパント化学種は、ヒ素(As)、リン(P)、アンチモン(Sb)、ホウ素(B)およびホウ素フッ素(BF2)の少なくとも一つを含む、請求項11に記載の方法。
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PCT/US2003/038559 WO2005067035A1 (en) | 2003-12-04 | 2003-12-04 | Method for forming non-amorphous, ultra-thin semiconductor devices using sacrificial implantation layer |
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US (1) | US20080311732A1 (ja) |
EP (1) | EP1695381A4 (ja) |
JP (1) | JP2007525813A (ja) |
CN (1) | CN100405581C (ja) |
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JP2007123406A (ja) * | 2005-10-26 | 2007-05-17 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
DE102006009226B9 (de) * | 2006-02-28 | 2011-03-10 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Herstellen eines Transistors mit einer erhöhten Schwellwertstabilität ohne Durchlass-Strombeeinträchtigung und Transistor |
JP5525127B2 (ja) * | 2007-11-12 | 2014-06-18 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその製造方法 |
US8598006B2 (en) * | 2010-03-16 | 2013-12-03 | International Business Machines Corporation | Strain preserving ion implantation methods |
US9040394B2 (en) * | 2013-03-12 | 2015-05-26 | Samsung Electronics Co., Ltd. | Method for fabricating a semiconductor device |
US9373512B2 (en) | 2013-12-03 | 2016-06-21 | GlobalFoundries, Inc. | Apparatus and method for laser heating and ion implantation |
US9876110B2 (en) * | 2014-01-31 | 2018-01-23 | Stmicroelectronics, Inc. | High dose implantation for ultrathin semiconductor-on-insulator substrates |
US9601333B2 (en) * | 2014-10-02 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Etching process |
US11018259B2 (en) * | 2015-12-17 | 2021-05-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device comprising gate structure and doped gate spacer |
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- 2003-12-04 AU AU2003298876A patent/AU2003298876A1/en not_active Abandoned
- 2003-12-04 US US10/596,168 patent/US20080311732A1/en not_active Abandoned
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CN1879210A (zh) | 2006-12-13 |
CN100405581C (zh) | 2008-07-23 |
EP1695381A4 (en) | 2008-09-17 |
US20080311732A1 (en) | 2008-12-18 |
AU2003298876A1 (en) | 2005-08-12 |
EP1695381A1 (en) | 2006-08-30 |
WO2005067035A1 (en) | 2005-07-21 |
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