CN1879210A - 用于使用牺牲的注入层形成非无定形超薄半导体器件的方法 - Google Patents

用于使用牺牲的注入层形成非无定形超薄半导体器件的方法 Download PDF

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CN1879210A
CN1879210A CNA2003801107858A CN200380110785A CN1879210A CN 1879210 A CN1879210 A CN 1879210A CN A2003801107858 A CNA2003801107858 A CN A2003801107858A CN 200380110785 A CN200380110785 A CN 200380110785A CN 1879210 A CN1879210 A CN 1879210A
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奥马尔·H·多库马西
保罗·郎西姆
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Abstract

一种用于形成半导体器件的方法，包括在单晶衬底(106)上方限定牺牲层(108)。以防止该单晶衬底(106)基本上无定形化的方式采用掺杂剂物质对该牺牲层(108)注入。对该牺牲层(108)退火以便驱使所述掺杂剂物质从所述牺牲层(108)进入所述单晶衬底(106)。

Description

用于使用牺牲的注入层形成 非无定形超薄半导体器件的方法
技术领域
本发明一般地涉及半导体器件处理，并且，更具体地涉及使用牺牲的注入层形成非无定形超薄半导体器件的方法。
背景技术
在硅衬底内形成超浅p+和n+掺杂区是在集成电路内使用的金属氧化物半导体(MOS)晶体管及其他半导体器件的制造中的决定性步骤。MOS晶体管不断减少的尺寸要求晶体管的所有横向和垂直尺寸都缩减。在传统的按比例缩放方案中，结的深度与栅长度线性地按比例缩放，该结形成MOS晶体管的源和漏区。因此，在目前的半导体制造业中需要具有适当地低表面电阻的p+和n+区的浅结。
在传统的半导体制造法中，浅结可以由离子注入继之以退火，如快速热退火(RTA)，而形成。此技术的可靠性在该技术中已知可以低至300到400埃的结深度。制造兼备小于300或400埃的结深度和适当地低表面电阻的掺杂区的任务是更大的挑战。完成此任务对于通过硼的注入和扩散特性实现p-型浅掺杂区尤其困难。在这方面重要的问题包括控制掺杂剂沟道、减少热扩散、和抑制暂时增强的扩散，特别是在硼和磷的情况下。而且以低的表面电阻的浅区(即，以高杂质浓度)仅能实现良好的器件性能。按比例缩放已经趋向于在保持总掺杂剂水平大体上恒定的同时降低离子注入能量，并且通过引入快速热退火和电火花退火，在不显著地恶化掺杂剂激活水平的情形下降低热聚积。
传统的按比例缩放预计在300至400埃的结深度以下变得困难，尤其对于p+结。制造大电流、低能量离子注入束的技术困难可以通过利用等离子体掺杂(换句话说称作等离子体浸入离子注入)来减轻。也已经考虑完全避免注入的替换处理工艺。这种工艺的例子包括快速热汽相掺杂、气体浸入激光掺杂、和固态热扩散，如从BSG(硅酸硼玻璃)、PSG(磷硅玻璃)、或ASG(砷硅玻璃)薄膜进行。然而，所有这些工艺在可制造性方面面临着一个或多个问题。
在制造超薄绝缘体上硅(SOI)器件(例如，SOI厚度＜100埃)或鳍场效应晶体管(FinFETs)(例如，厚度＜200埃)时，也应当小心，以便该器件的硅不会由于扩展和晕圈注入工艺无定形化。如果一直到掩埋氧化物(BOX)区的底部硅被无定形化，则在形成多晶硅时可能″再生长″(在退火之后)。另外，这种再生长也将会产生堆垛层错，从而可能使该器件短路。
在传统的厚的硅结构中，大剂量注入用来制造低电阻硅源/漏(S/D)扩展，并且无定形化的硅从在无定形化前端的硅晶格开始再生长。然而，直接地在超薄硅结构的前述大剂量注入完全使硅层无定形化，导致外延硅不良的固相再生长，因为不存在保留的模板。一般地，该硅再生长成为多晶硅，或多个晶粒，而不是一个连续的晶体。该多晶硅将具有比再生长的单晶硅更高的表面电阻，并且器件将经受低Ion。
为了防止完全的无定形化，一种可能的方法包括在薄SOI顶部上淀积未掺杂的氧化物，其后通过该氧化物注入并进入该薄膜。然而，在除去硅中的无定形化时，在注入步骤之后大部分掺杂剂将留在氧化物中。因此，期望能够在硅中引入所需浓度的掺杂剂用于扩展和晕圈形成，而没有在工艺中使硅无定形化。
发明内容
上述论述的先有技术的缺点和不足通过一种用于形成半导体器件的方法来克服或减轻。在示例性的实施例中，该方法包括在单晶衬底上方限定牺牲层。以防止单晶衬底基本上无定形化的方式采用掺杂剂物质对该牺牲层注入。对该牺牲层退火，以便驱使所述掺杂剂物质从所述牺牲层进入所述单晶衬底。
附图说明
参照示例性的附图，其中类似的要素以同样的方式编号，在图中：
图1-11说明按照本发明的一种实施方式的用于利用牺牲的注入层形成非无定形、超薄半导体器件的方法的示例性处理顺序的截面图。
具体实施方式
近来发现，在氧化物层内注入的砷(As)在小的热退火聚积时从该氧化物层中完全扩散出来，而不管掺杂剂浓度的主体是否在注入步骤后位于氧化物层内。对于BF2掺杂剂也已经观察到类似的现象。例如，如果1keV的砷注入被施加到单晶硅上的35埃的氧化物层，则置于下面的硅基本上没有无定形化。此外、已经发现，几乎所有的砷掺杂剂在随后的退火步骤期间从氧化物层中扩散出来。因此、该技术可被用作用于产生低电阻源/漏(S/D)扩展结的基础，而不会使硅无定形化。
对于采用S/D扩展形成的情形，薄SOI器件也可能在晕圈注入步骤期间被完全地无定形化。这尤其可能发生在PFET晕圈注入期间，该注入通常是砷或锑注入。在大约1×1014原子/cm2的剂量下砷开始使硅无定形化，而在大约5×1013原子/cm2，锑(Sb)开始无定形化。此外、砷晕圈注入在高能量例如在50kev下进行。如果该剂量超过无定形化阈值，那么获得的无定形层的深度将是大约500埃，这对于薄SOI器件是不能接受的。随着器件按比例缩小，情况变得更糟，因为对于未来一代技术，硅厚度将减小，并且晕圈剂量将增大。
因此，为了防止通过晕圈注入无定形化，可以适用利用牺牲的掺杂剂层的相同原理。也就是说晕圈注入可能在薄氧化物层内执行，其后扩散出来。然而，对于这类注入，在氧化物层中产生的注入损害程度可能不足以促进随后的掺杂剂从氧化物中扩散出来而进入硅。因此，中性损害产生物质(例如，如Si、Ge乃至稀有气体)也可以被注入到氧化物中以产生更大的损害。也可以注入来进一步促进其从氧化物层扩散出来的其他物质包括但是不局限于氟(F)和铟(In)。
产生于自氧化物层的晕圈/扩展注入的扩散的另一个重要的优点是晕圈/扩展将会更急剧。特别是，采用该方法获得的晕圈轮廓与高能量注入的晕圈相比将具有低得多的标准偏差，因为来自注入的延伸将被消除。这反过来将减少短沟道效应并允许器件更进一步的按比例缩放。
在完全耗尽的器件(这发生在硅厚度减少到低于200-300埃时)，晕圈轮廓在标称的沟道长度完全耗尽。由于耗尽的电荷量取决于硅厚度，因此薄Si器件的阈值电压对硅厚度敏感。这种情形的发生是因为在较厚的硅中比在较薄的硅中晕圈注入设置更大的剂量。而且，随着硅变薄，硅厚度横越晶片(尤其对于300mm的晶片)的变动增加。只要扩散距离小于最小的硅厚度，来自注入氧化物的掺杂对硅厚度的阈值敏感度降低。
因此，按照本发明的一种实施方式，公开了一种利用牺牲的注入层形成非无定形超薄半导体器件的方法。更具体地，可以执行本方法，用于为超薄半导体(例如硅、锗等)器件制造低电阻的S/D扩展区。本方法进一步用于为晕圈注入提供掺杂均匀控制，从而产生改善的电压阈值(Vt)特性和短沟道效应控制。
简而言之，在标准栅电极形成、隔离物淀积和刻蚀步骤之后，各个器件的晕圈和扩展区被薄牺牲材料(如通过氧化衬底形成的二氧化硅或其他适当的淀积或生长材料)覆盖。然后，在光致抗蚀掩膜和低能量中打开用于掺杂的适当的区域，浅离子注入将受控制剂量的掺杂剂引入覆盖的牺牲薄膜。除去该光掩模并再应用于相反类型的掺杂剂(n或p)。然后采用退火程序以驱使掺杂剂从牺牲层(例如氧化物)进入半导体材料。如果要求晕圈注入工艺，则应在扩展处理之前进行。然后可以按照器件复杂性需要多次执行该程序。
现在一般地参看图1-11，显示了利用本方法的示例性的处理程序的截面图。虽然图中描述在绝缘体上硅衬底上形成FET器件，但将理解该方法也可能被应用于其他类型的器件，其中要求注入掺杂剂物质到衬底中而没有在晶体衬底中产生无定形区。如图1所示，包括栅电介质102和栅104的图案化的栅叠层100形成在薄的单晶结构衬底106如SOI衬底上。然而，再一次地，衬底106可以是任何适当的半导体材料，例如，诸如硅，锗或其组合。例如此起始结构可以是SOI器件或FinFET。然后，如图2所示，在衬底106和栅叠层100上方形成牺牲层108。
如果该衬底106是硅，该牺牲层108可能包括生长(或淀积)到大约15-100埃示例性厚度的薄氧化物层。除了氧化物层，牺牲层108也可以是例如通过在本技术领域可用的机制形成的氮化物薄膜、氮氧化合物薄膜或其他电介质膜，机制诸如热氧化、化学气相淀积(CVD)、等离子增强的CVD(PECVD)和高密度等离子体(HDP)CVD。不管所用的材料类型如何，一旦牺牲层材料通过注入用掺杂剂物质掺杂，则它将变成用于扩散的固体源。
图3说明晕圈注入进入牺牲层108中。对于如此注入，选择注入能量以便输送大多数剂量进入牺牲层108中，从而最小化通过牺牲层108注入的剂量以防止半导体衬底106中的晶体损伤。该器件最初被图案化用于n型或p型注入，然后图案被反转用于另一个极性掺杂剂的注入。在牺牲层内掺杂剂剂量的浓度在图3中通过曲线来图示，曲线反映了峰值掺杂及浓度大约在牺牲层厚度的中间处。
如同以前解释的那样，在某些情形中，用于晕圈注入的掺杂剂注入剂量可能未对牺牲层108(例如氧化物层)提供足够的损害。因此，图4说明附加的注入步骤，其中惰性物质(诸如Si或Ge)也被注入到该牺牲层108中。然后，在图5中，掺杂的牺牲层108被退火以便促进掺杂剂物质扩散进入单晶衬底106以产生晕圈区110。为了适当地定位晕圈区110，退火步骤比扩展退火时间更长，温度更高。
参照图6，示出了可选的扩展隔离物112的形成，该隔离物可以用于实现以叠加电容和电阻为特征的适当器件。隔离物112的厚度将由器件需求决定。然而，对于某些退火程序(例如对于NFET形成)，该隔离物可能不需要。无论如何，扩展注入如图7所示，其中用于晕圈注入扩散源的相同牺牲层108也可以用于扩展注入。与晕圈注入的情况一样，采用适合于将大多数掺杂剂剂量定位在牺牲层108中的能量注入用于扩展区的掺杂剂，优选地采用小于大约5×1014原子/cm2的剂量，更深地迁移到置于衬底106的下面的半导体材料中。PFET扩展注入被掩蔽以避开NFET区，反之亦然，从而执行两次注入工艺以提供NFET和PFET扩展。然后，如图8所示，从牺牲层108驱使该扩展掺杂剂材料进入衬底106，如114表示的那样。单个退火步骤可用于驱使n和p型扩展。
一旦该晕圈和扩展注入按照非无定形的方式完成，可以按照常规处理技术继续器件制造。在图9中，源/漏隔离物116(例如，由氮化物材料形成)用来分隔源/漏掺杂剂/注入和栅边缘。这在保持源/漏区用于电接触的同时保持器件受扩展和晕圈掺杂轮廓控制。在图10中，除去牺牲层108的暴露部分，并通过例如选择性外延生长采用额外的硅(或其它半导体)材料118增厚源/漏区。这为随后的硅化物形成提供了一个区域，而没有损失所有的先前注入的掺杂剂。栅104也可以采用额外的掺杂多晶硅材料来增厚，同样如图10所示。最后，对于NFET和PFET器件，图案化S/D注入，然后在形成硅化物区120之前退火。
正如将理解的那样，通过形成高度掺杂的、低电阻的S/D扩展已经克服了上述在超薄半导体构造中的传统器件制造问题(即直接向硅晶体中离子注入)，而没有无定形化注入的有害效应。当应用于器件晕圈注入时，本方法产生更陡峭的掺杂轮廓，比采用传统的注入掺杂所获得的短沟道效应(SCE)器件特性更佳。通过更精确的晕圈形状和电阻导致的芯片各个器件内的Vt变化减小，也将增强器件操作。
尽管类似于从诸如掺杂的多晶硅或BSG的固体源进行的扩散，但利用与薄半导体层直接接触的薄牺牲层(诸如氧化物层)以便将其中注入的掺杂剂扩散到下面的半导体材料中使得在现有的工艺中集成简单多了。例如，注入位置的掩蔽对于注入相对容易，而对于CVD薄膜相对困难。同样，掺杂剂的量和扩散的深度可以采用注入剂量和退火方法更好地控制。通过除去半导体中的无定形层，该材料保留晶态，并在通过扩散物质重掺杂时将具有低电阻。不采用该方法，超薄器件材料将完全地无定形化并再生长成为高电阻率、多晶粒的材料，产生不良的器件特性(例如Ion/Ioff比)。
晕圈注入用来控制器件Vt和短沟道效应。在超薄器件中，该晕圈注入也可能无定形化材料，导致不良的电阻和漏电的结。通过利用对于晕圈形成从注入的牺牲层进行扩散的该方法，掺杂轮廓将比注入的情形下更陡峭，并且将更均匀，导致改善的短沟道效应。由于制造困难，半导体层的厚度可以变化较大的量(例如在20纳米薄膜中±5纳米)，这影响器件的Vt控制。利用氧化扩散的晕圈将提供与层厚度无关的晕圈分布，从而改善来自层厚度的器件Vt均匀性。．
虽然已经参考优选的一个实施方案或多个实施方案描述了本发明，但本技术领域的人员将理解可以进行各种变化，并且等价物可以代替其要素，而不背离本发明的范围。另外，对本发明的教导可以进行许多修改以适应特定的情形或材料，而不背离其实质的范围。因此，希望本发明不限于作为用于执行此发明构思的最佳方式公开的特定实施方式，本发明将包括落在附加的权利要求书的范围中的所有实施方式。
工业实用性
本公开在半导体器件处理领域、特别是在通过掺杂剂注入操作形成具有未受损伤的(非无定形化)的硅区的超薄半导体器件的领域具有工业实用性。

Claims (20)

1.一种用于形成半导体器件的方法，该方法包括：
在单晶衬底(106)上方限定牺牲层(108)；
以防止所述单晶衬底(106)基本上无定形化的方式采用掺杂剂物质对所述牺牲层(108)注入；和
对所述牺牲层(108)退火以便驱使所述掺杂剂物质从所述牺牲层(108)进入所述单晶衬底(106)。
2.权利要求1的方法，其中所述牺牲层(108)是介质层，进一步包括以下至少一种：氧化物层、氮化物层、和氮氧化合物层。
3.权利要求1的方法，进一步包括形成晕圈注入，其中，除了所述掺杂剂物质，在对所述牺牲层(108)退火之前，采用损伤产生物质进一步对所述牺牲层(108)注入。
4.权利要求3的方法，其中所述损伤产生物质进一步包括以下至少一种：硅、锗、铟、氟和稀有气体。
5.权利要求3的方法，进一步包括利用所述牺牲层(108)形成扩展注入。
6.权利要求5的方法，其中用于所述晕圈注入的退火在比所述扩展注入更高的温度下执行更大的持续时间。
7.权利要求1的方法，其中所述牺牲层(108)进一步包括形成在硅衬底上方的氧化物层，所述氧化物层被形成为大约15到大约100埃的厚度。
8.权利要求7的方法，其中选择所述掺杂剂物质的注入能量以便将所述掺杂剂物质的峰值浓度定位在所述氧化物层的大约中间处。
9.权利要求1的方法，其中所述单晶衬底进一步包括绝缘体上硅(SOI)器件的硅区，该硅区具有小于大约100埃的硅厚度。
10.权利要求1的方法，其中所述单晶衬底进一步包括场效应晶体管(FET)器件的硅区，该硅区具有小于大约200埃的厚度。
11.权利要求1的方法，进一步包括：
在形成在所述单晶衬底(106)上的图案化的栅叠层(100)上方限定所述牺牲层(108)；
通过对所述牺牲层(108)注入和对所述牺牲层(108)退火而形成晕圈注入；和通过对所述牺牲层(108)的额外的注入和退火而形成扩展注入。
12.权利要求11的方法，其中所述牺牲层(108)是介质层，该介质层进一步包括以下至少一种：氧化物层、氮化物层、和氮氧化合物层。
13.权利要求12的方法，其中，在形成所述晕圈注入期间，除了所述掺杂剂物质，在对所述牺牲层(108)退火之前，采用损伤产生物质进一步对所述牺牲层(108)注入。
14.权利要求13的方法，其中所述损伤产生物质进一步包括以下至少一种：硅、锗、铟、氟和稀有气体。
15.利要求13的方法，其中用于所述晕圈注入的退火在比所述扩展注入更高的温度下执行更长的持续时间。
16.权利要求12的方法，其中所述牺牲层(108)进一步包括形成在硅衬底上方的氧化物层，所述氧化物层被形成为大约15到大约100埃的厚度。
17.利要求16的方法，其中选择所述掺杂剂物质的注入能量以便将所述掺杂剂物质的峰值浓度定位在所述氧化物层的大约中间处。
18.权利要求11的方法，其中所述单晶衬底进一步包括绝缘体上硅(SOI)器件的硅区，该硅区具有小于大约100埃的硅厚度。
19.权利要求11的方法，其中所述单晶衬底进一步包括场效应晶体管(FET)器件的硅区，该硅区具有小于大约200埃的厚度。
20.权利要求11的方法，其中所述掺杂剂物质包括以下至少一种：砷(As)、磷(P)、锑(Sb)、硼(B)和硼氟(BF2)。
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CN100405581C (zh) 2008-07-23
US20080311732A1 (en) 2008-12-18
AU2003298876A1 (en) 2005-08-12
JP2007525813A (ja) 2007-09-06
WO2005067035A1 (en) 2005-07-21
EP1695381A4 (en) 2008-09-17

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