JP5244908B2 - ドレインおよびソース領域にリセスを形成することによってトランジスタの接合容量を低減する方法 - Google Patents
ドレインおよびソース領域にリセスを形成することによってトランジスタの接合容量を低減する方法 Download PDFInfo
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- JP5244908B2 JP5244908B2 JP2010514849A JP2010514849A JP5244908B2 JP 5244908 B2 JP5244908 B2 JP 5244908B2 JP 2010514849 A JP2010514849 A JP 2010514849A JP 2010514849 A JP2010514849 A JP 2010514849A JP 5244908 B2 JP5244908 B2 JP 5244908B2
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- 238000000034 method Methods 0.000 title claims description 169
- 239000004065 semiconductor Substances 0.000 claims abstract description 124
- 230000008569 process Effects 0.000 claims description 123
- 239000002019 doping agent Substances 0.000 claims description 78
- 238000000137 annealing Methods 0.000 claims description 50
- 239000000463 material Substances 0.000 claims description 46
- 125000006850 spacer group Chemical group 0.000 claims description 41
- 238000005530 etching Methods 0.000 claims description 32
- 238000002513 implantation Methods 0.000 claims description 31
- 238000005468 ion implantation Methods 0.000 claims description 19
- 239000010410 layer Substances 0.000 abstract description 88
- 229910045601 alloy Inorganic materials 0.000 abstract description 55
- 239000000956 alloy Substances 0.000 abstract description 55
- 239000003989 dielectric material Substances 0.000 abstract description 5
- 230000001939 inductive effect Effects 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 29
- 239000010703 silicon Substances 0.000 description 29
- 238000009792 diffusion process Methods 0.000 description 27
- 229910052710 silicon Inorganic materials 0.000 description 24
- 238000004519 manufacturing process Methods 0.000 description 21
- 239000000758 substrate Substances 0.000 description 20
- 229910052732 germanium Inorganic materials 0.000 description 12
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000013078 crystal Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 230000001965 increasing effect Effects 0.000 description 9
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 8
- 229910052799 carbon Inorganic materials 0.000 description 8
- 229910021332 silicide Inorganic materials 0.000 description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 239000007943 implant Substances 0.000 description 6
- 230000007246 mechanism Effects 0.000 description 6
- 229910000927 Ge alloy Inorganic materials 0.000 description 5
- 229910000676 Si alloy Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 125000004429 atom Chemical group 0.000 description 4
- 239000002800 charge carrier Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000000717 retained effect Effects 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000012876 carrier material Substances 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 238000005280 amorphization Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 150000002291 germanium compounds Chemical class 0.000 description 2
- 125000005843 halogen group Chemical group 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H01L21/26—Bombardment with radiation
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- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Description
記録密度が改良され、さらに高性能の集積回路を開発するうえでの主要な問題となるのは、最新のCPUやメモリデバイスの製造に必要とされうる非常に多くのトランジスタ素子を設けるために、MOSトラ ンジスタ素子などのトランジスタ素子を縮小することである。縮小した電界効果トランジスタを製造する際の1つの重要な態様として、トランジスタのソース及びドレイン領域を分離する導電性チャネルの形成を制御するゲー ト電極の長さを縮小することが挙げられる。
トランジスタ素子のソース及びドレイン領域は、基板あるいはウェル領域などの、周囲の結晶活性領域のドーパントとは逆の導電型のドーパントを含む導電性の半導体領域である。
さらに、アニールプロセスの間の温度が高いとゲート絶縁層に悪影響を与えてしまい、そのためにゲート絶縁層の信頼性が低下してしまうおそれがある。つまり、アニール温度が高いとゲート絶縁層が劣化し、従って、その誘電特性にも影響を及ぼすおそれがあり、そのためにリーク電流の増加や、破壊電圧の低下等が生じるおそれがある。したがって、非常に高度なトランジスタに対しては、最終的なデバイス性能を定義するうえでの重要な特性として、ドーパントプロファイルを所望するように位置決めし、成形し、維持することが挙げられる。その理由は、ドレインコンタクトとソースコンタクトとの間の導電性パスの全体の直列抵抗がトランジスタの性能を決定する主要な要素となるからである。
Claims (4)
- トランジスタのゲート電極構造をエッチマスクとして使用して第1エッチングプロセスを実行することによって、前記トランジスタの半導体領域に第1リセスを形成するステップと、
前記ゲート電極構造を注入マスクとして使用して第1イオン注入プロセスを実行することによって、前記半導体領域にドレインおよびソース拡張領域を形成するステップと、
前記ゲート電極構造のサイドウォールにスペーサ構造を形成するステップと、
前記スペーサ構造を形成後、第2エッチングプロセスを実行し、前記半導体領域に複数の第2リセスを形成するようにするステップと、
前記スペーサ構造を注入マスクとして使用して、前記半導体領域下方に設けられる埋め込み絶縁層にまで及ぶドレインおよびソース領域を形成するために、前記第1リセスに第2イオン注入プロセスを実施するステップと、
前記ドレインおよびソース領域のドーパントを活性化させるためにアニールプロセスを実行するステップと、
前記トランジスタのチャネル領域に歪みを誘起させるように、前記第1イオン注入プロセスを実施する前に前記第1リセスに歪み半導体材料を形成するステップと、を含み、前記歪み半導体材料の形成ステップにおいて、前記半導体領域に圧縮歪み半導体材料と引張歪み半導体材料のうちの少なくとも一方が形成される、方法。 - 前記アニールプロセスは、実効照射時間が約1秒かそれ未満の、照射によるアニールステップを含む、請求項1記載の方法。
- 前記アニールプロセスは、前記トランジスタの横方向の実効チャネル長を調整するように設計されているアニールステップを含む、請求項1記載の方法。
- 前記第2イオン注入プロセスを実行する前に、前記拡張領域をアニールするように設計された拡張アニールプロセスを実行するステップと、
前記ゲート電極構造の電極部の上面の上方にキャップ層を形成し、前記第1エッチングプロセスを実行する際に前記キャップ層をエッチングマスクとして用いるステップとをさらに含む、請求項1記載の方法。
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