JP5244908B2 - Method for reducing transistor junction capacitance by forming recesses in drain and source regions - Google Patents

Abstract

A semiconductor device, comprising a first transistor having recessed drain and source regions, said drain and source regions are provided in recessed portions of a semiconductor layer and extend to a buried insulating layer; a strained semiconductor alloy provided partially in said drain and source regions, said strained semiconductor alloy inducing a strain in a channel region of said first transistor, wherein a top surface of said strained semiconductor alloy opposite the buried insulating layer is recessed below an interface between a gate insulation layer and the channel region of the first transistor; and an interlayer dielectric material formed above the top surface and in a recessed portion of said strained semiconductor alloy.

Description

  In general, the present invention relates to the manufacture of integrated circuits, and more particularly to the manufacture of very advanced field effect transistors with heavily doped junctions with reduced junction capacitance, such as SOI-structure MOS transistor structures. Regarding technology.

Integrated circuit manufacturing processes continue to improve in a variety of ways resulting from continued efforts to reduce the processing dimensions of individual circuit elements. Silicon substrates are readily available, and with well-established process technologies that have been developed over the past decades, the majority of integrated circuits are based on silicon devices now and in the foreseeable future, Silicon devices will continue to be used as a base.
The main issue in developing higher performance integrated circuits with improved recording density is to provide a very large number of transistor elements that may be required for the manufacture of modern CPUs and memory devices. This is to reduce the size of transistor elements such as MOS transistor elements. One important aspect in fabricating a reduced field effect transistor is reducing the length of the gate electrode that controls the formation of a conductive channel that separates the source and drain regions of the transistor.
The source and drain regions of the transistor element are conductive semiconductor regions including a dopant having a conductivity type opposite to that of the surrounding crystal active region, such as a substrate or well region.

  To reduce the size and speed of high-speed transistor elements, it is necessary to reduce the gate length. However, it is clear that several problems arise in order to properly maintain the transistor performance with the reduced gate length. It is. One difficulty in this respect is to provide a shallow junction region at least in the region near the channel region, that is, in the source and drain extension regions. This region exhibits high conductivity, and therefore the resistance when conducting charge carriers from the channel to each contact region of the drain and source regions can be minimized. In general, the requirements for highly conductive shallow junctions are met by performing an ion implantation sequence to obtain a high dopant concentration where the profile varies laterally and in depth. However, by introducing a high dose of dopant into the crystal substrate region, the crystal structure is greatly damaged. Thus, one or more annealing cycles are required to activate the dopant, that is, to place the dopant at the crystal site and to recover the heavily damaged crystal.

  However, the electrically effective dopant concentration is limited by the ability of the annealing cycle to electrically activate the dopant. This annealing cycle capability is also limited by the solid solubility of the dopant in the silicon crystal and the temperature and duration of the annealing process corresponding to the process requirements. Furthermore, during annealing, dopants are activated and crystal damage is restored, as well as diffusion of the dopants, resulting in a “blurring” dopant profile. There is a risk that. It may be advantageous to limit the degree of blurring in defining critical characteristics of the transistor (eg, overlap between the extended region and the gate electrode). In other regions of the drain and source regions, that is, deeper portions, the dopant concentration in the corresponding PN junction region is lowered by diffusion, and thus the conductivity in the vicinity of these regions may be lowered.

Therefore, on the other hand, it is desirable that the annealing temperature be high in consideration of advanced dopant activation, recrystallization of lattice damage caused by implantation, and desired diffusion in the shallow region of the extended region. But on the other hand, to reduce the dopant slope in the deep drain and source regions, which reduces the dopant slope of each PN junction and also reduces the overall conductivity by lowering the average dopant concentration. It is necessary to shorten the annealing process time.
Furthermore, if the temperature during the annealing process is high, the gate insulating layer may be adversely affected, which may reduce the reliability of the gate insulating layer. That is, when the annealing temperature is high, the gate insulating layer is deteriorated, and therefore, there is a possibility that the dielectric characteristics thereof may be affected. For this reason, an increase in leakage current or a decrease in breakdown voltage may occur. Thus, for very advanced transistors, an important characteristic in defining the final device performance is positioning, shaping and maintaining the dopant profile as desired. This is because the overall series resistance of the conductive path between the drain contact and the source contact is a major factor that determines the performance of the transistor.

  Recently, extremely high temperatures have been achieved in the surface portion of the substrate, thereby activating the dopant and transferring enough energy to the atoms to recrystallize the lattice damage, yet the dopant can still be processed in a short time. State-of-the-art annealing techniques have been developed that can substantially suppress the diffusion of substantial amounts of other impurities in the seed and carrier material. Each state-of-the-art annealing technique is typically performed based on a radiation source. The radiation source is configured to provide the appropriate wavelength of light that is efficiently absorbed by the substrate and the components formed on the substrate, and the effective duration of the irradiation is, for example, a few milliseconds and more Can be controlled to a desired short time interval, such as a substantially short time. For example, each flash lamp exposure source that provides light of a defined wavelength range that heats the material near the surface can be used, so that each atom of the material provided near the surface of the carrier material has a short distance. Conditions for exercising are given.

  In other cases, laser irradiation is used in the form of short laser pulses or continuous beams that can be scanned across the substrate surface based on an appropriate scanning regime to heat each point on the substrate as desired for a short period of time. May be. Therefore, unlike conventional Rapid Thermal Anneal (RTA) processes where the entire carrier material is often heated to the desired temperature, the latest annealing technology by irradiation uses large quantities in very short time intervals. Of energy, which allows very thin layers to be brought to very high temperatures as required, while the remaining material of the substrate substantially reduces the effects of energy deposition during the annealing process. A non-equilibrium state occurs.

  Thus, in advanced manufacturing regimes, dopant diffusion may be advantageous when the dopant is highly activated and the drain and source regions are recrystallized while considering the steep dopant slope of each PN junction. The latest irradiation annealing process that does not affect more than necessary is often used instead of the conventional RTA process. However, incorporating an effective channel length adjustment step based on well-controlled dopant diffusion into a conventional process flow is difficult unless significant effort is made, thus further complicating the process. End up. On the other hand, to form an effective channel length based on conventional well-established annealing techniques when the efficient process flow is continued, the spacer width is increased and thus the lateral dimensions of the transistor May need to be increased.

  A further problem with the drain and source regions, and thus the lateral and vertical dopant profiles of the PN junction, is that of the PN junction, which can be roughly related to the effective interface formed by the PN junction with respect to the remaining active region of the semiconductor device. Indicated by the total capacity. To further enhance the performance of the SOI transistor, the parasitic capacitance of the PN junction can be significantly reduced by designing the vertical dopant profile to obtain a high dopant concentration that extends to the buried insulating layer. In this way, only the lateral interface, i.e., the PN junctions in the drain and source regions, are affected by the overall junction capacitance, while still having the desired PN junction characteristics due to the high dopant concentration extending to the buried insulating layer. And the overall series resistance in the drain and source regions can be reduced.

  However, providing a deep drain and source region with a high dopant concentration up to the buried insulating layer requires advanced implantation techniques, which complicates the overall process. In other cases, a moderately high dopant concentration is achieved in the buried insulating layer by adjusting the process parameters of each anneal process such that the desired vertical dopant profile is formed by dopant diffusion during the anneal process. be able to. However, each anneal parameter may not correspond to a reduced transistor length. The reason is that, for example, side diffusion may also be performed in the extended region, which changes the channel length. In this case, it may be necessary to increase the spacer width to accommodate the increased diffusion activity during each annealing process. Thus, in view of increasing the recording density of advanced semiconductor devices, a long processing time, high temperature annealing process that increases diffusion activity and thus creates a lot of thermal budget or thermal history is an attractive approach. I can't say that.

  Furthermore, transistor performance (eg, P-channel transistor performance) can be significantly improved by providing a strained semiconductor material (eg, silicon / germanium compound) that can be formed in the drain and source regions of the silicon-based active transistor region. Technology that can be developed. Strained silicon / germanium compounds, also referred to as silicon / germanium alloys, can be supplied in a strained state because the lattice spacing between the original silicon and the original silicon / germanium alloy does not match. That is, the silicon / germanium material is formed based on the lattice spacing of silicon, thereby forming a strained silicon / germanium crystal lattice.

  The crystal lattice then interacts with the adjacent semiconductor material, creating a stress that causes a certain strain. When a strained silicon / germanium alloy is supplied to the drain and source regions, each stress generated by the strained material affects the channel region of the transistor, thereby generating each compressive stress in the channel region, Charge carrier mobility in the channel region is improved. In highly scaled transistor devices based on SOI structures, providing a highly distorted semiconductor alloy near the channel region that extends along a substantial portion of the semiconductor layer in the depth direction has a significant effect on performance. Can be obtained. Therefore, the overall performance can be improved by combining the efficient strain induction mechanism of the SOI device with the reduced parasitic junction capacitance. Furthermore, as described above, it is desirable to significantly reduce the thermal budget of each thermal annealing process so as to provide the possibility of reducing the lateral dimensions of the transistor device. Therefore, in view of the above-described situation, it is desirable to have a high technology that improves the characteristics of the transistor while not complicating the process more than necessary and / or does not impair the scalability of each process technology.

  The present invention relates to various methods and devices that can avoid or at least reduce the effects of the problems described above.

  The following provides an overview of the present invention in order to provide a basic understanding of some aspects of the present invention. This summary is not an extensive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. The purpose here is to provide some concepts of the invention in a simplified form as a prelude to the more detailed description that follows.

  In general, the subject matter disclosed herein improves the transistor performance and reduces the overall transistor of the SOI device by thinning each active semiconductor layer of the SOI device before forming each deep drain and source region. The present invention relates to a method and a semiconductor device aimed at reducing dimensions. Each process for removing material may be performed at an appropriate manufacturing stage to provide the possibility of introducing strained semiconductor alloys in the preceding manufacturing stage. The strained semiconductor alloy may be held along the depth direction near its channel region and at its initial thickness when removing material from the drain and source regions.

  Therefore, by thinning the drain and source regions before implanting the deep drain and source regions, dopant species can be introduced at a high concentration so as to reach the buried insulating layer based on the effective implantation parameters. This re-crystallizes the drain and source regions by activating the dopant in view of the desired lateral dopant profile rather than having to diffuse the dopant into the buried insulating layer to reduce the junction capacitance. It is also possible to prioritize the design of each annealing process to achieve. Thus, overall lateral transistor dimensions are reduced over strategies using annealing parameters to increase diffusion activity, while efficient strain induction mechanisms in the form of strained semiconductor alloys in the drain and source regions Can be introduced.

  In one exemplary method disclosed herein, drain and source extension regions are formed in a semiconductor region of a transistor by performing a first ion implantation process using the gate electrode of the transistor as an implantation mask. In the above method, a spacer structure is formed on the sidewall of the gate electrode structure, and a recess is formed in the semiconductor region by performing an etching process. Furthermore, in the above method, by performing the second ion implantation process using the spacer structure as an implantation mask, the drain and source regions extending to the buried insulating layer provided below the semiconductor region are formed. Further, in the above method, an annealing process is performed to activate the dopants in the drain and source regions.

  In another exemplary method disclosed herein, a first strained semiconductor alloy is formed in a first semiconductor region of a first transistor. The first strain semiconductor alloy is at least partially provided in the drain and source regions, and induces a first type strain in the channel region of the first transistor. In this exemplary method, a recess is further formed in each of the drain and source regions of the first transistor. Further, in the above method, dopant species are implanted into the drain and source regions so as to form deep drain and source regions extending to the buried insulating layer formed in the first semiconductor region.

  The exemplary semiconductor device disclosed herein includes a first transistor having recessed drain and source regions that extend to a buried insulating layer. The semiconductor device further includes a strained semiconductor alloy that is provided in a portion of the drain and source regions and induces strain in the channel region of the first transistor.

FIG. 2 is a schematic cross-sectional view of a transistor device during various manufacturing steps in forming a deep drain and source region that extends to a buried insulating layer of an SOI structure, according to an exemplary embodiment, each portion being a deep drain And a schematic cross-sectional view in which a recess is formed prior to ion implantation to define the source region. FIG. 2 is a schematic cross-sectional view of a transistor device during various manufacturing steps in forming a deep drain and source region that extends to a buried insulating layer of an SOI structure, according to an exemplary embodiment, each portion being a deep drain And a schematic cross-sectional view in which a recess is formed prior to ion implantation to define the source region. FIG. 2 is a schematic cross-sectional view of a transistor device during various manufacturing steps in forming a deep drain and source region that extends to a buried insulating layer of an SOI structure, according to an exemplary embodiment, each portion being a deep drain And a schematic cross-sectional view in which a recess is formed prior to ion implantation to define the source region. FIG. 2 is a schematic cross-sectional view of a transistor device during various manufacturing steps in forming a deep drain and source region that extends to a buried insulating layer of an SOI structure, according to an exemplary embodiment, each portion being a deep drain And a schematic cross-sectional view in which a recess is formed prior to ion implantation to define the source region. FIG. 2 is a schematic cross-sectional view of a transistor device during various manufacturing steps in forming a deep drain and source region that extends to a buried insulating layer of an SOI structure, according to an exemplary embodiment, each portion being a deep drain And a schematic cross-sectional view in which a recess is formed prior to ion implantation to define the source region. FIG. 2 is a schematic cross-sectional view of a transistor device during various manufacturing steps in forming a deep drain and source region that extends to a buried insulating layer of an SOI structure, according to an exemplary embodiment, each portion being a deep drain And a schematic cross-sectional view in which a recess is formed prior to ion implantation to define the source region. FIG. 6 is a schematic diagram schematically illustrating a variation of the transistor illustrated in FIGS. 1 a-1 f according to yet another exemplary embodiment, wherein an annealing process is used that significantly reduces diffusion activity. Further annealing processes can be performed to define the lateral dopant profile and thus the effective channel length of the extended region before forming the recessed deep drain and source regions according to a further exemplary embodiment. Schematic of the transistor in the early manufacturing stage. In accordance with further exemplary embodiments, recesses have been formed that extend to the buried insulating layer during the manufacturing stage to introduce further species to facilitate further processing of the transistor and / or enhance performance. FIG. 3 is a schematic cross-sectional view of a transistor having a deep drain and source region. 2 is a schematic cross-sectional view of a semiconductor device including two different types of transistors, with different strained semiconductor alloy types (as shown) or different recessed and sourced drain structures. FIG.

  The present invention will be described with reference to the accompanying drawings. In the drawings, like reference numbers indicate like elements. The subject matter disclosed herein may be modified in various ways and may take other forms, specific embodiments of which are illustrated by way of example in the drawings and are described in detail in the text. However, the specific embodiments described herein are not intended to limit the invention to the particular form disclosed, but rather to all within the spirit and scope of the invention as defined in the appended claims. Covers variations, equivalents, and alternatives.

  Various exemplary embodiments of the invention are described below. For the sake of simplicity, not all features of actual mounting products are described here. Of course, in the development of such real-world implementations, many specific implementation decisions, such as reconciliation with system and business limitations, are made to achieve specific goals for developers. The They vary depending on each embodiment. Moreover, such development efforts are naturally complex and time consuming, but nevertheless fall within the normal work for those skilled in the art having the benefit of this disclosure.

  Hereinafter, the present invention will be described with reference to the accompanying drawings. Various structures, systems and devices are schematically depicted in each drawing for purposes of explanation only and so as to not obscure the present invention with detailed descriptions well known to those skilled in the art. However, the attached drawings are attached for the purpose of explaining and explaining embodiments of the present invention. Terms and phrases used herein should be understood and interpreted to have a meaning consistent with words and phrases understood by those skilled in the relevant art. The consistent use of terms or phrases in this specification means definitions that are different from any particular definition of these terms or phrases, that is, from the ordinary and conventional meanings understood by those of ordinary skill in the art. Not what you want. When a term or phrase is used in a range that has a specific meaning, that is, when used in a different meaning than that understood by those skilled in the art, the specification directly and clearly identifies such words and phrases. Define.

  In general, the subject matter disclosed herein includes state-of-the-art transistor elements based on silicon-on-insulator (SOI) structures, and further includes semiconductor device fabrication techniques with extreme dimensions of, for example, 100 nm or much smaller and each The transistor performance can be substantially determined by the overall resistivity of the conductive path established between the drain contact and the source contact and the capacitance of each body region. In order to improve overall transistor performance, various embodiments disclosed herein efficiently introduce strained semiconductor material into the drain and source regions of the transistor to increase the charge carrier mobility in the channel region. On the other hand, however, deep drain and source regions extending to the buried insulating layer can be formed with high dopant concentration to reduce junction capacitance, yet still substantially maintain the strain inducing mechanism of the strained semiconductor alloy The possibility is given. In addition, the thermal budget can be reduced, thereby using an appropriate annealing technique as described above that can reduce the transistor length.

  A desired high dopant in the deep drain and source regions based on an additional etch process prior to each implantation process based on a suitable spacer structure to provide the desired lateral offset to the strained semiconductor alloy. Concentration may be obtained, so that a substantial portion of the semiconductor alloy is retained along its entire extension, so that its strain-inducing mechanism is not affected more than necessary. Is done. Thus, according to the principles disclosed herein, a high dopant concentration is given to the deep drain and source regions extending to the buried insulating layer, while on the other hand, regardless of the vertical dopant profile of this deep drain and source region, The effective channel length (eg, the degree of overlap between the gate electrode and the drain and / or source extension region) for high performance transistors can also be designed. Furthermore, by performing an implantation process to form deep drain and source regions based on the recessed semiconductor material, the vertical extensions of these regions can be adjusted based on the ion implantation process. Thereafter, dopant activation may be performed on the entire lateral dopant profile without the need for a substantial amount of vertical diffusion. Thus, advanced annealing techniques can be efficiently used without substantially requiring diffusion or significantly reducing the extent of diffusion so that the dopant is highly activated as desired.

  In an exemplary embodiment, an annealing process may be performed at various manufacturing stages, including individually designed process parameters, to adjust the lateral diffusion of the extended region as desired as desired. While the subsequent short-time annealing process provides the desired dopant diffusion without substantially affecting the lateral dopant profile obtained with the uniquely designed annealing step. be able to. For example, after implanting each dopant species to form drain and source extension regions, an appropriate annealing process may be performed to fine tune the lateral dopant profile as needed, and then appropriately Based on the designed spacer structure, a sufficient amount of strain is provided if recesses are formed in the remaining drain and source regions, dopant species are implanted into the deep drain and source regions, and a strained semiconductor alloy is provided. A desired offset is provided in the lateral direction to hold the semiconductor alloy. Thereafter, dopant activation can be efficiently achieved based on the latest irradiation annealing process without substantially changing the lateral dopant profile already formed.

  As a result, the drain and source regions are in contact with the buried insulating layer in the depth direction, which reduces the overall capacitance of the SOI transistor body, so that an effective surface area that can be used to form a PN junction in the SOI transistor. Will be significantly reduced. Combining the reduced parasitic junction capacitance with an efficient strain-induced semiconductor alloy can enhance transistor performance. In this case, the overall lateral dimension in the length direction of the transistor is also reduced because a reduced spacer width may be selected to define the lateral dopant profile.

  It will be appreciated that the principles disclosed herein are highly advantageous in semiconductor devices including transistor elements with gate lengths of about 50 nm or less. The reason is that while a clear dopant profile is required here at the PN junction, charge carrier mobility and dopant activity in the channel region are also important, considering reducing the overall series resistance of the transistor. It is because it is an aspect. However, the techniques disclosed herein can be efficiently applied to less critical semiconductor devices. This reduces the thermal budget, increases device uniformity and reduces yield loss, and as a result, can suppress both vertical and lateral diffusion, thereby reducing parameter variations. it can. Accordingly, the invention is not limited to specific device dimensions, unless explicitly limited by the specification or the appended claims.

  FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100, which in one exemplary embodiment is a field effect transistor. The semiconductor device 100 can include a substrate 101. A semiconductor layer 102 such as a silicon-based semiconductor layer is formed above the substrate. This semiconductor layer is understood as a semiconductor material containing silicon and may be combined with other species such as germanium, carbon. In the illustrated manufacturing stage, the semiconductor layer 102 includes a recess 112A formed in the active semiconductor region 111, that is, a part of the semiconductor layer 102, and the conductivity is clarified based on the dopant profile. The semiconductor region 111 may be defined by an insulating structure 108.

  This insulating structure is composed of any suitable dielectric material, such as silicon dioxide, silicon nitride, etc. and may be provided, for example, in the form of trench isolation, whereby the channel region 109 and each drain and source region ( An active semiconductor region 111 is defined in which an unillustrated) is to be formed. The semiconductor device 100 may further include a buried insulating layer 103 provided between the substrate 101 and the semiconductor layer 102, thereby forming an SOI structure. The buried insulating layer 103 may be made of any appropriate dielectric material such as silicon dioxide or silicon nitride. In other cases, the semiconductor device 100 may have a “bulk” structure, in which the thickness of the semiconductor layer 102 is much greater than the vertical depth of any circuit elements formed in the device, and thus A common semiconductor body can be provided for a number of circuit elements. In other cases, the semiconductor device 100 may be an SOI structure combined with a bulk structure (not shown) as shown in FIG. 1a if a high performance transistor element is required in combination with a transistor that benefits from the bulk structure. It may be.

  In this respect, the description of the position of the feature of the semiconductor device 100 or other semiconductor device described in the text is considered as relative position information, and includes the substrate 101, the embedded insulating layer 103, or these Each specific surface or interface formed by the component is shown as a reference. That is, terms such as “above”, “over”, “above”, and other similar terms that refer to an overlaid structure include surfaces such as buried insulating layer 103 and / or substrate 101. The position of the feature under consideration to the substrate or buried insulating layer 103 is farther than the feature provided “below” the feature under consideration. In this sense, the semiconductor layer 102 is formed above the buried insulating layer 103, for example. Similarly, the lateral direction indicates a direction extending substantially parallel to the buried insulating layer 103 or the interface formed with respect to the substrate 101. Thus, in FIG. 1a, the lateral direction is understood as the horizontal direction, indicating the length direction of the transistor, and the direction substantially perpendicular to the drawing plane of FIG. 1a is the width direction of the transistor. Show.

  The semiconductor device 100 may further include a gate electrode structure 105 formed above the semiconductor layer 102 and further separated by a gate insulating layer 104. The gate electrode structure 105 may include an electrode portion 105A, which is a conductive portion of the electrode structure 105 and may have a length of about 50 nm or less. An offset spacer 107 that can be made of any appropriate material such as silicon dioxide or silicon nitride may be provided on the sidewall of the electrode portion 105A. The gate electrode structure 105 may be formed in the form of any appropriate material such as polysilicon for the electrode portion 105A. However, in other exemplary embodiments, the term “gate electrode structure” may further indicate a placeholder or sacrificial structure that can be substituted for any suitable material in the next manufacturing step. Further, in the illustrated embodiment, the gate electrode structure 105 can include a cap layer 106 comprised of any suitable material such as silicon nitride, silicon dioxide, and the like.

  The semiconductor device 100 shown in FIG. 1a may be formed based on the following process. After providing the substrate 101 on which the buried insulating layer 103 and the semiconductor layer 102 are formed, the insulating structure 108 can be formed based on well-established techniques such as photolithography, etching techniques, evaporation and planarization processes. Thereafter, an appropriate dopant concentration can be generated in the semiconductor region 111 defined by the insulating structure 108 based on well-established implantation techniques. Next, the gate electrode structure 105 and the gate insulating layer 104 can be formed based on well-established techniques. At this time, the material of the gate insulating layer 104 may be provided by advanced oxidation and / or vapor deposition techniques that may include surface treatment, and then an appropriate material is deposited on the electrode portion 105A. Thereafter, advanced lithography and etching processes may be performed to form the electrode portion 105A and the gate insulating layer 104A. For example, the cap layer 106 may be similarly formed during the patterning of the electrode portion 105A.

  This cap layer may be part of a material layer that has already been deposited. Thereafter, the electrode portion 105A (which may include the cap layer 106) may be “encapsulated” by forming the offset spacer 107 based on well-established vapor deposition technique and anisotropic etching technique. . The cap layer 106 and offset spacer 107 are designed to remove material from the semiconductor layer 102 to form each recess 112A, which can be refilled with a suitable semiconductor alloy as described below. During the subsequent etching process 112, sufficient etch resistance is provided. The dimensions and shape of the recess 112A may be determined by the width of the offset spacer 107 and / or designed as a substantially anisotropic etching process, an isotropic etching process, or a combination thereof. It may be determined by the process parameters of the etching process 112 that may be performed. The depth of the recess 112A is such that a certain amount of the material of the layer 102 is retained above the buried insulating layer 103, and still a substantial amount of the portion along the depth direction of the layer 102 is refilled with a strained semiconductor alloy. , Selected such that a particular stress can be applied to the channel region 109 along a substantial amount of depth of the layer 102.

  It will be appreciated that each recess 112A cannot be formed in other device regions if deemed inappropriate for each transistor. In this case, when the offset spacer 107 is patterned, each etching mask may be provided to hold each spacer material in these device regions.

  FIG. 1b schematically shows the semiconductor device 100 in a further subsequent manufacturing stage. As shown, the recess 112A is refilled with a strained semiconductor material 113, such as silicon / germanium, silicon / carbon, silicon / germanium / tin. In the strained semiconductor alloy 113, for example, a substantial amount of material deposition is substantially limited to the exposed region of the semiconductor layer 102, so that a substantial amount of material deposition is not performed on the gate electrode structure 105 and the insulating structure 108. It may be formed based on a selective epitaxial growth technique which is not a problem. During each epitaxial growth, the semiconductor alloy 113 may have a substantially crystalline structure if its original crystal structure is similar to that of the template material of the layer 102. Thus, the alloy 113 may have substantially each lattice spacing and can therefore grow in a strained state. In so doing, the strain type and magnitude are substantially determined by the composition and concentration of the various components of the alloy 113. For example, a silicon / germanium alloy grown on a silicon-based, substantially unstrained material creates a substantial amount of compressive strain, which in turn induces each compressive strain in the channel region 109 as described above. The For example, when the device 100 is a P-channel transistor, the hole mobility in the channel region 109 is significantly improved by a germanium concentration of 20 to 30 atomic percent or more.

  In other exemplary embodiments, the semiconductor alloy 113 may be any other suitable material, such as silicon / carbon, whose native lattice constant is less than that of silicon, thereby growing a tensile strain alloy. To do. The semiconductor alloy 113 having compressive strain or tensile strain may be formed based on a well-established vapor deposition technique using the recess 112A as described above. However, in other exemplary embodiments, the semiconductor alloy 113 may be formed based on other process techniques such as implantation. For example, the etching process 112 may be omitted, or the etching process 112 may be performed in a selected region of the device 100. In such a region that does not include the recess 112A, the strained semiconductor alloy 113 is, for example, germanium. May be formed based on an ion implantation sequence appropriately designed to introduce tin, carbon, and the like.

  For example, the compressed semiconductor alloy is formed by implanting germanium and / or tin, and possibly recrystallizing the material of layer 102, possibly by a prior amorphization implantation. Thereby, the compressive strain semiconductor alloy 113 is formed. In other cases, for example, carbon may be implanted into the semiconductor layer 102 prior to the amorphization implantation, and when the damaged region is recrystallized, the semiconductor alloy 113 is subject to tensile strain. Can be formed. In still other exemplary embodiments, the step of forming the strained semiconductor alloy 113 by a suitable deposition technique based on the recess 112A may be combined with an implantation process performed in other device regions, It is advantageous if appropriate selective deposition techniques cannot be used efficiently under the conditions. For example, a compressed semiconductor alloy may be formed in the recess 112A based on selective epitaxial growth, while a tensile semiconductor alloy may be formed in other device regions based on a carbon implantation technique.

  Thereafter, the offset spacer 107 may be removed by a suitable etching process, possibly along with a portion of the cap layer 106. Alternatively, in other cases, if the width of the spacer 107 is deemed appropriate for the subsequent ion implantation process 114, the spacer 107 is used as an implantation mask and a specific offset of the drain and source extension regions 115E. May be provided. Before or after the implantation process 114, another implantation process is performed, for example to form a so-called halo region (not shown), and the steepness required for the PN junction formed by the extension region 115E and the channel region 109 is achieved. A dopant gradient may be obtained. For example, each halo implant includes a gradient implant process. In the process, a dopant having a conductivity type opposite to that of the extension region 115E is introduced below the end portion of the electrode portion 105A.

  FIG. 1 c schematically shows the semiconductor device 100 in a further subsequent manufacturing stage. As shown, a spacer structure 116 may be formed on the sidewall of the gate electrode structure 105. The structure 105 may still include offset spacers, such as spacers 107, and in other cases, each offset spacer may already have been removed. Further, the cap layer 106 or a part thereof may still cover the upper surface of the gate electrode portion 105A. The spacer structure 116 may be provided with a width 116W. This width is selected to substantially define the lateral dopant profile of future deep drain and source regions. Since a substantial amount of diffusion in the vertical direction cannot be required to form deep source and drain regions extending to the buried insulating layer 103, each side diffusion due to the spacer width 116W is also unnecessary, thereby The lateral dimensions of the device 100 can be reduced. The spacer structure 116 is formed based on a well-established technique such as deposition of a suitable material such as silicon nitride, silicon dioxide, followed by a suitable etching technique.

  FIG. 1d schematically illustrates the semiconductor device 100 during an etching process 117 that removes the material of the semiconductor layer 102 from the strained semiconductor alloy 113 and forms a recess 117A. This etching process 117 may be performed based on a well-established etching recipe in which isotropicity can be selected according to device requirements. That is, each process parameter, such as an etch chemistry, or a plasma parameter, etc., may be selected if a dry etching process is used to obtain each direction during the process 117. For example, advanced anisotropic etching techniques may be used to selectively remove material of layer 102 and form recess 117A such that the offset to channel region 109 is substantially determined by spacer width 116W. Also good. In other cases, the operation may be substantially selected for the process 117 to obtain some degree of underetching, as shown by the dashed line 117B. For example, by using an isotropic etch recipe, selectivity for other materials such as insulating structure 108 and spacer structure 116 can be increased. The etching process 117 may be controlled based on the etching time during which the recess 117A can be adjusted to a desired depth based on the predicted or measured etching rate.

  In other exemplary embodiments, each implantation process is already performed, e.g., before or after forming the extension region 115E, so as to introduce an indicator species appropriate to the desired depth. This indicator species is released during the etching process 117 and an efficient signal is sent to control the etching process 117. For example, in an optical endpoint detection system such as commonly used in plasma etching processes, an appropriate species that transmits a fully detectable endpoint detection signal may be injected, and each “exotic” species selected. A moderately low concentration is sufficient. Therefore, it is possible to efficiently suppress variations in the etching rate that may change the depth of the substrate 117 in the recess 117A. In other exemplary embodiments, a species indicative of each etch may be introduced during the process for forming the strained semiconductor alloy 113. For example, during the selective epitaxial growth process, each indicator species may be added to the deposition environment to form a reasonably clear boundary between a portion with and without indicator material. Good. In general, the deposition process is controlled with higher accuracy than each etching process and the process variation is small. In this case, the substrate-to-substrate variation of the recess 117A can be reduced.

  FIG. 1e schematically shows the semiconductor device 100 in a further subsequent manufacturing stage. In the figure, a further implantation process 118 is performed such that a deep drain and source region 115D is formed that extends at least to the buried insulating layer 103 having a reasonably high dopant concentration. This process can be realized by removing a substantial portion of the semiconductor material alloy 113. Thus, the implantation process 118 allows a reasonably high concentration over the entire depth of the deep drain and source region 115D. Supplying various maximum concentrations to various depths of the corresponding semiconductor material required a complex implantation sequence using various implantation energies, which resulted in a complex using various implantation energies. It is possible to avoid the injection sequence.

  In an exemplary embodiment, a ramped implant 118A is performed in the implant process 118 to increase the dopant concentration in the drain and source extension regions 115E and increase the concentration below the spacer structure 116 to reduce each series resistance. May be. As shown, in certain exemplary embodiments, cap layer 106 may be removed prior to implantation 118 if the respective dopant concentration may be desired in electrode portion 105A. For this, the cap layer 106 may be thinned to the appropriate value required to function as an efficient etch mask during the etching process, after which the thinned cap layer 106 is It may be removed by a highly selective etching process. In this case, the spacer structure cannot be significantly affected. In other cases, the reduction of the spacer width 116W may be adjusted during the corresponding process for removing the cap layer 106, depending on the degree of corresponding under-etching already described with respect to FIG.

  Thus, after the ion implantation process 118, which may include a tilted implantation sequence 118A, the drain and source regions comprised of deep drain and source regions 115D having a high dopant concentration extending to the extension region 115E and the buried insulating layer 103. 115 is formed. Further, the strained semiconductor alloy 113 is held at its original thickness in the drain and source regions 115 below the spacer structure 116, thereby providing an efficient strain inducing mechanism in the channel region 109.

  FIG. 1f schematically illustrates the semiconductor device 100 during an annealing process 119 designed to activate the dopants in the drain and source regions 115 and recrystallize the implant damage in these regions. In one exemplary embodiment, the anneal process 119 includes an anneal step designed to perform a specific lateral diffusion as shown by arrow 119A to adjust the desired effective channel length in the channel region 109. sell. For example, the annealing process 119 is performed based on well-established annealing techniques at a temperature in the range of about 600 degrees to 1000 degrees in combination with a processing time appropriately selected to achieve the desired thermal budget. This may define the desired lateral dopant profile. Vertical diffusion is not necessary because of the high dopant concentration in the deep drain and source regions 115D obtained by providing the recess 117A (FIG. 1e).

  Thus, only each process parameter may be selected in view of appropriately adjusting the lateral profile. As already explained, with a short exposure time, eg 1 second or significantly shorter (eg several milliseconds or less), before or after each annealing step to form the effective channel length. An annealing process by advanced irradiation may be performed. Thus, in this case, a substantial amount of diffusion is substantially suppressed, thereby increasing the diffusion profile already established or in a subsequent “low temperature” anneal process to adjust the effective channel length. Is retained. At that time, the dopant is efficiently activated by a moderately high-temperature short-time annealing process performed at a temperature of about 1100 ° C. to 1300 ° C. or higher. Accordingly, the drain and source regions 115 have a high dopant concentration and a low capacitance, and are provided with a desired lateral dopant profile.

  FIG. 1g schematically shows the device 100 during the annealing process 119, which is designed as an annealing process with short exposure and the dopant profile is kept implanted. Therefore, in this case, the position and characteristics of each PN junction defined by the extension region 115E and the deep drain and source regions 115D are determined by the offset spacer 107 formed when the drain and source regions 115 are formed (profiling). (FIG. 1b) and the spacer width, such as spacer structure 116, can be adjusted based on the implantation process. Therefore, the offset spacer 107 and the spacer structure 116 have a “minimum” width so that no substantial amount of lateral diffusion is required due to the short time, modern laser or flash light annealing process 119 feature. As can be provided, the device 100 can be formed with significantly reduced lateral dimensions.

  FIG. 1h schematically illustrates a semiconductor device 100 according to a further exemplary embodiment in which an annealing step 119B may be performed after formation of the extension region 115E and before formation of the deep drain and source regions 115D. For example, as shown in FIG. 1h, when a laser or flashlight annealing process is used, a high degree of process uniformity is provided because the interaction of the corresponding radiation with the spacer structure 116 is avoided. As such, an anneal process 119B may be performed prior to forming the spacer structure 116. In other cases, a conventional short time thermal anneal (RTA) regime may be used, in which case each process parameter is individually set to adjust the diffusion behavior to properly define the effective channel length. Designed to. In this case, the dopant is activated during the annealing process 119 (FIG. 1g), and the shape of the extension region 115E that has already been formed can be substantially retained, so that the activity of the dopant can be selected in selecting appropriate process parameters. Other criteria such as degree of conversion cannot be relevant.

  FIG. 1 i schematically shows a semiconductor device 100 according to a further exemplary embodiment. As shown, the semiconductor device 100 may be exposed to a process 120 for introducing additional species into the material of the semiconductor layer 120, where the additional species does not extend to the buried insulating layer 103. Can be positioned. In one exemplary embodiment, the process 120 includes an ion implantation process to increase the concentration of non-silicon components in the semiconductor alloy 113 and / or to increase the extension of the semiconductor alloy 113 toward the buried insulating layer 103. May be included.

  Since the remaining deep drain and source regions 150D are thinned, each alloy component is positioned in close proximity to the buried insulating layer 103 and still to recrystallize the damaged portions of the drain and source regions 115. The corresponding implantation process after treatment 120 is highly accurate so as to retain a sufficient amount of template material adhering to the buried insulating layer 103 so that a strained semiconductor alloy can be obtained during a subsequent annealing process 119. Can be implemented. For example, if the semiconductor alloy 113 includes silicon / carbon, which can typically include a carbon concentration of about 1-5 atomic percent, similar concentrations can also be obtained based on the implantation process. Similarly, in a silicon / germanium alloy, tin is efficiently introduced by high-precision ion implantation. Thereby, the atoms of tin can have a much larger covalent bond radius than the atoms of germanium, so that the whole is significantly distorted.

  In other exemplary embodiments, in addition to or in place of the implantation process described above, in process 120, suitable near the exposed surface of drain and source regions 115 to facilitate further processing of device 100. A seed 120A may be introduced. For example, if it is necessary to further reduce the series resistance of the drain and source regions 115 based on metal silicide, the dopant concentration near its surface may be increased or germanium to affect the subsequent silicidation process. The concentration may be increased. In this case, the increased concentration of each species can function as a silicide block material that can significantly reduce the reaction rate in forming the metal silicide. This is advantageous in preventing silicide growth in the direction of the PN junction, and may thus short the PN junction in the region 115 where the distance between the PN junction and the metal silicide may be the shortest.

  Further, since each seed 120a is effectively blocked by the cap layer 106, and silicide formation in the electrode portion 105a is not hindered, the formation of silicide between the electrode portion 105A and the drain and source regions 115 is substantially prevented. Can be separated. In some other exemplary embodiments, some silicidation regimes are less efficient and less stable for silicon-based semiconductor alloys such as silicon / germanium with a high concentration of germanium. Appropriate species may be introduced in process 120 to facilitate or stabilize the silicidation process. In this case, for example, silicon may be implanted at a high dose to significantly reduce the concentration of other alloy components.

  After forming the drain and source regions 115, a metal silicide is formed in some cases as discussed with respect to FIG. 1i, followed by further processing based on well established techniques in which an interlayer dielectric material is deposited. In an exemplary embodiment, high intrinsic stress may be applied to at least a portion of each material to further increase each strain in the channel region 109. Thanks to the recessed structure, even each stress transfer mechanism from the overlying dielectric material to the channel region 109 can be enhanced compared to conventional substantially planar drain and source structures.

  FIG. 2 schematically illustrates a semiconductor device 200 including a first transistor 200A and a second transistor 200B. In the figure, at least one of the transistors 200A and 200B may have a structure as described in connection with the device 100. That is, the device 200 includes a buried insulating layer 103 and a substrate 101 on which a semiconductor layer 202 is formed. These components may have the same characteristics as previously described for each component of device 100. Further, the transistors 200A and 200B have at least one characteristic such as a conductivity type, a structure of drain and source regions, that is, whether a recess is formed or not, or a strain type induced in each channel region. May be different.

  In the illustrated embodiment, transistors 200A, 200B may be P-channel transistors and N-channel transistors, respectively, in which case both transistors 200A, 200B are strained semiconductor alloy 231A so as to induce respective strains. And 231B may be introduced respectively. Further, both transistors 200A, 200B may have a drain / source structure with a recess, as already described with respect to device 100, in which case one of transistors 200A, 200B is otherwise It will be appreciated that may have a substantially planar structure.

  Therefore, as illustrated, the transistors 200A and 200B include an electrode portion 205A formed in the gate insulating layer 204, and the gate insulating layer 204 separates the electrode portion 205A from the channel region 209. Further, a spacer structure 216 may be provided that can substantially determine the recess width of each of the drain and source regions 215 that may include the extension region 215E and the deep drain and source regions 215D. In the illustrated example, the drain and source regions 215 of the first transistor 200A can include a high concentration of P-type dopant material, and the drain and source regions 215 of the transistor 200B can include a high concentration of N-type dopant material. Furthermore, the strained semiconductor alloy 213A can apply the respective compressive strains 221A to the channel region 209 of the first transistor 200A, and the semiconductor alloy 213B can apply the tensile strain 221B to the second transistor 200B.

  The semiconductor device 200 may be formed based on process techniques as described above with respect to the device 100. For example, as described above, each strained semiconductor alloy 213A, 213B may be generated based on a suitable process sequence, for example, a combination of different epitaxial growth techniques, implantation techniques, and the like, in some cases. Thereafter, as described above, further processing may be continued. That is, each extended region 215E is formed based on a well-established masking regime, and then a recess is formed by a common etching process such as process 117, and the source where the recess as shown is formed. / A drain structure may be obtained. Thereafter, deep drain and source regions 215E may be formed based on the process techniques described above. Therefore, a drain / source structure in which a recess is formed in a drain and a source region based on a strained semiconductor alloy can be efficiently provided for different types of transistors. Compatibility can be maintained.

  As a result, the subject matter disclosed herein allows the recesses to have a high dopant concentration so that deep drain and source regions that can reach the buried insulating layer can be reduced to reduce the effective junction capacitance of the SOI transistor. A method and a semiconductor device are provided that feature a drain / source structure formed. Since the recess is formed after the introduction of the strained semiconductor alloy based on the spacer structure that provides an offset to the strained semiconductor alloy, the strain inducing effect of the strained semiconductor alloy can be substantially maintained along the original thickness of the alloy. . In addition, the techniques disclosed herein provide the possibility to adjust the effective channel length separately without undue diffusion, or each implant profile is implanted based on the latest irradiation annealing technique. The lateral transistor dimensions can be further reduced.

  It will be apparent to those skilled in the art who are able to benefit from the present invention that various modifications and implementations are possible within the equivalent scope of the present invention, so that the individual embodiments described above are exemplary. It's just a thing. For example, the execution order of each step in the above-described method can be changed. Further, the details of the configuration or the design described above are not intended to limit the present invention at all, and are limited only to the description of the claims. Thus, it will be apparent that the particular embodiments described above can be varied and modified and such variations are within the spirit and scope of the invention. Accordingly, the protection of the present invention is limited only by the scope of the claims.

Claims (4)

Forming a first recess in the semiconductor region of the transistor by performing a first etching process using the gate electrode structure of the transistor as an etch mask;
Forming a drain and source extension regions by, before Symbol semi conductor region performing a first ion implantation process using the gate electrode structure as an implantation mask,
Forming a spacer structure on a sidewall of the gate electrode structure;
After forming the spacer structure, performing a second etching process to form a plurality of second recesses in the semiconductor region;
Performing a second ion implantation process on the first recess to form drain and source regions extending to a buried insulating layer provided below the semiconductor region using the spacer structure as an implantation mask;
Performing an annealing process to activate the dopant in the drain and source regions;
Forming a strained semiconductor material in the first recess before performing the first ion implantation process so as to induce strain in the channel region of the transistor, wherein the step of forming the strained semiconductor material comprises: The method wherein at least one of a compressive strain semiconductor material and a tensile strain semiconductor material is formed in the semiconductor region.   The method of claim 1, wherein the annealing process comprises an annealing step by irradiation with an effective irradiation time of about 1 second or less.   The method of claim 1, wherein the annealing process includes an annealing step designed to adjust an effective lateral channel length of the transistor. Before performing the second ion implantation process, and executing the extended annealing process designed to anneal to the extension region,
The method according to claim 1, further comprising: forming a cap layer above an upper surface of the electrode portion of the gate electrode structure, and using the cap layer as an etching mask when performing the first etching process .

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