JP2010532571A - ドレインおよびソース領域にリセスを形成することによってトランジスタの接合容量の低減 - Google Patents
ドレインおよびソース領域にリセスを形成することによってトランジスタの接合容量の低減 Download PDFInfo
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- JP2010532571A JP2010532571A JP2010514849A JP2010514849A JP2010532571A JP 2010532571 A JP2010532571 A JP 2010532571A JP 2010514849 A JP2010514849 A JP 2010514849A JP 2010514849 A JP2010514849 A JP 2010514849A JP 2010532571 A JP2010532571 A JP 2010532571A
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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Abstract
Description
記録密度が改良され、さらに高性能の集積回路を開発するうえでの主要な問題となるのは、最新のCPUやメモリデバイスの製造に必要とされうる非常に多くのトランジスタ素子を設けるために、MOSトラ ンジスタ素子などのトランジスタ素子を縮小することである。縮小した電界効果トランジスタを製造する際の1つの重要な態様として、トランジスタのソース及びドレイン領域を分離する導電性チャネルの形成を制御するゲー ト電極の長さを縮小することが挙げられる。
トランジスタ素子のソース及びドレイン領域は、基板あるいはウェル領域などの、周囲の結晶活性領域のドーパントとは逆の導電型のドーパントを含む導電性の半導体領域である。
さらに、アニールプロセスの間の温度が高いとゲート絶縁層に悪影響を与えてしまい、そのためにゲート絶縁層の信頼性が低下してしまうおそれがある。つまり、アニール温度が高いとゲート絶縁層が劣化し、従って、その誘電特性にも影響を及ぼすおそれがあり、そのためにリーク電流の増加や、破壊電圧の低下等が生じるおそれがある。したがって、非常に高度なトランジスタに対しては、最終的なデバイス性能を定義するうえでの重要な特性として、ドーパントプロファイルを所望するように位置決めし、成形し、維持することが挙げられる。その理由は、ドレインコンタクトとソースコンタクトとの間の導電性パスの全体の直列抵抗がトランジスタの性能を決定する主要な要素となるからである。
Claims (10)
- トランジスタのゲート電極構造を注入マスクとして使用して第1イオン注入プロセスを実行することによって、前記トランジスタの半導体領域にドレインおよびソース拡張領域を形成するステップと、
前記ゲート電極構造のサイドウォールにスペーサ構造を形成するステップと、
前記スペーサ構造を形成後、エッチングプロセスを実行し、前記半導体領域に複数のリセスを形成するようにするステップと、
前記スペーサ構造を注入マスクとして使用して、前記半導体領域下方に設けられる埋め込み絶縁層にまで及ぶドレインおよびソース領域を形成するために、前記リセスに第2イオン注入プロセスを実行するステップと、
前記ドレインおよびソース領域のドーパントを活性化させるためにアニールプロセスを実行するステップと、を含む方法。 - 前記トランジスタのチャネル領域に歪みを誘起させるように前記半導体領域に歪み半導体材料を形成するステップをさらに含み、前記歪み半導体材料の形成ステップにおいて、前記半導体領域に圧縮歪み半導体材料と引張歪み半導体材料のうちの少なくとも一方が形成される、請求項1記載の方法。
- 前記アニールプロセスは、実効照射時間が約1秒かそれ未満の、照射によるアニールステップを含む、請求項1記載の方法。
- 前記アニールプロセスは、前記トランジスタの横方向の実効チャネル長を調整するように設計されているアニールステップを含む、請求項1記載の方法。
- 前記第2イオン注入プロセスを実行する前に、前記拡張領域をアニールするように設計された拡張アニールプロセスを実行し、前記ゲート電極構造の電極部の上面の上方にキャップ層を形成し、前記半導体領域にリセスを形成する際に前記キャップ層をエッチングマスクとして用いるステップをさらに含む、請求項1記載の方法。
- 第1トランジスタの第1半導体領域に第1歪み半導体合金を形成するステップを含み、前記第1歪み半導体合金は、少なくとも一部がドレインおよびソース領域に設けられており、前記第1トランジスタのチャネル領域に第1タイプの歪みを誘起するものであって、
前記第1トランジスタの前記ドレインおよびソース領域の各々の一部にリセスを形成するステップと、
前記第1半導体領域に形成される埋め込み絶縁層にまで及ぶ深いドレインおよびソース領域を形成するために、前記ドレインおよびソース領域の前記リセスにドーパント種を注入するステップと、を含む、方法。 - 第2トランジスタの第2半導体領域に第2歪み半導体合金を形成するステップをさらに含み、前記第2歪み半導体合金は少なくとも一部がドレインおよびソース領域に設けられており、前記第2トランジスタのチャネル領域に第2タイプの歪みを誘起するものであり、前記第1タイプの歪みは前記第2タイプの歪みとは逆のタイプの歪みであって、
前記第2トランジスタの前記ドレインおよびソース領域の各々の一部にリセスを形成するステップと、
深いドレインおよびソース領域を形成するために、前記第2トランジスタの前記ドレインおよびソース領域にドーパント種を注入するステップと、
埋め込み絶縁層にまで及ぶ前記第2トランジスタの深いドレインおよびソース領域を形成するために、前記第2トランジスタの前記ドレインおよびソース領域にドーパント種を注入するステップと、を含む、方法 - 前記第1トランジスタに前記リセスを形成する前に前記第1トランジスタにドレインおよびソース拡張領域を形成するステップと、前記第1トランジスタをアニールするステップとをさらに含み、前記第1トランジスタのアニールステップにおいて、前記第1トランジスタの実効チャネル長を調整するように前記第1トランジスタの前記ドレインおよびソース領域の拡張領域がアニーリングされる、請求項6記載の方法。
- 埋め込み絶縁層にまで及び、リセスが形成されたドレインおよびソース領域を有する第1トランジスタと、
前記第1トランジスタのチャネル領域に歪みを誘起する、前記ドレインおよびソース領域の一部に設けられた歪み半導体合金と、を含む半導体デバイス。 - 前記歪み半導体合金は、圧縮歪みあるいは引張歪みのうちの少なくとも一方を有しており、さらに、前記第1トランジスタに対して異なる導電型の第2トランジスタを含む、請求項9記載の半導体デバイス。
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JP2020535632A (ja) * | 2017-09-25 | 2020-12-03 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | ソース領域またはドレイン領域あるいはその両方とチャネル領域との間の直列抵抗の低減 |
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KR20190059200A (ko) * | 2017-11-22 | 2019-05-30 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Soi 구조들을 사용하는 임베디드 메모리 및 방법들 |
KR102195675B1 (ko) * | 2017-11-22 | 2020-12-29 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Soi 구조들을 사용하는 임베디드 메모리 및 방법들 |
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DE102007030053A1 (de) | 2009-01-02 |
CN101755326B (zh) | 2013-02-27 |
ATE542238T1 (de) | 2012-02-15 |
EP2428986B1 (en) | 2018-08-22 |
JP5244908B2 (ja) | 2013-07-24 |
EP2428986A2 (en) | 2012-03-14 |
TW200908161A (en) | 2009-02-16 |
WO2009005785A1 (en) | 2009-01-08 |
CN101755326A (zh) | 2010-06-23 |
US7754556B2 (en) | 2010-07-13 |
US8183605B2 (en) | 2012-05-22 |
DE102007030053B4 (de) | 2011-07-21 |
EP2168152A1 (en) | 2010-03-31 |
US20100237431A1 (en) | 2010-09-23 |
TWI471944B (zh) | 2015-02-01 |
US20090001484A1 (en) | 2009-01-01 |
EP2168152B1 (en) | 2012-01-18 |
EP2428986A3 (en) | 2012-09-12 |
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