TWI627664B - 於p通道金屬氧化物半導體場效電晶體中形成氟摻雜通道矽鍺層的方法及其p通道金屬金屬氧化物半導體場效電晶體 - Google Patents

於p通道金屬氧化物半導體場效電晶體中形成氟摻雜通道矽鍺層的方法及其p通道金屬金屬氧化物半導體場效電晶體 Download PDF

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TWI627664B
TWI627664B TW102143198A TW102143198A TWI627664B TW I627664 B TWI627664 B TW I627664B TW 102143198 A TW102143198 A TW 102143198A TW 102143198 A TW102143198 A TW 102143198A TW I627664 B TWI627664 B TW I627664B
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尼可拉斯 薩斯特
顏然
簡 渥契爾
翁祥陽
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Abstract

本發明所揭示的是用於在通道矽鍺(cSiGe)層具有改良型介面粗糙度的P型通道金屬氧化物半導體場效電晶體(PMOSFET)的形成方法以及所產生的裝置。具體實施例可包括在基底中指定作為通道區的區域、在所指定通道區上面形成通道矽鍺層、以及將氟直接佈植到通道矽鍺層內。具體實施例或可包括將氟佈植到基底中被指定為通道區的區域內、在所指定通道區上面形成通道矽鍺層、以及加熱矽基底和通道矽鍺層以將氟擴散到通道矽鍺層內。

Description

於p通道金屬氧化物半導體場效電晶體中形成氟摻雜通道矽鍺層的方法及其p通道金屬氧化物半導體場效電晶體
本揭示係關於半導體裝置中的通道矽鍺(cSiGe)層。本揭示尤其適用於形成具有改良型介面粗糙度的通道矽鍺層，同時維持p通道金屬氧化物半導體場效電晶體(PMOSFET)中的臨界電壓效率。
針對高k介電金屬閘極技術在PMOSFET中使用通道矽鍺層可降低臨界電壓。然而，降低臨界電壓所需之例如等於或大於100埃(Å)的厚度提高通道矽鍺層與其它層(例如矽基底及/或閘極介電層)之間的粗糙度。介面粗糙度的增加使電晶體的可靠度及效能降低。
因此，存在令具有改良型介面粗糙度之通道矽鍺層較厚又同時維持有效臨界電壓之方法、及所產生之裝置的需求。
本揭示的一個態樣是用於在PMOSFET中形成氟摻雜通道矽鍺層的有效方法。
本揭示的另一個態樣是具有氟摻雜通道矽鍺層的PMOSFET。
本揭示的另外態樣及其它特徵將在下文的說明中提 出，並且在審閱下文後對於所屬領域具有普通技術的人員將是顯 而易知或可學習自本揭示的實踐。可如所附申請專利範圍特別指出而實現並且取得本揭示的優點。
根據本揭示，某些技術功效可藉由包括如下所述的方法而部分達成：在基底中指定作為通道區的區域，在所指定通道區之上形成通道矽鍺層，以及將氟直接佈植到通道矽鍺層內。
本揭示的一個態樣包括以8×1014至2×1015原子/平方公分(cm2)的劑量在通道矽鍺層中佈植氟。本揭示的一個態樣是以5至10仟電子伏特(keV)的能量在通道矽鍺層中佈植氟。本揭示的又一個態樣是在佈植氟之後以400至650℃對通道矽鍺進行退火。本揭示另外的態樣是形成通道矽鍺層至40到80Å的厚度。本揭示的另一個態樣是在通道矽鍺層上方形成閘極介電層。本揭示另外的態樣是在閘極介電層上形成閘極。
進一步技術功效也可藉由包括如下所述的方法而部分達成：將氟佈植到矽基底中被指定為通道區的區域，在所指定通道區之上形成通道矽鍺層，以及加熱矽基底和通道矽鍺層以使氟擴散到通道矽鍺層內。
另一個態樣包括以1×1015至3×1015原子/平方公分的劑量在所指定通道區中佈植氟。另外的態樣包括以5至10仟電子伏特的能量在所指定通道區中佈植氟。又一個態樣包括在佈植氟之後以及形成通道矽鍺層之前以650至1050℃對矽基底進行退火。進一步態樣包括形成通道矽鍺層至40到80Å的厚度。其它態樣包括在通道矽鍺層之上形成閘極介電層，其中矽基底和通道矽鍺層之加熱發生在形成閘極介電層期間及/或之後。進一步態樣 包括在閘極介電層上形成閘極，其中矽基底和通道矽鍺層的加熱發生在形成閘極期間及/或之後。
本揭示的另一個態樣是裝置，其包括：基底，基底中的P型通道區，以及基底上之P型通道區之上的氟摻雜通道矽鍺層，通道矽鍺層係形成至40到80Å的厚度。
態樣包括以5至10keV的能量佈植的氟。另外的態樣包括以1×1015至3×1015原子/平方公分的劑量佈植並且以650至1050℃進行退火的氟。進一步態樣包括以8×1014至2×1015原子/平方公分的劑量佈植並且以400至650℃進行退火的氟。又一個態樣包括通道矽鍺層之上的閘極介電層。另一個態樣包括閘極介電層之上的高k介電質金屬閘極。
本揭示另外的態樣及技術功效經由下文所述實施方式對所屬領域的技術人員而言將顯而易見，其中本揭示的具體實施例係單純地藉由描述經考慮用以實施本揭示的最佳模式予以說明。將瞭解的是，本揭示能有其它及不同的具體實施例，並且其細節能以各種明顯方式改進，全部都不脫離本揭示內容。因此，圖式及說明本質上係視為描述性而非限制性。
101‧‧‧基底
103‧‧‧區域
201‧‧‧通道矽鍺層
301‧‧‧氟摻雜通道矽鍺層
401‧‧‧閘極介電層
403‧‧‧閘極
405‧‧‧間隔件
407‧‧‧源極/汲極區
409‧‧‧通道
411‧‧‧氟摻雜通道矽鍺層
501‧‧‧氟摻雜層
701‧‧‧氟摻雜通道矽鍺層
本揭示係藉由實施例而非經由限制予以在所附圖式的圖示中描述，並且相同的元件符號意指類似元件，以及其中：第1至4圖根據一個示例性具體實施例示意性描述用於在PMOSFET中形成氟摻雜通道矽鍺層的方法；以及第5至7圖根據替代之示例性具體實施例示意性描述用於在PMOSFET中形成氟摻雜通道矽鍺層的方法。
在下文的說明中，為了解釋，提出許多特定細節以便透徹理解示例性具體實施例。然而，應該顯而易知的是，可無需這些特定細節或利用等效配置來實踐示例性具體實施例。在其它實例中，方塊圖中顯示眾所周知的結構和裝置以防示例性具體實施例受到不必要的混淆。另外，除非另有所指，說明書及申請專利範圍中用來表達數量、比率、以及成分之數值特性、反應條件等等的所有數字在所有實例中都應理解為藉由術語「大約」修飾。
本揭示處理並且解決了目前為了降低PMOSFET中之臨界電壓將通道矽鍺層形成至足夠厚度所伴隨而來之效能及可靠度不良的問題。根據本揭示的具體實施例，氟摻雜通道矽鍺層係在PMOSFET內縮減厚度形成，以改良裝置可靠度及效能同時維持足夠的臨界電壓。
根據本揭示一個具體實施例的方法包括在基底中指定區域作為通道區。其次，在所指定通道區之上形成通道矽鍺層。可將通道矽鍺層形成至40到80Å的厚度。接著，將氟直接佈植到通道矽鍺層內。後續步驟可包括在通道矽鍺層上方形成閘極介電層及閘極。
根據本揭示另一個具體實施例的方法包括將氟佈植到矽基底中被指定為通道區的區域內。其次，在所指定通道區之上形成通道矽鍺層。可將通道矽鍺層形成至40到80Å的厚度。隨後，加熱矽基底及通道矽鍺層以使氟擴散到通道矽鍺層內。
請參閱第1圖，根據一個示例性具體實施例，用於 在PMOSFET中形成氟摻雜通道矽鍺層的方法始於基底101。如圖所示，基底101可為塊體矽(Si)晶圓。或者，基底101可為絕緣體上覆矽(SOI)晶圓。在下文所述後續處理後，基底可包括將變成通道區的區域103。
其次，如第2圖所示，在基底101上方形成通道矽鍺層201。通道矽鍺層201可形成至40到80Å的厚度並且可根據諸如藉由磊晶生長等習知處理技術形成。
隨後，將氟直接佈植到通道矽鍺層201內以形成氟摻雜通道矽鍺層301，如第3圖所示。可以8×1014至2×1015原子/平方公分(atoms/cm2)的劑量及5至10仟電子伏特(keV)的能量佈植氟。所佈植的氟使產生的PMOSFET之臨界電壓降低並且使通道矽鍺層更薄。佈植氟之後，通道矽鍺層301於400至650℃進行退火4分鐘以修復將氟直接佈植到通道矽鍺層201內所造成的任何佈植損壞。
隨後，如第4圖所示，在氟摻雜通道矽鍺層301上方形成閘極介電層401、閘極403、以及間隔件405。接著形成源極/汲極區407，通道409則在先前置於閘極403下面並且介於源極/汲極區407之間的區域103處形成，從而形成PMOSFET。可將氟摻雜通道矽鍺層301蝕刻至與閘極403的寬度一樣，如所蝕刻之氟摻雜通道矽鍺層411所示。閘極介電層401可為諸如氮化矽酸鉿(HfSiON)的高k介電質，並且閘極403可為金屬閘極。
較薄的氟摻雜通道矽鍺層301/411導致比提供等效臨界電壓之習知、較厚(例如，等於或大於100Å)、非氟摻雜通道矽鍺層更小的介面粗糙度。較薄的氟摻雜通道矽鍺層301/411也 使介面電荷捕捉(trapping)與去陷(de-trapping)更少以及裝置遷移率更高。而且，在基底101的表面上控制氟佈植比控制SiGe生長更容易。通道矽鍺層之厚度縮減再加上諸如SiGe(例如SixGeyOz)頂部上所形成之氧化層中或後續所形成之高k介電層中的氟消耗型帶電氧空位(fluorine consuming charged oxygen vacancies)的特性改良了所產生之PMOSFET的可靠度及效能。例如，氟摻雜通道矽鍺層301/411比習知、非氟摻雜通道矽鍺層改良了25至70毫伏(mV)的最大電壓供給(VDDMAX)以及20至40mV的時變性介電質崩潰電壓(TDDB)。
請參閱第5圖，根據另一個示例性具體實施例用於在PMOSFET層中形成氟摻雜通道矽鍺層的方法始於第1圖中具有區域103的基底101。其次，將氟佈植到形成氟摻雜層501之區域103內的基底101之頂部表面內，如第5圖所示。可將氟以1×1015至3×1015/cm2的劑量及5至10keV的能量佈植到基底101內。氟以此劑量使產生的PMOSFET之臨界電壓降低並且使通道矽鍺層更薄。在佈植氟之後，視溫度而定，以650至1050℃退火基底5至240秒以修復任何由氟佈植造成的損壞。
其次，如第6圖所示，在基底101之上形成通道矽鍺層201。通道矽鍺層201可形成至40到80Å的厚度並且可根據諸如藉由磊晶生長的習知處理技術形成。基底101內佈植的氟也降低SiGe生長率，使得通道矽鍺層201更薄。
隨後，如第7圖所示，可進行諸如在通道矽鍺層201之上形成閘極介電層401、閘極403、以及間隔件405等額外處理步驟。可進行其它處理步驟以形成源極/汲極區407，其中在區域 103先前置於閘極403下面並且介於源極/汲極區407之間處形成通道區409，從而形成PMOSFET。任何含括加熱基底101的後續處理步驟將造成氟摻雜層501中的氟擴散到通道矽鍺層201內以產生氟摻雜通道矽鍺層，其可進一步予以遮罩並且蝕刻以形成寬度更窄的氟摻雜通道矽鍺層701，如第7圖所示。任何後續加熱也將進一步修復氟佈植所造成之基底101的介面損壞。
本揭示的具體實施例達到許多技術功效，包括維持有效臨界電壓同時降低PMOSFET中通道矽鍺層與附加層(例如，Si基底和閘極介電層)之間的介面粗糙度，從而改良電晶體的效能和可靠度。本揭示的具體實施例享有各種工業應用的用途，舉例如微處理器、智慧型手機、行動電話、蜂巢式手機、機上盒、DVD記錄器與播放器、汽車導航、列印機與周邊裝置、網路與電信設備、遊戲系統、以及數位相機。本揭示因而在各類高整合度半導體裝置中享有產業利用性。
在前述說明中，本揭示係參照其特定示例性具體實施例予以說明。然而，顯而易見的是，可對其進行各種改進及變更而不脫離本揭示更廣泛的精神與範疇，如申請專利範圍所述者。說明書及圖式因而係視為描述性而非限制性。要理解的是，本揭示能夠使用各種其它組合與具體實施例並且能夠在如本文所表達發明概念的範疇內進行任何變更或改進。

Claims (8)

  1. 一種用於在PMOSFET中形成氟摻雜通道矽鍺層的方法，該方法係包含：在基底中指定作為通道區的區域；在該指定通道區之上形成通道矽鍺(cSiGe)層至40到80埃(Å)的厚度；將氟直接佈植到該通道矽鍺層中以形成氟摻雜通道矽鍺層，在佈植該氟之後，退火該通道矽鍺層240秒；在該氟摻雜通道矽鍺層上方形成閘極介電層；以及在該閘極介電層上形成閘極，其中將該氟摻雜通道矽鍺層蝕刻至與該閘極的寬度一樣。
  2. 如申請專利範圍第1項所述的方法，係包含以8×1014至2×1015原子/平方公分(cm2)的劑量佈植該氟到該通道矽鍺層中。
  3. 如申請專利範圍第1項所述的方法，係包含以5至10仟電子伏特(keV)的能量佈植該氟到該通道矽鍺層中。
  4. 如申請專利範圍第1項所述的方法，其中，在佈植該氟之後，以範圍400至650℃的溫度執行退火該通道矽鍺層。
  5. 一種用於在PMOSFET中形成氟摻雜通道矽鍺層的方法，該方法係包含：將氟佈植到矽基底中被指定為通道區的區域；在佈植該氟之後，退火該矽基底240秒或小於240秒；在該指定通道區之上形成通道矽鍺(cSiGe)層至40到80埃(Å)的厚度； 加熱該矽基底和該通道矽鍺層，以使該氟擴散到該通道矽鍺層中，接著形成氟摻雜通道矽鍺層；在該氟摻雜通道矽鍺層上方形成閘極介電層；以及在該閘極介電層上形成閘極，其中將該氟摻雜通道矽鍺層蝕刻至與該閘極的寬度一樣。
  6. 如申請專利範圍第5項所述的方法，係包含以1×1015至3×1015原子/平方公分(cm2)的劑量在該指定通道區中佈植該氟。
  7. 如申請專利範圍第5項所述的方法，係包含以5至10仟電子伏特(keV)的能量在該指定通道區中佈植該氟。
  8. 如申請專利範圍第5項所述的方法，其中，在佈植該氟之後以及形成該通道矽鍺層之前，以範圍650至1050℃的溫度執行退火該矽基底。
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