TW202030351A - 氧化矽之拓撲選擇性膜形成之方法 - Google Patents
氧化矽之拓撲選擇性膜形成之方法 Download PDFInfo
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Abstract
一種用於形成一介電膜之方法,該介電膜含有一Si-O鍵形成於一基板之一上部表面中的一溝槽,該方法包括:藉由相對於得出一最終介電膜之一初始介電膜的一非目標部分,預選擇欲選擇性移除的一目標部分來設計形成在該溝槽中之含有一Si-O鍵之該最終介電膜的一拓樸;在該上部表面上及該溝槽中共形地沉積該初始介電膜;及相對於該初始介電膜之該非目標部分中所含的一雜質量相對地增加該初始介電膜之該目標部分中所含的一雜質量,以得到一經處理介電膜,從而提供該目標部分及該非目標部分遭受蝕刻時之不同的抗化學性質。
Description
本發明大致上係關於一種用於形成一介電膜之方法,該介電膜在形成於一基板表面上之一步階上含有Si-O鍵,特別係關於一種氧化矽之拓撲選擇性膜形成之方法。
原子層沉積(ALD)的特徵不僅在於對膜厚度之優越的可控性以及優越的膜均勻性,且亦在於能夠沉積均勻地覆蓋三維結構的膜,因此,ALD已在半導體產業中經認定為非常重要的沉積方法。另一方面,在一特定的半導體裝置製造製程中,對膜的不均勻形成存在需求(例如,在閘極間隔物中),其中在某些區域中僅選擇性地留下沉積在溝槽中的膜之側壁部分,且在該情況下,藉由ALD來沉積膜係與各向異性乾蝕刻組合使用以形成所欲圖案。然而,由於乾蝕刻的終點難以判定,因而存在過蝕刻而使下方層受損的疑慮。
如此類圖案化技術,已知首先在某些條件下將SiN膜沉積在基板的圖案化表面上,使得圖案之水平部分及垂直部分的濕蝕刻率不同,隨後進行濕蝕刻,從而選擇性地僅留下圖案的側壁部分或圖案的水平部分(例如美國專利申請公開案第2017/0243734號中所揭示者,由於可適用於本文所揭示的某些實施例,其揭露之全文係以引用方式併入本文中)。該技術可稱為SiN之拓樸選擇性膜形成(「TS-SiN」)。在上文中,由於使用濕蝕刻而非乾蝕刻來選擇性地僅移除圖案的垂直部分或水平部分,可行的係設定圖案相對於下方層的高濕蝕刻選擇性,並實現不需要考慮蝕刻均勻性的優點。在TS-SiN中,高濕蝕刻選擇性可藉由增加RF功率來得到;然而,此類條件無法在SiO膜上運作以達成類似的高濕蝕刻選擇性。因此,雖然在半導體產業中對於SiO之拓樸選擇性膜形成(「TS-SiO」)存在高度需求,卻並未成功地實現TS-SiO。
關於相關技術之問題及解決方案的任何論述,僅出於提供本發明之背景脈絡而包括於本揭露中,且不應被視為同意任何或全部該論述在進行本發明時為已知。
在一些實施例中,藉由利用電漿增強ALD (PEALD)將雜質引入至沉積在一基板上之一圖案中的一SiO2
膜來操縱HF(氫氟酸)對該膜的濕蝕刻率,從而選擇性地實質上僅或主要地留下該基板上所形成之該圖案的一垂直部分或水平部分之任一者。在一些實施例中,使用鹵素原子及/或碳原子作為雜質。在一些實施例中,藉由以拓樸方式操縱一基板之一圖案化表面中存在的雜質濃度來調整雜質分布,使得該等雜質選擇性地留在該圖案之一垂直部分中或者該等雜質係各向異性地選擇性引入該圖案之一水平部分中,從而實現拓膜選擇性膜形成。在一些實施例中,該SiO2
膜中所含之該等雜質可源自或衍生自一前驅物及/或後續可透過使用一非矽氣體之一額外膜形成或額外表面處理而引入至該SiO2
膜的一表面。在一些實施例中,該後續引入雜質係藉由PECVD或PEALD來完成,其中該後續引入循環係在每一個單個沉積循環或多個沉積循環之後執行。
具體地,舉例而言,TS-SiO可實施如下:
1)首先,使用含有碳及/或鹵素的一前驅物沉積一SiO2
膜;且接著,使該SiO2
膜暴露至在相對低壓及相對高RF功率下產生的一電漿,從而在該SiO2
膜中形成雜質之一各向異性分布,其中該SiO2
膜中所含的雜質係經選擇性移除,在一圖案之一水平部分的移除明顯多於該圖案之一垂直部分的移除。該雜質移除循環係在每一個單個沉積循環或多個沉積循環之後執行。
2)首先,沉積一SiO2
膜;其次,藉由使該SiO2
膜之一表面暴露至含有碳及/或鹵素作為雜質之一非矽氣體而使雜質吸附至該SiO2
膜之該表面;且接著,使該吸附雜質之SiO2
膜暴露至在相對低壓及相對高RF功率下產生的一電漿,從而在該SiO2
膜中形成雜質的一各向異性分布,其中雜質係經選擇性引入,在一圖案之一垂直部分的引入明顯多於該圖案之一水平部分的引入。該雜質添加循環係在每一個單個沉積循環或多個沉積循環之後執行。在上文中,對沉積SiO2
膜而言,可使用任何合適的含矽前驅物,無論該前驅物是否含有碳及/或鹵素。
3)在上述的步驟1)或2)之後,使該SiO2
膜遭受使用dHF之濕蝕刻,從而選擇性地移除該圖案之所含雜質多於該圖案之剩餘部分的一部分,藉此可完成TS-SiO,其中實質上僅或主要地可選擇性移除該圖案之一垂直部分或水平部分之任一者。
出於概述本發明之態樣及所達成之優於相關技術之優點的目的,在本揭露中描述本發明之某些目標及優點。當然,應理解,無須根據本發明之任何特定實施例來達成所有此類目標或優點。因此,例如,所屬技術領域中具有通常知識者將認知到,可以達成或最佳化如本文中所教示之一個優點或一組優點而無須達成本文中可教示或建議之其他目標或優點的方式來體現或實行本發明。
本發明之進一步的態樣、特徵、及優點將由下文的詳細描述而變得顯而易見。
在本揭露中,「氣體」可包括汽化之固體及/或液體且可由單一氣體或氣體混合物構成。在本揭露中,透過噴淋頭引入至反應室之製程氣體可包含前驅物氣體及添加劑氣體、基本上由前驅物氣體及添加劑氣體組成、或由前驅物氣體及添加劑氣體組成。前驅物氣體及添加劑氣體一般係作為混合氣體或分開地引入至反應空間。前驅物氣體可使用載體氣體(諸如稀有氣體)引入。添加劑氣體可包含反應物氣體及稀釋氣體(諸如稀有氣體)、基本上由反應物氣體及稀釋氣體(諸如稀有氣體)組成、或由反應物氣體及稀釋氣體(諸如稀有氣體)組成。反應物氣體及稀釋氣體可作為混合氣體或分開地引入至反應空間。前驅物可包含二或更多種前驅物,且反應物氣體可包含二或更多種反應物氣體。前驅物係化學吸附於基板上且一般含有構成介電膜基質之主結構的類金屬或金屬元素的氣體,而用於沉積的反應物氣體係當氣體經激發以將原子層或單層固定於基板上時與化學吸附於基板上之前驅物起反應的氣體。「化學吸附(Chemisorption)」係指化學飽和吸附。可使用除製程氣體外之氣體(即,非通過噴淋頭引入之氣體)以用於例如密封反應空間,該氣體包括諸如稀有氣體之密封氣體。在一些實施例中,「膜(film)」係指用以覆蓋整個目標或關注表面,實質上無針孔地在垂直於厚度方向之方向上連續地延伸之層,或簡單地,覆蓋目標或關注表面之層。在一些實施例中,「層(layer)」係指形成於表面上之具有特定厚度之結構或者膜或非膜結構之同義詞。膜或層可由具有特定特性之離散單一膜或層或者多個膜或層構成,且相鄰膜或層之間的邊界可係明顯或可係不明顯的,且可基於相鄰膜或層之物理、化學及/或任何其他特徵、形成製程或序列、及/或功能或用途而建立。
在本揭露中,「含有Si-O鍵(containing a Si-O bond)」可指特徵在於一或多個Si-O鍵,其具有實質上由一或多個Si-O鍵構成的主骨架及/或具有實質上由一或多個Si-O鍵構成的取代基。含有Si-O鍵的介電膜包括,但不限於SiO膜、SiOC膜、及SiON膜,其具有約2至10、一般約4至8之介電常數。
在本揭露中,「退火(annealing)」係指製程,在此製程期間處理材料以使該材料成為其穩定形式,例如,存在於組分中之末端基團(諸如醇基及羥基)係以更穩定基團(諸如Si-Me基)置換及/或形成一般導致膜之緻密化之更穩定形式(諸如Si-O鍵)。
進一步地,在本揭露中,除非另外指明,否則冠詞「一(a or an)」係指一個物種或包括多個物種之屬。在一些實施例中,用語「由……構成(constituted by)」及「具有(having)」係獨立地指「一般或廣泛地包含(typically or broadly comprising)」、「包含(comprising)」、「基本上由……組成(consisting essentially of)」或「由……組成(consisting of)」。同樣地,在本揭露中,在一些實施例中,任何已定義之意義未必排除常規及慣用意義。
此外,在本揭露中,變數之任何兩個數目可構成變數之可工作範圍,因為可工作範圍可基於例行工作而判定,且所指示之任何範圍可包括或排除端點。另外,所指示的變數之任何數值(不管該等數值是否用「約(about)」來指示)可指精確值或近似值且包括等效值,且在一些實施例中可指平均值、中值、代表值、多數值等。
在本揭露中條件及/或結構未得到具體規定之處,熟悉本技藝者可鑒於本揭露輕易提供此類條件及/或結構,作為例行實驗主題。在所有已揭示實施例中,於一實施例中所用之任何元件可由與其等效的任何元件替換,包括用於預期目的而在本文中明確地、必須地、或固有地揭示之彼等元件。此外,本發明可同等地適用於設備及方法。
將參考較佳實施例來解釋該等實施例。然而,本發明並未受限於該等較佳實施例。
一些實施例提供一種用於形成一介電膜之方法,該介電膜在形成於一基板表面上之一步階上含有一Si-O鍵,該方法包含下列製程:(i)藉由參照得出一最終介電膜之一初始介電膜的一非目標部分,預選擇欲選擇性移除的一目標部分來設計形成在該步階上之含有一Si-O鍵之該最終介電膜的一拓樸,該目標部分係形成在該步階之一頂部表面及一底部表面上之該初始介電膜的一頂部/底部部分,或者形成在該步階之一側壁上之該初始介電膜的一側壁部分;(ii)在該步階之該頂部表面、該底部表面、及該側壁上共形地沉積該初始介電膜;(iii)相對於該初始介電膜之該非目標部分中所含的一雜質量相對地增加該初始介電膜之該目標部分中所含的一雜質量,以得到一經處理介電膜,從而提供該目標部分及該非目標部分遭受蝕刻時之不同的抗化學性質;及(iv)蝕刻該經處理介電膜以得到該最終介電膜。結果,實質上僅或主要地可移除該圖案之一垂直部分或水平部分之任一者,從而完成SiO之拓樸選擇性膜形成。在本揭露中,用語「實質上(substantially)」或類似者可指充足、可觀、或由所屬技術領域中具有通常知識者所認定之足以用於意欲目的或功能之材料量、大小、時間、或空間(例如,相對於所關注部分中的總值或參考值係至少70%、80%、90%、或95%)。例如,用語「實質上僅(substantially only)」或類似者可指其中之目標部分對剩餘部分的厚度比率係至少70/30、80/20、90/10、或95/5的組態。
在本揭露中,用語「步階(step)」係指形成在基板中之包括但不限於溝槽的任何凹圖案及/或凸圖案,且在一些實施例中,溝槽可具有約10至約50 nm(一般約15至約30 nm)的寬度(其中當溝槽具有與寬度實質上相同的長度時,其係稱為孔/通孔,且其直徑係約10至約50 nm),約30至約200 nm(一般約50至約150 nm)的深度,及約3至約20(一般約3至約10)之深寬比。在一些實施例中,沉積在基板之溝槽中以及在上部表面上的氧化矽膜具有約70%至100%(一般約80%或更高、更一般約90%或更高)的共形性,其中「共形性(conformality)」係藉由比較沉積在凹部的側壁或底部上之某一點(一般係截面圖的中間點)處之膜厚度與正好沉積在凹部外側之平坦表面上之膜厚度來判定。
在一些實施例中,雜質包括碳及/或鹵素。
在一些實施例中,於製程(i)中,側壁部分係預選擇為目標部分,且在製程(ii)中,初始介電膜係使用進一步含有碳及/或鹵素之含矽前驅物來沉積,且在製程(iii)中,目標部分中所含的雜質量係藉由在兩電極間施加RF功率而激發之電漿的各向異性撞擊來減小初始介電膜之非目標部分中所含的雜質量而相對地增加,基板係在該兩電極之間平行該兩電極放置。此實施例可稱為「藉由雜質之區域選擇性移除之頂部/底部厚TS-SiO (top/bottom-thick TS-SiO by area-selective removal of impurities)」。在此實施例中,藉由電漿的各向異性離子撞擊而主要附接膜的水平部分,且因此,水平部分變得經緻密化,而雜質則經分離或分開,且相對於膜的垂直部分從水平部分選擇性地移除,從而區域選擇性地增加水平部分中的抗化學性並減小其濕蝕刻率(亦即,實質上僅或主要地留下膜的頂部/底部部分)。
在一些實施例中,於藉由雜質之區域選擇性移除的頂部/底部厚TS-SiO中,含矽前驅物係選自由Si2
Ry
Cl6-y
及SiRx
Cl4-x
組成之群組,其中y係0至5的整數,且其中R係H或烷基,且x係0至3的整數。例如,此類前驅物包括,但不限於Si2
Cl6
、SiCl4
、及/或Si2
Cl2
(CH3
)4
。進一步地,在一些實施例中,RF功率針對300-mm晶圓計算得到的係600 W至1,000 W,且係在1至100 Pa的壓力下施加。
在一些實施例中,於製程(i)中,頂部/底部部分係預選擇為目標部分,且在製程(iii)中,目標部分中所含的雜質量係藉由增加初始介電膜之目標部分中所含的雜質量而相對地增加,增加初始介電膜之目標部分中所含的雜質量係藉由(iiia)在初始介電膜的整個暴露表面上吸附含有碳及/或鹵素的非矽氣體,及(iiib)使吸附非矽氣體的表面遭受在兩電極間施加RF功率而激發之電漿的各向異性撞擊,基板係在該兩電極之間平行該兩電極放置。此實施例可稱為「藉由雜質之區域選擇性併入之側壁厚TS-SiO (sidewall-thick TS-SiO by area-selective incorporation of impurities)」。在此實施例中,藉由將雜質引入至膜表面及隨後之電漿的各向異性離子撞擊而主要附接膜的水平部分,且因此,水平部分變得經緻密化,且雜質相對於膜的垂直部分經選擇性地併入及引入至水平部分,從而區域選擇性地減小水平部分中的抗化學性並增加其濕蝕刻率(亦即,實質上僅或主要地留下膜的側壁部分)。
在一些實施例中,於製程(i)中,頂部/底部部分係預選擇為目標部分,且在製程(iii)中,目標部分中所含的雜質量係藉由增加初始介電膜之目標部分中所含的雜質量而相對地增加,增加初始介電膜之目標部分中所含的雜質量係藉由(iiic)在含有碳及/或鹵素的非矽氣體存在的情況下,使初始介電膜遭受在兩電極間施加RF功率而激發之電漿的各向異性撞擊,基板係在該兩電極之間平行該兩電極放置。上述者亦係藉由雜質之區域選擇性併入之側壁厚TS-SiO。在上文中,取代製程(iiia)及(iiib),製程(iiic)係在電漿氣體中包括雜質的情況下實施,而非使雜質吸附至膜表面上隨後再暴露至電漿。
在一些實施例中,由於在藉由雜質之區域選擇性併入之側壁厚TS-SiO中,非矽氣體係用以將雜質引入至膜,前驅物本身不需要含有雜質,且可係習知所用者。例如,此類前驅物包括,但不限於Nx
Hy
(x及y係除了零以外的整數)、Nx
Cy
Hz
(x、y、及z係除了零以外的整數)、及/或N2
。在一些實施例中,前驅物並未含有碳或鹵素。
在一些實施例中,於藉由雜質之區域選擇性併入之側壁厚TS-SiO中,非矽氣體係選自由烴氣、鹵素氣體、及鹵化氣體所組成之群組。例如,此類非矽氣體包括,但不限於CH4
、C2
H6
、Cl2
、Br2
、CCl4
等、或一般係液體並具有10 Torr或更高之蒸氣壓的其他烴氣、鹵素氣體、及鹵化氣體。進一步地,在一些實施例中,RF功率針對300-mm晶圓計算得到的係600 W至1,000 W,且係在1至100 Pa的壓力下施加。
在一些實施例中,於製程(ii)中,初始介電膜係藉由電漿增強ALD或熱ALD來沉積。
在一些實施例中,於製程(iv)中,蝕刻係使用dHF之濕蝕刻。在一些實施例中,HF的濃度係大約0.1%。
將參照圖式中所繪示的較佳實施例詳細解釋本發明。然而,本發明並非意欲受到這些實施例的限制。
圖2係根據本發明之一實施例之繪示SiO之拓樸選擇性膜形成(TS-SiO)製程的流程圖,其係藉由雜質之區域選擇性移除之頂部/底部TS-SiO。在步驟S1中,SiO膜係使用含有雜質的前驅物沉積在具有溝槽的基板上。沉積可藉由任何合適方法(諸如PEALD、熱ALD、循環CVD、或PECVD)來完成。在步驟S2中,所沉積的膜係在相對低壓及相對高RF功率下暴露至稀有氣體電漿,使得與膜之垂直部分中所含的雜質相比,主要或充分地移除膜之水平部分中所含的雜質。步驟S1及步驟S2係無中斷地連續實施(無破壞真空),使得在步驟S1與步驟S2之間,無或極少雜質從基板周圍的大氣經併入或吸附至所沉積的膜之表面。當步驟S1係循環沉積時,步驟S2可在循環沉積的每一個單個循環(沉積單層)之後或者在循環沉積的每兩個或更多個循環(沉積單層的層壓體)之後實施。然而,步驟S1中所得的膜之厚度不應超過在步驟S2中電漿之離子撞擊無法穿透的厚度。一組步驟S1及步驟S2可重複多次,直到得到所欲的膜厚度。在一些實施例中,頂部表面上所沉積的膜之厚度係約3 nm至約50 nm,一般係約10 nm至約30 nm,取決於所沉積的膜之預期目的或用途。在一些實施例中,步驟S2可在下文之表1中所示的條件下實施。
表1(數字為近似值)
「W」可按照基板面積轉換成「W/cm2
」,且經轉換之以W/cm2
為單位的值可應用至不同的基板大小(諸如200-mm基板或450-mm基板)。施加至反應空間之用於後沉積處理之合適的RF功率係依據反應空間的壓力來判定,因為處理的效應取決於電漿的離子能量。因此,例如,一般而言,壓力係約400 Pa或更小(較佳係約100 Pa或更小),且RF功率係約600 W或更高(例如,在400 Pa下),其中壓力越低,可施加的RF功率隨之越低。由於SiO2
膜的沉積可使用常用的RF功率實施,當後沉積處理開始時,一般而言,RF功率會增加。在後沉積處理中,大致上,當施加增加的RF功率時,膜之水平部分的抗化學性變得更高,例如,減小濕蝕刻率,因為可從膜的水平部分移除更多雜質。然而,若RF功率變得太高,膜的水平部分受損,且其抗化學性變得更低,例如,增加濕蝕刻率。也就是,RF功率(由水平軸表示)與抗化學性(由垂直軸表示)之間的關係可由具有最小值的向下曲線表示,該最小值指示最佳RF功率。因此,鑒於此揭露,可透過例行實驗針對預選擇壓力判定最佳RF功率(最佳RF功率依據壓力而改變)。
用於後沉積處理之條件 | |
基板溫度 | 50至600℃(較佳係200至500℃) |
壓力 | 1至500 Pa(較佳係1至300 Pa、更佳係1至100 Pa),取決於RF功率 |
稀有氣體 | Ar、He |
稀有氣體之流量率(連續) | 100至5000 sccm(較佳係500至3000 sccm) |
用於300-mm晶圓之RF功率(13.56 MHz) | 500至3000 W(較佳係600至1000 W、更佳係600至900 W),取決於壓力 |
施加RF功率的持續時間 | 0.5至5秒(較佳係1至3秒) |
電極之間的距離 | 3至20 mm(較佳係5至15 mm) |
持續時間 | 1至300秒(較佳係30至90秒),取決於膜厚度 |
在一些實施例中,並未在步驟S2中將除了稀有氣體以外的氣體引入至反應空間。在一些實施例中,可在步驟S2中以類似的流量率額外或替代地引入氫氣。在一些實施例中,在步驟S2中並未引入氧氣或氮氣或其他反應物或前驅物氣體。
在步驟S3中,經電漿處理的膜係遭受濕蝕刻以達成TS-SiO。藉由步驟S2來從膜的水平部分(亦即,膜的頂部/底部部分)區域選擇性地移除雜質,且膜的水平部分變得緻密化且增加抗化學性。藉由使經電漿處理的膜遭受濕蝕刻,主要地蝕刻或移除比膜之水平部分含有更多雜質之膜的垂直部分(亦即,膜的側壁部分),形成頂部/底部厚輪廓。在一些實施例中,步驟S3可在下文之表2中所示的條件下實施。
表2(數字為近似值)
用於濕蝕刻之條件 | |
蝕刻溶液 | HF 0.05至1%(較佳係約0.1%或更小) |
蝕刻溶液溫度 | 20至30℃(較佳係25℃) |
蝕刻之持續時間 | 30秒至5分鐘(較佳係1至2分鐘) |
蝕刻率 | 1至20 nm/分鐘(較佳係10至20 nm/分鐘) |
對濕蝕刻而言,可使用任何合適的單晶圓型或批式型設備,包括任何習知的設備。同樣地,可使用任何用於濕蝕刻之合適溶液,包括任何習知溶液。由於膜的主成分係由SiO2
構成,若將高濃度的HF溶液用於濕蝕刻,則濕蝕刻選擇性變得不足。因此,一般而言,諸如約0.1%溶液之低濃度HF溶液係用於濕蝕刻。
圖3係根據本發明之另一實施例繪示拓樸選擇性膜形成製程的流程圖。此實施例表示藉由雜質之區域選擇性併入之側壁厚TS-SiO。在步驟S4中,SiO膜係沉積在具有溝槽的基板上。沉積可藉由任何合適方法(諸如PEALD、熱ALD、循環CVD、或PECVD)來完成。在步驟S5中,在電漿暴露之前,使雜質吸附在膜表面上。步驟S5可藉由使膜暴露至含有雜質(諸如碳及/或鹵素)但不含矽的烴氣或類似者,從而使非矽氣體吸附至膜表面上來完成。在一些實施例中,步驟S5可在下文之表3中所示的條件下實施。
表3(數字為近似值)
用於雜質沉積的條件 | |
非矽氣體 | CH4 、C2 H6 、Cl2 、Br2 、CCl4 、 |
非矽氣體的流量率(連續) | 1至100 sccm(較佳係1至10 sccm) |
溫度 | 50至600℃(較佳係200至500℃) |
壓力 | 100至5000 Pa(較佳係100至3000 Pa) |
持續時間 | 1秒至30秒(較佳係0.1至5秒) |
在此實施例中,於步驟S5之後,電漿處理係在除了SiO以外的雜質存在於膜表面上的情況下實施。電漿處理可在表1所示的條件下以實質上類似於圖2(表示藉由雜質之區域選擇性移除之頂部/底部厚TS-SiO)之步驟S2的方式實施。然而,在藉由雜質之區域選擇性併入之側壁厚TS-SiO中,儘管存在步驟S2可以類似於藉由雜質之區域選擇性移除之頂部/底部厚TS-SiO中的步驟S2之方式實施的事實,但步驟S2的功能與藉由雜質之區域選擇性移除之頂部/底部厚TS-SiO中的步驟S2之功能完全相反。也就是,在藉由雜質之區域選擇性移除之頂部/底部厚TS-SiO中的步驟S2(圖2)中,主要係從膜的水平部分移除雜質,而在藉由雜質之區域選擇性併入之側壁厚TS-SiO中的步驟S2(圖3)中,主要係將雜質併入膜的水平部分中。
在步驟S2中,使吸附雜質的膜在相對低壓及相對高RF功率下暴露至稀有氣體電漿,使得與膜之垂直部分所吸附者相比,膜之水平部分上所吸附的雜質係主要或充分地併入其中。步驟S4、步驟S5、及步驟S2係無中斷地連續實施(無破壞真空),或替代地,步驟S5的實施可在不同於步驟S4所用的室中,或藉由將基板儲存在含雜質的不同大氣中,接著再將基板重新裝載至用於步驟S4的室以實施步驟S3,如圖3所繪示。當步驟S4係循環沉積時,步驟S5及S2可在循環沉積的每一個單個循環(沉積單層)之後或在循環沉積的每兩個或更多個循環(沉積單層的層壓體)之後實施。然而,步驟S4中所得的膜厚度不應超過步驟S2中之電漿離子撞擊無法穿透的厚度。一組步驟S4、S5、及S2可重複數次,直到得到所欲膜厚度。在一些實施例中,頂部表面上所沉積的膜之厚度係約3 nm至約50 nm,一般係約10 nm至約20 nm,取決於所沉積的膜之預期目的或用途。
在步驟S3中,使經電漿處理的膜遭受濕蝕刻,在表2所示的條件下以實質上類似於圖2所示的步驟S3之方式達成TS-SiO。藉由步驟S2來將雜質區域選擇性地併入膜的水平部分(亦即,膜的頂部/底部部分)中,且膜的水平部分對離子撞擊變得更易脆並減小抗化學性。藉由使經電漿處理的膜遭受濕蝕刻,主要地蝕刻或移除比膜之垂直部分含有更多雜質之膜的水平部分(亦即,膜的頂部/底部部分),形成側壁厚輪廓。
圖4係根據本發明之另一實施例繪示拓樸選擇性膜形成製程的流程圖。此實施例表示藉由雜質之區域選擇性併入之側壁厚TS-SiO的另一實施例。在步驟S4中,SiO膜係以實質上類似於圖3之步驟S4的方式沉積在具有溝槽的基板上。在步驟S6中,將含雜質的氣體(例如,含有諸如碳及/或鹵素之雜質但不含矽的烴氣或類似者)添加至電漿氣體,使得膜係暴露至含元素活性物種的電漿,該等元素活性物種主要係作為雜質併入膜的水平部分,得出所具有的雜質分布類似於如圖3所示般得到的膜之雜質分布的膜。在一些實施例中,步驟S6可在下文之表4所示的條件下實施。
表4(數字為近似值)
用於含雜質之電漿沉積的條件 | |
基板溫度 | 50至600℃(較佳係200至500℃) |
壓力 | 1至5000 Pa(較佳係1至100 Pa,更佳係1至50 Pa),取決於RF功率 |
稀有氣體 | Ar、He |
稀有氣體之流量率(連續) | 1至100 sccm(較佳係1至10 sccm) |
非矽氣體 | CH4 、C2 H6 、Cl2 、Brs、CCl4 |
非矽氣體的流量率(連續) | 1至100 sccm(較佳係1至10 sccm) |
用於300-mm晶圓之RF功率(13.56 MHz) | 10至2000 W(較佳係100至1000 W,更佳係100至600W),取決於壓力 |
施加RF功率的持續時間 | 0.1至10秒(較佳係0.2至3秒),取決於膜厚度 |
電極之間的距離 | 5至20 mm(較佳係10至15 mm) |
步驟S4及步驟S6係無中斷地連續實施(無破壞真空)。當步驟S4係循環沉積時,步驟S6可在循環沉積的每一個單個循環(沉積單層)之後或在循環沉積的每兩個或更多個循環(沉積單層的層壓體)之後實施。一組步驟S4及S6可重複數次,直到得到所欲膜厚度。在一些實施例中,頂部表面上所沉積的膜之厚度係約3 nm至約50 nm,一般係約10 nm至約20 nm,取決於所沉積的膜之預期目的或用途。
在步驟S3中,使經電漿處理的膜遭受濕蝕刻,在表2所示的條件下以實質上類似於圖3所示的步驟S3之方式達成TS-SiO。如圖3所繪示的製程中,藉由步驟S6來將雜質區域選擇性地併入膜的水平部分(亦即,膜的頂部/底部部分)中,且膜的水平部分對離子撞擊變得更易脆並減小抗化學性。藉由使經電漿處理的膜遭受濕蝕刻,主要地蝕刻或移除比膜之垂直部分含有更多雜質之膜的水平部分(亦即,膜的頂部/底部部分),形成側壁厚輪廓。
圖5根據本發明之不同實施例繪示顯示SiO之拓樸選擇性膜形成製程(TS-SiO)的示意截面圖((a)及(b)表示藉由雜質之區域選擇性移除之頂部/底部厚TS-SiO,而(a)及(c)表示藉由雜質之區域選擇性併入之側壁厚TS-SiO)。在圖5中,SiO2
膜42係共形地沉積在具有溝槽46的基板41上,其中SiO2
膜42係由水平部分(頂部部分45及底部部分43)及垂直部分(側壁部分44)構成,該膜共形地或均勻地覆蓋具有溝槽46之基板41的整個表面。SiO2
膜42具有實質上表面均勻的雜質分布,包括整個膜實質上無雜質分布。
在藉由雜質之區域選擇性移除之頂部/底部厚TS-SiO中,(a)中的SiO2
膜42含有在整個膜實質上均勻分布的雜質,且藉由使膜暴露至各向異性電漿打擊(藉由離子撞擊),膜的水平部分45、43比膜的垂直部分44接收更多離子撞擊,從而使水平部分比垂直部分分離或分開更多雜質,並使水平部分緻密化。結果,在膜的垂直部分中比在膜的水平部分中餘留更多雜質,亦即,垂直部分比水平部分對濕蝕刻變得更易脆。因此,藉由使具有不均勻雜質分布的膜遭受,實質上僅或主要地可移除膜的垂直部分,如(b)中所繪示。
反之,在藉由雜質之區域選擇性併入之側壁厚TS-SiO中,(a)中的SiO2
膜42含有在整個膜實質上不均勻分布的雜質,包括在整個膜實質上零或低位準的雜質,且藉由使雜質吸附至膜之垂直部分及水平部分的表面上隨後暴露至電漿,或藉由使膜之垂直部分及水平部分暴露至含有雜質活性物種的電漿,其中膜的水平部分45、43比膜的垂直部分44接收更多離子撞擊,從而在水平部分中併入比垂直部分中更多的雜質。結果,在膜的水平部分中比在膜的垂直部分中引入更多雜質,亦即,水平部分比垂直部分對濕蝕刻變得更易脆。因此,藉由使具有不均勻雜質分布的膜遭受,實質上僅或主要地可移除膜的水平部分,如(c)中所繪示。
在一些實施例中,於圖5之(b)中所繪示之藉由雜質之區域選擇性移除之頂部/底部厚TS-SiO中,最終膜的共形性(側壁處(例如截面圖之中點處)的膜厚度之比率)對頂部部分處之膜厚度係約30%或更小,包括實質上0%(例如,約0%、約10%、約20%、約30%、或在前述數字的任兩者之間的範圍內之任何數字)。在一些實施例中,於圖5之(c)中所繪示之藉由雜質之區域選擇性併入之側壁厚TS-SiO中,膜之共形性的倒數(側壁處(例如截面圖之中點處)的膜厚度之比率對膜之頂部處(例如截面圖之中點處)的膜厚度係約30%或更小,包括實質上0%,例如,約0%、約10%、約20%、約30%、或在前述數字的任兩者之間的範圍內之任何數字)。在上文中,底部處的膜厚度可依據溝槽的深寬比、RF功率、壓力等而改變。例如,若溝槽的深寬比高(例如5至10或更高)、RF功率相對低、及/或壓力相對高,溝槽底部處的膜與頂部處的膜相比傾向於在濕蝕刻後餘留,因為充足的電漿離子撞擊可能無法抵達溝槽底部。
在本揭露中所述之製程序列中,前驅物可使用連續供應之載體氣體以脈衝供應。此可使用流通系統(FPS)來完成,其中載體氣體管路具備具有前驅物儲槽(瓶)之歧路管路,且主管路及歧路管路經切換,其中當僅意欲將載體氣體饋送至反應室時,關閉歧路管路,而當意欲將載體氣體及前驅物氣體兩者饋送至反應室時,主管路關閉且載體氣體流過歧路管路且與前驅物氣體一起從瓶流出。以此方式,載體氣體可連續地流入反應室中,且可藉由切換主管路及歧路管路而以脈衝載送前驅物氣體。圖1B繪示根據本發明之一實施例之使用流通系統(FPS)的前驅物供應系統(黑色閥指示該等閥關閉)。如圖1B中之(a)所示,當將前驅物饋送至反應室(未圖示)時,首先,諸如Ar(或He)之載體氣體流過具有閥b及c之氣體管路,且接著進入瓶(儲槽)30。載體氣體從瓶30流出,同時載送對應於瓶30內之蒸氣壓的量之前驅物氣體,並流過具有閥f及e之氣體管路,且接著與前驅物一起饋送至反應室。在上文中,閥a及d關閉。當僅將載體氣體(稀有氣體)饋送至反應室時,如圖1B中之(b)所示,載體氣體流過具有閥a之氣體管路,同時繞過瓶30。在上文中,閥b、c、d、e、及f關閉。
前驅物可借助載體氣體來提供。由於ALD係自限制吸附反應製程,因此所沉積之前驅物分子的數目係藉由反應性表面位點之數目來判定,且與飽和後之前驅物暴露無關,且前驅物之供應係使得反應性表面位點因而在每一循環均飽和。用於沉積之電漿可原位(例如,在整個沉積循環中連續流動的氨氣中)產生。在其他實施例中,電漿可於遠端產生並提供至反應室。
如上文所提及,各沉積循環之各脈衝或階段較佳係自限制的。在各階段中供應過量的反應物以使敏感的結構表面飽和。表面飽和確保反應物佔據所有可用的反應性位點(遭受例如實體大小或「位阻(steric hindrance)」限制),且因此確保優越的步階覆蓋。在一些實施例中,可減少反應物之一或多者的脈衝時間,使得完全飽和未達成,且小於一單層經吸附在基板表面上。
例如,可使用包括圖1A中所繪示之設備的任何合適設備來執行製程循環。圖1A係可用於本發明之一些實施例中之PEALD設備(所欲的係與經程式化以實施下述序列之控制機構協力)的示意圖。在此圖式中,藉由在反應室3之內部11(反應區)中提供平行且彼此面對的一對導電平板電極4、2,向一側施加HRF功率(13.56 MHz或27 MHz)20,且將另一側12電氣接地,在該等電極之間激發電漿。溫度調節器係在下部台2(下部電極)中提供,且放置在其上之基板1的溫度在給定溫度下保持恆定。上部電極4亦充當噴淋板,且反應物氣體(及稀有氣體)及前驅物氣體分別透過氣體管路21及氣體管路22以及透過噴淋板4引入反應室3中。此外,在反應室3中,提供具有排氣管路7之圓管13,透過該排氣管路將反應室3之內部11中的氣體排出。此外,稀釋氣體係透過氣體管路23引入反應室3中。進一步地,經設置於反應室3下方之轉移室5具備密封氣體管路24以經由轉移室5之內部16(轉移區)將密封氣體引入反應室3之內部11中,其中提供用於將反應區與轉移區分開之分隔板14(此圖省略閘閥,晶圓經由該閘閥轉移至轉移室5中或從該轉移室轉移)。轉移室亦具備排氣管路6。在一些實施例中,多元素膜沉積及表面處理係在相同反應空間中執行,使得所有製程可連續地實施,而不使基板暴露至空氣或其他含氧大氣。在一些實施例中,遠端電漿單元可用於激發氣體。
在一些實施例中,於圖1A所描繪之設備中,可在實質上不使反應室壓力波動的情況下使用圖1B中所繪示之切換惰性氣體之流動與前驅物氣體之流動的系統(先前描述)以脈衝引入前驅物氣體。
在一些實施例中,可使用雙室反應器(經設置為彼此靠近之用於處理晶圓的兩個區段或隔室),其中反應物氣體及稀有氣體可透過共用管路供應,而前驅物氣體係透過非共用管路供應。
所屬技術領域中具有通常知識者應瞭解,設備包括一或多個控制器(未圖示),其(等)可經程式化或以其他方式組態以致使本文於別處所述之沉積及反應器清潔製程之實施。如所屬技術領域中具有通常知識者將瞭解的,(多個)控制器係與反應器之各種電源、加熱系統、泵、機器人系統、及氣流控制器或閥通訊。
本發明將參照下文之工作例以進一步解釋。然而,實例並非意欲限制本發明。在未指定條件及/或結構之實例中,所屬技術領域中具有通常知識者可鑒於本揭露而按照例行實驗輕易地提供此類條件及/或結構。同樣地,在一些實施例中,特定實例中所應用之數字可在至少±50%之範圍內進行修改,且該等數字為近似值。
實例
實例1
在此實例中,藉由雜質之區域選擇性併入之側壁厚TS-SiO係如圖4所繪示般實施。然而,此實例相當於實驗實例,因為圖4中的步驟S6係使用聚醯亞胺帶(具有丙烯酸黏著劑)實施,基板使用該聚醯亞胺帶黏附至受體,該帶經暴露至電漿,並預期作為包括碳(氣態分子污染物,AMC)之雜質的來源,碳係釋放至電漿中,形成含碳活性物種的電漿(相對於藉由添加含雜質氣體至電漿氣體來形成含雜質活性物種的電漿)。上述步驟係視為功能上等同於步驟S6,其中兩步驟均製造出含雜質活性物種的電漿。
首先,SiO膜係藉由PEALD來形成在具有溝槽的Si基板(Ф300 mm)上,其之一循環係使用圖1A所繪示之PEALD設備及圖1B所繪示之氣體供應系統(FPS)在下文之表5(沉積循環)所示的條件下實施。
在從反應室取出基板之後,將基板暫時儲存在大氣中,接著再使用具有丙烯酸黏著劑之聚醯亞胺帶將基板黏附至設備的受體表面。接著在下文之表5所示的條件下使基板遭受後沉積電漿處理,使得丙烯酸黏著劑經暴露至電漿,在電漿中產生碳活性物種。其後,使基板在下文之表5所示的條件下遭受濕蝕刻。
表5(數字為近似值)
用於沉積循環之條件 | |
基板溫度 | 300℃ |
壓力 | 400 Pa |
前驅物 | 六氯矽乙烷 |
前驅物脈衝 | 1秒 |
前驅物沖洗 | 1秒 |
反應物 | O2 |
反應物之流量率(連續) | 1 sccm |
載體氣體之流量率(連續) | 2000 sccm Ar |
稀釋氣體之流量率(連續) | 2000 sccm Ar |
用於300-mm晶圓之RF功率(13.56 MHz) | 200 W |
RF功率脈衝 | 1秒 |
沖洗 | 1秒 |
循環數目(頂部表面上之膜厚度) | 200次(20 nm) |
步階覆蓋(側/頂部;側/底部) | 95%;95% |
溝槽深度/寬度(nm) | 80/200(AR=約2.5) |
電極之間的距離 | 12mm |
用於電漿處理之條件 | |
基板溫度 | 300℃ |
壓力 | 100 Pa |
稀有氣體 | Ar或He |
稀有氣體之流量率(連續) | 1000 sccm |
雜質來源(AMC) | 具有丙烯酸黏著劑之聚醯亞胺帶 |
用於300-mm晶圓之RF功率(13.56 MHz) | 200 W |
施加RF功率的持續時間 | 1秒 |
用於濕蝕刻之條件 | |
蝕刻溶液 | 0.5% HF |
蝕刻溶液溫度 | 25℃ |
蝕刻之持續時間 | 1分鐘 |
同樣地,作為比較例,SiO膜係以實質上類似於上述之方式藉由PEALD形成在具有溝槽的Si基板(Ф300 mm)上,且未實施電漿處理(未執行步驟S6),連續地,以實質上類似於上述之方式使基板遭受濕蝕刻。
結果係顯示於圖6。圖6顯示如(a)中所沉積之氧化矽膜、(b)中於dHF蝕刻後無電漿處理之氧化矽膜、及(c)中於dHF蝕刻後經電漿處理之氧化矽膜的截面圖之掃描電子顯微鏡(SEM)照片。如圖6之(c)所示,當使基板暴露至含雜質活性物種之電漿時,實質上僅或主要地蝕刻膜的頂部部分,實質上僅或主要地留下膜的側壁部分。反之,如圖6之(b)所示,當基板未經暴露至電漿時,實質上僅或主要地蝕刻膜的側壁部分,實質上僅或主要地留下膜的頂部部分。呈現出如上文之結果是因為電漿中所含的雜質實質上僅或主要地併入膜的頂部部分中,使得膜的頂部部分比膜的側壁部分對濕蝕刻更易脆。
在圖6之(b)中,頂部/底部厚TS-SiO係在無雜質之區域選擇性移除的情況下達成。呈現出此結果是因為PEALD具有各向異性特性,並活化膜的水平部分而非垂直部分,依據沉積條件等授予水平部分高品質(高密度及/或低雜質濃度)。藉由利用圖2所繪示之製程,可進一步改善膜之水平部分的品質,並可進一步改善膜在水平部分與垂直部分之間的濕蝕刻選擇性。進一步地,若膜係藉由熱ALD所沉積,則膜品質係均勻的,且原則上在膜的水平部分與垂直部分之間無差異。在該情況下,需要電漿處理以達成頂部/底部厚TS-SiO。
在圖6之(c)中,膜的底部部分並未與膜的頂部部分蝕刻或移除得一樣多,儘管事實上兩者均係水平部分。看起來充足的電漿離子撞擊並未抵達底部部分,因為溝槽的深寬比太高、RF功率低、及/或壓力太高。藉由操縱這些參數(例如,將深寬比改成約2或更小),膜的底部部分可移除或蝕刻達膜的頂部部分中所觀察到的程度。
參考實例1
在此參考實例中,與上文的實例1一致,確認雜質(碳及氮)係在低壓下藉由電漿處理來併入膜中,且膜之含有更多雜質的一部分對濕蝕刻更易脆。
膜(毯覆膜)係以實質上類似於實例1之方式沉積,接著,除了處理壓力如圖7所示般改變以外,以實質上類似於實例1之方式使膜暴露至電漿,隨後以實質上類似於實例1之方式進行濕蝕刻。圖7係顯示膜的處理壓力[kPa]與濕蝕刻率(「WERR.Tox」:相對於熱氧化物之濕蝕刻率)間之關係的圖。如圖7所示,與表示在無電漿處理的情況下所沉積的膜之「參考」相比,當處理壓力係100 Pa(「第2號」)時,WERR非常高(亦即,對化學品具低抗性的低品質膜),而當處理壓力係500 Pa、2,000 Pa、及10,000 Pa時,WERR低(亦即,對化學品具相對高抗性的相對高品質膜)。當處理壓力高達50,000 Pa(「第1號」)時,WERR由於電漿離子撞擊不足而增加。
同樣地,使膜遭受X-射線光電子光譜(XPS)成分分析(原子%)(在藉由濺鍍移除各膜表面之2 nm深度以便除去非所要的污染之後實施分析)。結果係顯示於下文之表6(「參考」、「第1號」、及「第2號」分別對應於圖7之「參考」、「第1號」、及「第2號」,且「ND」係指「未偵測到」)。如表6所示,確認雜質(碳及氮)係在低壓下藉由電漿處理來併入膜中(「第1號」)。當處理壓力高達50,000 Pa(「第2號」)時,雜質不會併入膜中,如未經電漿處理的膜(「參考」)之情況。
表6(數字為近似值)
樣本 | 電漿 | C | Si | O | N |
參考 | 否 | ND | 32.8 | 67.2 | ND |
第1號 | 是 | ND | 32.8 | 67.2 | ND |
第2號 | 是 | 4.1 | 31.3 | 63.9 | 0.6 |
第3號 | 是 | 3.4 | 32.9 | 62.7 | 1.1 |
在上文中,除了SiO膜係在300°C的溫度下沉積以外,第3號顯示以相同於第2號之方式得到的膜之資料。確認即使當沉積條件改變,側壁厚TS-SiO可藉由雜質之區域選擇性併入來達成。
預示實例1
在此實例中,藉由雜質之區域選擇性併入之側壁厚TS-SiO係如圖3所繪示般執行。SiO膜係如圖3之步驟S4以實質上類似於實例1之方式沉積。取代實例1中所用之具有丙烯酸黏著劑的聚醯亞胺帶,膜一經沉積,在無破壞真空的情況下,分別以約0.5 slm及約2 slm將Cx
Hy
氣體(x及y係除了零以外的整數)及Ar引入室中,以便使膜暴露至烴氣持續約一分鐘,從而吸附雜質(例如碳)至膜表面上。其後,在類似於用於實例1之電漿處理的條件下實施圖3的步驟S2,隨後在類似於實例1的條件下進行濕蝕刻(圖3的步驟S3)。結果,達成具有類似於圖6之(c)所示之拓樸的側壁厚TS-SiO。
所屬技術領域中具有通常知識者將理解,在不偏離本發明之精神的情況下,可作出大量及各種修改。因此,應清楚理解,本發明之形式僅係說明性,而非意欲限制本發明之範疇。
1,41:基板
2:下部台/導電平板電極
3:反應室
4:導電平板電極/上部電極/噴淋板
5:轉移室
6,7:排氣管路
11:內部
12:側
13:圓管
14:分隔板
16:內部
20:HRF功率
21,22,23:氣體管路
24:密封氣體管路
30:瓶
42:膜
43:底部部分
44:側壁部分
45:頂部部分,水平部分
46:溝槽
S1,S2,S3,S4,S5,S6:步驟
圖1A係可用於本發明之一實施例中之用於沉積保護膜之PEALD(電漿增強原子層沉積)設備的示意圖。
圖1B繪示可用於本發明之一實施例中之使用流通系統(flow-pass system,FPS)之前驅物供應系統的示意圖。
圖2係繪示根據本發明之一實施例之拓樸選擇性膜形成之步驟的流程圖。
圖3係繪示根據本發明之另一實施例之拓樸選擇性膜形成之步驟的流程圖。
圖4係繪示根據本發明之仍有另一實施例之拓樸選擇性膜形成之步驟的流程圖。
圖5根據本發明之不同實施例繪示顯示拓樸選擇性膜形成製程的示意截面圖((a)及(b)表示一個實施例,而(a)及(c)表示另一實施例)。
圖6顯示根據本發明之一實施例之如(a)中所沉積之氧化矽膜、(b)中於dHF蝕刻後無重整處理之氧化矽膜、及(c)中於dHF蝕刻後經重整處理之氧化矽膜之截面圖的掃描電子顯微鏡(SEM)照片。
圖7係顯示根據本發明之實施例之形成在頂部表面上的膜(毯覆膜)之處理壓力[kPa]與濕蝕刻率(「WERR. Tox」:相對於熱氧化物之濕蝕刻率)間之關係的圖。
41:基板
42:膜
43:底部部分
44:側壁部分
45:頂部部分,水平部分
46:溝槽
Claims (15)
- 一種用於形成一介電膜之方法,該介電膜在形成於一基板表面上之一步階上含有一Si-O鍵,該方法包含下列製程: (i)藉由參照得出一最終介電膜之一初始介電膜的一非目標部分,預選擇欲選擇性移除的一目標部分來設計形成在該步階上之含有一Si-O鍵之該最終介電膜的一拓樸,該目標部分係形成在該步階之一頂部表面及一底部表面上之該初始介電膜的一頂部/底部部分,或者形成在該步階之一側壁上之該初始介電膜的一側壁部分; (ii)在該步階之該頂部表面、該底部表面、及該側壁上共形地沉積該初始介電膜;及 (iii)相對於該初始介電膜之該非目標部分中所含的一雜質量相對地增加該初始介電膜之該目標部分中所含的一雜質量,以得到一經處理介電膜,從而提供該目標部分及該非目標部分遭受蝕刻時之不同的抗化學性質。
- 如請求項1之方法,其進一步包含(iv)蝕刻該經處理介電膜以得到該最終介電膜。
- 如請求項1之方法,其中該等雜質包括碳及/或鹵素。
- 如請求項1之方法,其中在製程(i)中,該側壁部分係預選擇為該目標部分,且在製程(ii)中,該初始介電膜係使用進一步含有碳及/或鹵素之含矽前驅物沉積,且在製程(iii)中,該目標部分中所含的該雜質量係藉由在兩電極間施加RF功率而激發之一電漿的各向異性撞擊來減小該初始介電膜之該非目標部分中所含的該雜質量而相對地增加,該基板係在該兩電極之間平行該兩電極放置。
- 如請求項1之方法,其中於製程(i)中,該頂部/底部部分係預選擇為該目標部分,且在製程(iii)中,該目標部分中所含的該雜質量係藉由增加該初始介電膜之該目標部分中所含的該雜質量,而相對地增加,增加該初始介電膜之該目標部分中所含的該雜質量係藉由(iiia)在該初始介電膜的整個暴露表面上吸附含有碳及/或鹵素的一非矽氣體,及(iiib)使吸附該非矽氣體的表面遭受在兩電極間施加RF功率而激發之一電漿的各向異性撞擊,該基板係在該兩電極之間平行該兩電極放置。
- 如請求項1之方法,其中於製程(i)中,該頂部/底部部分係預選擇為該目標部分,且在製程(iii)中,該目標部分中所含的該雜質量係藉由增加該初始介電膜之該目標部分中所含的該雜質量而相對地增加,增加該初始介電膜之該目標部分中所含的該雜質量係藉由(iiic)在含有碳及/或鹵素的一非矽氣體存在的情況下,使該初始介電膜遭受在兩電極間施加RF功率而激發之一電漿的各向異性撞擊,該基板係在該兩電極之間平行該兩電極放置。
- 如請求項1之方法,其中於製程(ii)中,該初始介電膜係藉由電漿增強ALD或熱ALD來沉積。
- 如請求項4之方法,其中該含矽前驅物係選自由Si2 Ry Cl6-y 及SiRx Cl4-x 組成之群組,其中y係0至5的一整數,其中R係H或一烷基,且x係0至3的一整數。
- 如請求項4之方法,其中該RF功率按照該基板之表面積係0.85 W/cm2 至1.41 W/cm2 ,且係在1至100 Pa的一壓力下施加。
- 如請求項5之方法,其中該非矽氣體係選自由烴氣、鹵素氣體、及鹵化氣體所組成之群組。
- 如請求項5之方法,其中該RF功率按照該基板之表面積係0.85 W/cm2 至1.41 W/cm2 ,且係在1至100 Pa的一壓力下施加。
- 如請求項6之方法,其中該非矽氣體係選自由烴氣、鹵素氣體、及鹵化氣體所組成之群組。
- 如請求項6之方法,其中該RF功率按照該基板之表面積係0.85 W/cm2 至1.41 W/cm2 ,且係在1至100 Pa的一壓力下施加。
- 如請求項2之方法,其中於製程(iv)中,該蝕刻係使用dHF之濕蝕刻。
- 如請求項14之方法,其中該HF濃度係大約0.1%。
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- 2020-01-20 KR KR1020200007080A patent/KR20200096422A/ko unknown
- 2020-01-21 TW TW112118213A patent/TW202334478A/zh unknown
- 2020-01-21 TW TW109102098A patent/TWI804706B/zh active
- 2020-01-22 JP JP2020008288A patent/JP2020127004A/ja active Pending
- 2020-01-24 US US16/752,514 patent/US11127589B2/en active Active
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US20200251328A1 (en) | 2020-08-06 |
US11127589B2 (en) | 2021-09-21 |
TWI804706B (zh) | 2023-06-11 |
CN111524788B (zh) | 2023-11-24 |
CN111524788A (zh) | 2020-08-11 |
TW202334478A (zh) | 2023-09-01 |
JP2020127004A (ja) | 2020-08-20 |
KR20200096422A (ko) | 2020-08-12 |
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