TWI753633B - 利用電漿輔助原子層沉積技術製造的半導體裝置及其方法 - Google Patents

利用電漿輔助原子層沉積技術製造的半導體裝置及其方法 Download PDF

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TWI753633B
TWI753633B TW109137882A TW109137882A TWI753633B TW I753633 B TWI753633 B TW I753633B TW 109137882 A TW109137882 A TW 109137882A TW 109137882 A TW109137882 A TW 109137882A TW I753633 B TWI753633 B TW I753633B
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layer
plasma
substrate
stacked layers
deposition
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TW109137882A
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TW202217951A (zh
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顏聰富
張光瑞
蔡群賢
李庭鵑
蔡群榮
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台灣奈米碳素股份有限公司
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Priority to TW109137882A priority Critical patent/TWI753633B/zh
Priority to JP2021175972A priority patent/JP7263484B2/ja
Priority to CN202111258113.8A priority patent/CN114446801A/zh
Priority to US17/513,055 priority patent/US20220139701A1/en
Priority to DE102021128387.6A priority patent/DE102021128387A1/de
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Abstract

一種利用電漿輔助原子層沉積技術製造半導體裝置的方法，包括：提供基板，基板包括矽基板及第一氧化層。沉積多個堆疊層於基板之上，堆疊層包括介電層及導體層。蝕刻堆疊層以形成至少一溝槽。使用電漿輔助原子層沈積裝置沉積第二氧化層於堆疊層及溝槽上。電漿輔助原子層沈積裝置包括腔室、上電極及下電極，上電極位於腔室的上方並包括多個噴頭。第一射頻功率裝置讓上電極的該些噴頭產生電漿，第二射頻功率裝置清潔該些噴頭，下電極設置於腔室的下方並連接一第三射頻功率裝置。沉積一高電阻層於第二氧化層上，沉積一低電阻層於高電阻層上。

Description

利用電漿輔助原子層沉積技術製造的半導體裝置及其方法
本發明是有關於一種製造半導體裝置的方法，且特別關於一種利用電漿輔助原子層沉積技術製造半導體裝置的方法。
半導體工業正不斷的蓬勃發展當中。半導體設計和材料的技術進步讓半導體裝置具有更小、更複雜的電路。半導體裝置的功能密度通常增加而尺寸縮小，可以提高生產效率及降低成本。
半導體裝置的功能受到半導體晶片面積的限制，而隨著半導體技術的發展，越來越多裝置採用三維堆疊技術來增加元件的密度。然而，三維堆疊技術增加了半導體裝置製程的複雜度，並更難維持半導體裝置的製程品質及穩定度，且會影響產量。三維積體電路的半導體晶片對結構與製程要求很高。現有的三維半導體製程仍存在有許多問題，從而影響半導體晶片的電性和機械性質。因此，在半導體裝置的製程中進行對應的發展，以提升製程品質及穩定度是亟需解決的問題。
“先前技術”段落只是用來幫助了解本發明內容，因此在“先前技術”段落所揭露的內容可能包含一些沒有構成所屬技術領域中具有通常知識者所知道的習知技術。在“先前技術”段落所揭露的內容，不代表該內容或者本發明一個或多個實施例所要解決的問題，在本發明申請前已被所屬技術領域中具有通常知識者所知曉或認知。
本發明提供一種利用電漿輔助原子層沉積技術製造半導體裝置的方法，可以大幅提高沉積的薄膜的均勻度。
本發明另提供一種半導體裝置，可以大幅提高沉積的薄膜的均勻度。本發明的其他目的和優點可以從本發明所揭露的技術特徵中得到進一步的了解。
本發明的一種利用電漿輔助原子層沉積技術製造半導體裝置的方法包括：提供一基板，該基板包括一矽基板及一第一氧化層，該第一氧化層位於該矽基板上。沉積多個堆疊層於該基板之上，每一該堆疊層包括一介電層及一導體層。通過圖案化的一光阻層蝕刻該些堆疊層，以在該些堆疊層形成至少一溝槽，該溝槽的底部暴露該第一氧化層。使用一電漿輔助原子層沈積(plasma-enhanced atomic layer deposition，PEALD)裝置沉積一第二氧化層於該些堆疊層及該至少一溝槽上，其中該電漿輔助原子層沈積裝置包括一腔室、一上電極及一下電極，該上電極位於該腔室的上方並連接一第一射頻功率裝置及一第二射頻功率裝置，該上電極包括多個噴頭，該第一射頻功率裝置用於讓該上電極的該些噴頭產生一電漿，該第二射頻功率裝置用於清潔該些噴頭，該下電極設置於該腔室的下方並連接一第三射頻功率裝置，該基板設置於該下電極上以進行一沉積製程。使用該電漿輔助原子層沈積裝置沉積一高電阻層於該第二氧化層上。以及使用該電漿輔助原子層沈積裝置沉積一低電阻層於該高電阻層上。
在本發明的一實施例中，上述之每一該噴頭具有一槽孔，該槽孔自該上電極的一上表面貫穿至一下表面。
在本發明的一實施例中，上述之該槽孔在該上表面的開口是一上開口，該槽孔在該下表面的開口是一下開口，該下開口大於該上開口，該槽孔自該下開口往該上開口逐漸縮小。
在本發明的一實施例中，上述之該槽孔在該上表面的開口是一上開口，該槽孔在該下表面的開口是一下開口，該下開口的輪廓是一六邊形。
在本發明的一實施例中，上述之該電漿輔助原子層沈積裝置還包括一三維旋轉裝置，該三維旋轉裝置設置於該腔室的下方，該下電極設置於該三維旋轉裝置上，在該沉積製程中，該三維旋轉裝置帶動該基板旋轉，以致使沉積均勻。
在本發明的一實施例中，上述之該下電極至該上電極的方向是一第一方向，該三維旋轉裝置不旋轉時，該基板的一法線方向平行該第一方向，該三維旋轉裝置帶動該基板旋轉時，該基板的該法線方向與該第一方向具有一角度，該角度介於0度至15度之間。
在本發明的一實施例中，上述之該上電極連接一上加熱器，在該沉積製程中，該上加熱器對該上電極進行加熱，以致使沈積均勻。
在本發明的一實施例中，上述之該下電極連接一下加熱器，在該沉積製程中，該下加熱器對該下電極進行加熱，以致使沈積均勻。
在本發明的一實施例中，上述之該高電阻層包括一第一多晶矽層及一第一導電化合物層，該低電阻層包括一第二多晶矽層及一第二導電化合物層，該第二多晶矽層的厚度大於該第一多晶矽層，該第二導電化合物層的厚度大於該第一導電化合物層。
在本發明的一實施例中，上述之該堆疊層的層數大於20，每一該堆疊層中，該介電層位於該導體層上方，或該導體層位於該介電層上方。
在本發明的一實施例中，上述之該導體層是一P型半導體層或一N型半導體層，該介電層是一氧化物層。
在本發明的一實施例中，上述之該溝槽的一寬度介於45nm至65nm之間。
在本發明的一實施例中，上述之該矽基板的厚度介於520nm至580nm之間，該第一氧化層的厚度介於90nm至110nm之間，該介電層的厚度介於18nm至22nm之間，該導體層的厚度介於27nm至33nm之間。
本發明的半導體裝置包括：一基板，該基板包括一矽基板及一第一氧化層，該第一氧化層位於該矽基板上。多個堆疊層沉積於該基板之上，每一該堆疊層包括一介電層及一導體層。至少一溝槽，該至少一溝槽通過圖案化的一光阻層蝕刻該些堆疊層而形成，該溝槽的底部暴露該第一氧化層。一第二氧化層，沉積於該些堆疊層及該至少一溝槽上，其中使用一電漿輔助原子層沈積(plasma-enhanced atomic layer deposition，PEALD)裝置沉積該第二氧化層，該電漿輔助原子層沈積裝置包括一腔室、一上電極及一下電極，該上電極位於該腔室的上方並連接一第一射頻功率裝置及一第二射頻功率裝置，該上電極包括多個噴頭，該第一射頻功率裝置用於讓該上電極的該些噴頭產生一電漿，該第二射頻功率裝置用於清潔該些噴頭，該下電極設置於該腔室的下方並連接一第三射頻功率裝置，該基板設置於該下電極上以進行一沉積製程。一高電阻層，該高電阻層使用該電漿輔助原子層沈積裝置沉積於該第二氧化層上。以及一低電阻層，該低電阻層使用該電漿輔助原子層沈積裝置沉積於該高電阻層上。
基於上述，本發明提供的半導體裝置及其製造方法，透過設置堆疊層、第二氧化層、高電阻層及低電阻層，可以大幅提高半導體裝置的品質及 穩定度。透過在電漿輔助原子層沉積裝置的上電極設置多個噴頭，可以產生均勻穩定的電漿，並可以對噴頭進行清潔。藉此，電漿輔助原子層沉積裝置可以大幅提高沉積的薄膜的均勻度。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
1:半導體裝置
100:製造方法
11:基板
111:矽基板
113:第一氧化層
13a、13b、13c:堆疊層
131:導體層
133:介電層
15:第二氧化層
17:高電阻層
171:第一多晶矽層
173:第一導電化合物層
19:低電阻層
191:第二多晶矽層
193:第二導電化合物層
20:電漿輔助原子層沉積裝置
21:腔室
23:上電極
231:噴頭
2311:上開口
2313:下開口
233:上加熱器
24a:第一射頻功率裝置
24b:第二射頻功率裝置
25:下電極
251:下加熱器
26:第三射頻功率裝置
27:三維旋轉裝置
A:角度
D:沉積製程
D1:第一方向
E:蝕刻製程
h:槽孔
N:法線方向
P:電漿
PR:光阻層
S101~S111:步驟
t:溝槽
t1:溝槽
w:寬度
圖1、圖2、圖3、圖4是根據一些實施例所繪示出一種利用電漿輔助原子層沉積技術製造半導體裝置的方法的製程的中間階段的剖面圖。
圖5是本發明一實施例的半導體裝置的示意圖。
圖6是本發明一實施例的電漿輔助原子層沉積裝置的示意圖。
圖7A是本發明一實施例的電漿輔助原子層沉積裝置的局部的示意圖。
圖7B是本發明一實施例的電漿輔助原子層沉積裝置的局部的示意圖。
圖8是本發明一實施例的一種利用電漿輔助原子層沉積技術製造半導體裝置的方法的流程圖。
有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之一較佳實施例的詳細說明中，將可清楚的呈現。以下實施例中所提到的方向用語，例如：上、下、左、右、前或後等，僅是參考附加圖式的方向。因此，使用的方向用語是用來說明並非用來限制本發明。
在本文中，「約」、「大約」以及「實質上」之用語通常表示在一給定值的+/- 20%內，更通常是在給定值的+/- 10%內，更通常是在給定值的 +/- 5%內，更通常是在給定值的3%內，更通常是在給定值的+/- 2%內，更通常是在給定值的+/- 1%內，甚至更通常是在給定值的+/- 0.5%內。本揭露給定的數值為大約的數值，亦即在沒有特定說明「約」或「實質上」的情況下，給定值仍可隱含「約」或「實質上」的含義。
請參照圖1、圖2、圖3、圖4及圖5，圖1、圖2、圖3及圖4是根據一些實施例所繪示出一種利用電漿輔助原子層沉積技術製造半導體裝置的方法的中間階段的剖面圖，圖5是本發明一實施例的半導體裝置1的示意圖。如圖1所示，在步驟S101中，提供一基板11。該基板11包括一矽基板111及一第一氧化層113。該第一氧化層113位於該矽基板111上。
如圖2所示，在步驟S103中，沉積多個堆疊層13a、13b、13c於該基板11之上。每一該堆疊層13a、13b、13c包括一介電層及一導體層，其中圖2以該堆疊層13a包括一介電層133及一導體層131作為說明。圖2以沉積3個堆疊層13a、13b、13c作為舉例說明，但本發明並不限制堆疊層的數量。在本實施例中，在其中一堆疊層中，該介電層133位於該導體層131的上方，但本發明並不以此為限。在本發明的其他實施例中，在一堆疊層中，導體層位於介電層的上方。
在本發明一實施例中，半導體裝置的該些堆疊層的層數大於20。每一該堆疊層中，該介電層位於該導體層上方，或該導體層位於該介電層上方。
如圖3所示，在步驟S105中，通過圖案化的一光阻層PR進行一蝕刻製程E，以蝕刻該些堆疊層13a、13b、13c。如圖4所示，同樣在步驟S105中，該蝕刻製程E在該些堆疊層13a、13b、13c形成至少一溝槽t。該溝槽t的底部暴露該第一氧化層113。為了方便說明，圖4僅以1個該溝槽t作為舉例說明，但本發明並不限制溝槽的數量。
請先參照圖6，圖6是本發明一實施例的電漿輔助原子層沉積(plasma-enhanced atomic layer deposition，PEALD)裝置20的示意圖。該電漿輔助原子層沉積裝置20包括一腔室21、一上電極23及一下電極25。該上電極23位於該腔室21的上方並連接一第一射頻功率裝置24a及一第二射頻功率裝置24b。
請同時參照圖7A，圖7A是本發明一實施例的電漿輔助原子層沉積裝置20的局部的示意圖。該電漿輔助原子層沉積裝置20的該上電極23包括多個噴頭231。該第一射頻功率裝置24a用於讓該上電極23的該些噴頭231產生一電漿P。該第二射頻功率裝置24b用於清潔該些噴頭231。該下電極25設置於該腔室21的下方並連接一第三射頻功率裝置26，該基板11設置於該下電極25上以進行一沉積製程D。圖6所示的該基板11僅為示意性說明，並非用以限制本發明。
如圖5所示，在步驟S107中，使用如圖6所示的該電漿輔助原子層沉積裝置20沉積一第二氧化層15於該些堆疊層13a、13b、13c及該溝槽t上。在步驟S109中，使用如圖6所示的該電漿輔助原子層沉積裝置20沉積一高電阻層17於該第二氧化層15上。
接著，在步驟S111中，使用如圖6所示的該電漿輔助原子層沉積裝置20沉積一低電阻層19於該高電阻層17上。透過在該上電極23設置多個噴頭231，可以產生均勻穩定的該電漿P，可以大幅提高沉積的薄膜的均勻度。該上電極23並可以對該些噴頭231進行清潔。藉此，該電漿輔助原子層沉積裝置20可以大幅提高沉積的薄膜的均勻度。
在本實施例中，透過該下電極25的設置，該下電極25可以將各沉積製程拉入該溝槽t的深處。該上電極23產生的該電漿P在該下電極25的作用下，可以沉積至該溝槽t的更深處。藉此可以大幅提高沉積的薄膜的均勻度。
在本發明一實施例中，該高電阻層17包括一第一多晶矽層171及一第一導電化合物層173，但本發明並不以此為限制。在本發明一實施例中，該第一導電化合物層173位於該第一多晶矽層171的上方。
在本發明一實施例中，該低電阻層19包括一第二多晶矽層191及一第二導電化合物層193，但本發明並不以此為限制。在本發明一實施例中，該第二導電化合物層193位於該第二多晶矽層191的上方。
在本發明一實施例中，該第二多晶矽層191的厚度大於該第一多晶矽層171，該第二導電化合物層193的厚度大於該第一導電化合物層173，但本發明並不以此為限制。
如圖7A所示，詳細來說，該電漿輔助原子層沉積裝置20的該上電極23的每一該噴頭231具有一槽孔h。該槽孔h自該上電極23的一上表面貫穿至一下表面。該槽孔h在該上表面的開口是一上開口2311，該槽孔h在該下表面的開口是一下開口2313。在本發明一實施例中，該下開口2313大於該上開口2311，該槽孔h自該下開口2313往該上開口2311逐漸縮小。具體而言，該槽孔h在該下開口2313處例如可以是一喇叭的形狀。藉此，透過該噴頭231的設置，該電漿輔助原子層沉積裝置20的該上電極23可以產生均勻穩定的該電漿P，可以大幅提高沉積的薄膜的均勻度。
請同時參閱圖7B，圖7B是本發明一實施例的電漿輔助原子層沉積裝置20的局部的示意圖。在本發明一實施例中，該上電極23的該噴頭231的該槽孔h的該下開口2313在該下表面的輪廓是一六邊形。藉此，透過該噴頭 231的設置，該電漿輔助原子層沉積裝置20的該上電極23可以產生均勻穩定的該電漿P，可以大幅提高沉積的薄膜的均勻度。在本發明一實施例中，該上電極23的該噴頭231的該槽孔h的該下開口2313在該下表面的輪廓是一正六邊形。
此外，該電漿輔助原子層沈積裝置20例如還可以還包括一三維旋轉裝置27。該三維旋轉裝置27設置於該腔室21的下方。該下電極25設置於該三維旋轉裝置27上。在該沉積製程D中，該三維旋轉裝置27帶動該基板11旋轉，以致使沉積均勻。透過該三維旋轉裝置27的設置，該電漿輔助原子層沉積裝置20可以大幅提高沉積的薄膜的均勻度。
詳細來說，在上述各沉積製程中，該溝槽t越深處越難以進行沉積。即該上電極23產生的該電漿P在該溝槽t的深處的側壁上難以進行沉積製程。透過該三維旋轉裝置27的設置，在上述各沉積製程中，該三維旋轉裝置27帶動該基板11旋轉，可以讓該溝槽t深處的側壁沉積更為均勻。藉此可以大幅提高沉積的薄膜的均勻度。
如圖6所示，詳細來說，該電漿輔助原子層沉積裝置20的該下電極25至該上電極23的方向是一第一方向D1。該三維旋轉裝置27不旋轉時，該基板11的一法線方向N平行該第一方向D1。該三維旋轉裝置27帶動該基板11旋轉時，該基板11的法線方向與該第一方向D1具有一角度A。在本實施例中，該角度A介於0度至15度之間。藉此，該電漿輔助原子層沉積裝置20可以大幅提高沉積的薄膜的均勻度。
在本發明一實施例中，該電漿輔助原子層沉積裝置20的該上電極23還可以連接一上加熱器233。在前述的各該沉積製程D中，該上加熱器233對 該上電極23進行加熱，以致使沉積均勻。藉此，該電漿輔助原子層沉積裝置20可以大幅提高沉積的薄膜的均勻度。
在本發明一實施例中，該電漿輔助原子層沉積裝置20的該下電極25連接一下加熱器251。在前述的各該沉積製程D中，該下加熱器251對該下電極25進行加熱，以致使沉積均勻。藉此，該電漿輔助原子層沉積裝置20可以大幅提高沉積的薄膜的均勻度。
在本實施例中，該第二多晶矽層191的厚度大於該第一多晶矽層171，該第二導電化合物層193的厚度大於該第一導電化合物層173。具體而言，該高電阻層17的電阻值高於該低電阻層19。透過該些堆疊層13a、13b、13c、該第二氧化層15、該高電阻層17及該低電阻層19的設置，可以大幅提高該半導體裝置1的品質及穩定度。
在本發明一實施例中，該第二導電化合物層193的厚度在20nm至50nm之間。
如圖5所示，在步驟S111中沉積該低電阻層19後，該溝槽t仍存在有一溝槽t1，但本發明並不以此為限制。在本發明的其他實施例中，沉積該低電阻層19後，該低電阻層19可以填滿該溝槽t，即不存在如圖5所示的該溝槽t1。
在本發明一實施例中，該些堆疊層13a、13b、13c的該導體層是一P型半導體層或一N型半導體層，該介電層是一氧化物層(Oxide)。舉例而言，該堆疊層13a的該導體層131是一P型半導體層或一N型半導體層，該介電層133是一氧化物層。
在本發明一實施例中，該第一導電化合物層173及/或該第二導電化合物層193的材料為BN、BP、BAs、AlN、AlP、AlAs、GaN、GaP、GaAs、InN、InP、InAs或前述至少兩種的材料。
在本發明一實施例中，該高電阻層17的導電率大約為1×1015S‧m-1，該低電阻層19的導電率大約為1×1020S‧m-1。該高電阻層17的厚度大約為20nm，該低電阻層19的厚度大約為30nm。
如圖4所示，在本發明一實施例中，該溝槽t的一寬度w介於45nm至65nm之間。該基板11的該矽基板111的厚度介於520nm至580nm之間，該第一氧化層113的厚度介於90nm至110nm之間。該些堆疊層13a、13b、13c中(以該堆疊層13a舉例說明)，該介電層133的厚度介於18nm至22nm之間，該導體層131的厚度介於27nm至33nm之間。
請參照圖8，圖8是本發明一實施例的電漿輔助原子層沉積裝置20的製造方法的流程圖。具體而言，圖7是圖5所示的該半導體裝置1的製造方法100的流程圖。該製造方法100包括的步驟S101、S103、S105、S107、S109、S111的多個實施細節，在前述的實施例及實施方式都有詳細的說明，以下恕不多贅述。
綜上所述，本發明實施例的半導體裝置及其製造方法，透過設置堆疊層、第二氧化層、高電阻層及低電阻層，可以大幅提高半導體裝置的品質及穩定度。透過在電漿輔助原子層沉積裝置的上電極設置多個噴頭，可以產生均勻穩定的電漿，並可以對噴頭進行清潔。藉此，電漿輔助原子層沉積裝置可以大幅提高沉積的薄膜的均勻度。
11:基板
20:電漿輔助原子層沉積裝置
21:腔室
23:上電極
231:噴頭
233:上加熱器
24a:第一射頻功率裝置
24b:第二射頻功率裝置
25:下電極
251:下加熱器
26:第三射頻功率裝置
27:三維旋轉裝置
A:角度
D1:第一方向
N:法線方向
P:電漿

Claims (14)

  1. 一種利用電漿輔助原子層沉積技術製造半導體裝置的方法，包括： 提供一基板，該基板包括一矽基板及一第一氧化層，該第一氧化層位於該矽基板上； 沉積多個堆疊層於該基板之上，每一該堆疊層包括一介電層及一導體層； 通過圖案化的一光阻層蝕刻該些堆疊層，以在該些堆疊層形成至少一溝槽，該溝槽的底部暴露該第一氧化層； 使用一電漿輔助原子層沈積裝置沉積一第二氧化層於該些堆疊層及該至少一溝槽上，其中該電漿輔助原子層沈積裝置包括一腔室、一上電極及一下電極，該上電極位於該腔室的上方並連接一第一射頻功率裝置及一第二射頻功率裝置，該上電極包括多個噴頭，該第一射頻功率裝置用於讓該上電極的該些噴頭產生一電漿，該第二射頻功率裝置用於清潔該些噴頭，該下電極設置於該腔室的下方並連接一第三射頻功率裝置，該基板設置於該下電極上以進行一沉積製程； 使用該電漿輔助原子層沈積裝置沉積一高電阻層於該第二氧化層上；以及 使用該電漿輔助原子層沈積裝置沉積一低電阻層於該高電阻層上。
  2. 如請求項1所述的方法，其中每一該噴頭具有一槽孔，該槽孔自該上電極的一上表面貫穿至一下表面。
  3. 如請求項2所述的方法，其中該槽孔在該上表面的開口是一上開口，該槽孔在該下表面的開口是一下開口，該下開口大於該上開口，該槽孔自該下開口往該上開口逐漸縮小。
  4. 如請求項2所述的方法，其中該槽孔在該上表面的開口是一上開口，該槽孔在該下表面的開口是一下開口，該下開口的輪廓是一六邊形。
  5. 如請求項1所述的方法，其中該電漿輔助原子層沈積裝置還包括一三維旋轉裝置，該三維旋轉裝置設置於該腔室的下方，該下電極設置於該三維旋轉裝置上，在該沉積製程中，該三維旋轉裝置帶動該基板旋轉，以致使沉積均勻。
  6. 如請求項5所述的方法，其中該下電極至該上電極的方向是一第一方向，該三維旋轉裝置不旋轉時，該基板的一法線方向平行該第一方向，該三維旋轉裝置帶動該基板旋轉時，該基板的該法線方向與該第一方向具有一角度，該角度介於0度至15度之間。
  7. 如請求項1所述的方法，其中該上電極連接一上加熱器，在該沉積製程中，該上加熱器對該上電極進行加熱，以致使沈積均勻。
  8. 如請求項1所述的方法，其中該下電極連接一下加熱器，在該沉積製程中，該下加熱器對該下電極進行加熱，以致使沈積均勻。
  9. 如請求項1所述的方法，其中該高電阻層包括一第一多晶矽層及一第一導電化合物層，該低電阻層包括一第二多晶矽層及一第二導電化合物層，該第二多晶矽層的厚度大於該第一多晶矽層，該第二導電化合物層的厚度大於該第一導電化合物層。
  10. 如請求項1所述的方法，其中該堆疊層的層數大於20，每一該堆疊層中，該介電層位於該導體層上方，或該導體層位於該介電層上方。
  11. 如請求項1所述的方法，其中該導體層是一P型半導體層或一N型半導體層，該介電層是一氧化物層。
  12. 如請求項1所述的方法，其中該溝槽的一寬度介於45 nm至65 nm之間。
  13. 如請求項1所述的方法，其中該矽基板的厚度介於520 nm至580 nm之間，該第一氧化層的厚度介於90 nm至110 nm之間，該介電層的厚度介於18 nm至22 nm之間，該導體層的厚度介於27 nm至33 nm之間。
  14. 一種半導體裝置，包括： 一基板，該基板包括一矽基板及一第一氧化層，該第一氧化層位於該矽基板上； 多個堆疊層沉積於該基板之上，每一該堆疊層包括一介電層及一導體層； 至少一溝槽，該至少一溝槽通過圖案化的一光阻層蝕刻該些堆疊層而形成，該溝槽的底部暴露該第一氧化層； 一第二氧化層，沉積於該些堆疊層及該至少一溝槽上，其中使用一電漿輔助原子層沈積裝置沉積該第二氧化層，該電漿輔助原子層沈積裝置包括一腔室、一上電極及一下電極，該上電極位於該腔室的上方並連接一第一射頻功率裝置及一第二射頻功率裝置，該上電極包括多個噴頭，該第一射頻功率裝置用於讓該上電極的該些噴頭產生一電漿，該第二射頻功率裝置用於清潔該些噴頭，該下電極設置於該腔室的下方並連接一第三射頻功率裝置，該基板設置於該下電極上以進行一沉積製程； 一高電阻層，該高電阻層使用該電漿輔助原子層沈積裝置沉積於該第二氧化層上；以及 一低電阻層，該低電阻層使用該電漿輔助原子層沈積裝置沉積於該高電阻層上。
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